[Bug middle-end/110573] MIPS64: Enhancement PR of load of pointer to atomic

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110573

--- Comment #3 from Andrew Pinski  ---
See
https://inbox.sourceware.org/gcc/d7787b3f-9450-5642-ffac-21cf36176...@redhat.com/
also.

[Bug middle-end/110573] MIPS64: Enhancement PR of load of pointer to atomic

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110573

--- Comment #2 from Andrew Pinski  ---
volatile (atomics) stores are not considered for branch delay slots.

https://inbox.sourceware.org/gcc/3077458.gu9dx72...@arcturus.home/

[Bug middle-end/110573] MIPS64: Enhancement PR of load of pointer to atomic

[luke.geeson at cs dot ucl.ac.uk via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110573

--- Comment #1 from Luke Geeson  ---
My apologies - I should have put the ld on the line with L7:
```
.L7:ld  $3,%got_disp(P1_r0)($5). 

```