[Bug middle-end/113179] [11/12/13/14/15 Regression] MIPS: INS is used for long long, before SLL

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113179

--- Comment #7 from Andrew Pinski  ---
(In reply to YunQiang Su from comment #6)
> With some test on some CPUs, in fact, the lacking of `sll` won't make
> troubles to us.
> It seems that most of MIPS64 CPUs can process it well as expected.

When I was working at Marvell(Cavium), only the Octeon simulator which cause
issues with the lacking of `sll` rather than the actual hardware.

[Bug middle-end/113179] [11/12/13/14/15 Regression] MIPS: INS is used for long long, before SLL

[syq at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113179

--- Comment #6 from YunQiang Su  ---
With some test on some CPUs, in fact, the lacking of `sll` won't make troubles
to us.
It seems that most of MIPS64 CPUs can process it well as expected.

[Bug middle-end/113179] [11/12/13/14/15 Regression] MIPS: INS is used for long long, before SLL

[syq at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113179

YunQiang Su  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #5 from YunQiang Su  ---
Fixed in GCC 15. Should we backport it to the previous versions?

[Bug middle-end/113179] [11/12/13/14/15 Regression] MIPS: INS is used for long long, before SLL

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113179

--- Comment #4 from GCC Commits  ---
The master branch has been updated by YunQiang Su :

https://gcc.gnu.org/g:7d5d2b879ae7636ca118fb4f3a08b22705cdeacb

commit r15-171-g7d5d2b879ae7636ca118fb4f3a08b22705cdeacb
Author: YunQiang Su 
Date:   Mon Apr 29 00:33:44 2024 +0800

expmed: TRUNCATE value1 if needed in store_bit_field_using_insv

PR target/113179.

In `store_bit_field_using_insv`, we just use SUBREG if value_mode
>= op_mode, while in some ports, a sign_extend will be needed,
such as MIPS64:
  If either GPR rs or GPR rt does not contain sign-extended 32-bit
  values (bits 63..31 equal), then the result of the operation is
  UNPREDICTABLE.

The problem happens for the code like:
  struct xx {
int a:4;
int b:24;
int c:3;
int d:1;
  };

  void xx (struct xx *a, long long b) {
a->d = b;
  }

In the above code, the hard register contains `b`, may be note well
sign-extended.

gcc/
PR target/113179
* expmed.cc(store_bit_field_using_insv): TRUNCATE value1 if
needed.

gcc/testsuite
PR target/113179
* gcc.target/mips/pr113179.c: New tests.

[Bug middle-end/113179] [11/12/13/14/15 Regression] MIPS: INS is used for long long, before SLL

[syq at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113179

--- Comment #3 from YunQiang Su  ---
36088299955f95ab58a5758cba2f29b84c8fbfbc is the first bad commit
commit 36088299955f95ab58a5758cba2f29b84c8fbfbc 
Author: Richard Biener   
Date:   Wed Jun 29 07:17:57 2016 +  

match.pd ((T)(T2)x -> (T)x): Remove restriction on final precision not
matching mode precision.

2016-07-29  Richard Biener   

* match.pd ((T)(T2)x -> (T)x): Remove restriction on final  
precision not matching mode precision. 

From-SVN: r237838   

 gcc/ChangeLog |  5 +   
 gcc/match.pd  | 11 +++ 
 2 files changed, 8 insertions(+), 8 deletions(-)