[Bug middle-end/114733] [14] Miscompile with -march=rv64gcv -O3 on riscv

2024-04-16 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114733

--- Comment #4 from GCC Commits  ---
The master branch has been updated by Richard Biener :

https://gcc.gnu.org/g:45a41ace55d0ffb1097e374868242329788ec82a

commit r14-9992-g45a41ace55d0ffb1097e374868242329788ec82a
Author: Richard Biener 
Date:   Tue Apr 16 10:46:03 2024 +0200

tree-optimization/114733 - neg induction fails for 1 element vectors

The neg induction vectorization code isn't prepared to deal with
single element vectors.

PR tree-optimization/114733
* tree-vect-loop.cc (vectorizable_nonlinear_induction): Reject
neg induction vectorization of single element vectors.

* gcc.dg/vect/pr114733.c: New testcase.

[Bug middle-end/114733] [14] Miscompile with -march=rv64gcv -O3 on riscv

2024-04-16 Thread rguenth at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114733

--- Comment #3 from Richard Biener  ---
So the issue is that we do

  switch (induction_type)
{
case vect_step_op_neg:
  if (TREE_CODE (init_expr) != INTEGER_CST
  && TREE_CODE (init_expr) != REAL_CST)
{
  /* Check for backend support of NEGATE_EXPR and vec_perm.  */
  if (!directly_supported_p (NEGATE_EXPR, vectype))
return false;

  /* The encoding has 2 interleaved stepped patterns.  */
  vec_perm_builder sel (nunits, 2, 3);
  machine_mode mode = TYPE_MODE (vectype);
  sel.quick_grow (6);
  for (i = 0; i < 3; i++)
{
  sel[i * 2] = i;
  sel[i * 2 + 1] = i + nunits;
}

but this scheme doesn't work for a V1DImode vector type.

[Bug middle-end/114733] [14] Miscompile with -march=rv64gcv -O3 on riscv

2024-04-16 Thread rguenth at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114733

Richard Biener  changed:

   What|Removed |Added

 Status|UNCONFIRMED |ASSIGNED
 Ever confirmed|0   |1
   Assignee|unassigned at gcc dot gnu.org  |rguenth at gcc dot 
gnu.org

--- Comment #2 from Richard Biener  ---
   [local count: 9582068]:
  b_lsm.9_16 = b;
  _20 = -b_lsm.9_16;
  b = _20;
  __builtin_printf ("%ld\n", _20);
  return 0;

we unroll the inner loop and then vectorize with 8 byte vectors which
means exposing V1DImode vectors which I think runs into the very same
issue (VF is "even").

[Bug middle-end/114733] [14] Miscompile with -march=rv64gcv -O3 on riscv

2024-04-16 Thread rdapp at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114733

--- Comment #1 from Robin Dapp  ---
Confirmed, also shows up here.