[Bug rtl-optimization/57032] [4.9 Regression]: internal compiler error: Max. number of generated reload insns per insn is achieved (90)

2013-11-22 Thread rguenth at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57032

Richard Biener  changed:

   What|Removed |Added

   Priority|P3  |P4


[Bug rtl-optimization/57032] [4.9 Regression]: internal compiler error: Max. number of generated reload insns per insn is achieved (90)

2013-04-22 Thread ubizjak at gmail dot com


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57032



Uros Bizjak  changed:



   What|Removed |Added



 Status|RESOLVED|SUSPENDED

   Last reconfirmed||2013-04-22

 Resolution|FIXED   |

 Ever Confirmed|0   |1



--- Comment #3 from Uros Bizjak  2013-04-22 21:00:26 
UTC ---

Suspended, until LRA is reenabled on alpha.


[Bug rtl-optimization/57032] [4.9 Regression]: internal compiler error: Max. number of generated reload insns per insn is achieved (90)

2013-04-22 Thread ubizjak at gmail dot com


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57032



Uros Bizjak  changed:



   What|Removed |Added



 Status|UNCONFIRMED |RESOLVED

 Resolution||FIXED

   Target Milestone|--- |4.9.0



--- Comment #2 from Uros Bizjak  2013-04-22 17:22:17 
UTC ---

Fixed by revert:



Author: uros

Date: Mon Apr 22 16:58:30 2013

New Revision: 198145



URL: http://gcc.gnu.org/viewcvs?rev=198145&root=gcc&view=rev

Log:

PR target/57032

Revert:

2013-03-17  Uros Bizjak  



* config/alpha/alpha.c (TARGET_LRA_P): New define.





Modified:

trunk/gcc/ChangeLog

trunk/gcc/config/alpha/alpha.c


[Bug rtl-optimization/57032] [4.9 Regression]: internal compiler error: Max. number of generated reload insns per insn is achieved (90)

2013-04-22 Thread ubizjak at gmail dot com


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57032



--- Comment #1 from Uros Bizjak  2013-04-22 15:20:38 
UTC ---

For some reason, LRA does not fix-up (insn 12):



(insn 12 11 13 2 (set (reg/v:DI 72 [ hi ])

(unsigned_fix:DI (reg:DF 83 [ D.5360 ])))

../../../gcc-svn/trunk/libgcc/libgcc2.c:1334 138 {*fix_truncdfdi2}

 (expr_list:REG_DEAD (reg:DF 83 [ D.5360 ])

(nil)))



with a spill to memory via *movdi combo (as is the case with reload):



cvttq/c $f10,$f10 # 12*fix_truncdfdi2[length = 4]

stt $f10,0($30) # 60*movdi/12[length = 4]

ldq $1,0($30) # 61*movdi/8[length = 4]



But ignores the above alternative and goes with:



   12: r108:DI=uns_fix(r83:DF)

  REG_DEAD r83:DF

Inserting insn reload after:

   58: r72:DI=r108:DI



  Creating newreg=109, assigning class NO_REGS to secondary r109

   58: r109:DI=r108:DI

Inserting the sec. move after:

   59: r72:DI=r109:DI



 Choosing alt 7 in insn 59:  (0) r  (1) m

 Choosing alt 0 in insn 13:  (2) rJ

 Choosing alt 0 in insn 14:  (0) =f  (1) f

  Creating newreg=110 from oldreg=72, assigning class FLOAT_REGS to r110

   14: r87:DF=float(r110:DI)

Inserting insn reload before:

   60: r110:DI=r72:DI



  Creating newreg=111, assigning class NO_REGS to secondary r111

   60: r111:DI=r72:DI

Inserting the sec. move after:

   61: r110:DI=r111:DI



 Choosing alt 9 in insn 61:  (0) *f  (1) *fJ

  Creating newreg=112 from oldreg=111, assigning class FLOAT_REGS to r112

   61: r110:DI=r112:DI

Inserting insn reload before:

   62: r112:DI=r111:DI



 Choosing alt 9 in insn 62:  (0) *f  (1) *fJ

  Creating newreg=113 from oldreg=111, assigning class FLOAT_REGS to r113

   62: r112:DI=r113:DI

Inserting insn reload before:

   63: r113:DI=r111:DI



...



This creates a reload loop.