[Bug rtl-optimization/84842] [7/8/9 Regression] ICE in verify_target_availability, at sel-sched.c:1569
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84842 Andrey Belevantsev changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigned at gcc dot gnu.org |abel at gcc dot gnu.org --- Comment #17 from Andrey Belevantsev --- Created attachment 45991 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=45991=edit tentative patch This is a rather complex situation. The assert checks that we have correctly calculated the availability bit, which tells us that the original destination insn register is free to use for the code motion. In our case we have merged several insns into one expression, and the resulting bit came from the variant when it was really unavailable; however, during looking for the original insn in the flow graph, we have been looking for really another variant, thus we didn't get to the place with the first variant and initially unavailable stuff. It can be fixed with the rather crude attached patch that somewhat relaxes the assert. While doing this, we need to mark the above situation has actually occurred, but we don't know which of the move_op or find_best_regs we're doing there -- Alexander, maybe you could come up with something better.
[Bug rtl-optimization/84842] [7/8/9 Regression] ICE in verify_target_availability, at sel-sched.c:1569
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84842 --- Comment #16 from Arseny Solokha --- (In reply to Arseny Solokha from comment #15) > Finally. As of r267906 it doesn't ICE for me anymore, but gcc/testsuite/gfortran.dg/dependency_36.f90 does: % powerpc-e300c3-linux-gnu-gfortran-9.0.0-alpha20190113 -m32 -mcpu=power8 -O2 -fselective-scheduling2 -c gcc/testsuite/gfortran.dg/dependency_36.f90
[Bug rtl-optimization/84842] [7/8/9 Regression] ICE in verify_target_availability, at sel-sched.c:1569
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84842 Richard Biener changed: What|Removed |Added Target Milestone|7.4 |7.5
[Bug rtl-optimization/84842] [7/8/9 Regression] ICE in verify_target_availability, at sel-sched.c:1569
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84842
--- Comment #15 from Arseny Solokha ---
(In reply to Alexander Monakov from comment #14)
> Arseny, in the meantime if by chance you have another x86_64 variant of this
> failure that doesn't require -funroll-all-loops, please post it as well.
Finally.
float
z6 (float gg, int rv)
{
long int v9;
while (-v9 / (!rv + 10) < (long unsigned int) ((gg + 1) / gg))
gg = (int) ((long unsigned int) (rv * 1.1f));
return gg;
}
% x86_64-pc-linux-gnu-gcc-9.0.0-alpha20180701 -O2 -ffast-math -fschedule-insns
-fsel-sched-pipelining -fselective-scheduling -fsplit-paths -fno-tree-loop-im
-c scfabdxr.c
(as of 262290).
[Bug rtl-optimization/84842] [7/8/9 Regression] ICE in verify_target_availability, at sel-sched.c:1569
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84842 --- Comment #14 from Alexander Monakov --- Thanks. I think the root cause on this x86_64 testcase is different. Arseny, in the meantime if by chance you have another x86_64 variant of this failure that doesn't require -funroll-all-loops, please post it as well.
[Bug rtl-optimization/84842] [7/8/9 Regression] ICE in verify_target_availability, at sel-sched.c:1569
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84842
Arseny Solokha changed:
What|Removed |Added
Target|powerpc-*-linux-gnu*|powerpc-*-linux-gnu*,
||x86_64-unknown-linux-gnu
--- Comment #13 from Arseny Solokha ---
This one fails for x86_64:
int zq;
void
x3 (int th, int gk)
{
while (th < 1)
{
int w6;
long int s9;
if (th == 0)
{
gk = zq;
w6 = gk;
}
else
w6 = 0;
s9 = !!gk ? th : 1;
gk *= w6 + s9;
++th;
}
}
% x86_64-unknown-linux-gnu-gcc-8.0.0-alpha20180427 -O1 -fschedule-insns
-fsel-sched-pipelining -fselective-scheduling -funroll-all-loops -fno-tree-ch
-fno-tree-loop-im -fno-web -c etlogwpw.c
during RTL pass: sched1
etlogwpw.c: In function 'x3':
etlogwpw.c:23:1: internal compiler error: in verify_target_availability, at
sel-sched.c:1570
}
^
0x64e645 verify_target_availability
/var/tmp/portage/sys-devel/gcc-8.0.0_alpha20180427/work/gcc-8-20180427/gcc/sel-sched.c:1567
0x64e645 find_best_reg_for_expr
/var/tmp/portage/sys-devel/gcc-8.0.0_alpha20180427/work/gcc-8-20180427/gcc/sel-sched.c:1680
0x64e645 fill_vec_av_set
/var/tmp/portage/sys-devel/gcc-8.0.0_alpha20180427/work/gcc-8-20180427/gcc/sel-sched.c:3798
0xc6fbcf fill_ready_list
/var/tmp/portage/sys-devel/gcc-8.0.0_alpha20180427/work/gcc-8-20180427/gcc/sel-sched.c:4028
0xc6fbcf find_best_expr
/var/tmp/portage/sys-devel/gcc-8.0.0_alpha20180427/work/gcc-8-20180427/gcc/sel-sched.c:4388
0xc6fbcf fill_insns
/var/tmp/portage/sys-devel/gcc-8.0.0_alpha20180427/work/gcc-8-20180427/gcc/sel-sched.c:5549
0xc6fbcf schedule_on_fences
/var/tmp/portage/sys-devel/gcc-8.0.0_alpha20180427/work/gcc-8-20180427/gcc/sel-sched.c:7366
0xc6fbcf sel_sched_region_2
/var/tmp/portage/sys-devel/gcc-8.0.0_alpha20180427/work/gcc-8-20180427/gcc/sel-sched.c:7504
0xc71f78 sel_sched_region_1
/var/tmp/portage/sys-devel/gcc-8.0.0_alpha20180427/work/gcc-8-20180427/gcc/sel-sched.c:7546
0xc727fe sel_sched_region(int)
/var/tmp/portage/sys-devel/gcc-8.0.0_alpha20180427/work/gcc-8-20180427/gcc/sel-sched.c:7647
0xc73711 run_selective_scheduling()
/var/tmp/portage/sys-devel/gcc-8.0.0_alpha20180427/work/gcc-8-20180427/gcc/sel-sched.c:7733
0xc52e2d rest_of_handle_sched
/var/tmp/portage/sys-devel/gcc-8.0.0_alpha20180427/work/gcc-8-20180427/gcc/sched-rgn.c:3718
0xc52e2d execute
/var/tmp/portage/sys-devel/gcc-8.0.0_alpha20180427/work/gcc-8-20180427/gcc/sched-rgn.c:3828
(as of r259733).
