[Bug rtl-optimization/97684] [11 Regression] ICE in reg_preferred_class, at reginfo.c:789 by r11-4577
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97684 Torbjörn SVENSSON changed: What|Removed |Added CC||torbjorn.svensson at foss dot st.c ||om --- Comment #9 from Torbjörn SVENSSON --- In https://gcc.gnu.org/g:081c96621da658760b4a67c07530805f770fa22c, a regression was introduced that causes GCC to segfault randomly. The regression is due to that resize_reg_info() is no longer called after remove_scratches() and remove_scratches() can increase the number of registers. Due to the increase of number of registers in remove_scratches(), the resulting out-of-bounds usage of the reg_renumber global array will have unpredictable result. I sent a proposal patch to resolve this issue that can be reviewed here: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604295.html >From what I can tell, this regression exist in gcc-11, gcc-12 and master.
[Bug rtl-optimization/97684] [11 Regression] ICE in reg_preferred_class, at reginfo.c:789 by r11-4577
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97684 Jakub Jelinek changed: What|Removed |Added Status|NEW |RESOLVED CC||jakub at gcc dot gnu.org Resolution|--- |FIXED --- Comment #8 from Jakub Jelinek --- Assuming fixed.
[Bug rtl-optimization/97684] [11 Regression] ICE in reg_preferred_class, at reginfo.c:789 by r11-4577
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97684 seurer at gcc dot gnu.org changed: What|Removed |Added CC||seurer at gcc dot gnu.org --- Comment #7 from seurer at gcc dot gnu.org --- The two bits of code shown seem to compile fine now on powerpc. Is this done then?
[Bug rtl-optimization/97684] [11 Regression] ICE in reg_preferred_class, at reginfo.c:789 by r11-4577
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97684 --- Comment #6 from CVS Commits --- The master branch has been updated by Vladimir Makarov : https://gcc.gnu.org/g:081c96621da658760b4a67c07530805f770fa22c commit r11-6943-g081c96621da658760b4a67c07530805f770fa22c Author: Vladimir N. Makarov Date: Wed Jan 27 14:53:28 2021 -0500 [PR97684] IRA: Recalculate pseudo classes if we added new pseduos since last calculation before updating equiv regs update_equiv_regs can use reg classes of pseudos and they are set up in register pressure sensitive scheduling and loop invariant motion and in live range shrinking. This info can become obsolete if we add new pseudos since the last set up. Recalculate it again if the new pseudos were added. gcc/ChangeLog: PR rtl-optimization/97684 * ira.c (ira): Call ira_set_pseudo_classes before update_equiv_regs when it is necessary. gcc/testsuite/ChangeLog: PR rtl-optimization/97684 * gcc.target/i386/pr97684.c: New.
[Bug rtl-optimization/97684] [11 Regression] ICE in reg_preferred_class, at reginfo.c:789 by r11-4577
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97684 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org --- Comment #5 from Vladimir Makarov --- I've reproduced x86-64 case and started to work on it. I think the patch will be ready soon.
[Bug rtl-optimization/97684] [11 Regression] ICE in reg_preferred_class, at reginfo.c:789 by r11-4577
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97684 H.J. Lu changed: What|Removed |Added Summary|[11 Regression] ICE in |[11 Regression] ICE in |reg_preferred_class, at |reg_preferred_class, at |reginfo.c:789 |reginfo.c:789 by r11-4577 CC||vmakarov at redhat dot com --- Comment #4 from H.J. Lu --- It is caused by commit 44fbc9c6e02ca5b8f98f25b514ed7588e7ba733d Author: Vladimir N. Makarov Date: Fri Oct 30 15:05:22 2020 -0400 Take insn scratch RA requirements into account in IRA.
[Bug rtl-optimization/97684] [11 Regression] ICE in reg_preferred_class, at reginfo.c:789
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97684 Richard Biener changed: What|Removed |Added Priority|P3 |P1 --- Comment #3 from Richard Biener --- Guessing GCC 10.x works, but I see no bisection.
[Bug rtl-optimization/97684] [11 Regression] ICE in reg_preferred_class, at reginfo.c:789
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97684
Uroš Bizjak changed:
What|Removed |Added
Component|target |rtl-optimization
Ever confirmed|0 |1
Last reconfirmed||2020-12-27
Status|UNCONFIRMED |NEW
--- Comment #2 from Uroš Bizjak ---
Confirmed as rtl-optimization PR.
Backtrace:
#2 0x006ac7a0 in reg_preferred_class (regno=regno@entry=170) at
../../git/gcc/gcc/reginfo.c:794
#3 0x00bebf37 in update_equiv_regs () at ../../git/gcc/gcc/ira.c:3521
#4 0x00bf23fb in ira (f=) at
../../git/gcc/gcc/ira.c:5554
where in reg_preferred_class, an assert is triggered:
789 reg_preferred_class (int regno)
790 {
791 if (reg_pref == 0)
792 return GENERAL_REGS;
793
794 gcc_assert (regno < reg_info_size);
795 return (enum reg_class) reg_pref[regno].prefclass;
796 }
(gdb) p regno
$4 = 170
(gdb) p reg_info_size
$5 = 167
where regno is outside reg_info_size.
