[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106 --- Comment #7 from CVS Commits --- The releases/gcc-11 branch has been updated by Richard Biener : https://gcc.gnu.org/g:5155015ce57dc133e006f87fdf0237a5f259bebd commit r11-9786-g5155015ce57dc133e006f87fdf0237a5f259bebd Author: Bernd Edlinger Date: Wed Apr 21 14:13:04 2021 +0200 Fix target/100106 ICE in gen_movdi As the test case shows, the outer mode may have a higher alignment requirement than the inner mode here. 2021-04-27 Bernd Edlinger PR target/100106 * simplify-rtx.c (simplify_context::simplify_subreg): Check the memory alignment for the outer mode. * gcc.c-torture/compile/pr100106.c: New testcase. (cherry picked from commit c33db31d9ad96f6414460315c12b4b505fad5dd7)
[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106 --- Comment #6 from Richard Biener --- What about backporting this fix?
[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106 Bernd Edlinger changed: What|Removed |Added Summary|[10/11/12 Regression] ICE |[10/11 Regression] ICE in |in gen_movdi, at|gen_movdi, at |config/arm/arm.md:6187 |config/arm/arm.md:6187 |since r10-2840-g70cdb21e|since r10-2840-g70cdb21e Status|NEW |ASSIGNED --- Comment #5 from Bernd Edlinger --- fixed on trunk
[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106 --- Comment #3 from Bernd Edlinger --- Yes, indeed something like the following seems to fix the issue: diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c index d13c390..56271e9 100644 --- a/gcc/simplify-rtx.c +++ b/gcc/simplify-rtx.c @@ -7217,6 +7217,7 @@ simplify_context::simplify_subreg (machine_mode outermode have instruction to move the whole thing. */ && (! MEM_VOLATILE_P (op) || ! have_insn_for (SET, innermode)) + && (STRICT_ALIGNMENT && GET_MODE_ALIGNMENT (outermode) < MEM_ALIGN (op)) && known_le (outersize, innersize)) return adjust_address_nv (op, outermode, byte);
[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106 Richard Biener changed: What|Removed |Added CC||rsandifo at gcc dot gnu.org --- Comment #2 from Richard Biener --- simplify_subreg has /* If we have a SUBREG of a register that we are replacing and we are replacing it with a MEM, make a new MEM and try replacing the SUBREG with it. Don't do this if the MEM has a mode-dependent address or if we would be widening it. */ if (MEM_P (op) && ! mode_dependent_address_p (XEXP (op, 0), MEM_ADDR_SPACE (op)) /* Allow splitting of volatile memory references in case we don't have instruction to move the whole thing. */ && (! MEM_VOLATILE_P (op) || ! have_insn_for (SET, innermode)) && known_le (outersize, innersize)) return adjust_address_nv (op, outermode, byte); at least on STRICT_ALIGN targets I miss an alignment check? The code is quite old, of course.
[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106
Richard Biener changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Ever confirmed|0 |1
Priority|P3 |P2
Last reconfirmed||2021-04-16
--- Comment #1 from Richard Biener ---
Confirmed.
#1 0x01d9f1c5 in gen_movdi (operand0=0x763ae390,
operand1=0x763ae480)
at /home/rguenther/src/trunk/gcc/config/arm/arm.md:6187
6187 gcc_checking_assert (aligned_operand (operands[1], DImode));
(gdb) p debug_rtx (operands[1])
(mem/u/c:DI (reg/f:SI 114) [0 S8 A32])
I think the bug is that
/* Use the subreg machinery either to narrow OP0 to the required
words or to cope with mode punning between equal-sized modes.
In the latter case, use subreg on the rhs side, not lhs. */
rtx sub;
HOST_WIDE_INT regnum;
poly_uint64 regsize = REGMODE_NATURAL_SIZE (GET_MODE (op0));
if (known_eq (bitnum, 0U)
&& known_eq (bitsize, GET_MODE_BITSIZE (GET_MODE (op0
{
sub = simplify_gen_subreg (GET_MODE (op0), value, fieldmode, 0);
if (sub)
{
if (reverse)
sub = flip_storage_order (GET_MODE (op0), sub);
here simplify_gen_subreg simplifies (subreg:DI ((mem/u/c:SC (reg/f:SI 114) [0
S8 A32])) to (mem/u/c:DI (reg/f:SI 114) [0 S8 A32]) but SCmode has
different alignment requirement than DImode.
[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106 Alex Coplan changed: What|Removed |Added Target||arm Keywords||ice-on-valid-code Known to fail||10.2.1, 11.0 Target Milestone|--- |10.4 Known to work||9.2.1
