https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111857
--- Comment #2 from CVS Commits ---
The master branch has been updated by Pan Li :
https://gcc.gnu.org/g:66c26e5cfdf65ae024fcb658629dc5a9a10f3f85
commit r14-4812-g66c26e5cfdf65ae024fcb658629dc5a9a10f3f85
Author: Pan Li
Date: Fri Oct 20 16:20:45 2023 +0800
RISC-V: Support partial VLS mode when preference fixed-vlmax [PR111857]
Given we have code like below:
typedef char vnx16i __attribute__ ((vector_size (16)));
vnx16i __attribute__ ((noinline, noclone))
test (vnx16i x, vnx16i y)
{
return __builtin_shufflevector (x, y, 11, 12, 13, 14, 11, 12, 13, 14,
11, 12, 13, 14, 11, 12, 13, 14);
}
It can perform the auto vectorization when
-march=rv64gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax
but cannot when
-march=rv64gcv_zvl2048b --param=riscv-autovec-preference=fixed-vlmax
The reason comes from the miniaml machine mode of QI is RVVMF8QI, which
is 1024 / 8 = 128 bits, aka the size of VNx16QI. When we set zvl2048b,
the bit size of RVVMFQI is 2048 / 8 = 256, which is not matching the
bit size of VNx16QI (128 bits).
Thus, this patch would like to enable the VLS mode for such case, aka
VNx16QI vls mode for zvl2048b.
Before this patch:
test:
srlia4,a1,40
andia4,a4,0xff
srlia3,a1,32
srlia5,a1,48
sllia0,a4,8
andia3,a3,0xff
andia5,a5,0xff
sllia2,a5,16
or a0,a3,a0
srlia1,a1,56
or a0,a0,a2
sllia2,a1,24
sllia3,a3,32
or a0,a0,a2
sllia4,a4,40
or a0,a0,a3
sllia5,a5,48
or a0,a0,a4
or a0,a0,a5
sllia1,a1,56
or a0,a0,a1
mv a1,a0
ret
After this patch:
test:
vsetivlizero,16,e8,mf8,ta,ma
vle8.v v2,0(a1)
vsetivlizero,4,e32,mf2,ta,ma
vrgather.vi v1,v2,3
vsetivlizero,16,e8,mf8,ta,ma
vse8.v v1,0(a0)
ret
PR target/111857
gcc/ChangeLog:
* config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): Remove.
* config/riscv/riscv-protos.h (vls_mode_valid_p): New func decl.
* config/riscv/riscv-v.cc (autovectorize_vector_modes): Replace
macro reference to func.
(vls_mode_valid_p): New func impl for vls mode valid or not.
* config/riscv/riscv-vector-switch.def (VLS_ENTRY): Replace
macro reference to func.
* config/riscv/vector-iterators.md: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Adjust checker.
* gcc.target/riscv/rvv/autovec/vls/def.h: Add help define.
* gcc.target/riscv/rvv/autovec/vls-vlmax/pr111857-0.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/pr111857-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/pr111857-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/pr111857-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/pr111857-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/pr111857-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/pr111857-6.c: New test.
Signed-off-by: Pan Li
