[Bug target/112433] RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

2023-11-13 Thread kito at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433

--- Comment #4 from Kito Cheng  ---
Yeah, 3 major goal in LLVM is improving scheduling, partial spilling and
re-materialization, but none of those points are issue for RISC-V GCC :P

Ref:
https://docs.google.com/presentation/d/1BOYNYKe1T-u3Q5HXRrcObLUkdKSPASmnuQTkALvJXto/edit

[Bug target/112433] RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

2023-11-13 Thread juzhe.zhong at rivai dot ai via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433

--- Comment #3 from JuzheZhong  ---
Just talked with Lehua offline.

We don't think splitting RA can improve performance a lot.
We should consider it more seriously instead of support this blindly.
Since splitting RA will increase compile-time significantly with running RA
twice (RA consume most of the compile-time).

[Bug target/112433] RISC-V GCC-15 feature: Split register allocation into RVV and non-RVV, and make vsetvl PASS run between them

2023-11-12 Thread pinskia at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112433

Andrew Pinski  changed:

   What|Removed |Added

   Severity|normal  |enhancement