https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114916
Bug ID: 114916 Summary: [14/15] RISC-V rv64gcv_zvl256b: miscompile at -O3 with -mrvv-vector-bits=zvl -fwhole-program Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: patrick at rivosinc dot com Target Milestone: --- Testcase: long long c; int d = 1; char f[18]; short g[18]; unsigned long long h[18][18][18]; char a[324]; long b[18]; short *i = g; unsigned long long (*j)[18][18] = h; void k(long long *l, int p) { *l ^= p; } int main() { for (long m = 0; m < 18; ++m) f[m] = 3; for (int m = 0; m < 18; m += d ) for (short n = 0; n < 18; n += 3) { a[m * 8 + n] = j[m][m][0] ? i[n] : 0; b[n] = f[n] ? -i[m] : 0; } for (long n = 0; n < 8; ++n) k(&c, a[n]); __builtin_printf("%ld\n", b[15]); } Commands: > /scratch/tc-testing/tc-apr-29/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc > -march=rv64gcv_zvl256b -flto -fno-strict-aliasing -O3 -mrvv-vector-bits=zvl > red.c -o red.out > QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true > /scratch/tc-testing/tc-apr-29/build-rv64gcv/bin/qemu-riscv64 red.out -771 > /scratch/tc-testing/tc-apr-29/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc > red.c -fno-strict-aliasing -o red.out > QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true > /scratch/tc-testing/tc-apr-29/build-rv64gcv/bin/qemu-riscv64 red.out 0 i and g are never written to.