[Bug target/115336] [15] rv64gcv_zvl256b miscompile at -O3

[rdapp at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115336

--- Comment #3 from Robin Dapp  ---
Follow-up on this one:  My workaround of emitting a vmv.v.i v[0-9],0 before any
(potentially) offending masked load is not going to work universally.
That's because on several instances we make use of the fact that a load has a
built-in EEW and will not load what the last vset specified (SEW) but rather
the ratio the built-in EEW specifies.

So for a case like

vsetivli zero,zero,e32,m8,tu,mu
vle8.v  v4,0(a0),v0.t

we would insert a vmv.v.i v4,0

vsetivli zero,zero,e32,m8,tu,mu
vmv.v.i v4,0
vle8.v  v4,0(a0),v0.t

but vmv.v.i observes the SEW/LMUL and thus doesn't touch the same set of
registers vle would.  vmv is indeed not even allowed to use register v4
directly due to LMUL.

I'm still experimenting with only adding a vmv to specific patterns but all
that can only ever be a stopgap solution and we definitely need middle-end
rework to properly fix it.  Actually we're lucky this wasn't triggered before. 

My other idea of adjusting the respective expanders is also not going to work
because we implicitly assume that a masked load "overwrites" its entire
destination and therefore optimizing away anything that writes the destination
before.  That's a bit of a semantics mismatch for RVV unfortunately.

I'm going to start with some middle-end work on this.  Hopefully it's not as
bad as I imagine it is.

[Bug target/115336] [15] rv64gcv_zvl256b miscompile at -O3

[rdapp at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115336

--- Comment #2 from Robin Dapp  ---
It looks to me as if we're expecting the result of a gather_load to be zero
when it's masked out (semantics of mask_gather_load) but for
mask_len_gather_load we actually describe it as undefined.  Here the mask is
all zeros and we OR the result with 1.  Because of stale values this doesn't
result in 1 but rather garbage.  Maybe our mask representation also plays a
part but I'm pretty sure zeroing the result before the gather would help.

[Bug target/115336] [15] rv64gcv_zvl256b miscompile at -O3

[patrick at rivosinc dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115336

Patrick O'Neill  changed:

   What|Removed |Added

   Keywords||wrong-code
 Target||riscv*-*-*
 CC||ewlu at rivosinc dot com,
   ||juzhe.zhong at rivai dot ai,
   ||kito.cheng at gmail dot com,
   ||rdapp at gcc dot gnu.org,
   ||vineetg at gcc dot gnu.org

--- Comment #1 from Patrick O'Neill  ---
Misread the assignment statement. All values should be 0 or 1.