[Bug target/43350] sparcv9 mode does not seem to produce LDX/STX insns
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43350 Jan Engelhardt jengelh at inai dot de changed: What|Removed |Added CC||hjl at gcc dot gnu.org --- Comment #2 from Jan Engelhardt jengelh at inai dot de 2012-11-06 16:19:09 UTC --- Thanks for the description. It seems that what you say also affects the x32 mode (-mx32) for x86_64, am I correct in that observation?
[Bug target/43350] sparcv9 mode does not seem to produce LDX/STX insns
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43350 --- Comment #3 from davem at gcc dot gnu.org 2012-11-06 18:00:30 UTC --- Unfortunately I'm not familiar enough with the i386 backend to say whether the situation is identical there for x32 code generation. But if it were the case, it would not surprise me.
[Bug target/43350] sparcv9 mode does not seem to produce LDX/STX insns
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43350 --- Comment #4 from H.J. Lu hjl.tools at gmail dot com 2012-11-06 22:15:02 UTC --- There is no x32 mode in hardware. Since x32 runs in 64-bit mode and only OS limits x32 address space to 32-bit, x32 process has full access to 64-bit insns, just like 64-bit process.
[Bug target/43350] sparcv9 mode does not seem to produce LDX/STX insns
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43350 --- Comment #5 from Jan Engelhardt jengelh at inai dot de 2012-11-07 00:00:01 UTC --- Dave, what do you think about a new mode for SPARC similar to -mx32, in other words, -m64+ILP32?
[Bug target/43350] sparcv9 mode does not seem to produce LDX/STX insns
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43350 --- Comment #6 from davem at gcc dot gnu.org 2012-11-07 05:44:52 UTC --- That's basically what -m32 -mcpu=v9 is Jan. The compiler just isn't taking advantage of it as well as it can due to how the sparc backend is designed. We have access to 16 64-bit registers at all times. Please, drop this discussion, when I get a large block of time I'll work on improving the sparc backend in this area. This discussion is just consuming my time and making it take longer for me to get to that task. Thanks.
[Bug target/43350] sparcv9 mode does not seem to produce LDX/STX insns
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43350 davem at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |SUSPENDED Last reconfirmed||2012-11-06 Ever Confirmed|0 |1 --- Comment #1 from davem at gcc dot gnu.org 2012-11-06 04:23:51 UTC --- The problem is that the compiler is very constrained about how it can or cannot use 64-bit operations in 32-bit v9 mode. When we do use 64-bit instructions, we do so in a very hackish way in 32-bit mode. We first allocate a safe 64-bit register (the OS only guarentees that %o0-%o7 and %g1-%g7 integer registers will have their full 64-bits saved if a trap or context switch occurs) and then we construct the 64-bit value from the 2 32-bit source operand pieces of each 64-bit input. Then we decompose the 64-bit safe register back into the 32-bit components of the output. We have some tricks and a very simplistic data flow analyzer that allows avoiding some aspects of the above work. This is suboptimal, but what it means is that by the time we do moves, we have the 64-bit values in 32-bit component registers, so stx/ldx isn't really an option. The basic issue is that it's an enormous task exposing to the compiler that we really can do full 64-bit operations in these registers. That is a huge amount of delicate work, and therefore this is really a feature request rather than a bug report, so I'm closing this.
