[Bug target/45637] Suspicious code for bit fields
--- Comment #1 from pinskia at gcc dot gnu dot org 2010-09-10 15:30 --- 1. index is constant or variable, and Yes that is correct. 2. the 'bar' field type. The alignment of the access is different in those cases. In any case byte accesses should be used. Why, word access is just as fast (if not faster) than a byte access on PPC. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45637
[Bug target/45637] Suspicious code for bit fields
--- Comment #2 from sebastian dot huber at embedded-brains dot de 2010-09-10 15:43 --- (In reply to comment #1) 1. index is constant or variable, and Yes that is correct. 2. the 'bar' field type. The alignment of the access is different in those cases. Sorry, the test case was not good. If you expand foo [1] to foo [4] you still have this behavior. In any case byte accesses should be used. Why, word access is just as fast (if not faster) than a byte access on PPC. Yes, but we have 'volatile struct type1 *varN;'. For volatile fields we should use accesses of the appropriate width. The background is that a major hardware manufacturer provided structure definitions like the above test case for register definitions. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45637
[Bug target/45637] Suspicious code for bit fields
--- Comment #3 from pinskia at gcc dot gnu dot org 2010-09-10 15:46 --- For volatile fields we should use accesses of the appropriate width. The PowerPC ABI has specific rules for accessing volatile bitfields and IIRC it says they should be doing the largest available (up to the register size) size. This is different from the ARM ABI which says the opposite. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45637
[Bug target/45637] Suspicious code for bit fields
--- Comment #4 from sebastian dot huber at embedded-brains dot de 2010-09-10 15:59 --- (In reply to comment #3) For volatile fields we should use accesses of the appropriate width. The PowerPC ABI has specific rules for accessing volatile bitfields and IIRC it says they should be doing the largest available (up to the register size) size. This is different from the ARM ABI which says the opposite. Thank you very much for your comments. I will investigate the PowerPC ABI issue and contact the manufacturer. Ironically they produced the ABI and these register definitions. -- sebastian dot huber at embedded-brains dot de changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution||INVALID http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45637
