[Bug target/47764] The constant load instruction should be hoisted out of loop

2011-08-10 Thread ramana at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47764

Ramana Radhakrishnan ramana at gcc dot gnu.org changed:

   What|Removed |Added

 CC||ramana at gcc dot gnu.org

--- Comment #4 from Ramana Radhakrishnan ramana at gcc dot gnu.org 2011-08-10 
22:17:23 UTC ---
(In reply to comment #3)
  Any ideas of how this improvement could be implemented, Carrot?
 
 The root cause of this problem is that arm/thumb store instruction can't
 directly store a immediate number to memory, but gcc doesn't realize this 
 early
 enough. In most part of the rtl phase, the following form is kept.
 
   (insn 41 38 42 3 (set (mem:HI (plus:SI (reg/f:SI 169)
   (const_int 60 [0x3c])) [2 MEM[(struct deflate_state 
 *)D.2085 
   _3 + 60B]+0 S2 A16])
   (const_int 0 [0])) src/trees.c:45 696 {*thumb2_movhi_insn}
(expr_list:REG_DEAD (reg/f:SI 169)
   (nil)))
 
 Until register allocation it finds the restriction of the store instruction 
 and
 split it into two instructions, load 0 into register and store register to
 memory. But it's too late to do a loop optimization.

Eh, how is splitting this early going to help with hoisting this out of a loop
? 

Ramana


[Bug target/47764] The constant load instruction should be hoisted out of loop

2011-02-20 Thread carrot at google dot com
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47764

--- Comment #3 from Carrot carrot at google dot com 2011-02-21 03:15:45 UTC 
---
 Any ideas of how this improvement could be implemented, Carrot?

The root cause of this problem is that arm/thumb store instruction can't
directly store a immediate number to memory, but gcc doesn't realize this early
enough. In most part of the rtl phase, the following form is kept.

  (insn 41 38 42 3 (set (mem:HI (plus:SI (reg/f:SI 169)
  (const_int 60 [0x3c])) [2 MEM[(struct deflate_state *)D.2085 
  _3 + 60B]+0 S2 A16])
  (const_int 0 [0])) src/trees.c:45 696 {*thumb2_movhi_insn}
   (expr_list:REG_DEAD (reg/f:SI 169)
  (nil)))

Until register allocation it finds the restriction of the store instruction and
split it into two instructions, load 0 into register and store register to
memory. But it's too late to do a loop optimization.

One possible method is to split this insn earlier than loop optimization (maybe
directly in expand pass), and let loop and cse optimizations do the rest. It
may increase register pressure in part of the program, we should rematerialize
it in such cases.


[Bug target/47764] The constant load instruction should be hoisted out of loop

2011-02-18 Thread pinskia at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47764

--- Comment #2 from Andrew Pinski pinskia at gcc dot gnu.org 2011-02-19 
03:23:51 UTC ---
This is most likely a cost issue.


[Bug target/47764] The constant load instruction should be hoisted out of loop

2011-02-18 Thread ibolton at gcc dot gnu.org
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47764

Ian Bolton ibolton at gcc dot gnu.org changed:

   What|Removed |Added

   Keywords||missed-optimization
 Status|UNCONFIRMED |NEW
   Last reconfirmed||2011.02.18 11:36:27
 CC||ibolton at gcc dot gnu.org
 Ever Confirmed|0   |1
  Known to fail||4.6.0

--- Comment #1 from Ian Bolton ibolton at gcc dot gnu.org 2011-02-18 11:36:27 
UTC ---
I have confirmed this for r170052 of trunk.

Any ideas of how this improvement could be implemented, Carrot?