[Bug target/52419] Wrong expansion of misaligned vector store
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52419 Martin Jambor jamborm at gcc dot gnu.org changed: What|Removed |Added Status|RESOLVED|REOPENED Last reconfirmed||2012-02-29 Resolution|DUPLICATE | Ever Confirmed|0 |1 --- Comment #2 from Martin Jambor jamborm at gcc dot gnu.org 2012-02-29 13:19:56 UTC --- Well, it turns out that even with Richi's patch the exact same testcase fails at -O1 and higher. Thus, reopening.
[Bug target/52419] Wrong expansion of misaligned vector store
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52419 Richard Guenther rguenth at gcc dot gnu.org changed: What|Removed |Added Status|REOPENED|NEW --- Comment #3 from Richard Guenther rguenth at gcc dot gnu.org 2012-02-29 13:28:00 UTC --- Confirmed. foo: .LFB0: .cfi_startproc pxor%xmm1, %xmm1 movhps .LC0(%rip), %xmm1 movdqu %xmm1, (%rdi) ret it looks like (insn 6 5 7 (set (reg:DI 61) (const_int 5 [0x5])) t.c:23 -1 (nil)) (insn 7 6 8 (set (reg:DI 62) (vec_select:DI (reg:V2DI 60) (parallel [ (const_int 0 [0]) ]))) t.c:23 -1 (nil)) (insn 8 7 9 (set (reg:V2DI 60) (vec_concat:V2DI (reg:DI 62) (reg:DI 61))) t.c:23 -1 (nil)) (insn 9 8 0 (set (mem:V16QI (reg/v/f:DI 59 [ p ]) [0 *p_1(D)+0 S16 A8]) (unspec:V16QI [ (subreg:V16QI (reg:V2DI 60) 0) ] UNSPEC_MOVU)) t.c:23 -1 (nil)) which of course does not work as ref:V2DI 60 is unsed uninitialized in insn 7.
[Bug target/52419] Wrong expansion of misaligned vector store
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52419
--- Comment #4 from Richard Guenther rguenth at gcc dot gnu.org 2012-02-29
13:46:01 UTC ---
We are not prepared to handle bitsize != GET_MODE_BITSIZE in expand_assignment
for the movmisalign case. The following fixes it
Index: gcc/expr.c
===
--- gcc/expr.c (revision 184656)
+++ gcc/expr.c (working copy)
@@ -4687,7 +4687,13 @@ expand_assignment (tree to, tree from, b
!= CODE_FOR_nothing))
{
misalignp = true;
- to_rtx = gen_reg_rtx (mode);
+ /* If we only partly store to the misaligned memory region
+perform a read-modify-write cycle. Otherwise use a scratch
+register for the 'read' part. */
+ if (bitsize != GET_MODE_BITSIZE (mode))
+ to_rtx = expand_normal (tem);
+ else
+ to_rtx = gen_reg_rtx (mode);
}
else
{
of course we then generate
foo:
.LFB0:
.cfi_startproc
movdqu (%rdi), %xmm0
movhps .LC0(%rip), %xmm0
movdqu %xmm0, (%rdi)
ret
which is rather sub-optimal. Not sure who would be supposed to fix that.
OTOH we could as well simply avoid going the movmisalign paths when
the word is not accessed in full. But that's harder because we'd somehow
have to circumvent the expand_normal case to fall into the movmisalign
trap.
[Bug target/52419] Wrong expansion of misaligned vector store
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52419 --- Comment #5 from Richard Guenther rguenth at gcc dot gnu.org 2012-02-29 13:52:05 UTC --- Failed to match this instruction: (set (reg:DI 62) (vec_select:DI (subreg:V2DI (unspec:V16QI [ (mem:V16QI (reg/v/f:DI 59 [ p ]) [0 *p_1(D)+0 S16 A8]) ] UNSPEC_MOVU) 0) (parallel [ (const_int 0 [0]) ]))) could at least be recognized.
[Bug target/52419] Wrong expansion of misaligned vector store
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52419 --- Comment #6 from Jakub Jelinek jakub at gcc dot gnu.org 2012-02-29 14:19:44 UTC --- Created attachment 26785 -- http://gcc.gnu.org/bugzilla/attachment.cgi?id=26785 alternative This patch avoids expand_expr on the MEM_REF's base twice, by moving the mem var computation earlier.
