http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53447
Bug #: 53447 Summary: missed optimization of 64bit ALU operation with small constant Classification: Unclassified Product: gcc Version: 4.8.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target AssignedTo: unassig...@gcc.gnu.org ReportedBy: car...@google.com Target: arm-unknown-linux-gnueabi Compile the following code with options -march=armv7-a -O2 -mthumb void t0p(long long *p) { *p += 1; } GCC 4.8 generates: t0p: ldrd r2, [r0] push {r4, r5} movs r4, #1 //A adds r2, r2, r4 //B mov r5, #0 //C adc r3, r3, r5 //D strd r2, [r0] pop {r4, r5} bx lr Instructions ABCD can be simplified as adds r2, r2, 1 adc r3, r3, 0 This sequence is smaller and faster than original code, it uses two less registers, so the push/pop instructions can also be removed. Both arm/thumb mode and Os/O2 generates similar code. This optimization can also be applied to other alu operations, such as sub/and/or/xor/cmp.