[Bug target/54457] [x32] Fail to combine 64bit index + constant

2012-09-24 Thread ubizjak at gmail dot com 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54457



Uros Bizjak  changed:



   What|Removed |Added



 Status|UNCONFIRMED |ASSIGNED

   Last reconfirmed||2012-09-24

 AssignedTo|unassigned at gcc dot   |ubizjak at gmail dot com

   |gnu.org |

 Ever Confirmed|0   |1



--- Comment #2 from Uros Bizjak  2012-09-24 22:48:37 
UTC ---

Created attachment 28261

  --> http://gcc.gnu.org/bugzilla/attachment.cgi?id=28261

Proposed patch



Patch that enhances combine_simplify_rtx to generate canonical binop sequences

that simplify_plus_minus can recognize and further optimize.



Bootstrapped and regression tested on x86_64-pc-linux-gnu.



Patched gcc generates expected code for the above testcase:



foo:

movzbl  array+1(%edi), %eax

ret

[Bug target/54457] [x32] Fail to combine 64bit index + constant

2012-09-24 Thread ubizjak at gmail dot com 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54457



--- Comment #1 from Uros Bizjak  2012-09-24 18:38:46 
UTC ---

(In reply to comment #0)



> combine fails on:

> 

> Trying 6 -> 8:

> Failed to match this instruction:

> (set (reg:QI 66)

> (mem/j:QI (plus:SI (subreg:SI (plus:DI (reg/v:DI 62 [ position ])

> (const_int 1 [0x1])) 0)

> (symbol_ref:SI ("array") [flags 0x40]   arra

> y>)) [0 array S1 A8]))

> 

> This should be a valid address.



In principle yes, but the RTX is not accepted in ix86_decompose_address since

we have two displacements here. Combine should simplify this RTX to:



(set (reg:QI 68)

(mem/j:QI (plus:SI (subreg:SI (reg/v:DI 62 [ position ]) 0)

(const:SI (plus:SI (symbol_ref:SI ("array") [flags 0x40]  )

(const_int 1 [0x1] [0 array S1 A8]))





as is the case with -m32 (but rejected in ix86_address_subreg_operand):



  /* Don't allow SUBREGs that span more than a word.  It can lead to spill

 failures when the register is one word out of a two word structure.  */

  if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)

return false;