[Bug target/67480] AVX512 bitwise logic operations pattern is incorrect

2015-10-06 Thread kyukhin at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67480

--- Comment #6 from Kirill Yukhin  ---
This bug is reproducible on gcc-5-branch

[Bug target/67480] AVX512 bitwise logic operations pattern is incorrect

2015-09-22 Thread kyukhin at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67480

--- Comment #4 from Kirill Yukhin  ---
Author: kyukhin
Date: Tue Sep 22 11:14:25 2015
New Revision: 228010

URL: https://gcc.gnu.org/viewcvs?rev=228010=gcc=rev
Log:
PR target/67480

gcc/
* config/i386/sse.md (define_mode_iterator VI48_AVX_AVX512F): New.
(define_mode_iterator VI12_AVX_AVX512F): New.
(define_insn "3"): Change
all iterators to VI48_AVX_AVX512F. Extract remaining modes ...
(define_insn "*3"): ... Into new pattern using
VI12_AVX_AVX512F iterators without masking.

gcc/testsuite/
* gcc.target/i386/pr67480.c: New test.

Added:
trunk/gcc/testsuite/gcc.target/i386/pr67480.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/i386/sse.md
trunk/gcc/testsuite/ChangeLog

[Bug target/67480] AVX512 bitwise logic operations pattern is incorrect

2015-09-22 Thread afomin.mailbox at gmail dot com 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67480

Alexander Fomin  changed:

   What|Removed |Added

 Status|UNCONFIRMED |RESOLVED
 Resolution|--- |FIXED

--- Comment #5 from Alexander Fomin  ---
Please note that my previous comment is misleading: forced instruction mode
implies no masking at all.

[Bug target/67480] AVX512 bitwise logic operations pattern is incorrect

2015-09-10 Thread afomin.mailbox at gmail dot com 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67480

--- Comment #3 from Alexander Fomin  ---
There is another problem with the same pattern.
Suppose an V16SF insn mode and AVX512F target (e.g. KNL).
We'll emit something like vandps %zmm1, %zmm2, %zmm3; however, vps
family requires AVX512VL and/or AVX512DQ CPUID.

[Bug target/67480] AVX512 bitwise logic operations pattern is incorrect

2015-09-07 Thread afomin.mailbox at gmail dot com 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67480

--- Comment #2 from Alexander Fomin  ---
Created attachment 36304
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=36304=edit
Proposed fix

Proposed fix.
Splitting instruction pattern into two patterns, namely:
(a) any logic instructions, S/D modes, masking is supported;
(b) any logic instructions, Q/H modes, masking is not supported;
fixes the problem.

[Bug target/67480] AVX512 bitwise logic operations pattern is incorrect

2015-09-07 Thread afomin.mailbox at gmail dot com 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67480

--- Comment #1 from Alexander Fomin  ---
Created attachment 36301
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=36301=edit
Testcase

A reproducer