[Bug target/68543] [AArch64] Implement overflow arithmetic standard names {u,}{add,sub,mul}v4 and/or negv3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 Richard Henderson changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED Target Milestone|--- |9.0 --- Comment #8 from Richard Henderson --- This feature was added in r262890, included in gcc 9.
[Bug target/68543] [AArch64] Implement overflow arithmetic standard names {u,}{add,sub,mul}v4 and/or negv3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 Richard Biener changed: What|Removed |Added Target Milestone|7.5 |---
[Bug target/68543] [AArch64] Implement overflow arithmetic standard names {u,}{add,sub,mul}v4 and/or negv3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 Richard Biener changed: What|Removed |Added Target Milestone|7.4 |7.5
[Bug target/68543] [AArch64] Implement overflow arithmetic standard names {u,}{add,sub,mul}v4 and/or negv3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 Richard Biener changed: What|Removed |Added Target Milestone|7.3 |7.4 --- Comment #7 from Richard Biener --- GCC 7.3 is being released, adjusting target milestone.
[Bug target/68543] [AArch64] Implement overflow arithmetic standard names {u,}{add,sub,mul}v4 and/or negv3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 Richard Biener changed: What|Removed |Added Target Milestone|7.2 |7.3
[Bug target/68543] [AArch64] Implement overflow arithmetic standard names {u,}{add,sub,mul}v4 and/or negv3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 Richard Biener changed: What|Removed |Added Target Milestone|7.2 |7.3 --- Comment #7 from Richard Biener --- GCC 7.2 is being released, adjusting target milestone.
[Bug target/68543] [AArch64] Implement overflow arithmetic standard names {u,}{add,sub,mul}v4 and/or negv3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 Jakub Jelinek changed: What|Removed |Added Target Milestone|7.0 |7.2 --- Comment #6 from Jakub Jelinek --- GCC 7.1 has been released.
[Bug target/68543] [AArch64] Implement overflow arithmetic standard names {u,}{add,sub,mul}v4 and/or negv3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 Richard Henderson changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed||2016-01-28 CC||rth at gcc dot gnu.org Target Milestone|--- |7.0 Ever confirmed|0 |1 Severity|normal |enhancement --- Comment #5 from Richard Henderson --- Confirmed. Note that negv3 isn't required if subv4 accepts zero as its first argument. I don't believe that there is anything that aarch64 can usefully do with mulv4 -- generic code should use the widening multiplies as efficiently as anything we can do. Patch for some of this at https://gcc.gnu.org/ml/gcc-patches/2016-01/msg01903.html
[Bug target/68543] [AArch64] Implement overflow arithmetic standard names {u,}{add,sub,mul}v4 and/or negv3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 --- Comment #3 from ktkachov at gcc dot gnu.org --- After some discussion on IRC, WORD_REGISTER_OPERATIONS seems wrong for aarch64 since 32-bit operations i.e. in SImode operate like normal 32-bit operations because they use the 32-bit W-form of the registers. Thus they don't behave like word_mode operations, because word_mode is DImode on aarch64. So we may want to look at implementing the standard names after all
[Bug target/68543] [AArch64] Implement overflow arithmetic standard names {u,}{add,sub,mul}v4 and/or negv3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 --- Comment #4 from Michael Collison --- Okay thanks. After looking into the topic I did not see the direct connection either. On 12/11/2015 7:21 AM, ktkachov at gcc dot gnu.org wrote: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 > > --- Comment #3 from ktkachov at gcc dot gnu.org --- > After some discussion on IRC, WORD_REGISTER_OPERATIONS seems wrong for aarch64 > since 32-bit operations i.e. in SImode operate like normal 32-bit operations > because they use the 32-bit W-form of the registers. Thus they don't behave > like word_mode operations, because word_mode is DImode on aarch64. > So we may want to look at implementing the standard names after all >
[Bug target/68543] [AArch64] Implement overflow arithmetic standard names {u,}{add,sub,mul}v4 and/or negv3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 --- Comment #2 from Michael Collison --- Great idea I will look into this. On 12/10/2015 4:02 AM, ktkachov at gcc dot gnu.org wrote: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 > > --- Comment #1 from ktkachov at gcc dot gnu.org --- > Maybe we can avoid defining custom expanders if we define > WORD_REGISTER_OPERATIONS for aarch64. > It's defined for arm and the documentation hints that it should be true for > most RISC targets. > > Then the default fallback codegen for the given example is much improved: > foo: > uxthx0, w0 > uxthx1, w1 > mul x0, x0, x1 > cmp x0, x0, sxtw > bne .L10 > ret > .L10: > stp x29, x30, [sp, -16]! > add x29, sp, 0 > bl abort > > > However, we need to investigate the other codegen effects that come with > WORD_REGISTER_OPERATIONS, in particular to make sure that the aarch64 patterns > cope with the slightly different strategies of using subregs and sign/zero > extends in combine >
[Bug target/68543] [AArch64] Implement overflow arithmetic standard names {u,}{add,sub,mul}v4 and/or negv3
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68543 --- Comment #1 from ktkachov at gcc dot gnu.org --- Maybe we can avoid defining custom expanders if we define WORD_REGISTER_OPERATIONS for aarch64. It's defined for arm and the documentation hints that it should be true for most RISC targets. Then the default fallback codegen for the given example is much improved: foo: uxthx0, w0 uxthx1, w1 mul x0, x0, x1 cmp x0, x0, sxtw bne .L10 ret .L10: stp x29, x30, [sp, -16]! add x29, sp, 0 bl abort However, we need to investigate the other codegen effects that come with WORD_REGISTER_OPERATIONS, in particular to make sure that the aarch64 patterns cope with the slightly different strategies of using subregs and sign/zero extends in combine
