[Bug target/69135] [5/6 Regression][ARM] instruction cannot be conditional -- `vcvtpne.s32.f32 s0,s0'

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69135

--- Comment #5 from ktkachov at gcc dot gnu.org ---
Author: ktkachov
Date: Tue Jan 19 14:30:23 2016
New Revision: 232566

URL: https://gcc.gnu.org/viewcvs?rev=232566=gcc=rev
Log:
[ARM] PR target/69135: Mark ARMv8 vcvt instructions as unconditional

PR target/69135
* config/arm/vfp.md (lsi2): Set "conds"
attribute to unconditional.  Remove %? from output template.

* gcc.target/arm/pr69135_1.c: New test.


Added:
trunk/gcc/testsuite/gcc.target/arm/pr69135_1.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/arm/vfp.md
trunk/gcc/testsuite/ChangeLog

[Bug target/69135] [5/6 Regression][ARM] instruction cannot be conditional -- `vcvtpne.s32.f32 s0,s0'

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69135

ktkachov at gcc dot gnu.org changed:

   What|Removed |Added

 Status|ASSIGNED|RESOLVED
 Resolution|--- |FIXED

--- Comment #7 from ktkachov at gcc dot gnu.org ---
Fixed on trunk and GCC 5.

[Bug target/69135] [5/6 Regression][ARM] instruction cannot be conditional -- `vcvtpne.s32.f32 s0,s0'

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69135

--- Comment #6 from ktkachov at gcc dot gnu.org ---
Author: ktkachov
Date: Tue Jan 19 15:02:15 2016
New Revision: 232570

URL: https://gcc.gnu.org/viewcvs?rev=232570=gcc=rev
Log:
[ARM] PR target/69135: Mark ARMv8 vcvt instructions as unconditional

Backport from mainline
2016-01-19  Kyrylo Tkachov  

PR target/69135
* config/arm/vfp.md (lsi2): Set "conds"
attribute to unconditional.  Remove %? from output template.

* gcc.target/arm/pr69135_1.c: New test.


Added:
branches/gcc-5-branch/gcc/testsuite/gcc.target/arm/pr69135_1.c
Modified:
branches/gcc-5-branch/gcc/ChangeLog
branches/gcc-5-branch/gcc/config/arm/vfp.md
branches/gcc-5-branch/gcc/testsuite/ChangeLog

[Bug target/69135] [5/6 Regression][ARM] instruction cannot be conditional -- `vcvtpne.s32.f32 s0,s0'

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69135

Richard Biener  changed:

   What|Removed |Added

   Priority|P3  |P2

[Bug target/69135] [5/6 Regression][ARM] instruction cannot be conditional -- `vcvtpne.s32.f32 s0,s0'

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69135

ktkachov at gcc dot gnu.org changed:

   What|Removed |Added

 Target||arm*
 Status|NEW |ASSIGNED
 CC||ktkachov at gcc dot gnu.org
  Known to work||4.9.4
   Assignee|unassigned at gcc dot gnu.org  |ktkachov at gcc dot 
gnu.org
   Target Milestone|--- |5.4
Summary|[5/6][ARM] instruction  |[5/6 Regression][ARM]
   |cannot be conditional --|instruction cannot be
   |`vcvtpne.s32.f32 s0,s0' |conditional --
   ||`vcvtpne.s32.f32 s0,s0'
  Known to fail||5.3.1, 6.0

--- Comment #2 from ktkachov at gcc dot gnu.org ---
Confirmed, mine.

[Bug target/69135] [5/6 Regression][ARM] instruction cannot be conditional -- `vcvtpne.s32.f32 s0,s0'

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69135

--- Comment #3 from ktkachov at gcc dot gnu.org ---
(In reply to Richard Earnshaw from comment #1)
> Confirmed based on inspection.
> 
> The patch suggested is not correct, since vcvtr can be conditional and it
> shares the same basic pattern.

In the lsi2 pattern we use the VCVT iterator
which iterates over [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA] all of which
cannot be conditional. 

UNSPEC_VRINTR is handled by the vrint_variant int attribute, but it's not
utilised in this pattern because the VCVT iterator doesn't include
UNSPEC_VRINTR

So I think the proposed patch is correct, but would need to be sent to
gcc-patches with a the testcase properly added to the testsuite.

[Bug target/69135] [5/6 Regression][ARM] instruction cannot be conditional -- `vcvtpne.s32.f32 s0,s0'

[cctsai57 at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69135

--- Comment #4 from cctsai57  ---
Following
gcc/testsuite/gcc.target/arm/{lceil-vcvt_1.c,lfloor-vcvt_1.c,lround-vcvt_1.c},
suggest:

/* { dg-do compile } */
/* { dg-require-effective-target arm_v8_vfp_ok } */
/* { dg-options "-O2 -march=armv8-a -ffast-math" } */
/* { dg-add-options arm_v8_vfp } */

int global;

void
lceil_float (float x, int b)
{
  if (b) global = __builtin_lceilf (x);
  /* { dg-final { scan-assembler-times "vcvtp.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1
} } */
}

void
lceil_double (double x, int b)
{
  if (b) global = __builtin_lceil (x);
  /* { dg-final { scan-assembler-times "vcvtp.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1
} } */
}

void
lfloor_float (float x, int b)
{
  if (b) global =  __builtin_lfloorf (x);
  /* { dg-final { scan-assembler-times "vcvtm.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1
} } */
}

void
lfloor_double (double x, int b)
{
  if (b) global = __builtin_lfloor (x);
  /* { dg-final { scan-assembler-times "vcvtm.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1
} } */
}

void
lround_float (float x, int b)
{
  if (b) global = __builtin_lroundf (x);
  /* { dg-final { scan-assembler-times "vcvta.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1
} } */
}

void
lround_double (double x, int b)
{
  if (b) global = __builtin_lround (x);
  /* { dg-final { scan-assembler-times "vcvta.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1
} } */
}