https://gcc.gnu.org/bugzilla/show_bug.cgi?id=72804
Bug ID: 72804
Summary: Poor code gen with -mvsx-timode
Product: gcc
Version: 7.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: bergner at gcc dot gnu.org
Target Milestone: ---
The option -mvsx-timode generates very poor code in some circumstances. The
following two test cases show the problem:
bergner@genoa:~/gcc/BUGS/$ cat t.i
__int128_t
foo (__int128_t *p)
{
return p[1];
}
With -O2 -mcpu=power7 -mno-vsx-timode, we get:
foo:
ld 4,24(3)
ld 3,16(3)
blr
With -O2 -mcpu=power7 -mvsx-timode, we get:
foo:
li 9,16
add 3,3,9
ld 4,8(3)
ld 3,0(3)
blr
For bool3-p7.c:ptr4() from the test suite, we see even worse code gen:
bergner@genoa:~/gcc/BUGS/$ cat ptr4.i
void ptr4 (__int128_t *p)
{
__int128_t a = p[1];
__int128_t b;
__asm__ ("# gpr reg %0" : "+r" (a));
b = ~a;
__asm__ ("# gpr reg %0" : "+r" (b));
p[0] = b;
}
bergner@genoa:~/gcc/BUGS/$
/home/bergner/gcc/build/gcc-fsf-mainline-vsx-timode-debug/gcc/xgcc
-B/home/bergner/gcc/build/gcc-fsf-mainline-vsx-timode-debug/gcc/ -O2
-mcpu=power7 -mno-vsx-timode -S ptr4.i
ptr4:
ld 8,16(3)
ld 9,24(3)
# gpr reg 8
not 10,8
not 11,9
# gpr reg 10
std 10,0(3)
std 11,8(3)
blr
bergner@genoa:~/gcc/BUGS/$
/home/bergner/gcc/build/gcc-fsf-mainline-vsx-timode-debug/gcc/xgcc
-B/home/bergner/gcc/build/gcc-fsf-mainline-vsx-timode-debug/gcc/ -O2
-mcpu=power7 -mvsx-timode -S ptr4.i
bergner@genoa:~/gcc/BUGS/$ cat ptr4.s
ptr4:
li 9,16
std 23,-72(1)
lxvd2x 0,3,9
std 24,-64(1)
std 25,-56(1)
std 26,-48(1)
std 27,-40(1)
std 28,-32(1)
std 29,-24(1)
std 30,-16(1)
xxpermdi 0,0,0,2
std 31,-8(1)
stdu 1,-368(1)
xxpermdi 0,0,0,2
addi 9,1,144
addi 23,1,272
stxvd2x 0,0,9
addi 9,1,272
addi 8,1,48
xxpermdi 0,0,0,2
addi 7,1,64
addi 6,1,80
addi 5,1,96
addi 4,1,112
addi 12,1,128
addi 31,1,144
xxpermdi 0,0,0,2
addi 30,1,160
addi 29,1,176
addi 28,1,192
addi 27,1,208
addi 26,1,224
addi 25,1,240
stxvd2x 0,0,9
addi 24,1,256
ori 2,2,0
ld 10,0(9)
ld 11,8(9)
addi 9,1,32
# gpr reg 10
std 10,0(23)
std 11,8(23)
ori 2,2,0
lxvd2x 0,0,23
xxpermdi 0,0,0,2
xxlnor 0,0,0
xxpermdi 0,0,0,2
stxvd2x 0,0,23
ori 2,2,0
ld 10,0(23)
ld 11,8(23)
# gpr reg 10
std 10,0(23)
std 11,8(23)
ori 2,2,0
lxvd2x 0,0,23
stxvd2x 0,0,24
stxvd2x 0,0,25
stxvd2x 0,0,26
stxvd2x 0,0,27
stxvd2x 0,0,28
stxvd2x 0,0,29
stxvd2x 0,0,30
stxvd2x 0,0,31
stxvd2x 0,0,12
stxvd2x 0,0,4
stxvd2x 0,0,5
stxvd2x 0,0,6
stxvd2x 0,0,7
stxvd2x 0,0,8
stxvd2x 0,0,9
addi 1,1,368
ld 23,-72(1)
ld 24,-64(1)
ld 25,-56(1)
ld 26,-48(1)
ld 27,-40(1)
ld 28,-32(1)
ld 29,-24(1)
ld 30,-16(1)
ld 31,-8(1)
stxvd2x 0,0,3
blr
