[Bug target/83467] [7/8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83467 Uroš Bizjak changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #6 from Uroš Bizjak --- Fixed for 7.3+.
[Bug target/83467] [7/8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83467 --- Comment #5 from uros at gcc dot gnu.org --- Author: uros Date: Thu Dec 21 20:48:34 2017 New Revision: 255956 URL: https://gcc.gnu.org/viewcvs?rev=255956=gcc=rev Log: PR target/83467 * config/i386/i386.md (*ashl3_mask): Add operand constraints to operand 2. (*3_mask): Ditto. (*3_mask): Ditto. testsuite/ChangeLog: PR target/83467 * gcc.target/i386/pr83467-1.c: New test. * gcc.target/i386/pr83467-2.c: Ditto. Added: branches/gcc-7-branch/gcc/testsuite/gcc.target/i386/pr83467-1.c branches/gcc-7-branch/gcc/testsuite/gcc.target/i386/pr83467-2.c Modified: branches/gcc-7-branch/gcc/ChangeLog branches/gcc-7-branch/gcc/config/i386/i386.md branches/gcc-7-branch/gcc/testsuite/ChangeLog
[Bug target/83467] [7/8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83467 --- Comment #4 from uros at gcc dot gnu.org --- Author: uros Date: Thu Dec 21 19:00:28 2017 New Revision: 255949 URL: https://gcc.gnu.org/viewcvs?rev=255949=gcc=rev Log: PR target/83467 * config/i386/i386.md (*ashl3_mask): Add operand constraints to operand 2. (*ashl3_mask_1): Ditto. (*3_mask): Ditto. (*3_mask_1): Ditto. (*3_mask): Ditto. (*3_mask_1): Ditto. testsuite/ChangeLog: PR target/83467 * gcc.target/i386/pr83467-1.c: New test. * gcc.target/i386/pr83467-2.c: Ditto. Added: trunk/gcc/testsuite/gcc.target/i386/pr83467-1.c trunk/gcc/testsuite/gcc.target/i386/pr83467-2.c Modified: trunk/gcc/ChangeLog trunk/gcc/config/i386/i386.md trunk/gcc/testsuite/ChangeLog
[Bug target/83467] [7/8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83467 --- Comment #3 from Uroš Bizjak --- *** Bug 83494 has been marked as a duplicate of this bug. ***
[Bug target/83467] [7/8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83467 Uroš Bizjak changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigned at gcc dot gnu.org |ubizjak at gmail dot com --- Comment #2 from Uroš Bizjak --- Created attachment 42929 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=42929=edit Prototype patch in testing Attached patch prevents combine to generate shift insn pattern with hard registers other than CL in the count operand.
[Bug target/83467] [7/8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83467 Jakub Jelinek changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed||2017-12-19 CC||jakub at gcc dot gnu.org, ||uros at gcc dot gnu.org Ever confirmed|0 |1 --- Comment #1 from Jakub Jelinek --- Started with r239511.
[Bug target/83467] [7/8 Regression] ICE: in assign_by_spills, at lra-assigns.c:1476: unable to find a register to spill with -flive-range-shrinkage -m8bit-idiv
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83467 Richard Biener changed: What|Removed |Added Target Milestone|--- |7.3
