[Bug target/87511] [9 Regression][AArch64] UBFIZ instruction with invalid immediate emitted

2018-10-04 Thread rguenth at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87511

Richard Biener  changed:

   What|Removed |Added

   Keywords||wrong-code
   Target Milestone|--- |9.0

[Bug target/87511] [9 Regression][AArch64] UBFIZ instruction with invalid immediate emitted

2018-10-10 Thread wilco at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87511

Wilco  changed:

   What|Removed |Added

 Status|UNCONFIRMED |NEW
   Last reconfirmed||2018-10-10
 CC||wilco at gcc dot gnu.org
 Ever confirmed|0   |1

--- Comment #1 from Wilco  ---
Confirmed. The issue is in aarch64_mask_and_shift_for_ubfiz_p:

&& (INTVAL (mask) & ((1 << INTVAL (shft_amnt)) - 1)) == 0;

This evaluates the shift as a 32-bit int rather than HOST_WIDE_INT.

[Bug target/87511] [9 Regression][AArch64] UBFIZ instruction with invalid immediate emitted

2018-10-11 Thread wilco at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87511

--- Comment #2 from Wilco  ---
Author: wilco
Date: Thu Oct 11 19:10:12 2018
New Revision: 265058

URL: https://gcc.gnu.org/viewcvs?rev=265058&root=gcc&view=rev
Log:
[AArch64] Fix PR87511

As mentioned in PR87511, the shift used in aarch64_mask_and_shift_for_ubfiz_p
should be evaluated as a HOST_WIDE_INT rather than int.

Passes bootstrap & regress.

gcc/
PR target/87511
* config/aarch64/aarch64.c (aarch64_mask_and_shift_for_ubfiz_p):
Use HOST_WIDE_INT_1U for shift.

testsuite/
PR target/87511
* gcc.target/aarch64/pr87511.c: Add new test.

Added:
trunk/gcc/testsuite/gcc.target/aarch64/pr87511.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/aarch64/aarch64.c
trunk/gcc/testsuite/ChangeLog

[Bug target/87511] [9 Regression][AArch64] UBFIZ instruction with invalid immediate emitted

2018-10-16 Thread wilco at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87511

--- Comment #3 from Wilco  ---
Author: wilco
Date: Tue Oct 16 12:26:00 2018
New Revision: 265191

URL: https://gcc.gnu.org/viewcvs?rev=265191&root=gcc&view=rev
Log:
[AArch64] Fix PR87511

As mentioned in PR87511, the shift used in aarch64_mask_and_shift_for_ubfiz_p
should be evaluated as a HOST_WIDE_INT rather than int.

Backported from mainline

gcc/
PR target/87511
* config/aarch64/aarch64.c (aarch64_mask_and_shift_for_ubfiz_p):
Use HOST_WIDE_INT_1U for shift.

testsuite/
PR target/87511
* gcc.target/aarch64/pr87511.c: Add new test.

Modified:
branches/gcc-8-branch/gcc/ChangeLog
branches/gcc-8-branch/gcc/config/aarch64/aarch64.c
branches/gcc-8-branch/gcc/testsuite/ChangeLog

[Bug target/87511] [9 Regression][AArch64] UBFIZ instruction with invalid immediate emitted

2018-10-16 Thread wilco at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87511

--- Comment #4 from Wilco  ---
Author: wilco
Date: Tue Oct 16 13:40:57 2018
New Revision: 265195

URL: https://gcc.gnu.org/viewcvs?rev=265195&root=gcc&view=rev
Log:
[AArch64] Fix PR87511

As mentioned in PR87511, the shift used in aarch64_mask_and_shift_for_ubfiz_p
should be evaluated as a HOST_WIDE_INT rather than int.

Backported from mainline

gcc/
PR target/87511
* config/aarch64/aarch64.c (aarch64_mask_and_shift_for_ubfiz_p):
Use HOST_WIDE_INT_1U for shift.

testsuite/
PR target/87511
* gcc.target/aarch64/pr87511.c: Add new test.

Added:
branches/gcc-7-branch/gcc/testsuite/gcc.target/aarch64/pr87511.c
Modified:
branches/gcc-7-branch/gcc/ChangeLog
branches/gcc-7-branch/gcc/config/aarch64/aarch64.c
branches/gcc-7-branch/gcc/testsuite/ChangeLog

[Bug target/87511] [9 Regression][AArch64] UBFIZ instruction with invalid immediate emitted

2018-10-16 Thread wilco at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87511

Wilco  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
Version|9.0 |7.3.1
 Resolution|--- |FIXED

--- Comment #5 from Wilco  ---
Fixed on trunk, gcc8 and gcc7, so closing as resolved.