[Bug target/89607] Missing optimization for store of multiple registers on aarch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89607 --- Comment #4 from Andrew Pinski --- For aarch64, there was talk about adding stp for q registers. Also it does not help the current set of aarch64 processors that much to add stp support for q registers.
[Bug target/89607] Missing optimization for store of multiple registers on aarch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89607 --- Comment #5 from Yichao Yu --- I just compiled the 9-20190303 snapshot and this is indeed seems to be fixed. Should this be closed now or after GCC 9 is released?
[Bug target/89607] Missing optimization for store of multiple registers on aarch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89607 --- Comment #6 from Yichao Yu --- > For aarch64, there was talk about adding stp for q registers. What do you mean? I was initially unsure about it too but I assume it already exist since clang (and now GCC 9) emits it and the arm arch reference manual also mentions it without mentioning it only available in a later version.
[Bug target/89607] Missing optimization for store of multiple registers on aarch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89607 --- Comment #7 from Andrew Pinski --- (In reply to Yichao Yu from comment #6) > > For aarch64, there was talk about adding stp for q registers. > > What do you mean? I was initially unsure about it too but I assume it > already exist since clang (and now GCC 9) emits it and the arm arch > reference manual also mentions it without mentioning it only available in a > later version. I mean the support to emit stp for q registers. I did not follow the disussion close enough but from your mention, it was committed. The problem with stp for q registers on some targets is that it is single issue or it is split into two instructions anyways.
[Bug target/89607] Missing optimization for store of multiple registers on aarch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89607 --- Comment #8 from Yichao Yu --- I see. I don't imagine this to cause a major local speed up though I assume it should at least not be slower? That's also why I mentioned that this should at least be done for `-Os`.
[Bug target/89607] Missing optimization for store of multiple registers on aarch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89607 Wilco changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED CC||wilco at gcc dot gnu.org Resolution|--- |FIXED Target Milestone|--- |9.0 --- Comment #9 from Wilco --- Fixed in GCC9 already, so closing.
