[Bug target/90317] [7/8/9/10] ICE for arm sha1h and wrong optimisations on sha1h/c/m/p

2019-07-18 Thread ktkachov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90317

--- Comment #2 from ktkachov at gcc dot gnu.org ---
Author: ktkachov
Date: Thu Jul 18 15:42:13 2019
New Revision: 273574

URL: https://gcc.gnu.org/viewcvs?rev=273574&root=gcc&view=rev
Log:
[patch1/2][arm][PR90317]: fix sha1 patterns

This patch fixes:

1) Ice message thrown when using the crypto_sha1h intrinsic due to
incompatible mode used for zero_extend. Removed zero extend as it is
not a good choice for vector modes and using an equivalent single
mode like TI (128bits) instead of V4SI produces extra instructions
making it inefficient.

This affects gcc version 8 and above.

2) Incorrect combine optimizations made due to vec_select usage
in the sha1 patterns on arm. The patterns should only combine
a vec select within a sha1h instruction when the lane is 0.

This affects gcc version 5 and above.

- Fixed by explicitly declaring the valid const int for such
optimizations. For cases when the lane is not 0, the vector
lane selection now occurs in a e.g. vmov instruction prior
to sha1h.

- Updated the sha1h testcases on arm to check for additional
cases with custom vector lane selection.

The intrinsic functions for the sha1 patterns have also been
simplified which seems to eliminate extra vmovs like:
- vmov.i32 q8, #0.


2019-07-18  Sylvia Taylor  

PR target/90317
* config/arm/arm_neon.h
(vsha1h_u32): Refactor.
(vsha1cq_u32): Likewise.
(vsha1pq_u32): Likewise.
(vsha1mq_u32): Likewise.
* config/arm/crypto.md:
(crypto_sha1h): Remove zero extend, correct vec select.
(crypto_sha1c): Correct vec select.
(crypto_sha1m): Likewise.
(crypto_sha1p): Likewise.

* gcc.target/arm/crypto-vsha1cq_u32.c (foo): Change return type to
uint32_t.
(GET_LANE, TEST_SHA1C_VEC_SELECT): New.
* gcc.target/arm/crypto-vsha1h_u32.c (foo): Change return type to
uint32_t.
(GET_LANE, TEST_SHA1H_VEC_SELECT): New.
* gcc.target/arm/crypto-vsha1mq_u32.c (foo): Change return type to
uint32_t.
(GET_LANE, TEST_SHA1M_VEC_SELECT): New.
* gcc.target/arm/crypto-vsha1pq_u32.c (foo): Change return type to
uint32_t.
(GET_LANE, TEST_SHA1P_VEC_SELECT): New.

Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/arm/arm_neon.h
trunk/gcc/config/arm/crypto.md
trunk/gcc/testsuite/ChangeLog
trunk/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c
trunk/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c
trunk/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c
trunk/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c

[Bug target/90317] [7/8/9/10] ICE for arm sha1h and wrong optimisations on sha1h/c/m/p

2019-05-29 Thread wilco at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90317

Wilco  changed:

   What|Removed |Added

 Status|UNCONFIRMED |NEW
   Last reconfirmed||2019-05-29
 CC||wilco at gcc dot gnu.org
 Ever confirmed|0   |1

--- Comment #1 from Wilco  ---
Confirmed