[Bug target/94678] aarch64: unexpected result with -mgeneral-regs-only and sve

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94678

--- Comment #4 from CVS Commits  ---
The master branch has been updated by Richard Sandiford :

https://gcc.gnu.org/g:857d1fa3f0a04569382bab12829e5bfd3725ecbf

commit r10-7917-g857d1fa3f0a04569382bab12829e5bfd3725ecbf
Author: Fei Yang 
Date:   Thu Apr 23 16:08:03 2020 +0100

testsuite: Add extra aarch64 predefine tests

Add extra testing in the following two tests to make sure CPP predefines
redefinitions on #pragma works as expected when -mgeneral-regs-only
option is specified (See PR94678):
gcc.target/aarch64/pragma_cpp_predefs_2.c
gcc.target/aarch64/pragma_cpp_predefs_3.c

2020-04-23  Felix Yang  

gcc/testsuite/
PR target/94678
* gcc.target/aarch64/pragma_cpp_predefs_2.c: Fix typos, pop_pragma
->
pop_options. Add tests for general-regs-only.
* gcc.target/aarch64/pragma_cpp_predefs_3.c: Add tests for
general-regs-only.

[Bug target/94678] aarch64: unexpected result with -mgeneral-regs-only and sve

[rsandifo at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94678

rsandifo at gcc dot gnu.org  changed:

   What|Removed |Added

 CC||rsandifo at gcc dot gnu.org
 Resolution|--- |FIXED
 Status|UNCONFIRMED |RESOLVED

--- Comment #3 from rsandifo at gcc dot gnu.org  
---
Fixed on master.  Thanks for the patch.

[Bug target/94678] aarch64: unexpected result with -mgeneral-regs-only and sve

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94678

--- Comment #2 from CVS Commits  ---
The master branch has been updated by Richard Sandiford :

https://gcc.gnu.org/g:154ae7d4e921d704118d6a16ee5cc2a10b9047da

commit r10-7891-g154ae7d4e921d704118d6a16ee5cc2a10b9047da
Author: Fei Yang 
Date:   Wed Apr 22 18:24:59 2020 +0100

aarch64: unexpected result with -mgeneral-regs-only and sve [PR94678]

As the two testcases for PR94678 show, -mgeneral-regs-only is handled
properly with SVE.  We should issue an error message instead of expanding
SVE builtin funtions when -mgeneral-regs-only option is specified.

The middle end should never try to use vector patterns when the vector
modes have been disabled by !have_regs_of_mode.  But it's still wrong
for the target to provide patterns that would inevitably lead to spill
failure due to lack of registers.  So we should also add check for
!TARGET_GENERAL_REGS_ONLY in TARGET_SVE and other SVE related macros.

2020-04-22  Felix Yang  

gcc/
PR target/94678
* config/aarch64/aarch64.h (TARGET_SVE):
Add && !TARGET_GENERAL_REGS_ONLY.
(TARGET_SVE2): Add && TARGET_SVE.
(TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3,
TARGET_SVE2_SM4): Add && TARGET_SVE2.
* config/aarch64/aarch64-sve-builtins.h
(sve_switcher::m_old_general_regs_only): New member.
* config/aarch64/aarch64-sve-builtins.cc
(check_required_registers):
New function.
(reported_missing_registers_p): New variable.
(check_required_extensions): Call check_required_registers before
return if all required extenstions are present.
(sve_switcher::sve_switcher): Save TARGET_GENERAL_REGS_ONLY in
m_old_general_regs_only and clear MASK_GENERAL_REGS_ONLY in
global_options.x_target_flags.
(sve_switcher::~sve_switcher): Set MASK_GENERAL_REGS_ONLY in
global_options.x_target_flags if m_old_general_regs_only is true.

gcc/testsuite/
PR target/94678
* gcc.target/aarch64/sve/acle/general/nosve_6.c: New test.

[Bug target/94678] aarch64: unexpected result with -mgeneral-regs-only and sve

[felix.yang at huawei dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94678

--- Comment #1 from Fei Yang  ---
crash log for test2.c:

during RTL pass: expand
foo.c: In function 'f2':
foo.c:14:10: internal compiler error: in emit_move_insn, at expr.c:3815
   14 |   return svadd_m (*x, *y, 1);
  |  ^~~
0xd21797 emit_move_insn(rtx_def*, rtx_def*)
../../gcc-git/gcc/expr.c:3814
0xcf52cb copy_to_mode_reg(machine_mode, rtx_def*)
../../gcc-git/gcc/explow.c:634
0x11021f7 maybe_legitimize_operand
../../gcc-git/gcc/optabs.c:7283
0x1102caf maybe_legitimize_operands(insn_code, unsigned int, unsigned int,
expand_operand*)
../../gcc-git/gcc/optabs.c:7415
0x1102d9b maybe_gen_insn(insn_code, unsigned int, expand_operand*)
../../gcc-git/gcc/optabs.c:7434
0x1103223 maybe_expand_insn(insn_code, unsigned int, expand_operand*)
../../gcc-git/gcc/optabs.c:7477
0x11032c3 expand_insn(insn_code, unsigned int, expand_operand*)
../../gcc-git/gcc/optabs.c:7508
0x10edec3 expand_vector_broadcast(machine_mode, rtx_def*)
../../gcc-git/gcc/optabs.c:419
0x1859ec3 aarch64_sve::function_expander::add_input_operand(insn_code,
rtx_def*)
../../gcc-git/gcc/config/aarch64/aarch64-sve-builtins.cc:2790
0x185b1b3 aarch64_sve::function_expander::use_cond_insn(insn_code, unsigned
int)
../../gcc-git/gcc/config/aarch64/aarch64-sve-builtins.cc:3078
0x185b753 aarch64_sve::function_expander::map_to_rtx_codes(rtx_code, rtx_code,
int, unsigned int)
../../gcc-git/gcc/config/aarch64/aarch64-sve-builtins.cc:3224
0x18768d7
aarch64_sve::rtx_code_function::expand(aarch64_sve::function_expander&) const
../../gcc-git/gcc/config/aarch64/aarch64-sve-builtins-functions.h:211
0x185b9fb aarch64_sve::function_expander::expand()
../../gcc-git/gcc/config/aarch64/aarch64-sve-builtins.cc:3281
0x185dcab aarch64_sve::expand_builtin(unsigned int, tree_node*, rtx_def*)
../../gcc-git/gcc/config/aarch64/aarch64-sve-builtins.cc:3569
0x17c0ceb aarch64_expand_builtin
../../gcc-git/gcc/config/aarch64/aarch64.c:13147
0xb3782f expand_builtin(tree_node*, rtx_def*, rtx_def*, machine_mode, int)
../../gcc-git/gcc/builtins.c:7736
0xd4039b expand_expr_real_1(tree_node*, rtx_def*, machine_mode,
expand_modifier, rtx_def**, bool)
../../gcc-git/gcc/expr.c:11132
0xd3338f expand_expr_real(tree_node*, rtx_def*, machine_mode, expand_modifier,
rtx_def**, bool)
../../gcc-git/gcc/expr.c:8359
0xd28337 store_expr(tree_node*, rtx_def*, int, bool, bool)
../../gcc-git/gcc/expr.c:5755
0xd26d27 expand_assignment(tree_node*, tree_node*, bool)
../../gcc-git/gcc/expr.c:5514
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