[Bug target/95958] [meta-bug] Inefficient arm_neon.h code for AArch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95958 Bug 95958 depends on bug 102171, which changed state. Bug 102171 Summary: vget_low_*/vget_high_* intrinsics should become BIT_FIELD_REF during gimple https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102171 What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED
[Bug target/95958] [meta-bug] Inefficient arm_neon.h code for AArch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95958 Bug 95958 depends on bug 88212, which changed state. Bug 88212 Summary: IRA Register Coalescing not working for the testcase https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88212 What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|--- |FIXED
[Bug target/95958] [meta-bug] Inefficient arm_neon.h code for AArch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95958 Bug 95958 depends on bug 94442, which changed state. Bug 94442 Summary: [11/12/13/14 regression] Redundant loads/stores emitted at -O3 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94442 What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED
[Bug target/95958] [meta-bug] Inefficient arm_neon.h code for AArch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95958 Bug 95958 depends on bug 95969, which changed state. Bug 95969 Summary: Use of __builtin_aarch64_im_lane_boundsi in AArch64 arm_neon.h interferes with gimple optimisation https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95969 What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED
[Bug target/95958] [meta-bug] Inefficient arm_neon.h code for AArch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95958 Bug 95958 depends on bug 91598, which changed state. Bug 91598 Summary: [9 regression] 60% speed drop on neon intrinsic loop https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91598 What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED
[Bug target/95958] [meta-bug] Inefficient arm_neon.h code for AArch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95958 Bug 95958 depends on bug 91753, which changed state. Bug 91753 Summary: Bad register allocation of multi-register types https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91753 What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED
[Bug target/95958] [meta-bug] Inefficient arm_neon.h code for AArch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95958 Bug 95958 depends on bug 89057, which changed state. Bug 89057 Summary: [9 Regression] AArch64 ld3 st4 less optimized https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89057 What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED
[Bug target/95958] [meta-bug] Inefficient arm_neon.h code for AArch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95958 Bug 95958 depends on bug 82074, which changed state. Bug 82074 Summary: [aarch64] vmlsq_f32 compiled into 2 instructions https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82074 What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED
[Bug target/95958] [meta-bug] Inefficient arm_neon.h code for AArch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95958 Bug 95958 depends on bug 95265, which changed state. Bug 95265 Summary: aarch64: suboptimal code generation for common neon intrinsic sequence involving shrn and mull https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95265 What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED
[Bug target/95958] [meta-bug] Inefficient arm_neon.h code for AArch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95958 rsandifo at gcc dot gnu.org changed: What|Removed |Added Keywords||missed-optimization Depends on||66675, 80283, 88212, 89057, ||89606, 89967, 91753, 94442, ||95265, 91598, 82074 --- Comment #1 from rsandifo at gcc dot gnu.org --- At the time of writing, PR80283 doesn't have an AArch64 testcase, only an AArch32 one. However, the underlying issue applies across targets. The content probably overlaps a lot with PR91598, which is AArch64-specific. Referenced Bugs: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66675 [Bug 66675] Could improve vector lane folding style operations. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80283 [Bug 80283] [8/9/10/11 Regression] bad SIMD register allocation https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82074 [Bug 82074] [aarch64] vmlsq_f32 compiled into 2 instructions https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88212 [Bug 88212] IRA Register Coalescing not working for the testcase https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89057 [Bug 89057] [8/9/10/11 Regression] AArch64 ld3 st4 less optimized https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89606 [Bug 89606] Extra mov after structure load instructions on aarch64 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89967 [Bug 89967] Inefficient code generation for vld2q_lane_u8 under aarch64 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91598 [Bug 91598] [8/9 regression] 60% speed drop on neon intrinsic loop https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91753 [Bug 91753] Bad register allocation of multi-register types https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94442 [Bug 94442] [10/11 regression] Redundant loads/stores emitted at -O3 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95265 [Bug 95265] aarch64: suboptimal code generation for common neon intrinsic sequence involving shrn and mull
[Bug target/95958] [meta-bug] Inefficient arm_neon.h code for AArch64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95958 rsandifo at gcc dot gnu.org changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed||2020-06-29 Status|UNCONFIRMED |NEW
