[Bug tree-optimization/113281] [14] RISC-V rv64gcv_zvl256b vector: Runtime mismatch with rv64gc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113281 Andrew Pinski changed: What|Removed |Added Last reconfirmed||2024-01-09 Status|UNCONFIRMED |NEW Ever confirmed|0 |1 Component|target |tree-optimization Target|riscv |riscv aarch64-linux-gnu --- Comment #6 from Andrew Pinski --- Confirmed on aarch64 too: [apinski@xeond2 upstream-full-cross]$ ./install/bin/aarch64-linux-gnu-gcc -O3 -march=armv9-a+sve2 t.c -static -fno-vect-cost-model [apinski@xeond2 upstream-full-cross]$ ./install-qemu/bin/qemu-aarch64 a.out ;echo $? 1
[Bug tree-optimization/113281] [14] RISC-V rv64gcv_zvl256b vector: Runtime mismatch with rv64gc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113281 --- Comment #7 from Andrew Pinski --- > short b = a = 0; s/short/int/ allows it to work ...
[Bug tree-optimization/113281] [14] RISC-V rv64gcv_zvl256b vector: Runtime mismatch with rv64gc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113281 --- Comment #8 from JuzheZhong --- (In reply to Andrew Pinski from comment #7) > > short b = a = 0; > > s/short/int/ allows it to work ... Thanks Andrew. I think we should change the tittle. It should be mismatch on both RISC-V and ARM SVE with -fno-vect-cost-model.