[Bug tree-optimization/42172] inefficient bit fields assignments

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

Andrew Pinski  changed:

   What|Removed |Added

 Resolution|--- |FIXED
   Target Milestone|--- |7.0
 Status|NEW |RESOLVED

--- Comment #12 from Andrew Pinski  ---
Fixed already fully in GCC 7, there are already testcases committed for this.
Most likely r7-4171 .

[Bug tree-optimization/42172] inefficient bit fields assignments

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

Andrew Pinski  changed:

   What|Removed |Added

   Keywords||missed-optimization
   Severity|normal  |enhancement

[Bug tree-optimization/42172] inefficient bit fields assignments

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

Segher Boessenkool  changed:

   What|Removed |Added

 CC||segher at gcc dot gnu.org

--- Comment #11 from Segher Boessenkool  ---
I have code to improve zero_extract (and similar) handling in
combine.  For stage1, obviously.

[Bug tree-optimization/42172] inefficient bit fields assignments

[amker at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

--- Comment #10 from amker at gcc dot gnu.org ---
The optimal code is generated on pre-armv7 processors.  The difference starts
from expand.  On armv7-processors, zero_extract operator is generated, rather
than logic operation.  Seem combiner can't handle bit-field in the form of
zero_extract as well as logic forms.

I uploaded ud_dce&combine dumps for both cortex-m0 and cortex-m3.  Apparently,
code for m0 is what we want.

[Bug tree-optimization/42172] inefficient bit fields assignments

[amker at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

amker at gcc dot gnu.org changed:

   What|Removed |Added

 CC||amker at gcc dot gnu.org

--- Comment #9 from amker at gcc dot gnu.org ---
Created attachment 35265
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=35265&action=edit
rtl dump for both cortex-m0 and cortex-m3

[Bug tree-optimization/42172] inefficient bit fields assignments

[janis at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172



Janis Johnson  changed:



   What|Removed |Added



 CC||janis at gcc dot gnu.org



--- Comment #8 from Janis Johnson  2013-01-17 
00:26:10 UTC ---

The test gcc.target/arm/pr42172-1.c currently passes for armv6t2, armv7*, and

armv8* with and without -mthumb.  At this point can the test be limited to

those processors, or XFAILed for others?

[Bug tree-optimization/42172] inefficient bit fields assignments

[rguenth at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

Richard Guenther  changed:

   What|Removed |Added

   Target Milestone|4.6.1   |---

[Bug tree-optimization/42172] inefficient bit fields assignments

[jakub at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

Jakub Jelinek  changed:

   What|Removed |Added

   Target Milestone|4.6.0   |4.6.1

--- Comment #7 from Jakub Jelinek  2011-03-25 
19:53:14 UTC ---
GCC 4.6.0 is being released, adjusting target milestone.

[Bug tree-optimization/42172] inefficient bit fields assignments

[ramana at gcc dot gnu dot org]

-- 

ramana at gcc dot gnu dot org changed:

   What|Removed |Added

   Target Milestone|--- |4.6.0


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

[Bug tree-optimization/42172] inefficient bit fields assignments

[ramana at gcc dot gnu dot org]

--- Comment #6 from ramana at gcc dot gnu dot org  2010-09-01 09:07 ---
Leaving this open as per comment #4


-- 

ramana at gcc dot gnu dot org changed:

   What|Removed |Added

 Status|UNCONFIRMED |NEW
 Ever Confirmed|0   |1
   Last reconfirmed|-00-00 00:00:00 |2010-09-01 09:07:00
   date||


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

[Bug tree-optimization/42172] inefficient bit fields assignments

[bernds at gcc dot gnu dot org]

--- Comment #5 from bernds at gcc dot gnu dot org  2010-08-19 17:32 ---
Subject: Bug 42172

Author: bernds
Date: Thu Aug 19 17:31:57 2010
New Revision: 163383

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=163383
Log:
PR target/42172
* combine.c (combine_validate_cost): New arg I0.  All callers changed.
Take its cost into account if nonnull.
(insn_a_feeds_b): New static function.
(combine_instructions): Look for four-insn combinations.
(can_combine_p): New args PRED2, SUCC2.  All callers changed.  Take
them into account when computing all_adjacent and looking for other
uses.
(combinable_i3pat): New args I0DEST, I0_NOT_IN_SRC.  All callers
changed.  Treat them like I1DEST and I1_NOT_IN_SRC.
(try_combine): New arg I0.  Handle four-insn combinations.
(distribute_notes): New arg ELIM_I0.  All callers changed.  Treat it
like ELIM_I1.

Modified:
trunk/gcc/ChangeLog
trunk/gcc/combine.c


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

[Bug tree-optimization/42172] inefficient bit fields assignments

[bernds at gcc dot gnu dot org]

--- Comment #4 from bernds at gcc dot gnu dot org  2010-08-09 15:04 ---
I'm reopening this as it's not fixed, and even if we fix it in the RTL
optimizers, it should stay open as a reminder that we produce poor initial RTL.


-- 

bernds at gcc dot gnu dot org changed:

   What|Removed |Added

 Status|RESOLVED|UNCONFIRMED
  Component|target  |tree-optimization
 Resolution|DUPLICATE   |


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172