[gcc r14-9417] Revert "[committed] Adjust expectations for pr59533-1.c"
https://gcc.gnu.org/g:6f7d000fcacef31a6947f95021e445c846170f92
commit r14-9417-g6f7d000fcacef31a6947f95021e445c846170f92
Author: jlaw
Date: Sat Mar 9 21:33:47 2024 -0700
Revert "[committed] Adjust expectations for pr59533-1.c"
This reverts commit 7e16f819ff413c48702f9087b62eaac39a060a14.
Diff:
---
gcc/testsuite/gcc.target/sh/pr59533-1.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/sh/pr59533-1.c
b/gcc/testsuite/gcc.target/sh/pr59533-1.c
index 859b8e2d24c..b0469859df5 100644
--- a/gcc/testsuite/gcc.target/sh/pr59533-1.c
+++ b/gcc/testsuite/gcc.target/sh/pr59533-1.c
@@ -2,15 +2,15 @@
/* { dg-do compile } */
/* { dg-options "-O1" } */
-/* { dg-final { scan-assembler-times "shll" 3 } } */
+/* { dg-final { scan-assembler-times "shll" 1 } } */
/* { dg-final { scan-assembler-times "movt" 5 } } */
/* { dg-final { scan-assembler-times "rotcl" 1 } } */
/* { dg-final { scan-assembler-times "and" 3 } } */
/* { dg-final { scan-assembler-times "extu.b" 5 } } */
-/* { dg-final { scan-assembler-times "cmp/pz" 25 { target { ! sh2a } } } } */
-/* { dg-final { scan-assembler-times "addc" 6 { target { ! sh2a } } } } */
-/* { dg-final { scan-assembler-times "subc" 14 { target { ! sh2a } } } } */
+/* { dg-final { scan-assembler-times "cmp/pz" 27 { target { ! sh2a } } } } */
+/* { dg-final { scan-assembler-times "addc" 4 { target { ! sh2a } } } } */
+/* { dg-final { scan-assembler-times "subc" 16 { target { ! sh2a } } } } */
/* { dg-final { scan-assembler-times "cmp/pz" 25 { target { sh2a } } } } */
/* { dg-final { scan-assembler-times "addc" 6 { target { sh2a } } } } */
[gcc r14-9416] [committed] [target/102250] Document python requirement for risc-v
https://gcc.gnu.org/g:7c8f0a79a7e1e42f846ddbca14b98b47ddcfd178
commit r14-9416-g7c8f0a79a7e1e42f846ddbca14b98b47ddcfd178
Author: jlaw
Date: Sat Mar 9 20:11:39 2024 -0700
[committed] [target/102250] Document python requirement for risc-v
PR target/102250
gcc/
* doc/install.texi: Document need for python when building
RISC-V compilers.
Diff:
---
gcc/doc/install.texi | 5 +
1 file changed, 5 insertions(+)
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 173233096d1..e3650e0c4f4 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -253,6 +253,11 @@ name of the package depends on your distro) or you must
build GCC as a
@option{--disable-multilib}. Otherwise, you may encounter an error such as
@samp{fatal error: gnu/stubs-32.h: No such file}
+@item Python
+If you configure a RISC-V compiler with the option @option{--with-arch} and
+the specified architecture string is non-canonical, then you will need
+@command{python} installed on the build system.
+
@item @anchor{GNAT-prerequisite}GNAT
In order to build GNAT, the Ada compiler, you need a working GNAT
[gcc r14-9415] [committed] [PR target/111362] Fix compare-debug issue with mode switching
https://gcc.gnu.org/g:50531b6d400945793a1d549e6ee941d989319d42
commit r14-9415-g50531b6d400945793a1d549e6ee941d989319d42
Author: jlaw
Date: Sat Mar 9 19:27:32 2024 -0700
[committed] [PR target/111362] Fix compare-debug issue with mode switching
The issue here is the code we emit for mode-switching can change when -g is
added to the command line. This is caused by processing debug notes
occurring
after a call which is the last real statement in a basic block.
Without -g the CALL_INSN is literally the last insn in the block and the
loop
exits. If mode switching after the call is needed, it'll be handled as we
process outgoing edges.
With -g the loop iterates again and in the processing of the node the
backend
signals that a mode switch is necessary.
I pondered fixing this in the target, but the better fix is to ignore the
debug
notes in the insn stream.
I did a cursory review of some of the other compare-debug failures, but did
not
immediately see others which would likely be fixed by this change. Sigh.
Anyway, bootstrapped and regression tested on x86. Regression tested on
rv64
as well.
PR target/111362
gcc/
* mode-switching.cc (optimize_mode_switching): Only process
NONDEBUG insns.
gcc/testsuite
* gcc.target/riscv/compare-debug-1.c: New test.
* gcc.target/riscv/compare-debug-2.c: New test.
Diff:
---
gcc/mode-switching.cc| 2 +-
gcc/testsuite/gcc.target/riscv/compare-debug-1.c | 9 +
gcc/testsuite/gcc.target/riscv/compare-debug-2.c | 3 +++
3 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/gcc/mode-switching.cc b/gcc/mode-switching.cc
index 583929184ce..a145b77397d 100644
--- a/gcc/mode-switching.cc
+++ b/gcc/mode-switching.cc
@@ -959,7 +959,7 @@ optimize_mode_switching (void)
FOR_BB_INSNS (bb, insn)
{
- if (INSN_P (insn))
+ if (NONDEBUG_INSN_P (insn))
{
int mode = targetm.mode_switching.needed (e, insn, live_now);
rtx link;
diff --git a/gcc/testsuite/gcc.target/riscv/compare-debug-1.c
b/gcc/testsuite/gcc.target/riscv/compare-debug-1.c
new file mode 100644
index 000..d65bb287b9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/compare-debug-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O -fno-tree-ch --param=max-completely-peel-times=0
-march=rv64iv -mabi=lp64d -fcompare-debug" } */
+
+
+void
+foo(void) {
+ for (unsigned i = 0; i < sizeof(foo); i++)
+__builtin_printf("%d", i);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/compare-debug-2.c
b/gcc/testsuite/gcc.target/riscv/compare-debug-2.c
new file mode 100644
index 000..d87758475e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/compare-debug-2.c
@@ -0,0 +1,3 @@
+/* { dg-do compile } */
+/* { dg-options "-O -fno-tree-ch --param=max-completely-peel-times=0
-march=rv64iv -mabi=lp64d -fno-dce -fschedule-insns -fcompare-debug" } */
+#include "compare-debug-1.c"
[gcc r14-9413] AVR: Fix typos in comment, indentation glitches in avr.md.
https://gcc.gnu.org/g:f5a805d82902fe2d6e0a7af8c0e6519f9d25a8f3
commit r14-9413-gf5a805d82902fe2d6e0a7af8c0e6519f9d25a8f3
Author: Georg-Johann Lay
Date: Sat Mar 9 13:07:17 2024 +0100
AVR: Fix typos in comment, indentation glitches in avr.md.
gcc/
* config/avr/avr.md: Fix typos in comment, indentation glitches
and some other nits.
Diff:
---
gcc/config/avr/avr.md | 87 +--
1 file changed, 43 insertions(+), 44 deletions(-)
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 59ec724f7da..bc408633eb5 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -31,7 +31,7 @@
;; j Branch condition.
;; k Reverse branch condition.
;;..m..Constant Direct Data memory address.
-;; i Print the SFR address quivalent of a CONST_INT or a CONST_INT
+;; i Print the SFR address equivalent of a CONST_INT or a CONST_INT
;; RAM address. The resulting address is suitable to be used in IN/OUT.
;; o Displacement for (mem (plus (reg) (const_int))) operands.
;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z)
@@ -475,7 +475,7 @@
// (reg:HI 28)))
//(set (mem:HI (post_dec:HI (reg:HI 32 SP))
// (reg:HI **)))
-
+
emit_insn (gen_pushhi1_insn (operands[0]));
DONE;
}
@@ -540,7 +540,7 @@
"#"
"&& reload_completed"
[(parallel [(set (reg:MOVMODE 22)
-(match_dup 0))
+ (match_dup 0))
(clobber (reg:CC REG_CC))])]
""
[(set_attr "isa" "rjmp,jmp")])
@@ -576,7 +576,7 @@
[(clobber (const_int 0))]
{
// Split away the high part of the address. GCC's register allocator
-// in not able to allocate segment registers and reload the resulting
+// is not able to allocate segment registers and reload the resulting
// expressions. Notice that no address register can hold a PSImode.
rtx addr = XEXP (operands[1], 0);
@@ -614,14 +614,13 @@
rtx reg_z = gen_rtx_REG (HImode, REG_Z);
rtx addr_hi8 = simplify_gen_subreg (QImode, addr, PSImode, 2);
addr_space_t as = MEM_ADDR_SPACE (operands[1]);
-rtx_insn *insn;
// Split the address to R21:Z
emit_move_insn (reg_z, simplify_gen_subreg (HImode, addr, PSImode, 0));
emit_move_insn (gen_rtx_REG (QImode, 21), addr_hi8);
// Load with code from libgcc.
-insn = emit_insn (gen_xload__libgcc ());
+rtx_insn *insn = emit_insn (gen_xload__libgcc ());
set_mem_addr_space (SET_SRC (single_set (insn)), as);
// Move to destination.
@@ -1704,7 +1703,7 @@
"reload_completed"
"sub %A0,%2\;sbc %B0,%B0"
[(set_attr "length" "2")])
-
+
(define_insn_and_split "*addhi3_sp"
[(set (match_operand:HI 1 "stack_register_operand" "=q")
(plus:HI (match_operand:HI 2 "stack_register_operand" "q")
@@ -2169,8 +2168,8 @@
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0)
- (minus:HI (match_dup 1)
-(sign_extend:HI (match_dup 2
+ (minus:HI (match_dup 1)
+ (sign_extend:HI (match_dup 2
(clobber (reg:CC REG_CC))])])
@@ -2506,7 +2505,7 @@
"&& reload_completed"
[(parallel [(set (reg:HI 24)
(mult:HI (zero_extend:HI (reg:QI 22))
- (zero_extend:HI (reg:QI 24
+(zero_extend:HI (reg:QI 24
(clobber (reg:QI 21))
(clobber (reg:HI 22))
(clobber (reg:CC REG_CC))])])
@@ -2890,7 +2889,7 @@
;; Special case of a += 2*b as frequently seen with accesses to int arrays.
;; This is shorter, faster than MUL and has lower register pressure.
-
+;; See also "*addhi3_zero_extend.ashift1".
(define_insn_and_split "*umaddqihi4.2"
[(set (match_operand:HI 0 "register_operand"
"=r")
(plus:HI (mult:HI (zero_extend:HI (match_operand:QI 1
"register_operand" "r"))
@@ -3356,12 +3355,14 @@
? "mul %A1,%A1\;movw %0,r0\;mul %A1,%B1\;add %B0,r0\;add
%B0,r0\;clr r1"
: "mul %A1,%A2\;movw %0,r0\;mul %A1,%B2\;add %B0,r0\;mul
%B1,%A2\;add %B0,r0\;clr r1";
}
- [(set_attr "length" "7")])
+ [(set (attr "length")
+(symbol_ref ("7 - (REGNO (operands[1]) == REGNO (operands[2]))")))])
(define_expand "mulhi3_call"
[(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
(set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
- (parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
+ (parallel [(set (reg:HI 24)
+ (mult:HI (reg:HI 24) (reg:HI 22)))
(clobber (reg:HI 22))
(clobber (reg:QI 21))])
(set (match_operand:HI 0 "register_operand" "")
@@ -3373,19 +3374,22 @@
(define_insn_and_split "*mulhi3_call_split"
- [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
+ [(set (reg:HI
[gcc r14-9412] fwprop: Restore previous behavior for forward propagation of RTL with MEMs [PR114284]
https://gcc.gnu.org/g:3e3e4156a5f93e6d62101594ca6660ee9ce9c10e
commit r14-9412-g3e3e4156a5f93e6d62101594ca6660ee9ce9c10e
Author: Jakub Jelinek
Date: Sat Mar 9 13:04:26 2024 +0100
fwprop: Restore previous behavior for forward propagation of RTL with MEMs
[PR114284]
Before the recent PR111267 r14-8319 fwprop changes, fwprop would never try
to propagate what was not considered PROFITABLE, where the profitable part
actually was partly about profitability, partly about very good reasons
not to actually propagate and partly for cases where propagation is
completely incorrect.
In particular, classify_result has:
/* Allow (subreg (mem)) -> (mem) simplifications with the following
exceptions:
1) Propagating (mem)s into multiple uses is not profitable.
2) Propagating (mem)s across EBBs may not be profitable if the source
EBB
runs less frequently.
3) Propagating (mem)s into paradoxical (subreg)s is not profitable.
4) Creating new (mem/v)s is not correct, since DCE will not remove the
old
ones. */
if (single_use_p
&& single_ebb_p
&& SUBREG_P (old_rtx)
&& !paradoxical_subreg_p (old_rtx)
&& MEM_P (new_rtx)
&& !MEM_VOLATILE_P (new_rtx))
return PROFITABLE;
and didn't mark any other MEM_P (new_rtx) or rtxes which contain
a MEM in its subrtxes as PROFITABLE. Now, since r14-8319 profitable_p
method has been renamed to likely_profitable_p and has just a minor role.
Now, rule 4) above is something that isn't about profitability, but about
correct behavior, if you propagate mem/v, the code is miscompiled.
This particular case has been fixed elsewhere by Haochen in r14-9379.
But I think even the 1) and 2) and maybe 3) are a strong don't do it,
don't rely solely on rtx costs, increasing the number of loads of the same
memory, even when cached, is undesirable, canceling load hoisting can
be undesirable as well.
So, the following patch restores previous behavior of src contains any MEMs,
in that case likely_profitable_p () is taken as the old profitable_p ()
as a requirement rather than just a hint. For propagation of something
which doesn't load from memory this keeps the r14-8319 behavior.
2024-03-09 Jakub Jelinek
PR target/114284
* fwprop.cc (try_fwprop_subst_pattern): Don't propagate
src containing MEMs unless prop.likely_profitable_p ().
Diff:
---
gcc/fwprop.cc | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/fwprop.cc b/gcc/fwprop.cc
index cb6fd6700ca..de543923b92 100644
--- a/gcc/fwprop.cc
+++ b/gcc/fwprop.cc
@@ -451,6 +451,7 @@ try_fwprop_subst_pattern (obstack_watermark ,
insn_change _change,
if (!prop.likely_profitable_p ()
&& (prop.changed_mem_p ()
+ || contains_mem_rtx_p (src)
|| use_insn->is_asm ()
|| !single_set (use_rtl)))
{
[gcc r14-9411] LoongArch: Emit R_LARCH_RELAX for TLS IE with non-extreme code model to allow the IE to LE linker re
https://gcc.gnu.org/g:42cd49aa48c7ca99e8d5e91ce582d41fdb75f3fc
commit r14-9411-g42cd49aa48c7ca99e8d5e91ce582d41fdb75f3fc
Author: Xi Ruoyao
Date: Fri Jan 26 18:28:32 2024 +0800
LoongArch: Emit R_LARCH_RELAX for TLS IE with non-extreme code model to
allow the IE to LE linker relaxation
In Binutils we need to make IE to LE relaxation only allowed when there
is an R_LARCH_RELAX after R_LARCH_TLE_IE_PC_{HI20,LO12} so an invalid
"partial" relaxation won't happen with the extreme code model. So if we
are emitting %ie_pc_{hi20,lo12} in a non-extreme code model, emit an
R_LARCH_RELAX to allow the relaxation. The IE to LE relaxation does not
require the pcalau12i and the ld instruction to be adjacent, so we don't
need to limit ourselves to use the macro.
For the distro maintainers backporting changes: this change depends on
r14-8721, without r14-8721 R_LARCH_RELAX can be emitted mistakenly in
the extreme code model.
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
Support 'Q' for R_LARCH_RELAX for TLS IE.
(loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS
IE.
* config/loongarch/loongarch.md (ld_from_got): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/tls-ie-relax.c: New test.
* gcc.target/loongarch/tls-ie-norelax.c: New test.
* gcc.target/loongarch/tls-ie-extreme.c: New test.
Diff:
---
gcc/config/loongarch/loongarch.cc | 15 ++-
gcc/config/loongarch/loongarch.md | 2 +-
gcc/testsuite/gcc.target/loongarch/tls-ie-extreme.c | 5 +
gcc/testsuite/gcc.target/loongarch/tls-ie-norelax.c | 5 +
gcc/testsuite/gcc.target/loongarch/tls-ie-relax.c | 11 +++
5 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/gcc/config/loongarch/loongarch.cc
b/gcc/config/loongarch/loongarch.cc
index 0428b6e65d5..70e31bb831c 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -4981,7 +4981,7 @@ loongarch_output_move (rtx dest, rtx src)
if (type == SYMBOL_TLS_LE)
return "lu12i.w\t%0,%h1";
else
- return "pcalau12i\t%0,%h1";
+ return "%Q1pcalau12i\t%0,%h1";
}
if (src_code == CONST_INT)
@@ -6145,6 +6145,7 @@ loongarch_print_operand_reloc (FILE *file, rtx op, bool
hi64_part,
'L' Print the low-part relocation associated with OP.
'm' Print one less than CONST_INT OP in decimal.
'N' Print the inverse of the integer branch condition for comparison OP.
+ 'Q' Print R_LARCH_RELAX for TLS IE.
'r' Print address 12-31bit relocation associated with OP.
'R' Print address 32-51bit relocation associated with OP.
'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
@@ -6282,6 +6283,18 @@ loongarch_print_operand (FILE *file, rtx op, int letter)
letter);
break;
+case 'Q':
+ if (!TARGET_LINKER_RELAXATION)
+ break;
+
+ if (code == HIGH)
+ op = XEXP (op, 0);
+
+ if (loongarch_classify_symbolic_expression (op) == SYMBOL_TLS_IE)
+ fprintf (file, ".reloc\t.,R_LARCH_RELAX\n\t");
+
+ break;
+
case 'r':
loongarch_print_operand_reloc (file, op, false /* hi64_part */,
true /* lo_reloc */);
diff --git a/gcc/config/loongarch/loongarch.md
b/gcc/config/loongarch/loongarch.md
index f3b5c641fce..525e1e82183 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -2620,7 +2620,7 @@
(match_operand:P 2 "symbolic_operand")))]
UNSPEC_LOAD_FROM_GOT))]
""
- "ld.\t%0,%1,%L2"
+ "%Q2ld.\t%0,%1,%L2"
[(set_attr "type" "move")]
)
diff --git a/gcc/testsuite/gcc.target/loongarch/tls-ie-extreme.c
b/gcc/testsuite/gcc.target/loongarch/tls-ie-extreme.c
new file mode 100644
index 000..00c545a3e8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/tls-ie-extreme.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mcmodel=extreme
-mexplicit-relocs=auto -mrelax" } */
+/* { dg-final { scan-assembler-not "R_LARCH_RELAX" { target tls_native } } } */
+
+#include "tls-ie-relax.c"
diff --git a/gcc/testsuite/gcc.target/loongarch/tls-ie-norelax.c
b/gcc/testsuite/gcc.target/loongarch/tls-ie-norelax.c
new file mode 100644
index 000..dd6bf3634a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/tls-ie-norelax.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcmodel=normal -mexplicit-relocs -mno-relax" } */
+/* { dg-final { scan-assembler-not "R_LARCH_RELAX" { target tls_native } } } */
+
+#include "tls-ie-relax.c"
diff --git a/gcc/testsuite/gcc.target/loongarch/tls-ie-relax.c
b/gcc/testsuite/gcc.target/loongarch/tls-ie-relax.c
new file mode 100644
[gcc r14-9410] AVR: Add cost computation for some insn combine patterns.
https://gcc.gnu.org/g:e8cc1f956b75a6bf74c5f5262ddced9451dcccac
commit r14-9410-ge8cc1f956b75a6bf74c5f5262ddced9451dcccac
Author: Georg-Johann Lay
Date: Sat Mar 9 10:00:44 2024 +0100
AVR: Add cost computation for some insn combine patterns.
gcc/
* config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
usum_widenqihi and add_zero_extend1.
[MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
sub+sign_extend.
* config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
Compute exact insn lengths.
(*usum_widenqihi3): Allow input operands to commute.
Diff:
---
gcc/config/avr/avr.cc | 40 +++-
gcc/config/avr/avr.md | 20 ++--
2 files changed, 49 insertions(+), 11 deletions(-)
diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc
index 1fa4b557f5d..00fce8da15f 100644
--- a/gcc/config/avr/avr.cc
+++ b/gcc/config/avr/avr.cc
@@ -12524,10 +12524,25 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int
outer_code,
return true;
}
+ // *usum_widenqihi
+ if (mode == HImode
+ && GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
+ && GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
+ {
+ *total = COSTS_N_INSNS (3);
+ return true;
+ }
+
if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
&& REG_P (XEXP (x, 1)))
{
- *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) - 1);
+ *total = COSTS_N_INSNS (GET_MODE_SIZE (mode));
+ return true;
+ }
+ if (REG_P (XEXP (x, 0))
+ && GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
+ {
+ *total = COSTS_N_INSNS (GET_MODE_SIZE (mode));
return true;
}
@@ -12610,6 +12625,29 @@ avr_rtx_costs_1 (rtx x, machine_mode mode, int
outer_code,
return true;
case MINUS:
+ // *udiff_widenqihi
+ if (mode == HImode
+ && GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
+ && GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
+ {
+ *total = COSTS_N_INSNS (2);
+ return true;
+ }
+ // *sub3_zero_extend1
+ if (REG_P (XEXP (x, 0))
+ && GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
+ {
+ *total = COSTS_N_INSNS (GET_MODE_SIZE (mode));
+ return true;
+ }
+ // *sub3.sign_extend2
+ if (REG_P (XEXP (x, 0))
+ && GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
+ {
+ *total = COSTS_N_INSNS (2 + GET_MODE_SIZE (mode));
+ return true;
+ }
+
if (AVR_HAVE_MUL
&& QImode == mode
&& register_operand (XEXP (x, 0), QImode)
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 52b6cff4a8b..59ec724f7da 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -1588,12 +1588,10 @@
""
"#"
"&& reload_completed"
- [(parallel
- [(set (match_dup 0)
-(plus:HI
- (sign_extend:HI (match_dup 1))
- (match_dup 2)))
- (clobber (reg:CC REG_CC))])])
+ [(parallel [(set (match_dup 0)
+ (plus:HI (sign_extend:HI (match_dup 1))
+(match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
(define_insn "*addhi3.sign_extend1"
@@ -1607,7 +1605,8 @@
? "mov __tmp_reg__,%1\;add %A0,%1\;adc %B0,__zero_reg__\;sbrc
__tmp_reg__,7\;dec %B0"
: "add %A0,%1\;adc %B0,__zero_reg__\;sbrc %1,7\;dec %B0";
}
- [(set_attr "length" "5")])
+ [(set (attr "length")
+(symbol_ref ("4 + reg_overlap_mentioned_p (operands[0],
operands[1])")))])
(define_insn_and_split "*addhi3_zero_extend.const_split"
[(set (match_operand:HI 0 "register_operand" "=d")
@@ -1665,7 +1664,7 @@
(define_insn_and_split "*usum_widenqihi3_split"
[(set (match_operand:HI 0 "register_operand" "=r")
-(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
+(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
(zero_extend:HI (match_operand:QI 2 "register_operand"
"r"]
""
"#"
@@ -1678,7 +1677,7 @@
(define_insn "*usum_widenqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
-(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
+(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
(zero_extend:HI (match_operand:QI 2 "register_operand"
"r"
(clobber (reg:CC REG_CC))]
"reload_completed"
@@ -2186,7 +2185,8 @@
? "mov __tmp_reg__,%2\;sub %A0,%2\;sbc %B0,__zero_reg__\;sbrc
__tmp_reg__,7\;inc %B0"
: "sub %A0,%2\;sbc %B0,__zero_reg__\;sbrc %2,7\;inc %B0";
}
- [(set_attr "length" "5")])
+ [(set (attr "length")
+(symbol_ref ("4 + reg_overlap_mentioned_p (operands[0],
operands[2])")))])
;; "subsi3"
;; "subsq3" "subusq3"
[gcc r14-9409] i386: Regenerate i386.opt.urls
https://gcc.gnu.org/g:e9753f4b633608ae4adc6efb747e638783cd6196 commit r14-9409-ge9753f4b633608ae4adc6efb747e638783cd6196 Author: Jakub Jelinek Date: Sat Mar 9 09:37:07 2024 +0100 i386: Regenerate i386.opt.urls When I've added the -mnoreturn-no-callee-saved-registers option to i386.opt, I forgot to regenerate i386.opt.urls and Mark's CI kindly reminded me of that. Fixed thusly. 2024-03-09 Jakub Jelinek * config/i386/i386.opt.urls: Regenerate. Diff: --- gcc/config/i386/i386.opt.urls | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls index 0f2015610ae..fa821eba200 100644 --- a/gcc/config/i386/i386.opt.urls +++ b/gcc/config/i386/i386.opt.urls @@ -184,6 +184,9 @@ UrlSuffix(gcc/x86-Options.html#index-mmove-max) mstore-max= UrlSuffix(gcc/x86-Options.html#index-mstore-max) +mnoreturn-no-callee-saved-registers +UrlSuffix(gcc/x86-Options.html#index-mnoreturn-no-callee-saved-registers) + m32 UrlSuffix(gcc/x86-Options.html#index-m32-2)
