[gcc(refs/users/meissner/heads/work164-test)] Update ChangeLog.*
https://gcc.gnu.org/g:f8aff8ceb76e648416011419087304701c6e8911 commit f8aff8ceb76e648416011419087304701c6e8911 Author: Michael Meissner Date: Fri Apr 12 22:48:06 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.test | 16 1 file changed, 16 insertions(+) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test index fcdb9e19c32..8b12e86f37b 100644 --- a/gcc/ChangeLog.test +++ b/gcc/ChangeLog.test @@ -1,3 +1,19 @@ + Branch work164-test, patch #302 + +Remove moves for tar register. + +2024-04-12 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.md (movcc_): Remove tar register moves. + (movsf_hardfloa): Likewise. + (movsd_hardfloa): Likewise. + (mov_hardfloat64): Likewise. + (mov_softfloat6): Likewise. + (_): Likewise. + (tf_): Likewise. + Branch work164-test, patch #301 Update debug register number for the tar register.
[gcc(refs/users/meissner/heads/work164-test)] Remove moves for tar register.
https://gcc.gnu.org/g:42d3d30eb66b4fb8d0a1ce0b96f3fbf24728e18e commit 42d3d30eb66b4fb8d0a1ce0b96f3fbf24728e18e Author: Michael Meissner Date: Fri Apr 12 22:45:36 2024 -0400 Remove moves for tar register. 2024-04-12 Michael Meissner gcc/ * config/rs6000/rs6000.md (movcc_): Remove tar register moves. (movsf_hardfloa): Likewise. (movsd_hardfloa): Likewise. (mov_hardfloat64): Likewise. (mov_softfloat6): Likewise. (_): Likewise. (tf_): Likewise. Diff: --- gcc/config/rs6000/rs6000.md | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 404ff3d9cb2..d422e1c184b 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8120,9 +8120,9 @@ (define_insn "*movcc_" [(set (match_operand:CC_any 0 "nonimmediate_operand" - "=y,x,?y,y,r,r,r,r, r,*wt*c*l,r,m") + "=y,x,?y,y,r,r,r,r, r,*c*l,r,m") (match_operand:CC_any 1 "general_operand" - " y,r, r,O,x,y,r,I,*h, r,m,r"))] + " y,r, r,O,x,y,r,I,*h,r,m,r"))] "register_operand (operands[0], mode) || register_operand (operands[1], mode)" "@ @@ -8210,7 +8210,7 @@ [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, v, wa,m, wY, Z, m, wa, !r,f, wa, - !r,*wt*c*l, !r, *h,wa") + !r,*c*l, !r, *h,wa") (match_operand:SF 1 "input_operand" "m, m, wY, Z, f, v, wa,r, j, j, f, wa, @@ -8256,7 +8256,7 @@ (define_insn "movsd_hardfloat" [(set (match_operand:SD 0 "nonimmediate_operand" "=!r, d, m, ?Z,?d,?r, - f, !r,*wt*c*l, !r,*h") + f, !r,*c*l, !r,*h") (match_operand:SD 1 "input_operand" "m, ?Z,r, wx,r, d, f, r, r, *h,0"))] @@ -8286,7 +8286,7 @@ ;; LIS G-const. F/n-const NOP (define_insn "*mov_softfloat" [(set (match_operand:FMOVE32 0 "nonimmediate_operand" - "=r, *wt*c*l, r, r, m, r, + "=r, *c*l, r, r, m, r, r, r, r, *h") (match_operand:FMOVE32 1 "input_operand" @@ -8600,7 +8600,7 @@ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, , wY, ,Z, , , !r, - YZ, r, !r, *wt*c*l*wt, !r, + YZ, r, !r, *c*l, !r, *h, r, , wa") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , @@ -8652,7 +8652,7 @@ (define_insn "*mov_softfloat64" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" - "=Y, r, r, *wt*c*l, r, r, + "=Y, r, r, *c*l,r, r, r, r, *h") (match_operand:FMOVE64 1 "input_operand" @@ -13698,7 +13698,7 @@ (const_int 1)) (label_ref (match_operand 0)) (pc))) - (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wa*wt*c*l") + (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*c*l") (plus:P (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "=X,,,")) @@ -13774,7 +13774,7 @@ (const_int 0)])) (label_ref (match_operand 0)) (pc))) - (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wa*wt*c*l") + (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wa*c*l") (plus:P (match_dup 1) (const_int -1))) (clobber (match_scratch:P 5 "=X,X,,r"))
[gcc r14-9951] aarch64: Enable +cssc for armv8.9-a
https://gcc.gnu.org/g:b18162759a6d464256b0195bc6447f0a1c9dd5dd
commit r14-9951-gb18162759a6d464256b0195bc6447f0a1c9dd5dd
Author: Andrew Carlotti
Date: Thu Apr 11 17:00:30 2024 +0100
aarch64: Enable +cssc for armv8.9-a
FEAT_CSSC is mandatory in the architecture from Armv8.9.
gcc/ChangeLog:
* config/aarch64/aarch64-arches.def: Add CSSC to V8_9A
dependencies.
Diff:
---
gcc/config/aarch64/aarch64-arches.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64-arches.def
b/gcc/config/aarch64/aarch64-arches.def
index 9bec30e9203..4634b272e28 100644
--- a/gcc/config/aarch64/aarch64-arches.def
+++ b/gcc/config/aarch64/aarch64-arches.def
@@ -39,7 +39,7 @@ AARCH64_ARCH("armv8.5-a", generic_armv8_a, V8_5A,
8, (V8_4A, SB, SSBS
AARCH64_ARCH("armv8.6-a", generic_armv8_a, V8_6A, 8, (V8_5A, I8MM,
BF16))
AARCH64_ARCH("armv8.7-a", generic_armv8_a, V8_7A, 8, (V8_6A))
AARCH64_ARCH("armv8.8-a", generic_armv8_a, V8_8A, 8, (V8_7A, MOPS))
-AARCH64_ARCH("armv8.9-a", generic_armv8_a, V8_9A, 8, (V8_8A))
+AARCH64_ARCH("armv8.9-a", generic_armv8_a, V8_9A, 8, (V8_8A, CSSC))
AARCH64_ARCH("armv8-r", generic_armv8_a, V8R , 8, (V8_4A))
AARCH64_ARCH("armv9-a", generic_armv9_a, V9A , 9, (V8_5A, SVE2))
AARCH64_ARCH("armv9.1-a", generic_armv9_a, V9_1A, 9, (V8_6A, V9A))
[gcc(refs/users/meissner/heads/work164-test)] Update ChangeLog.*
https://gcc.gnu.org/g:cc0ccb073996f9df58b7390b24478bc229ecfca7 commit cc0ccb073996f9df58b7390b24478bc229ecfca7 Author: Michael Meissner Date: Fri Apr 12 19:32:34 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.test | 11 +++ 1 file changed, 11 insertions(+) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test index 5ebe8ec4286..fcdb9e19c32 100644 --- a/gcc/ChangeLog.test +++ b/gcc/ChangeLog.test @@ -1,3 +1,14 @@ + Branch work164-test, patch #301 + +Update debug register number for the tar register. + +2024-04-12 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (rs6000_debugger_regno): Fix tar register + number. + Branch work164-test, patch #300 Add support for -mtar
[gcc(refs/users/meissner/heads/work164-test)] Update debug register number for the tar register.
https://gcc.gnu.org/g:6180d85c1ffa6273af5bde06c7fc258e130232b6 commit 6180d85c1ffa6273af5bde06c7fc258e130232b6 Author: Michael Meissner Date: Fri Apr 12 19:31:24 2024 -0400 Update debug register number for the tar register. 2024-04-12 Michael Meissner gcc/ * config/rs6000/rs6000.cc (rs6000_debugger_regno): Fix tar register number. Diff: --- gcc/config/rs6000/rs6000.cc | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 1aac21c4243..72e26dc2afd 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -24217,7 +24217,7 @@ rs6000_debugger_regno (unsigned int regno, unsigned int format) if (regno == CTR_REGNO) return 109; if (regno == TAR_REGNO) - return 112; + return 111; if (regno == CA_REGNO) return 101; /* XER */ /* Special handling for CR for .debug_frame: rs6000_emit_prologue has @@ -24235,7 +24235,7 @@ rs6000_debugger_regno (unsigned int regno, unsigned int format) /* These do not make much sense. */ if (regno == FRAME_POINTER_REGNUM) - return 111; + return FIRST_PSEUDO_REGISTER; if (regno == ARG_POINTER_REGNUM) return 67; if (regno == 64) @@ -24258,6 +24258,8 @@ rs6000_debugger_regno (unsigned int regno, unsigned int format) return 65; if (regno == CTR_REGNO) return 66; + if (regno == TAR_REGNO) +return 111; if (regno == CA_REGNO) return 76; /* XER */ if (CR_REGNO_P (regno))
[gcc(refs/users/meissner/heads/work164-test)] Update ChangeLog.*
https://gcc.gnu.org/g:9cf198d403a5281fb999be669b79f5914594c233 commit 9cf198d403a5281fb999be669b79f5914594c233 Author: Michael Meissner Date: Fri Apr 12 19:08:08 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.test | 195 - 1 file changed, 194 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test index 8ee53e57958..5ebe8ec4286 100644 --- a/gcc/ChangeLog.test +++ b/gcc/ChangeLog.test @@ -1,6 +1,199 @@ + Branch work164-test, patch #300 + +Add support for -mtar + +2024-04-12 Michael Meissner + +gcc/ + + * config/rs6000/constraints.md (h constraint): Add tar register to + documentation. + (wt constraint): New constraint. + * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add -mtar. + (POWERPC_MASKS): Likewise. + * config/rs6000/rs6000.cc (rs6000_reg_names): Add new tar register. + (alt_reg_names): Likewise. + (rs6000_debug_reg_global): Likewise. + (rs6000_init_hard_regno_mode_ok): Likewise. + (rs6000_option_override_internal): Likewise. + (rs6000_conditional_register_usage): Likewise. + (print_operand): Likewise. + (rs6000_debugger_regno): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Likewise. + (FiXED_REGISTERS): Likewise. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (reg_class): Add new TAR_REGS register class. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Likewise. + (r6000_reg_class_enum): Add RS6000_CONSTRAINT_wt. + (REG_NAMES): Add tar register. + * config/rs6000/rs6000.md (TAR_REGNO): New constant. + (movcc_): Add support for tar register. + (movsf_hardfloat): Likewise. + (movsf_hardfloat): Likewise. + (mov_softfloat): Likewise. + (mov_hardfloat64): Likewise. + (mov_softfloat6): Likewise. + (indirect_jump): Likewise. + (@indirect_jump_nospec): Likewise. + (@tablejump_absolute): Likewise. + (@tablejump_insn_nospec): Likewise. + (_): Likewise. + (tf_): Likewise. + * config/rs6000/rs6000.opt (-mtar): New option. + * doc/invoke.texi (RS/6000 options): Document -mtar. + + Branch work164-test, patch #10 from work164 + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-04-08 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + + Branch work164-test, patch #3 from work164 + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-04-08 Michael Meissner + +gcc/testsuite/ + + *
[gcc(refs/users/meissner/heads/work164-test)] Add support for -mtar
https://gcc.gnu.org/g:374cc9624abe4af886b159a2a0beefdc27cbac40
commit 374cc9624abe4af886b159a2a0beefdc27cbac40
Author: Michael Meissner
Date: Fri Apr 12 19:05:11 2024 -0400
Add support for -mtar
2024-04-12 Michael Meissner
gcc/
* config/rs6000/constraints.md (h constraint): Add tar register to
documentation.
(wt constraint): New constraint.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add -mtar.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_reg_names): Add new tar register.
(alt_reg_names): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_conditional_register_usage): Likewise.
(print_operand): Likewise.
(rs6000_debugger_regno): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Likewise.
(FiXED_REGISTERS): Likewise.
(CALL_REALLY_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(reg_class): Add new TAR_REGS register class.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(r6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.
(REG_NAMES): Add tar register.
* config/rs6000/rs6000.md (TAR_REGNO): New constant.
(movcc_): Add support for tar register.
(movsf_hardfloat): Likewise.
(movsf_hardfloat): Likewise.
(mov_softfloat): Likewise.
(mov_hardfloat64): Likewise.
(mov_softfloat6): Likewise.
(indirect_jump): Likewise.
(@indirect_jump_nospec): Likewise.
(@tablejump_absolute): Likewise.
(@tablejump_insn_nospec): Likewise.
(_): Likewise.
(tf_): Likewise.
* config/rs6000/rs6000.opt (-mtar): New option.
* doc/invoke.texi (RS/6000 options): Document -mtar.
Diff:
---
gcc/config/rs6000/constraints.md | 5 -
gcc/config/rs6000/rs6000-cpus.def | 4 +++-
gcc/config/rs6000/rs6000.cc | 36 +++-
gcc/config/rs6000/rs6000.h| 31 +++
gcc/config/rs6000/rs6000.md | 31 ---
gcc/config/rs6000/rs6000.opt | 4
gcc/doc/invoke.texi | 12 ++--
7 files changed, 87 insertions(+), 36 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 369a7b75042..14f0465d7ae 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -57,7 +57,7 @@
"@internal A compatibility alias for @code{wa}.")
(define_register_constraint "h" "SPECIAL_REGS"
- "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).")
+ "@internal A special register (@code{vrsave}, @code{ctr}, @code{lr} or
@code{tar}).")
(define_register_constraint "c" "CTR_REGS"
"The count register, @code{ctr}.")
@@ -91,6 +91,9 @@
"@internal Like @code{r}, if @option{-mpowerpc64} is used; otherwise,
@code{NO_REGS}.")
+(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
+ "The tar register, @code{tar}.")
+
(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
"@internal Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise,
@code{NO_REGS}.")
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 47365534af8..7ea3ce09c8d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -52,7 +52,8 @@
| OPTION_MASK_DIRECT_MOVE \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_QUAD_MEMORY \
-| OPTION_MASK_QUAD_MEMORY_ATOMIC)
+| OPTION_MASK_QUAD_MEMORY_ATOMIC \
+| OPTION_MASK_TAR)
/* ISA masks setting fusion options. */
#define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \
@@ -159,6 +160,7 @@
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL\
+| OPTION_MASK_TAR \
| OPTION_MASK_VSX)
#endif
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 2921e72aea8..1aac21c4243 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1224,8 +1224,8 @@ char rs6000_reg_names[][8] =
"lr", "ctr", "ca", "ap",
/* cr0..cr7 */
[gcc r14-9950] c++: ICE with temporary of class type in array DMI [PR109966]
https://gcc.gnu.org/g:6039925631780741ba77666ef2ef743aa2a925a8
commit r14-9950-g6039925631780741ba77666ef2ef743aa2a925a8
Author: Marek Polacek
Date: Mon Mar 11 17:45:55 2024 -0400
c++: ICE with temporary of class type in array DMI [PR109966]
This ICE started with the fairly complicated r13-765. We crash in
gimplify_var_or_parm_decl because a stray VAR_DECL leaked there.
The problem is ultimately that potential_prvalue_result_of wasn't
correctly handling arrays and replace_placeholders_for_class_temp_r
replaced a PLACEHOLDER_EXPR in a TARGET_EXPR which is used in the
context of copy elision. If I have
M m[2] = { M{""}, M{""} };
then we don't invoke the M(const M&) copy-ctor.
One part of the fix is to use TARGET_EXPR_ELIDING_P rather than
potential_prvalue_result_of. That unfortunately doesn't handle the
case like
struct N { N(M); };
N arr[2] = { M{""}, M{""} };
because TARGET_EXPRs that initialize a function argument are not
marked TARGET_EXPR_ELIDING_P even though gimplify_arg drops such
TARGET_EXPRs on the floor. We can use a pset to avoid replacing
placeholders in them.
I made an attempt to use set_target_expr_eliding in
convert_for_arg_passing but that regressed constexpr-diag1.C, and does
not seem like a prudent change in stage 4 anyway.
PR c++/109966
gcc/cp/ChangeLog:
* typeck2.cc (potential_prvalue_result_of): Remove.
(replace_placeholders_for_class_temp_r): Check
TARGET_EXPR_ELIDING_P.
Use a pset. Don't replace_placeholders in TARGET_EXPRs that
initialize
a function argument.
gcc/testsuite/ChangeLog:
* g++.dg/cpp1y/nsdmi-aggr20.C: New test.
* g++.dg/cpp1y/nsdmi-aggr21.C: New test.
Diff:
---
gcc/cp/typeck2.cc | 55 +---
gcc/testsuite/g++.dg/cpp1y/nsdmi-aggr20.C | 17 +
gcc/testsuite/g++.dg/cpp1y/nsdmi-aggr21.C | 59 +++
3 files changed, 92 insertions(+), 39 deletions(-)
diff --git a/gcc/cp/typeck2.cc b/gcc/cp/typeck2.cc
index 31198b2f9f5..2985bfdf9ec 100644
--- a/gcc/cp/typeck2.cc
+++ b/gcc/cp/typeck2.cc
@@ -1399,41 +1399,6 @@ digest_init_flags (tree type, tree init, int flags,
tsubst_flags_t complain)
return digest_init_r (type, init, 0, flags, complain);
}
-/* Return true if SUBOB initializes the same object as FULL_EXPR.
- For instance:
-
- A a = A{}; // initializer
- A a = (A{});// initializer
- A a = (1, A{}); // initializer
- A a = true ? A{} : A{}; // initializer
- auto x = A{}.x; // temporary materialization
- auto x = foo(A{}); // temporary materialization
-
- FULL_EXPR is the whole expression, SUBOB is its TARGET_EXPR subobject. */
-
-static bool
-potential_prvalue_result_of (tree subob, tree full_expr)
-{
- if (subob == full_expr)
-return true;
- else if (TREE_CODE (full_expr) == TARGET_EXPR)
-{
- tree init = TARGET_EXPR_INITIAL (full_expr);
- if (TREE_CODE (init) == COND_EXPR)
- return (potential_prvalue_result_of (subob, TREE_OPERAND (init, 1))
- || potential_prvalue_result_of (subob, TREE_OPERAND (init, 2)));
- else if (TREE_CODE (init) == COMPOUND_EXPR)
- return potential_prvalue_result_of (subob, TREE_OPERAND (init, 1));
- /* ??? I don't know if this can be hit. */
- else if (TREE_CODE (init) == PAREN_EXPR)
- {
- gcc_checking_assert (false);
- return potential_prvalue_result_of (subob, TREE_OPERAND (init, 0));
- }
-}
- return false;
-}
-
/* Callback to replace PLACEHOLDER_EXPRs in a TARGET_EXPR (which isn't used
in the context of guaranteed copy elision). */
@@ -1441,11 +1406,13 @@ static tree
replace_placeholders_for_class_temp_r (tree *tp, int *, void *data)
{
tree t = *tp;
- tree full_expr = *static_cast(data);
+ auto pset = static_cast *>(data);
/* We're looking for a TARGET_EXPR nested in the whole expression. */
if (TREE_CODE (t) == TARGET_EXPR
- && !potential_prvalue_result_of (t, full_expr))
+ /* That serves as temporary materialization, not an initializer. */
+ && !TARGET_EXPR_ELIDING_P (t)
+ && !pset->add (t))
{
tree init = TARGET_EXPR_INITIAL (t);
while (TREE_CODE (init) == COMPOUND_EXPR)
@@ -1460,6 +1427,16 @@ replace_placeholders_for_class_temp_r (tree *tp, int *,
void *data)
gcc_checking_assert (!find_placeholders (init));
}
}
+ /* TARGET_EXPRs initializing function arguments are not marked as eliding,
+ even though gimplify_arg drops them on the floor. Don't go replacing
+ placeholders in them. */
+ else if (TREE_CODE (t) == CALL_EXPR || TREE_CODE (t) == AGGR_INIT_EXPR)
+for (int i = 0; i < call_expr_nargs (t); ++i)
+ {
+ tree arg
gcc-wwwdocs branch master updated. d18a80a52a7ec2edd7ef9a583d8920d61c0b48e5
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via d18a80a52a7ec2edd7ef9a583d8920d61c0b48e5 (commit) from 3ca51fec661f3340fe308662405e602bcf3fe8d7 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log - commit d18a80a52a7ec2edd7ef9a583d8920d61c0b48e5 Author: Marek Polacek Date: Fri Apr 12 18:02:35 2024 -0400 cxx-dr-status: Update CWG 1996 diff --git a/htdocs/projects/cxx-dr-status.html b/htdocs/projects/cxx-dr-status.html index 24c54cfd..a5f45359 100644 --- a/htdocs/projects/cxx-dr-status.html +++ b/htdocs/projects/cxx-dr-status.html @@ -14005,8 +14005,9 @@ https://wg21.link/cwg1996;>1996 drafting Reference list-initialization ignores conversion functions - - - https://gcc.gnu.org/PR;>PR90390 + 14 + https://gcc.gnu.org/PR90390;>PR90390, + https://gcc.gnu.org/PR113141;>PR113141 https://wg21.link/cwg1997;>1997 @@ -19928,7 +19929,7 @@ This page is currently maintained by mailto:pola...@redhat.com;>pola...@redhat.com. Last update: -Fri Apr 12 02:22:38 PM EDT 2024 +Fri Apr 12 06:02:20 PM EDT 2024 --- Summary of changes: htdocs/projects/cxx-dr-status.html | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) hooks/post-receive -- gcc-wwwdocs
[gcc r14-9949] rs6000: Add OPTION_MASK_POWER8 [PR101865]
https://gcc.gnu.org/g:aa57af93ba22865be747f926e4e5f219e7f8758a commit r14-9949-gaa57af93ba22865be747f926e4e5f219e7f8758a Author: Will Schmidt Date: Fri Apr 12 14:55:16 2024 -0500 rs6000: Add OPTION_MASK_POWER8 [PR101865] The bug in PR101865 is the _ARCH_PWR8 predefine macro is conditional upon TARGET_DIRECT_MOVE, which can be false for some -mcpu=power8 compiles if the -mno-altivec or -mno-vsx options are used. The solution here is to create a new OPTION_MASK_POWER8 mask that is true for -mcpu=power8, regardless of Altivec or VSX enablement. Unfortunately, the only way to create an OPTION_MASK_* mask is to create a new option, which we have done here, but marked it as WarnRemoved since we do not want users using it. For stage1, we will look into how we can create ISA mask flags for use in the compiler without the need for explicit options. 2024-04-12 Will Schmidt Peter Bergner gcc/ PR target/101865 * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use TARGET_POWER8. * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use OPTION_MASK_POWER8. * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_POWER8. (ISA_2_7_MASKS_SERVER): Likewise. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Update comment. Use OPTION_MASK_POWER8 and TARGET_POWER8. * config/rs6000/rs6000.h (TARGET_SYNC_HI_QI): Use TARGET_POWER8. * config/rs6000/rs6000.md (define_attr "isa"): Add p8. (define_attr "enabled"): Handle it. (define_insn "prefetch"): Use TARGET_POWER8. * config/rs6000/rs6000.opt (mpower8-internal): New. gcc/testsuite/ PR target/101865 * gcc.target/powerpc/predefine-p7-novsx.c: New test. * gcc.target/powerpc/predefine-p8-noaltivec-novsx.c: New test. * gcc.target/powerpc/predefine-p8-noaltivec.c: New test. * gcc.target/powerpc/predefine-p8-novsx.c: New test. * gcc.target/powerpc/predefine-p8-pragma-vsx.c: New test. * gcc.target/powerpc/predefine-p9-novsx.c: New test. Diff: --- gcc/config/rs6000/rs6000-builtin.cc| 2 +- gcc/config/rs6000/rs6000-c.cc | 2 +- gcc/config/rs6000/rs6000-cpus.def | 2 + gcc/config/rs6000/rs6000.cc| 7 +- gcc/config/rs6000/rs6000.h | 2 +- gcc/config/rs6000/rs6000.md| 8 +- gcc/config/rs6000/rs6000.opt | 4 + .../gcc.target/powerpc/predefine-p7-novsx.c| 22 + .../powerpc/predefine-p8-noaltivec-novsx.c | 26 ++ .../gcc.target/powerpc/predefine-p8-noaltivec.c| 26 ++ .../gcc.target/powerpc/predefine-p8-novsx.c| 26 ++ .../gcc.target/powerpc/predefine-p8-pragma-vsx.c | 101 + .../gcc.target/powerpc/predefine-p9-novsx.c| 26 ++ 13 files changed, 245 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index e7d6204074c..320affd79e3 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -165,7 +165,7 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) case ENB_P7_64: return TARGET_POPCNTD && TARGET_POWERPC64; case ENB_P8: - return TARGET_DIRECT_MOVE; + return TARGET_POWER8; case ENB_P8V: return TARGET_P8_VECTOR; case ENB_P9: diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 647f20de7f2..bd493ab87c5 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -429,7 +429,7 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); if ((flags & OPTION_MASK_POPCNTD) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); - if ((flags & OPTION_MASK_P8_VECTOR) != 0) + if ((flags & OPTION_MASK_POWER8) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8"); if ((flags & OPTION_MASK_MODULO) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9"); diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 45dd5a85901..6ee678e69c3 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -47,6 +47,7 @@ fusion here, instead set it in rs6000.cc if we are tuning for a power8 system. */ #define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \ +| OPTION_MASK_POWER8 \ | OPTION_MASK_P8_VECTOR\ | OPTION_MASK_CRYPTO
[gcc r14-9948] c++/modules: local type merging [PR99426]
https://gcc.gnu.org/g:716af95fd454871473c4b118b8412b6a68459b75
commit r14-9948-g716af95fd454871473c4b118b8412b6a68459b75
Author: Patrick Palka
Date: Fri Apr 12 15:50:04 2024 -0400
c++/modules: local type merging [PR99426]
One known missing piece in the modules implementation is merging of a
streamed-in local type (class or enum) with the corresponding in-TU
version of the local type. This missing piece turns out to cause a
hard-to-reduce use-after-free GC issue due to the entity_ary not being
marked as a GC root (deliberately), and manifests as a serialization
error on stream-in as in PR99426 (see comment #6 for a reduction). It's
also reproducible on trunk when running the xtreme-header tests without
-fno-module-lazy.
This patch implements this missing piece, making us merge such local
types according to their position within the containing function's
definition, analogous to how we merge FIELD_DECLs of a class according
to their index in the TYPE_FIELDS list.
PR c++/99426
gcc/cp/ChangeLog:
* module.cc (merge_kind::MK_local_type): New enumerator.
(merge_kind_name): Update.
(trees_out::chained_decls): Move BLOCK-specific handling
of DECL_LOCAL_DECL_P decls to ...
(trees_out::core_vals) : ... here. Stream
BLOCK_VARS manually.
(trees_in::core_vals) : Stream BLOCK_VARS
manually. Handle deduplicated local types..
(trees_out::key_local_type): Define.
(trees_in::key_local_type): Define.
(trees_out::get_merge_kind) : Return
MK_local_type for a local type.
(trees_out::key_mergeable) : Use
key_local_type.
(trees_in::key_mergeable) : Likewise.
(trees_in::is_matching_decl): Be flexible with type mismatches
for local entities.
(trees_in::register_duplicate): Also register the
DECL_TEMPLATE_RESULT of a TEMPLATE_DECL as a duplicate.
(depset_cmp): Return 0 for equal IDENTIFIER_HASH_VALUEs.
gcc/testsuite/ChangeLog:
* g++.dg/modules/merge-17.h: New test.
* g++.dg/modules/merge-17_a.H: New test.
* g++.dg/modules/merge-17_b.C: New test.
* g++.dg/modules/xtreme-header-7_a.H: New test.
* g++.dg/modules/xtreme-header-7_b.C: New test.
Reviewed-by: Jason Merrill
Diff:
---
gcc/cp/module.cc | 180 +++
gcc/testsuite/g++.dg/modules/merge-17.h | 58
gcc/testsuite/g++.dg/modules/merge-17_a.H| 3 +
gcc/testsuite/g++.dg/modules/merge-17_b.C| 3 +
gcc/testsuite/g++.dg/modules/xtreme-header-7_a.H | 4 +
gcc/testsuite/g++.dg/modules/xtreme-header-7_b.C | 5 +
6 files changed, 222 insertions(+), 31 deletions(-)
diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc
index ad1b6bf5ca4..9917a6abe4f 100644
--- a/gcc/cp/module.cc
+++ b/gcc/cp/module.cc
@@ -2758,6 +2758,7 @@ enum merge_kind
MK_enum, /* Found by CTX, & 1stMemberNAME. */
MK_keyed, /* Found by key & index. */
+ MK_local_type, /* Found by CTX, index. */
MK_friend_spec, /* Like named, but has a tmpl & args too. */
MK_local_friend, /* Found by CTX, index. */
@@ -2784,7 +2785,7 @@ static char const *const merge_kind_name[MK_hwm] =
"unique", "named", "field", "vtable", /* 0...3 */
"asbase", "partial", "enum", "attached", /* 4...7 */
-"friend spec", "local friend", NULL, NULL, /* 8...11 */
+"local type", "friend spec", "local friend", NULL, /* 8...11 */
NULL, NULL, NULL, NULL,
"type spec", "type tmpl spec", /* 16,17 type (template). */
@@ -2913,6 +2914,7 @@ public:
unsigned binfo_mergeable (tree *);
private:
+ tree key_local_type (const merge_key&, tree, tree);
uintptr_t *find_duplicate (tree existing);
void register_duplicate (tree decl, tree existing);
/* Mark as an already diagnosed bad duplicate. */
@@ -3071,6 +3073,7 @@ public:
void binfo_mergeable (tree binfo);
private:
+ void key_local_type (merge_key&, tree, tree);
bool decl_node (tree, walk_kind ref);
void type_node (tree);
void tree_value (tree);
@@ -4937,18 +4940,7 @@ void
trees_out::chained_decls (tree decls)
{
for (; decls; decls = DECL_CHAIN (decls))
-{
- if (VAR_OR_FUNCTION_DECL_P (decls)
- && DECL_LOCAL_DECL_P (decls))
- {
- /* Make sure this is the first encounter, and mark for
-walk-by-value. */
- gcc_checking_assert (!TREE_VISITED (decls)
- && !DECL_TEMPLATE_INFO (decls));
- mark_by_value (decls);
- }
- tree_node (decls);
-}
+tree_node (decls);
tree_node (NULL_TREE);
}
@@ -6198,7 +6190,21 @@ trees_out::core_vals (tree t)
/* DECL_LOCAL_DECL_P decls are first encountered here
[gcc r14-9946] c++: reference list-init, conversion fn [PR113141]
https://gcc.gnu.org/g:d435571b54b02946c97b5b24f20e5a7058fd96a1
commit r14-9946-gd435571b54b02946c97b5b24f20e5a7058fd96a1
Author: Jason Merrill
Date: Fri Apr 12 13:24:44 2024 -0400
c++: reference list-init, conversion fn [PR113141]
The original testcase in PR113141 is an instance of CWG1996; the standard
fails to consider conversion functions when initializing a reference
directly from an initializer-list of one element, but then does consider
them when initializing a temporary. I have a proposed fix for this defect,
which is implemented here.
DR 1996
PR c++/113141
gcc/cp/ChangeLog:
* call.cc (reference_binding): Check direct binding from
a single-element list.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/initlist-ref1.C: New test.
* g++.dg/cpp0x/initlist-ref2.C: New test.
* g++.dg/cpp0x/initlist-ref3.C: New test.
Co-authored-by: Patrick Palka
Diff:
---
gcc/cp/call.cc | 21 +
gcc/testsuite/g++.dg/cpp0x/initlist-ref1.C | 16
gcc/testsuite/g++.dg/cpp0x/initlist-ref2.C | 10 ++
gcc/testsuite/g++.dg/cpp0x/initlist-ref3.C | 13 +
4 files changed, 56 insertions(+), 4 deletions(-)
diff --git a/gcc/cp/call.cc b/gcc/cp/call.cc
index 9568b5eb2c4..15b5647298e 100644
--- a/gcc/cp/call.cc
+++ b/gcc/cp/call.cc
@@ -1596,7 +1596,9 @@ standard_conversion (tree to, tree from, tree expr, bool
c_cast_p,
return conv;
}
-/* Returns nonzero if T1 is reference-related to T2. */
+/* Returns nonzero if T1 is reference-related to T2.
+
+ This is considered when a reference to T1 is initialized by a T2. */
bool
reference_related_p (tree t1, tree t2)
@@ -1757,6 +1759,7 @@ reference_binding (tree rto, tree rfrom, tree expr, bool
c_cast_p, int flags,
}
bool copy_list_init = false;
+ bool single_list_conv = false;
if (expr && BRACE_ENCLOSED_INITIALIZER_P (expr))
{
maybe_warn_cpp0x (CPP0X_INITIALIZER_LISTS);
@@ -1783,6 +1786,11 @@ reference_binding (tree rto, tree rfrom, tree expr, bool
c_cast_p, int flags,
from = etype;
goto skip;
}
+ else if (CLASS_TYPE_P (etype) && TYPE_HAS_CONVERSION (etype))
+ /* CWG1996: jason's proposed drafting adds "or initializing T from E
+ would bind directly". We check that in the direct binding with
+ conversion code below. */
+ single_list_conv = true;
}
/* Otherwise, if T is a reference type, a prvalue temporary of the type
referenced by T is copy-list-initialized, and the reference is bound
@@ -1907,9 +1915,14 @@ reference_binding (tree rto, tree rfrom, tree expr, bool
c_cast_p, int flags,
(possibly cv-qualified) object to the (possibly cv-qualified) same
object type (or a reference to it), to a (possibly cv-qualified) base
class of that type (or a reference to it) */
- else if (CLASS_TYPE_P (from) && !related_p
- && !(flags & LOOKUP_NO_CONVERSION))
+ else if (!related_p
+ && !(flags & LOOKUP_NO_CONVERSION)
+ && (CLASS_TYPE_P (from) || single_list_conv))
{
+ tree rexpr = expr;
+ if (single_list_conv)
+ rexpr = CONSTRUCTOR_ELT (expr, 0)->value;
+
/* [dcl.init.ref]
If the initializer expression
@@ -1923,7 +1936,7 @@ reference_binding (tree rto, tree rfrom, tree expr, bool
c_cast_p, int flags,
the reference is bound to the lvalue result of the conversion
in the second case. */
- z_candidate *cand = build_user_type_conversion_1 (rto, expr, flags,
+ z_candidate *cand = build_user_type_conversion_1 (rto, rexpr, flags,
complain);
if (cand)
{
diff --git a/gcc/testsuite/g++.dg/cpp0x/initlist-ref1.C
b/gcc/testsuite/g++.dg/cpp0x/initlist-ref1.C
new file mode 100644
index 000..f893f12dafa
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/initlist-ref1.C
@@ -0,0 +1,16 @@
+// PR c++/113141
+// { dg-do compile { target c++11 } }
+
+struct ConvToRef {
+ operator int&();
+};
+
+struct A { int& r; };
+
+void f(A);
+
+int main() {
+ ConvToRef c;
+ A a{{c}};
+ f({{c}});
+}
diff --git a/gcc/testsuite/g++.dg/cpp0x/initlist-ref2.C
b/gcc/testsuite/g++.dg/cpp0x/initlist-ref2.C
new file mode 100644
index 000..401d868d820
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/initlist-ref2.C
@@ -0,0 +1,10 @@
+// CWG1996
+// { dg-do compile { target c++11 } }
+
+struct S { operator struct D &(); } s;
+D {s}; // OK, direct binding
+
+namespace N1 {
+ struct S { operator volatile struct D &(); } s;
+ const D {s};// { dg-error "invalid user-defined|discards qualifiers" }
+}
diff --git a/gcc/testsuite/g++.dg/cpp0x/initlist-ref3.C
b/gcc/testsuite/g++.dg/cpp0x/initlist-ref3.C
new file mode 100644
index
[gcc r14-9945] Regenerate opt.urls
https://gcc.gnu.org/g:c9500083073ff5e0f5c1c9db92d7ce6e51a62919
commit r14-9945-gc9500083073ff5e0f5c1c9db92d7ce6e51a62919
Author: Tatsuyuki Ishi
Date: Tue Apr 9 23:57:24 2024 +0900
Regenerate opt.urls
Fixes: 97069657c4e ("RISC-V: Implement TLS Descriptors.")
gcc/ChangeLog:
* config/riscv/riscv.opt.urls: Regenerated.
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Diff:
---
gcc/config/riscv/riscv.opt.urls | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/config/riscv/riscv.opt.urls b/gcc/config/riscv/riscv.opt.urls
index da31820e234..351f7f0dda2 100644
--- a/gcc/config/riscv/riscv.opt.urls
+++ b/gcc/config/riscv/riscv.opt.urls
@@ -89,3 +89,5 @@ UrlSuffix(gcc/RISC-V-Options.html#index-minline-strncmp)
minline-strlen
UrlSuffix(gcc/RISC-V-Options.html#index-minline-strlen)
+; skipping UrlSuffix for 'mtls-dialect=' due to finding no URLs
+
[gcc r14-9944] c++: Fix bogus warnings about ignored annotations [PR114691]
https://gcc.gnu.org/g:91146346f57cc54dfeb2669347edd0eb3d13af7f
commit r14-9944-g91146346f57cc54dfeb2669347edd0eb3d13af7f
Author: Jakub Jelinek
Date: Fri Apr 12 20:53:10 2024 +0200
c++: Fix bogus warnings about ignored annotations [PR114691]
The middle-end warns about the ANNOTATE_EXPR added for while/for loops
if they declare a var inside of the loop condition.
This is because the assumption is that ANNOTATE_EXPR argument is used
immediately in a COND_EXPR (later GIMPLE_COND), but simplify_loop_decl_cond
wraps the ANNOTATE_EXPR inside of a TRUTH_NOT_EXPR, so it no longer
holds.
The following patch fixes that by adding the TRUTH_NOT_EXPR inside of the
ANNOTATE_EXPR argument if any.
2024-04-12 Jakub Jelinek
PR c++/114691
* semantics.cc (simplify_loop_decl_cond): Use cp_build_unary_op with
TRUTH_NOT_EXPR on ANNOTATE_EXPR argument (if any) rather than
ANNOTATE_EXPR itself.
* g++.dg/ext/pr114691.C: New test.
Diff:
---
gcc/cp/semantics.cc | 6 +-
gcc/testsuite/g++.dg/ext/pr114691.C | 22 ++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index abaa4a3ca53..02c7c1bf5a4 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -799,7 +799,11 @@ simplify_loop_decl_cond (tree *cond_p, tree body)
*cond_p = boolean_true_node;
if_stmt = begin_if_stmt ();
- cond = cp_build_unary_op (TRUTH_NOT_EXPR, cond, false, tf_warning_or_error);
+ cond_p =
+ while (TREE_CODE (*cond_p) == ANNOTATE_EXPR)
+cond_p = _OPERAND (*cond_p, 0);
+ *cond_p = cp_build_unary_op (TRUTH_NOT_EXPR, *cond_p, false,
+ tf_warning_or_error);
finish_if_stmt_cond (cond, if_stmt);
finish_break_stmt ();
finish_then_clause (if_stmt);
diff --git a/gcc/testsuite/g++.dg/ext/pr114691.C
b/gcc/testsuite/g++.dg/ext/pr114691.C
new file mode 100644
index 000..f11731f2d5d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/pr114691.C
@@ -0,0 +1,22 @@
+// PR c++/114691
+// { dg-do compile }
+// { dg-options "-O2 -Wall" }
+
+void qux (int);
+int foo (int);
+
+void
+bar (int x)
+{
+ #pragma GCC novector
+ while (int y = foo (x)) // { dg-bogus "ignoring loop annotation" }
+qux (y);
+}
+
+void
+baz (int x)
+{
+ #pragma GCC novector
+ for (; int y = foo (x); )// { dg-bogus "ignoring loop annotation" }
+qux (y);
+}
[gcc r14-9943] c++: templated substitution into lambda-expr, cont [PR114393]
https://gcc.gnu.org/g:d74fe10b13336b9de2e025ced4af00a25ff1d3e7
commit r14-9943-gd74fe10b13336b9de2e025ced4af00a25ff1d3e7
Author: Patrick Palka
Date: Fri Apr 12 14:52:31 2024 -0400
c++: templated substitution into lambda-expr, cont [PR114393]
The original PR114393 testcase is unfortunately still not accepted after
r14-9938-g081c1e93d56d35 due to return type deduction confusion when a
lambda-expr is used as a default template argument.
The below reduced testcase demonstrates the bug. Here when forming the
dependent specialization b_v we substitute the default argument of F,
a lambda-expr, with _Descriptor=U. (In this case in_template_context is
true since we're in the context of the template c_v, so we don't defer.)
This substitution in turn lowers the level of the lambda's auto return
type from 2 to 1 and so later, when instantiating c_v we wrongly
substitute this auto with the template argument at level=0,index=0, i.e.
int, instead of going through do_auto_deduction which would yield char.
One way to fix this would be to use a level-less auto to represent a
deduced return type of a lambda, but that might be too invasive of a
change at this stage, and it might be better to do this across the board
for all deduced return types.
Another way would be to pass tf_partial from coerce_template_parms during
dependent substitution into a default template argument so that the
substitution doesn't do any level-lowering, but that wouldn't do the right
thing in this case due to the tf_partial early exit in the LAMBDA_EXPR
case of tsubst_expr.
Yet another way, and the approach that this patch takes, is to just
defer all dependent substitution into a lambda-expr, building upon the
logic added in r14-9938-g081c1e93d56d35. This also helps ensure
LAMBDA_EXPR_REGEN_INFO consists only of the concrete template arguments
that were ultimately substituted into the most general lambda.
PR c++/114393
gcc/cp/ChangeLog:
* pt.cc (tsubst_lambda_expr): Also defer all dependent
substitution.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/lambda-targ2a.C: New test.
Reviewed-by: Jason Merrill
Diff:
---
gcc/cp/pt.cc | 9 +++--
gcc/testsuite/g++.dg/cpp2a/lambda-targ2a.C | 14 ++
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index ec259ee0fbf..3b2106dd3f6 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -19622,11 +19622,16 @@ tsubst_lambda_expr (tree t, tree args, tsubst_flags_t
complain, tree in_decl)
in_decl = oldfn;
args = add_extra_args (LAMBDA_EXPR_EXTRA_ARGS (t), args, complain, in_decl);
- if (processing_template_decl && !in_template_context)
+ if (processing_template_decl
+ && (!in_template_context || any_dependent_template_arguments_p (args)))
{
/* Defer templated substitution into a lambda-expr if we lost the
necessary template context. This may happen for a lambda-expr
-used as a default template argument. */
+used as a default template argument.
+
+Defer dependent substitution as well so that we don't prematurely
+lower the level of a deduced return type or any other auto or
+template parameter belonging to the lambda. */
t = copy_node (t);
LAMBDA_EXPR_EXTRA_ARGS (t) = NULL_TREE;
LAMBDA_EXPR_EXTRA_ARGS (t) = build_extra_args (t, args, complain);
diff --git a/gcc/testsuite/g++.dg/cpp2a/lambda-targ2a.C
b/gcc/testsuite/g++.dg/cpp2a/lambda-targ2a.C
new file mode 100644
index 000..7136ce79872
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/lambda-targ2a.C
@@ -0,0 +1,14 @@
+// PR c++/114393
+// { dg-do compile { target c++20 } }
+
+template struct c1 {};
+
+template
+inline constexpr auto b_v = F;
+
+template
+inline constexpr auto c_v = b_v;
+
+auto f = c_v;
+using type = decltype(f());
+using type = char;
[gcc(refs/users/meissner/heads/work164-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:87d20d149ee92ba3ba0415299eae6dce12482bec commit 87d20d149ee92ba3ba0415299eae6dce12482bec Author: Michael Meissner Date: Fri Apr 12 14:39:02 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 1b5fe755ae5..ed1739ca4df 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -7,12 +7,17 @@ Simplify converting between SImode and SF/DFmode. gcc/ PR target/90822 - * gcc/config/rs6000.md (floatsidf2): If SImode can live in the floating - point registers, directly issue a conversion to DImode and do the - floating point conversion. + * gcc/config/rs6000.md (uns code attribute): Add sign_extend and + zero_extend. + (floatsidf2): If SImode can live in the floating point registers, + directly issue a conversion to DImode and do the floating point + conversion during expansion instead of using an UNSPEC. (floatunssisf2): Likewise. (floatunssidf2): Likewise. (floatsisf2): Likewise. + * gcc/config/rs6000/vsx.md (vsx_extract_si_float_df): Adjust + combiner to expect sign/zero extend of SImode to DImode in optimizing + V4SI extracts. Branch work164-bugs, patch #205
[gcc(refs/users/meissner/heads/work164-bugs)] Simplify converting between SImode and SF/DFmode.
https://gcc.gnu.org/g:2c9a83413db78aba0b788b199cbf94d69f71f6bd
commit 2c9a83413db78aba0b788b199cbf94d69f71f6bd
Author: Michael Meissner
Date: Fri Apr 12 14:37:52 2024 -0400
Simplify converting between SImode and SF/DFmode.
2024-04-12 Michael Meissner
gcc/
PR target/90822
* gcc/config/rs6000.md (uns code attribute): Add sign_extend and
zero_extend.
(floatsidf2): If SImode can live in the floating point registers,
directly issue a conversion to DImode and do the floating point
conversion during expansion instead of using an UNSPEC.
(floatunssisf2): Likewise.
(floatunssidf2): Likewise.
(floatsisf2): Likewise.
* gcc/config/rs6000/vsx.md (vsx_extract_si_float_df): Adjust
combiner to expect sign/zero extend of SImode to DImode in
optimizing
V4SI extracts.
Diff:
---
gcc/config/rs6000/rs6000.md | 48 -
gcc/config/rs6000/vsx.md| 18 +
2 files changed, 53 insertions(+), 13 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f1f120199f3..4ff80c34cb1 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -667,7 +667,9 @@
(define_code_attr uns [(fix"")
(unsigned_fix"uns")
(float "")
- (unsigned_float "uns")])
+ (unsigned_float "uns")
+ (sign_extend "")
+ (zero_extend "uns")])
; Various instructions that come in SI and DI forms.
; A generic w/d attribute, for things like cmpw/cmpd.
@@ -6041,6 +6043,10 @@
; with a '#' template, and a define_split (with C code). The idea is
; to allow constant folding with the template of the define_insn,
; then to have the insns split later (between sched1 and final).
+;
+; If we have direct support for SImode in floating point registers, just
+; convert the SImode value to DImode. If we are loading the value from memory,
+; we will use the LFIWAX/LXSIWAX
(define_expand "floatsidf2"
[(parallel [(set (match_operand:DF 0 "gpc_reg_operand")
@@ -6054,7 +6060,13 @@
{
if (TARGET_LFIWAX && TARGET_FCFID)
{
- emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
+ if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
+ {
+ rtx di_tmp = convert_to_mode (DImode, operands[1], false);
+ emit_insn (gen_floatdidf2 (operands[0], di_tmp));
+ }
+ else
+ emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6110,6 +6122,10 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
+;
+; If we have direct support for SImode in floating point registers, just
+; convert the SImode value to DImode. If we are loading the value from memory,
+; we will use the LFIWAX/LXSIWAX
(define_expand "floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6120,7 +6136,13 @@
{
if (TARGET_LFIWZX && TARGET_FCFIDUS)
{
- emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
+ if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
+ {
+ rtx di_tmp = convert_to_mode (DImode, operands[1], true);
+ emit_insn (gen_floatdisf2 (operands[0], di_tmp));
+ }
+ else
+ emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else
@@ -6145,7 +6167,13 @@
{
if (TARGET_LFIWZX && TARGET_FCFID)
{
- emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
+ if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
+ {
+ rtx di_tmp = convert_to_mode (DImode, operands[1], true);
+ emit_insn (gen_floatdidf2 (operands[0], di_tmp));
+ }
+ else
+ emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6905,6 +6933,10 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
+;
+; If we have direct support for SImode in floating point registers, just
+; convert the SImode value to DImode. If we are loading the value from memory,
+; we will use the LFIWAX/LXSIWAX
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6915,7 +6947,13 @@
{
if (TARGET_FCFIDS && TARGET_LFIWAX)
{
- emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
+ if
gcc-wwwdocs branch master updated. 3ca51fec661f3340fe308662405e602bcf3fe8d7
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via 3ca51fec661f3340fe308662405e602bcf3fe8d7 (commit) from 033976162ed4745f7f808f14ba62b1c055e35d16 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log - commit 3ca51fec661f3340fe308662405e602bcf3fe8d7 Author: Marek Polacek Date: Fri Apr 12 14:36:44 2024 -0400 cxx-dr-status: Minor update diff --git a/htdocs/projects/cxx-dr-status.html b/htdocs/projects/cxx-dr-status.html index fb3046cd..24c54cfd 100644 --- a/htdocs/projects/cxx-dr-status.html +++ b/htdocs/projects/cxx-dr-status.html @@ -15,7 +15,7 @@ This table tracks the implementation status of C++ defect reports in GCC. It is based on C++ Standard Core Language Issue Table of Contents, Revision - 111 (https://www.open-std.org/jtc1/sc22/wg21/docs/cwg_toc.html;>here). + 113 (https://www.open-std.org/jtc1/sc22/wg21/docs/cwg_toc.html;>here). @@ -18528,7 +18528,7 @@ https://wg21.link/cwg2642;>2642 C++23 Inconsistent use of T and C - ? + N/A @@ -18612,7 +18612,7 @@ https://wg21.link/cwg2654;>2654 C++23 Un-deprecation of compound volatile assignments - ? + 13 @@ -19025,7 +19025,7 @@ https://wg21.link/cwg2713;>2713 DRWP Initialization of reference-to-aggregate from designated initializer list - ? + Yes @@ -19375,8 +19375,8 @@ https://wg21.link/cwg2763;>2763 DR Ignorability of [[noreturn]] during constant evaluation - ? - + No + https://gcc.gnu.org/PR114705;>PR114705 https://wg21.link/cwg2764;>2764 @@ -19578,7 +19578,7 @@ https://wg21.link/cwg2792;>2792 DR Clean up specification of noexcept operator - ? + Yes @@ -19928,7 +19928,7 @@ This page is currently maintained by mailto:pola...@redhat.com;>pola...@redhat.com. Last update: -Thu Apr 11 07:49:50 PM EDT 2024 +Fri Apr 12 02:22:38 PM EDT 2024 --- Summary of changes: htdocs/projects/cxx-dr-status.html | 16 1 file changed, 8 insertions(+), 8 deletions(-) hooks/post-receive -- gcc-wwwdocs
[gcc r14-9942] c++: Diagnose or avoid constexpr dtors in classes with virtual bases [PR114426]
https://gcc.gnu.org/g:0fd824d717ca901319864a5eeba4e62b278f8329
commit r14-9942-g0fd824d717ca901319864a5eeba4e62b278f8329
Author: Jakub Jelinek
Date: Fri Apr 12 19:57:04 2024 +0200
c++: Diagnose or avoid constexpr dtors in classes with virtual bases
[PR114426]
I had another look at this P1 PR today.
You said in the "c++: fix in-charge parm in constexpr" mail back in December
(as well as in the r14-6507 commit message):
"Since a class with vbases can't have constexpr 'tors there isn't actually
a need for an in-charge parameter in a destructor" but the ICE is because
the destructor is marked implicitly constexpr.
https://eel.is/c++draft/dcl.constexpr#3.2 says that a destructor of a class
with virtual bases is not constexpr-suitable, but we were actually
implementing this just for constructors, so clearly my fault from the
https://wg21.link/P0784R7 implementation. That paper clearly added that
sentence in there and removed similar sentence just from the constructor
case.
So, the following patch makes sure the
else if (CLASSTYPE_VBASECLASSES (DECL_CONTEXT (fun)))
{
ret = false;
if (complain)
error ("%q#T has virtual base classes", DECL_CONTEXT (fun));
}
hunk is done no just for DECL_CONSTRUCTOR_P (fun), but also
DECL_DESTRUCTOR_P (fun) - in that case just for cxx_dialect >= cxx20,
as for cxx_dialect < cxx20 we already set ret = false; and diagnose
a different error, so no need to diagnose two.
2024-04-12 Jakub Jelinek
PR c++/114426
* constexpr.cc (is_valid_constexpr_fn): Return false/diagnose with
complain destructors in classes with virtual bases.
* g++.dg/cpp2a/pr114426.C: New test.
* g++.dg/cpp2a/constexpr-dtor16.C: New test.
Diff:
---
gcc/cp/constexpr.cc | 17 +++--
gcc/testsuite/g++.dg/cpp2a/constexpr-dtor16.C | 7 +++
gcc/testsuite/g++.dg/cpp2a/pr114426.C | 7 +++
3 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/gcc/cp/constexpr.cc b/gcc/cp/constexpr.cc
index 02b34cc060a..fcc847d85df 100644
--- a/gcc/cp/constexpr.cc
+++ b/gcc/cp/constexpr.cc
@@ -262,18 +262,15 @@ is_valid_constexpr_fn (tree fun, bool complain)
inform (DECL_SOURCE_LOCATION (fun),
"lambdas are implicitly % only in C++17 and later");
}
- else if (DECL_DESTRUCTOR_P (fun))
+ else if (DECL_DESTRUCTOR_P (fun) && cxx_dialect < cxx20)
{
- if (cxx_dialect < cxx20)
- {
- ret = false;
- if (complain)
- error_at (DECL_SOURCE_LOCATION (fun),
- "% destructors only available"
- " with %<-std=c++20%> or %<-std=gnu++20%>");
- }
+ ret = false;
+ if (complain)
+ error_at (DECL_SOURCE_LOCATION (fun),
+ "% destructors only available with "
+ "%<-std=c++20%> or %<-std=gnu++20%>");
}
- else if (!DECL_CONSTRUCTOR_P (fun))
+ else if (!DECL_CONSTRUCTOR_P (fun) && !DECL_DESTRUCTOR_P (fun))
{
tree rettype = TREE_TYPE (TREE_TYPE (fun));
if (!literal_type_p (rettype))
diff --git a/gcc/testsuite/g++.dg/cpp2a/constexpr-dtor16.C
b/gcc/testsuite/g++.dg/cpp2a/constexpr-dtor16.C
new file mode 100644
index 000..b84aaf95b9d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/constexpr-dtor16.C
@@ -0,0 +1,7 @@
+// PR c++/114426
+// { dg-do compile { target c++11 } }
+
+struct A { virtual ~A (); };
+struct B : virtual A { constexpr ~B () {} };
+// { dg-error "'struct B' has virtual base classes" "" { target c++20 } .-1 }
+// { dg-error "'constexpr' destructors only available with" "" { target
c++17_down } .-2 }
diff --git a/gcc/testsuite/g++.dg/cpp2a/pr114426.C
b/gcc/testsuite/g++.dg/cpp2a/pr114426.C
new file mode 100644
index 000..9000fa747d7
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/pr114426.C
@@ -0,0 +1,7 @@
+// PR c++/114426
+// { dg-do compile }
+// { dg-additional-options "-O2" }
+
+struct A { virtual ~A (); };
+struct B : virtual A { virtual void foo () = 0; };
+struct C : B { C () {} };
[gcc r14-9941] match: Fix `!a?b:c` and `a?~t:t` patterns for signed 1 bit types [PR114666]
https://gcc.gnu.org/g:245595d72818526e2ca857848831e8afa87ae2de
commit r14-9941-g245595d72818526e2ca857848831e8afa87ae2de
Author: Andrew Pinski
Date: Wed Apr 10 13:39:01 2024 -0700
match: Fix `!a?b:c` and `a?~t:t` patterns for signed 1 bit types [PR114666]
The problem is `!a?b:c` pattern will create a COND_EXPR with an 1bit signed
integer
which breaks patterns like `a?~t:t`. This rejects when we have a signed
operand for
both patterns.
Note for GCC 15, I am going to look at the canonicalization of `a?~t:t`
where t
was a constant since I think keeping it a COND_EXPR might be more canonical
and
is what VPR produces from the same IR; if anything expand should handle
which one
is better.
Bootstrapped and tested on x86_64-linux-gnu with no regressions.
PR tree-optimization/114666
gcc/ChangeLog:
* match.pd (`!a?b:c`): Reject signed types for the condition.
(`a?~t:t`): Likewise.
gcc/testsuite/ChangeLog:
* gcc.c-torture/execute/bitfld-signed1-1.c: New test.
Signed-off-by: Andrew Pinski
Diff:
---
gcc/match.pd | 6 +-
gcc/testsuite/gcc.c-torture/execute/bitfld-signed1-1.c | 13 +
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/gcc/match.pd b/gcc/match.pd
index 15a1e7350d4..d401e7503e6 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -5895,7 +5895,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
/* !A ? B : C -> A ? C : B. */
(simplify
(cnd (logical_inverted_value truth_valued_p@0) @1 @2)
- (cnd @0 @2 @1)))
+ /* For CONDs, don't handle signed values here. */
+ (if (cnd == VEC_COND_EXPR
+ || TYPE_UNSIGNED (TREE_TYPE (@0)))
+ (cnd @0 @2 @1
/* abs/negative simplifications moved from fold_cond_expr_with_comparison.
@@ -7095,6 +7098,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
(cond @0 @1 @2)
(with { bool wascmp; }
(if (INTEGRAL_TYPE_P (type)
+ && TYPE_UNSIGNED (TREE_TYPE (@0))
&& bitwise_inverted_equal_p (@1, @2, wascmp)
&& (!wascmp || TYPE_PRECISION (type) == 1))
(if ((!TYPE_UNSIGNED (type) && TREE_CODE (type) == BOOLEAN_TYPE)
diff --git a/gcc/testsuite/gcc.c-torture/execute/bitfld-signed1-1.c
b/gcc/testsuite/gcc.c-torture/execute/bitfld-signed1-1.c
new file mode 100644
index 000..b0ff120ea51
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/bitfld-signed1-1.c
@@ -0,0 +1,13 @@
+/* PR tree-optimization/114666 */
+/* We used to miscompile this to be always aborting
+ due to the use of the signed 1bit into the COND_EXPR. */
+
+struct {
+ signed a : 1;
+} b = {-1};
+char c;
+int main()
+{
+ if ((b.a ^ 1UL) < 3)
+__builtin_abort();
+}
[gcc(refs/users/meissner/heads/work164-bugs)] Revert all changes
https://gcc.gnu.org/g:94405026c6c064a9e08d9f956f0ce067b6002caa
commit 94405026c6c064a9e08d9f956f0ce067b6002caa
Author: Michael Meissner
Date: Fri Apr 12 12:26:03 2024 -0400
Revert all changes
Diff:
---
gcc/config/rs6000/rs6000.md | 44
1 file changed, 4 insertions(+), 40 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 32b0fd056fa..f1f120199f3 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6041,10 +6041,6 @@
; with a '#' template, and a define_split (with C code). The idea is
; to allow constant folding with the template of the define_insn,
; then to have the insns split later (between sched1 and final).
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatsidf2"
[(parallel [(set (match_operand:DF 0 "gpc_reg_operand")
@@ -6058,13 +6054,7 @@
{
if (TARGET_LFIWAX && TARGET_FCFID)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], false);
- emit_insn (gen_floatdidf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
+ emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6120,10 +6110,6 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6134,13 +6120,7 @@
{
if (TARGET_LFIWZX && TARGET_FCFIDUS)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], true);
- emit_insn (gen_floatdisf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
+ emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else
@@ -6165,13 +6145,7 @@
{
if (TARGET_LFIWZX && TARGET_FCFID)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], true);
- emit_insn (gen_floatdidf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
+ emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6931,10 +6905,6 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6945,13 +6915,7 @@
{
if (TARGET_FCFIDS && TARGET_LFIWAX)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], false);
- emit_insn (gen_floatdisf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
+ emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID && TARGET_LFIWAX)
[gcc r14-9939] s390: testsuite: Xfail range-sincos.c and vrp-float-abs-1.c
https://gcc.gnu.org/g:a76f236e084cbd02e4e3711cdfc3191dc7eeb460
commit r14-9939-ga76f236e084cbd02e4e3711cdfc3191dc7eeb460
Author: Stefan Schulze Frielinghaus
Date: Fri Apr 12 16:54:38 2024 +0200
s390: testsuite: Xfail range-sincos.c and vrp-float-abs-1.c
As mentioned in PR114678 those failures will be fixed by
https://gcc.gnu.org/pipermail/gcc-patches/2024-March/648303.html
For GCC 14 just xfail them which should be reverted once the patch is
applied.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/range-sincos.c: Xfail for s390.
* gcc.dg/tree-ssa/vrp-float-abs-1.c: Dito.
Diff:
---
gcc/testsuite/gcc.dg/tree-ssa/range-sincos.c| 2 +-
gcc/testsuite/gcc.dg/tree-ssa/vrp-float-abs-1.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/range-sincos.c
b/gcc/testsuite/gcc.dg/tree-ssa/range-sincos.c
index 337f9cda02f..35b38c3c914 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/range-sincos.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/range-sincos.c
@@ -40,4 +40,4 @@ stool (double x)
link_error ();
}
-// { dg-final { scan-tree-dump-not "link_error" "evrp" { target { { *-*-linux*
} && { glibc } } } } }
+// { dg-final { scan-tree-dump-not "link_error" "evrp" { target { { *-*-linux*
} && { glibc } } xfail s390*-*-* } } } xfail: PR114678
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vrp-float-abs-1.c
b/gcc/testsuite/gcc.dg/tree-ssa/vrp-float-abs-1.c
index 4b7b75833e0..a814a973963 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/vrp-float-abs-1.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/vrp-float-abs-1.c
@@ -14,4 +14,4 @@ foo (double x, double y)
}
}
-// { dg-final { scan-tree-dump-not "link_error" "evrp" } }
+// { dg-final { scan-tree-dump-not "link_error" "evrp" { xfail s390*-*-* } } }
xfail: PR114678
[gcc r14-9938] c++: templated substitution into lambda-expr [PR114393]
https://gcc.gnu.org/g:081c1e93d56d35c7314ed68e6d87628b430de917
commit r14-9938-g081c1e93d56d35c7314ed68e6d87628b430de917
Author: Patrick Palka
Date: Fri Apr 12 08:59:27 2024 -0400
c++: templated substitution into lambda-expr [PR114393]
The below testcases use a lambda-expr as a template argument and they
all trip over the below added tsubst_lambda_expr sanity check ultimately
because current_template_parms is empty which causes push_template_decl
to return error_mark_node from the call to begin_lambda_type. Were it
not for the sanity check this silent error_mark_node result leads to
nonsensical errors down the line, or silent breakage.
In the first testcase, we hit this assert during instantiation of the
dependent alias template-id c1_t<_Data> from instantiate_template, which
clears current_template_parms via push_to_top_level. Similar story for
the second testcase. For the third testcase we hit the assert during
partial instantiation of the member template from instantiate_class_template
which similarly calls push_to_top_level.
These testcases illustrate that templated substitution into a lambda-expr
is not always possible, in particular when we lost the relevant template
context. I experimented with recovering the template context by making
tsubst_lambda_expr fall back to using scope_chain->prev->template_parms if
current_template_parms is empty which worked but seemed like a hack. I
also experimented with preserving the template context by keeping
current_template_parms set during instantiate_template for a dependent
specialization which also worked but it's at odds with the fact that we
cache dependent specializations (and so they should be independent of
the template context).
So instead of trying to make such substitution work, this patch uses the
extra-args mechanism to defer templated substitution into a lambda-expr
when we lost the relevant template context.
PR c++/114393
PR c++/107457
PR c++/93595
gcc/cp/ChangeLog:
* cp-tree.h (LAMBDA_EXPR_EXTRA_ARGS): Define.
(tree_lambda_expr::extra_args): New field.
* module.cc (trees_out::core_vals) : Stream
LAMBDA_EXPR_EXTRA_ARGS.
(trees_in::core_vals) : Likewise.
* pt.cc (has_extra_args_mechanism_p): Return true for LAMBDA_EXPR.
(tree_extra_args): Handle LAMBDA_EXPR.
(tsubst_lambda_expr): Use LAMBDA_EXPR_EXTRA_ARGS to defer templated
substitution into a lambda-expr if we lost the template context.
Add sanity check for error_mark_node result from begin_lambda_type.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/lambda-targ2.C: New test.
* g++.dg/cpp2a/lambda-targ3.C: New test.
* g++.dg/cpp2a/lambda-targ4.C: New test.
Reviewed-by: Jason Merrill
Diff:
---
gcc/cp/cp-tree.h | 5 +
gcc/cp/module.cc | 2 ++
gcc/cp/pt.cc | 22 --
gcc/testsuite/g++.dg/cpp2a/lambda-targ2.C | 19 +++
gcc/testsuite/g++.dg/cpp2a/lambda-targ3.C | 12
gcc/testsuite/g++.dg/cpp2a/lambda-targ4.C | 12
6 files changed, 70 insertions(+), 2 deletions(-)
diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h
index 52d53589e51..1dbb577a38d 100644
--- a/gcc/cp/cp-tree.h
+++ b/gcc/cp/cp-tree.h
@@ -1538,6 +1538,10 @@ enum cp_lambda_default_capture_mode_type {
#define LAMBDA_EXPR_REGEN_INFO(NODE) \
(((struct tree_lambda_expr *)LAMBDA_EXPR_CHECK (NODE))->regen_info)
+/* Like PACK_EXPANSION_EXTRA_ARGS, for lambda-expressions. */
+#define LAMBDA_EXPR_EXTRA_ARGS(NODE) \
+ (((struct tree_lambda_expr *)LAMBDA_EXPR_CHECK (NODE))->extra_args)
+
/* The closure type of the lambda, which is also the type of the
LAMBDA_EXPR. */
#define LAMBDA_EXPR_CLOSURE(NODE) \
@@ -1550,6 +1554,7 @@ struct GTY (()) tree_lambda_expr
tree this_capture;
tree extra_scope;
tree regen_info;
+ tree extra_args;
vec *pending_proxies;
location_t locus;
enum cp_lambda_default_capture_mode_type default_capture_mode : 2;
diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc
index 4e91fa6e052..ad1b6bf5ca4 100644
--- a/gcc/cp/module.cc
+++ b/gcc/cp/module.cc
@@ -6312,6 +6312,7 @@ trees_out::core_vals (tree t)
WT (((lang_tree_node *)t)->lambda_expression.this_capture);
WT (((lang_tree_node *)t)->lambda_expression.extra_scope);
WT (((lang_tree_node *)t)->lambda_expression.regen_info);
+ WT (((lang_tree_node *)t)->lambda_expression.extra_args);
/* pending_proxies is a parse-time thing. */
gcc_assert (!((lang_tree_node *)t)->lambda_expression.pending_proxies);
if (state)
@@ -6814,6 +6815,7 @@ trees_in::core_vals (tree t)
RT (((lang_tree_node
[gcc r14-9937] libgfortran: Fix compilation of gf_vsnprintf
https://gcc.gnu.org/g:3bd3ca05b519b99b5ea570c10fd80737cd4c6c49
commit r14-9937-g3bd3ca05b519b99b5ea570c10fd80737cd4c6c49
Author: Ian McInerney
Date: Thu Apr 4 16:16:32 2024 +0100
libgfortran: Fix compilation of gf_vsnprintf
The fallback function (gf_vsnprintf) to provide a vsnprintf function
if the system library doesn't have one would not compile due to the
variable name for the string's destination buffer not being updated
after the refactor in 2018 in edaaef601d0d6d263fba87b42d6d04c99dd23dba.
This updates the internal logic of gf_vsnprintf to now use the str
variable defined in the function signature.
libgfortran/ChangeLog:
2024-04-04 Ian McInerney
* runtime/error.c (gf_vsnprintf): Fix compilation
Signed-off-by: Ian McInerney
Diff:
---
libgfortran/runtime/error.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/libgfortran/runtime/error.c b/libgfortran/runtime/error.c
index e840f539599..044298294d8 100644
--- a/libgfortran/runtime/error.c
+++ b/libgfortran/runtime/error.c
@@ -142,15 +142,15 @@ gf_vsnprintf (char *str, size_t size, const char *format,
va_list ap)
{
int written;
- written = vsprintf(buffer, format, ap);
+ written = vsprintf(str, format, ap);
if (written >= size - 1)
{
- /* The error message was longer than our buffer. Ouch. Because
+ /* The error message was longer than the string size. Ouch. Because
we may have messed up things badly, report the error and
quit. */
-#define ERROR_MESSAGE "Internal error: buffer overrun in gf_vsnprintf()\n"
- write (STDERR_FILENO, buffer, size - 1);
+#define ERROR_MESSAGE "Internal error: string overrun in gf_vsnprintf()\n"
+ write (STDERR_FILENO, str, size - 1);
write (STDERR_FILENO, ERROR_MESSAGE, strlen (ERROR_MESSAGE));
sys_abort ();
#undef ERROR_MESSAGE
[gcc r14-9936] RISC-V: Fix Werror=sign-compare in riscv_validate_vector_type
https://gcc.gnu.org/g:6e7e5943619a2c20d93fc7089c885483786558bc
commit r14-9936-g6e7e5943619a2c20d93fc7089c885483786558bc
Author: Pan Li
Date: Fri Apr 12 16:38:18 2024 +0800
RISC-V: Fix Werror=sign-compare in riscv_validate_vector_type
This patch would like to fix the Werror=sign-compare similar to below:
gcc/config/riscv/riscv.cc: In function ‘void
riscv_validate_vector_type(const_tree, const char*)’:
gcc/config/riscv/riscv.cc:5614:23: error: comparison of integer
expressions of different signedness: ‘int’ and ‘unsigned int’
[-Werror=sign-compare]
5614 | if (TARGET_MIN_VLEN < required_min_vlen)
The TARGET_MIN_VLEN is *int* by default but the required_min_vlen
returned from riscv_vector_required_min_vlen is **unsigned**. Thus,
adjust the related function and reference variable(s) to int type
to avoid such kind of Werror.
The below test suite is passed for this patch.
* The rv64gcv fully regression tests.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_vector_float_type_p): Take int
as the return value instead of unsigned.
(riscv_vector_element_bitsize): Ditto.
(riscv_vector_required_min_vlen): Ditto.
(riscv_validate_vector_type): Take int type for local variable(s).
Signed-off-by: Pan Li
Diff:
---
gcc/config/riscv/riscv.cc | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e5f00806bb9..74445bc977c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5499,7 +5499,7 @@ riscv_vector_float_type_p (const_tree type)
return strstr (name, "vfloat") != NULL;
}
-static unsigned
+static int
riscv_vector_element_bitsize (const_tree type)
{
machine_mode mode = TYPE_MODE (type);
@@ -5523,7 +5523,7 @@ riscv_vector_element_bitsize (const_tree type)
gcc_unreachable ();
}
-static unsigned
+static int
riscv_vector_required_min_vlen (const_tree type)
{
machine_mode mode = TYPE_MODE (type);
@@ -5531,7 +5531,7 @@ riscv_vector_required_min_vlen (const_tree type)
if (riscv_v_ext_mode_p (mode))
return TARGET_MIN_VLEN;
- unsigned element_bitsize = riscv_vector_element_bitsize (type);
+ int element_bitsize = riscv_vector_element_bitsize (type);
const char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)));
if (strstr (name, "bool64") != NULL)
@@ -5569,7 +5569,7 @@ riscv_validate_vector_type (const_tree type, const char
*hint)
return;
}
- unsigned element_bitsize = riscv_vector_element_bitsize (type);
+ int element_bitsize = riscv_vector_element_bitsize (type);
bool int_type_p = riscv_vector_int_type_p (type);
if (int_type_p && element_bitsize == 64
@@ -5609,7 +5609,7 @@ riscv_validate_vector_type (const_tree type, const char
*hint)
return;
}
- unsigned required_min_vlen = riscv_vector_required_min_vlen (type);
+ int required_min_vlen = riscv_vector_required_min_vlen (type);
if (TARGET_MIN_VLEN < required_min_vlen)
{
[gcc r12-10321] Objective-C, NeXT: Adjust symbol marking to match host tools.
https://gcc.gnu.org/g:076f07ddf9d7a348da1459a81a14eaf7d7c256a5
commit r12-10321-g076f07ddf9d7a348da1459a81a14eaf7d7c256a5
Author: Iain Sandoe
Date: Mon May 2 19:42:49 2022 +0100
Objective-C, NeXT: Adjust symbol marking to match host tools.
Current host tools mark some additional symbols as 'no dead strip' and also
expose one additional group to the linker. This does not affect older
Darwin
versions or x86_64, but omitting these changes results in link errors for
aarch64.
Signed-off-by: Iain Sandoe
gcc/ChangeLog:
* config/darwin.cc (darwin_label_is_anonymous_local_objc_name): Make
protocol class methods linker-visible.
gcc/objc/ChangeLog:
* objc-next-runtime-abi-02.cc (next_runtime_abi_02_protocol_decl):
Do
not dead-strip the runtime meta-data symbols.
(build_v2_classrefs_table): Likewise.
(build_v2_protocol_list_address_table): Likewise.
(cherry picked from commit ecd5727c0a662a8fea6b5f8eac6f3f15bf5ef851)
Diff:
---
gcc/config/darwin.cc | 2 ++
gcc/objc/objc-next-runtime-abi-02.cc | 6 --
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/gcc/config/darwin.cc b/gcc/config/darwin.cc
index f065a13d73d..1b3de338926 100644
--- a/gcc/config/darwin.cc
+++ b/gcc/config/darwin.cc
@@ -1936,6 +1936,8 @@ darwin_label_is_anonymous_local_objc_name (const char
*name)
}
else if (startswith ((const char *)p, "ClassMethods"))
return false;
+ else if (startswith ((const char *)p, "ClassProtocols"))
+return false;
else if (startswith ((const char *)p, "Instance"))
{
if (p[8] == 'I' || p[8] == 'M')
diff --git a/gcc/objc/objc-next-runtime-abi-02.cc
b/gcc/objc/objc-next-runtime-abi-02.cc
index e50ca6e89f5..9ea63b189c7 100644
--- a/gcc/objc/objc-next-runtime-abi-02.cc
+++ b/gcc/objc/objc-next-runtime-abi-02.cc
@@ -1033,6 +1033,7 @@ next_runtime_abi_02_protocol_decl (tree p)
else
decl = start_var_decl (objc_v2_protocol_template, buf);
OBJCMETA (decl, objc_meta, meta_protocol);
+ DECL_PRESERVE_P (decl) = 1;
return decl;
}
@@ -2115,8 +2116,8 @@ build_v2_classrefs_table (void)
expr = convert (objc_class_type, build_fold_addr_expr (expr));
}
/* The runtime wants this, even if it appears unused, so we must force
the
-output.
- DECL_PRESERVE_P (decl) = 1; */
+output. */
+ DECL_PRESERVE_P (decl) = 1;
finish_var_decl (decl, expr);
}
}
@@ -2318,6 +2319,7 @@ build_v2_protocol_list_address_table (void)
expr = convert (objc_protocol_type, build_fold_addr_expr (ref->refdecl));
OBJCMETA (decl, objc_meta, meta_label_protocollist);
finish_var_decl (decl, expr);
+ DECL_PRESERVE_P (decl) = 1;
}
/* TODO: delete the vec. */
[gcc r14-9935] analyzer: Bail out on function pointer for -Wanalyzer-allocation-size
https://gcc.gnu.org/g:67e1433a94f8ca82e2c36b79af44256430c73c38 commit r14-9935-g67e1433a94f8ca82e2c36b79af44256430c73c38 Author: Stefan Schulze Frielinghaus Date: Fri Apr 12 11:06:24 2024 +0200 analyzer: Bail out on function pointer for -Wanalyzer-allocation-size On s390 pr94688.c is failing due to excess error pr94688.c:6:5: warning: allocated buffer size is not a multiple of the pointee's size [CWE-131] [-Wanalyzer-allocation-size] This is because on s390 functions are by default aligned to an 8-byte boundary and during function type construction size is set to function boundary. Thus, for the assignment a.0_1 = (void (*) ()) we have that the right-hand side is pointing to a 4-byte memory region whereas the size of the function pointer is 8 byte and a warning is emitted. Since -Wanalyzer-allocation-size is not about pointers to code, bail out early. gcc/analyzer/ChangeLog: * region-model.cc (region_model::check_region_size): Bail out early on function pointers. Diff: --- gcc/analyzer/region-model.cc | 4 1 file changed, 4 insertions(+) diff --git a/gcc/analyzer/region-model.cc b/gcc/analyzer/region-model.cc index 665873dbe94..bebe2ed3cd6 100644 --- a/gcc/analyzer/region-model.cc +++ b/gcc/analyzer/region-model.cc @@ -3514,6 +3514,10 @@ region_model::check_region_size (const region *lhs_reg, const svalue *rhs_sval, || TYPE_SIZE_UNIT (pointee_type) == NULL_TREE) return; + /* Bail out early on function pointers. */ + if (TREE_CODE (pointee_type) == FUNCTION_TYPE) +return; + /* Bail out early on pointers to structs where we can not deduce whether the buffer size is compatible. */ bool is_struct = RECORD_OR_UNION_TYPE_P (pointee_type);
[gcc r14-9934] tree-cfg: Make the verifier returns_twice message translatable
https://gcc.gnu.org/g:8c6f13d2cc1884921e7c532e03786f0344bededd
commit r14-9934-g8c6f13d2cc1884921e7c532e03786f0344bededd
Author: Jakub Jelinek
Date: Fri Apr 12 11:00:43 2024 +0200
tree-cfg: Make the verifier returns_twice message translatable
While translation of the verifier messages is questionable, that case is
something that ideally should never happen except to gcc developers
and so pressumably English should be fine, we use error etc. APIs and
those imply translatations and some translators translate it.
The following patch adjusts the code such that we don't emit
appel returns_twice est not first dans le bloc de base 33
in French (i.e. 2 English word in the middle of a French message).
Similarly Swedish or Ukrainian.
Note, the German translator did differentiate between these verifier
messages vs. normal user facing and translated it to:
"Interner Fehler: returns_twice call is %s in basic block %d"
so just a German prefix before English message.
2024-04-12 Jakub Jelinek
* tree-cfg.cc (gimple_verify_flow_info): Make the misplaced
returns_twice diagnostics translatable.
Diff:
---
gcc/tree-cfg.cc | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/gcc/tree-cfg.cc b/gcc/tree-cfg.cc
index 96686db8ed3..d98b68d6787 100644
--- a/gcc/tree-cfg.cc
+++ b/gcc/tree-cfg.cc
@@ -5818,7 +5818,7 @@ gimple_verify_flow_info (void)
if (gimple_code (stmt) == GIMPLE_CALL
&& gimple_call_flags (stmt) & ECF_RETURNS_TWICE)
{
- const char *misplaced = NULL;
+ bool misplaced = false;
/* TM is an exception: it points abnormal edges just after the
call that starts a transaction, i.e. it must end the BB. */
if (gimple_call_builtin_p (stmt, BUILT_IN_TM_START))
@@ -5826,18 +5826,23 @@ gimple_verify_flow_info (void)
if (single_succ_p (bb)
&& bb_has_abnormal_pred (single_succ (bb))
&& !gsi_one_nondebug_before_end_p (gsi))
- misplaced = "not last";
+ {
+ error ("returns_twice call is not last in basic block "
+"%d", bb->index);
+ misplaced = true;
+ }
}
else
{
- if (seen_nondebug_stmt
- && bb_has_abnormal_pred (bb))
- misplaced = "not first";
+ if (seen_nondebug_stmt && bb_has_abnormal_pred (bb))
+ {
+ error ("returns_twice call is not first in basic block "
+"%d", bb->index);
+ misplaced = true;
+ }
}
if (misplaced)
{
- error ("returns_twice call is %s in basic block %d",
-misplaced, bb->index);
print_gimple_stmt (stderr, stmt, 0, TDF_SLIM);
err = true;
}
[gcc r14-9933] Limit special asan/ubsan/bitint returns_twice handling to calls in bbs with abnormal pred [PR114687]
https://gcc.gnu.org/g:c9e94ae448ba309dba74de3ee1974a3ed9248889
commit r14-9933-gc9e94ae448ba309dba74de3ee1974a3ed9248889
Author: Jakub Jelinek
Date: Fri Apr 12 10:59:54 2024 +0200
Limit special asan/ubsan/bitint returns_twice handling to calls in bbs with
abnormal pred [PR114687]
The tree-cfg.cc verifier only diagnoses returns_twice calls preceded
by non-label/debug stmts if it is in a bb with abnormal predecessor.
The following testcase shows that if a user lies in the attributes
(a function which never returns can't be pure, and can't return
twice when it doesn't ever return at all), when we figure it out,
we can remove the abnormal edges to the "returns_twice" call and perhaps
whole .ABNORMAL_DISPATCHER etc.
edge_before_returns_twice_call then ICEs because it can't find such
an edge.
The following patch limits the special handling to calls in bbs where
the verifier requires that.
2024-04-12 Jakub Jelinek
PR sanitizer/114687
* gimple-iterator.cc (gsi_safe_insert_before): Only use
edge_before_returns_twice_call if bb_has_abnormal_pred.
(gsi_safe_insert_seq_before): Likewise.
* gimple-lower-bitint.cc (bitint_large_huge::lower_call): Only
push to m_returns_twice_calls if bb_has_abnormal_pred.
* gcc.dg/asan/pr114687.c: New test.
Diff:
---
gcc/gimple-iterator.cc | 6 --
gcc/gimple-lower-bitint.cc | 2 +-
gcc/testsuite/gcc.dg/asan/pr114687.c | 22 ++
3 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/gcc/gimple-iterator.cc b/gcc/gimple-iterator.cc
index ac6cb4aa414..93646262eac 100644
--- a/gcc/gimple-iterator.cc
+++ b/gcc/gimple-iterator.cc
@@ -1049,7 +1049,8 @@ gsi_safe_insert_before (gimple_stmt_iterator *iter,
gimple *g)
gimple *stmt = gsi_stmt (*iter);
if (stmt
&& is_gimple_call (stmt)
- && (gimple_call_flags (stmt) & ECF_RETURNS_TWICE) != 0)
+ && (gimple_call_flags (stmt) & ECF_RETURNS_TWICE) != 0
+ && bb_has_abnormal_pred (gsi_bb (*iter)))
{
edge e = edge_before_returns_twice_call (gsi_bb (*iter));
basic_block new_bb = gsi_insert_on_edge_immediate (e, g);
@@ -1072,7 +1073,8 @@ gsi_safe_insert_seq_before (gimple_stmt_iterator *iter,
gimple_seq seq)
gimple *stmt = gsi_stmt (*iter);
if (stmt
&& is_gimple_call (stmt)
- && (gimple_call_flags (stmt) & ECF_RETURNS_TWICE) != 0)
+ && (gimple_call_flags (stmt) & ECF_RETURNS_TWICE) != 0
+ && bb_has_abnormal_pred (gsi_bb (*iter)))
{
edge e = edge_before_returns_twice_call (gsi_bb (*iter));
gimple *f = gimple_seq_first_stmt (seq);
diff --git a/gcc/gimple-lower-bitint.cc b/gcc/gimple-lower-bitint.cc
index 4c3b7f7b68e..7e8b6e3c51a 100644
--- a/gcc/gimple-lower-bitint.cc
+++ b/gcc/gimple-lower-bitint.cc
@@ -5320,7 +5320,7 @@ bitint_large_huge::lower_call (tree obj, gimple *stmt)
arg = make_ssa_name (TREE_TYPE (arg));
gimple *g = gimple_build_assign (arg, v);
gsi_insert_before (, g, GSI_SAME_STMT);
- if (returns_twice)
+ if (returns_twice && bb_has_abnormal_pred (gimple_bb (stmt)))
{
m_returns_twice_calls.safe_push (stmt);
returns_twice = false;
diff --git a/gcc/testsuite/gcc.dg/asan/pr114687.c
b/gcc/testsuite/gcc.dg/asan/pr114687.c
new file mode 100644
index 000..48cc8688176
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/asan/pr114687.c
@@ -0,0 +1,22 @@
+/* PR sanitizer/114687 */
+/* { dg-do compile } */
+
+int a;
+int foo (int);
+
+__attribute__((pure, returns_twice)) int
+bar (void)
+{
+ a = 1;
+ while (a)
+a = 2;
+ return a;
+}
+
+int
+baz (void)
+{
+ int d = bar ();
+ foo (d);
+ return 0;
+}
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commit 033976162ed4745f7f808f14ba62b1c055e35d16
Author: Haochen Jiang
Date: Fri Apr 12 16:34:48 2024 +0800
Uncomment MCore part title
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 14301157..8ac08e9a 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -828,7 +828,7 @@ __asm (".global __flmap_lock" "\n\t"
-
+MCore
Bitfields are now signed by default per GCC policy. If you need
bitfields
to be unsigned, use -funsigned-bitfields.
---
Summary of changes:
htdocs/gcc-14/changes.html | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
hooks/post-receive
--
gcc-wwwdocs
[gcc r11-11317] RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64
https://gcc.gnu.org/g:cb68221c59e8f98e107bb5842d319bee3a66b8dc
commit r11-11317-gcb68221c59e8f98e107bb5842d319bee3a66b8dc
Author: Kito Cheng
Date: Wed Feb 28 16:01:52 2024 +0800
RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64
atomic_compare_and_swapsi will use lr.w to do obtain the original value,
which sign extends to DI. RV64 only has DI comparisons, so we also need
to sign extend the expected value to DI as otherwise the comparison will
fail when the expected value has the 32nd bit set.
gcc/ChangeLog:
PR target/114130
* config/riscv/sync.md (atomic_compare_and_swap): Sign
extend the expected value if needed.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr114130.c: New.
Reviewed-by: Palmer Dabbelt
(cherry picked from commit fd07a29e39f5347d6cef3e7042a32306f97a1719)
Diff:
---
gcc/config/riscv/sync.md | 9 +
gcc/testsuite/gcc.target/riscv/pr114130.c | 12
2 files changed, 21 insertions(+)
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 747a799e237..396124563ec 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -129,6 +129,15 @@
(match_operand:SI 7 "const_int_operand" "")] ;; mod_f
"TARGET_ATOMIC"
{
+ if (word_mode != mode && operands[3] != const0_rtx)
+{
+ /* We don't have SI mode compare on RV64, so we need to make sure
expected
+value is sign-extended. */
+ rtx tmp0 = gen_reg_rtx (word_mode);
+ emit_insn (gen_extend_insn (tmp0, operands[3], word_mode, mode,
0));
+ operands[3] = simplify_gen_subreg (mode, tmp0, word_mode, 0);
+}
+
emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2],
operands[3], operands[4],
operands[6], operands[7]));
diff --git a/gcc/testsuite/gcc.target/riscv/pr114130.c
b/gcc/testsuite/gcc.target/riscv/pr114130.c
new file mode 100644
index 000..cd0a4e8236c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr114130.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -O" } */
+#include
+
+void foo(uint32_t *p) {
+uintptr_t x = *(uintptr_t *)p;
+uint32_t e = !p ? 0 : (uintptr_t)p >> 1;
+uint32_t d = (uintptr_t)x;
+__atomic_compare_exchange(p, , , 0, __ATOMIC_RELAXED,
__ATOMIC_RELAXED);
+}
+
+/* { dg-final { scan-assembler-times "sext.w\t" 1 } } */
[gcc r14-9932] contrib/check-params-in-docs.py: Ignore target-specific params
https://gcc.gnu.org/g:e30e760b51b108786946e04a26e92531762b022d
commit r14-9932-ge30e760b51b108786946e04a26e92531762b022d
Author: Filip Kastl
Date: Fri Apr 12 09:52:27 2024 +0200
contrib/check-params-in-docs.py: Ignore target-specific params
contrib/check-params-in-docs.py is a script that checks that all options
reported with gcc --help=params are in gcc/doc/invoke.texi and vice
versa.
gcc/doc/invoke.texi lists target-specific params but gcc --help=params
doesn't. This meant that the script would mistakenly complain about
parms missing from --help=params. Previously, the script was just set
to ignore aarch64 and gcn params which solved this issue only for x86.
This patch sets the script to ignore all target-specific params.
contrib/ChangeLog:
* check-params-in-docs.py: Ignore target specific params.
Signed-off-by: Filip Kastl
Diff:
---
contrib/check-params-in-docs.py | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/contrib/check-params-in-docs.py b/contrib/check-params-in-docs.py
index f7879dd8e08..ccdb8d72169 100755
--- a/contrib/check-params-in-docs.py
+++ b/contrib/check-params-in-docs.py
@@ -38,6 +38,9 @@ def get_param_tuple(line):
description = line[i:].strip()
return (name, description)
+def target_specific(param):
+return param.split('-')[0] in ('aarch64', 'gcn', 'x86')
+
parser = argparse.ArgumentParser()
parser.add_argument('texi_file')
@@ -45,13 +48,16 @@ parser.add_argument('params_output')
args = parser.parse_args()
-ignored = {'logical-op-non-short-circuit',
'gcn-preferred-vectorization-factor'}
-params = {}
+ignored = {'logical-op-non-short-circuit'}
+help_params = {}
for line in open(args.params_output).readlines():
if line.startswith(' ' * 2) and not line.startswith(' ' * 8):
r = get_param_tuple(line)
-params[r[0]] = r[1]
+help_params[r[0]] = r[1]
+
+# Skip target-specific params
+help_params = [x for x in help_params.keys() if not target_specific(x)]
# Find section in .texi manual with parameters
texi = ([x.strip() for x in open(args.texi_file).readlines()])
@@ -66,14 +72,13 @@ for line in texi:
texi_params.append(line[len(token):])
break
-# skip digits
+# Skip digits
texi_params = [x for x in texi_params if not x[0].isdigit()]
-# skip aarch64 params
-texi_params = [x for x in texi_params if not x.startswith('aarch64')]
-sorted_params = sorted(texi_params)
+# Skip target-specific params
+texi_params = [x for x in texi_params if not target_specific(x)]
texi_set = set(texi_params) - ignored
-params_set = set(params.keys()) - ignored
+params_set = set(help_params) - ignored
success = True
extra = texi_set - params_set
[gcc(refs/users/meissner/heads/work164-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:6ae9d9f24734d61f20bc06a96cecd6c02f77d5d7 commit 6ae9d9f24734d61f20bc06a96cecd6c02f77d5d7 Author: Michael Meissner Date: Fri Apr 12 03:30:47 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index b159df68df3..1b5fe755ae5 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -2,7 +2,7 @@ Simplify converting between SImode and SF/DFmode. -2024-04-11 Michael Meissner +2024-04-12 Michael Meissner gcc/
[gcc(refs/users/meissner/heads/work164-bugs)] Simplify converting between SImode and SF/DFmode.
https://gcc.gnu.org/g:70490d46340627347654fe28f885a8c8577583c1
commit 70490d46340627347654fe28f885a8c8577583c1
Author: Michael Meissner
Date: Fri Apr 12 03:29:58 2024 -0400
Simplify converting between SImode and SF/DFmode.
2024-04-12 Michael Meissner
gcc/
PR target/90822
* gcc/config/rs6000.md (floatsidf2): If SImode can live in the
floating
point registers, directly issue a conversion to DImode and do the
floating point conversion.
(floatunssisf2): Likewise.
(floatunssidf2): Likewise.
(floatsisf2): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.md | 44
1 file changed, 40 insertions(+), 4 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f1f120199f3..32b0fd056fa 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6041,6 +6041,10 @@
; with a '#' template, and a define_split (with C code). The idea is
; to allow constant folding with the template of the define_insn,
; then to have the insns split later (between sched1 and final).
+;
+; If we have direct support for SImode in floating point registers, just
+; convert the SImode value to DImode. If we are loading the value from memory,
+; we will use the LFIWAX/LXSIWAX
(define_expand "floatsidf2"
[(parallel [(set (match_operand:DF 0 "gpc_reg_operand")
@@ -6054,7 +6058,13 @@
{
if (TARGET_LFIWAX && TARGET_FCFID)
{
- emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
+ if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
+ {
+ rtx di_tmp = convert_to_mode (DImode, operands[1], false);
+ emit_insn (gen_floatdidf2 (operands[0], di_tmp));
+ }
+ else
+ emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6110,6 +6120,10 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
+;
+; If we have direct support for SImode in floating point registers, just
+; convert the SImode value to DImode. If we are loading the value from memory,
+; we will use the LFIWAX/LXSIWAX
(define_expand "floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6120,7 +6134,13 @@
{
if (TARGET_LFIWZX && TARGET_FCFIDUS)
{
- emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
+ if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
+ {
+ rtx di_tmp = convert_to_mode (DImode, operands[1], true);
+ emit_insn (gen_floatdisf2 (operands[0], di_tmp));
+ }
+ else
+ emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else
@@ -6145,7 +6165,13 @@
{
if (TARGET_LFIWZX && TARGET_FCFID)
{
- emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
+ if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
+ {
+ rtx di_tmp = convert_to_mode (DImode, operands[1], true);
+ emit_insn (gen_floatdidf2 (operands[0], di_tmp));
+ }
+ else
+ emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6905,6 +6931,10 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
+;
+; If we have direct support for SImode in floating point registers, just
+; convert the SImode value to DImode. If we are loading the value from memory,
+; we will use the LFIWAX/LXSIWAX
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6915,7 +6945,13 @@
{
if (TARGET_FCFIDS && TARGET_LFIWAX)
{
- emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
+ if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
+ {
+ rtx di_tmp = convert_to_mode (DImode, operands[1], false);
+ emit_insn (gen_floatdisf2 (operands[0], di_tmp));
+ }
+ else
+ emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID && TARGET_LFIWAX)
[gcc(refs/users/meissner/heads/work164-bugs)] Revert all changes
https://gcc.gnu.org/g:d97e784f9887aece6d857e5790ea931ea6e044ee
commit d97e784f9887aece6d857e5790ea931ea6e044ee
Author: Michael Meissner
Date: Fri Apr 12 03:25:09 2024 -0400
Revert all changes
Diff:
---
gcc/config/rs6000/rs6000.md | 44
1 file changed, 4 insertions(+), 40 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 251b5c486b0..f1f120199f3 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6041,10 +6041,6 @@
; with a '#' template, and a define_split (with C code). The idea is
; to allow constant folding with the template of the define_insn,
; then to have the insns split later (between sched1 and final).
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatsidf2"
[(parallel [(set (match_operand:DF 0 "gpc_reg_operand")
@@ -6058,13 +6054,7 @@
{
if (TARGET_LFIWAX && TARGET_FCFID)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], false);
- emit_insn (gen_floatdidf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
+ emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6120,10 +6110,6 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6134,13 +6120,7 @@
{
if (TARGET_LFIWZX && TARGET_FCFIDUS)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], true);
- emit_insn (gen_floatdisf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
+ emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else
@@ -6165,13 +6145,7 @@
{
if (TARGET_LFIWZX && TARGET_FCFID)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], false);
- emit_insn (gen_floatunsdidf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
+ emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID)
@@ -6931,10 +6905,6 @@
;; If we don't have a direct conversion to single precision, don't enable this
;; conversion for 32-bit without fast math, because we don't have the insn to
;; generate the fixup swizzle to avoid double rounding problems.
-;
-; If we have direct support for SImode in floating point registers, just
-; convert the SImode value to DImode. If we are loading the value from memory,
-; we will use the LFIWAX/LXSIWAX
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(float:SF (match_operand:SI 1 "nonimmediate_operand")))]
@@ -6945,13 +6915,7 @@
{
if (TARGET_FCFIDS && TARGET_LFIWAX)
{
- if (TARGET_POWERPC64 && TARGET_P8_VECTOR)
- {
- rtx di_tmp = convert_to_mode (DImode, operands[1], false);
- emit_insn (gen_floatdisf2 (operands[0], di_tmp));
- }
- else
- emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
+ emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
DONE;
}
else if (TARGET_FCFID && TARGET_LFIWAX)
[gcc r14-9931] testsuite: Fix loop-interchange-16.c
https://gcc.gnu.org/g:b6c8259076a336e8082853ed6dda083c25a465d0
commit r14-9931-gb6c8259076a336e8082853ed6dda083c25a465d0
Author: Stefan Schulze Frielinghaus
Date: Fri Apr 12 09:20:53 2024 +0200
testsuite: Fix loop-interchange-16.c
Prevent loop unrolling of the innermost loop because otherwise we are
left with no loop interchange for targets like s390 which have a more
aggressive loop unrolling strategy.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/loop-interchange-16.c: Prevent loop unrolling
of the innermost loop.
Diff:
---
gcc/testsuite/gcc.dg/tree-ssa/loop-interchange-16.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-interchange-16.c
b/gcc/testsuite/gcc.dg/tree-ssa/loop-interchange-16.c
index 781555e085d..bbcb14f9c6c 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-interchange-16.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-interchange-16.c
@@ -11,6 +11,7 @@ double s231(int iterations)
//loop with data dependency
for (int nl = 0; nl < 100*(iterations/LEN_2D); nl++) {
for (int i = 0; i < LEN_2D; ++i) {
+#pragma GCC unroll 0
for (int j = 1; j < LEN_2D; j++) {
aa[j][i] = aa[j - 1][i] + bb[j][i];
}
[gcc r14-9930] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P
https://gcc.gnu.org/g:dc51a6428f6d8e5a57b8b1bf559145288e87660b
commit r14-9930-gdc51a6428f6d8e5a57b8b1bf559145288e87660b
Author: Pan Li
Date: Fri Apr 12 11:12:24 2024 +0800
RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P
This patch would like to fix one ICE when vector is not enabled
in hook TARGET_FUNCTION_VALUE_REGNO_P implementation. The vector
regno is available if and only if the TARGET_VECTOR is true. The
previous implement missed this condition and then result in ICE
when rv64gc build option without vector.
The below test suite is passed for this patch.
* The rv64gcv fully regression tests.
* The rv64gc fully regression tests.
PR target/114639
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_function_value_regno_p): Add
TARGET_VECTOR predicate for V_RETURN regno.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr114639-1.c: New test.
* gcc.target/riscv/pr114639-2.c: New test.
* gcc.target/riscv/pr114639-3.c: New test.
* gcc.target/riscv/pr114639-4.c: New test.
Signed-off-by: Pan Li
Diff:
---
gcc/config/riscv/riscv.cc | 2 +-
gcc/testsuite/gcc.target/riscv/pr114639-1.c | 11 +++
gcc/testsuite/gcc.target/riscv/pr114639-2.c | 11 +++
gcc/testsuite/gcc.target/riscv/pr114639-3.c | 11 +++
gcc/testsuite/gcc.target/riscv/pr114639-4.c | 11 +++
5 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 91f017dd52a..e5f00806bb9 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -11008,7 +11008,7 @@ riscv_function_value_regno_p (const unsigned regno)
if (FP_RETURN_FIRST <= regno && regno <= FP_RETURN_LAST)
return true;
- if (regno == V_RETURN)
+ if (TARGET_VECTOR && regno == V_RETURN)
return true;
return false;
diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-1.c
b/gcc/testsuite/gcc.target/riscv/pr114639-1.c
new file mode 100644
index 000..f41723193a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr114639-1.c
@@ -0,0 +1,11 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -std=gnu89 -O3" } */
+
+g (a, b) {}
+
+f (xx)
+ void* xx;
+{
+ __builtin_apply ((void*)g, xx, 200);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-2.c
b/gcc/testsuite/gcc.target/riscv/pr114639-2.c
new file mode 100644
index 000..0c402c4b254
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr114639-2.c
@@ -0,0 +1,11 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64imac -mabi=lp64 -std=gnu89 -O3" } */
+
+g (a, b) {}
+
+f (xx)
+ void* xx;
+{
+ __builtin_apply ((void*)g, xx, 200);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-3.c
b/gcc/testsuite/gcc.target/riscv/pr114639-3.c
new file mode 100644
index 000..ffb0d6d162d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr114639-3.c
@@ -0,0 +1,11 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc -mabi=ilp32d -std=gnu89 -O3" } */
+
+g (a, b) {}
+
+f (xx)
+ void* xx;
+{
+ __builtin_apply ((void*)g, xx, 200);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-4.c
b/gcc/testsuite/gcc.target/riscv/pr114639-4.c
new file mode 100644
index 000..a6e229101ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr114639-4.c
@@ -0,0 +1,11 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv32imac -mabi=ilp32 -std=gnu89 -O3" } */
+
+g (a, b) {}
+
+f (xx)
+ void* xx;
+{
+ __builtin_apply ((void*)g, xx, 200);
+}
