[gcc r14-10192] driver: Move -fdiagnostics-urls= early like -fdiagnostics-color= [PR114980]

[Xi Ruoyao via Gcc-cvs]

https://gcc.gnu.org/g:21051de4bed3d541804bf965cbdc3e8047698777

commit r14-10192-g21051de4bed3d541804bf965cbdc3e8047698777
Author: Xi Ruoyao 
Date:   Wed May 8 11:25:57 2024 +0800

driver: Move -fdiagnostics-urls= early like -fdiagnostics-color= [PR114980]

In GCC 14 we started to emit URLs for "command-line option  is
valid for  but not " and "-Werror= argument
'-Werror=' is not valid for " warnings.  So we should
have moved -fdiagnostics-urls= early like -fdiagnostics-color=, or
-fdiagnostics-urls= wouldn't be able to control URLs in these warnings.

No test cases are added because with TERM=xterm-256colors PR114980
already triggers some test failures.

gcc/ChangeLog:

PR driver/114980
* opts-common.cc (prune_options): Move -fdiagnostics-urls=
early like -fdiagnostics-color=.

(cherry picked from commit f75806ec63ec1af2d76a194e5fa73e114b2b8857)

Diff:
---
 gcc/opts-common.cc | 13 +
 1 file changed, 13 insertions(+)

diff --git a/gcc/opts-common.cc b/gcc/opts-common.cc
index 4a2dff243b0c..2d1e86ff94fa 100644
--- a/gcc/opts-common.cc
+++ b/gcc/opts-common.cc
@@ -1152,6 +1152,7 @@ prune_options (struct cl_decoded_option **decoded_options,
   unsigned int options_to_prepend = 0;
   unsigned int Wcomplain_wrong_lang_idx = 0;
   unsigned int fdiagnostics_color_idx = 0;
+  unsigned int fdiagnostics_urls_idx = 0;
 
   /* Remove arguments which are negated by others after them.  */
   new_decoded_options_count = 0;
@@ -1185,6 +1186,12 @@ prune_options (struct cl_decoded_option 
**decoded_options,
++options_to_prepend;
  fdiagnostics_color_idx = i;
  continue;
+   case OPT_fdiagnostics_urls_:
+ gcc_checking_assert (i != 0);
+ if (fdiagnostics_urls_idx == 0)
+   ++options_to_prepend;
+ fdiagnostics_urls_idx = i;
+ continue;
 
default:
  gcc_assert (opt_idx < cl_options_count);
@@ -1248,6 +1255,12 @@ keep:
= old_decoded_options[fdiagnostics_color_idx];
  new_decoded_options_count++;
}
+  if (fdiagnostics_urls_idx != 0)
+   {
+ new_decoded_options[argv_0 + options_prepended++]
+   = old_decoded_options[fdiagnostics_urls_idx];
+ new_decoded_options_count++;
+   }
   gcc_checking_assert (options_to_prepend == options_prepended);
 }

[gcc r15-355] driver: Move -fdiagnostics-urls= early like -fdiagnostics-color= [PR114980]

[Xi Ruoyao via Gcc-cvs]

https://gcc.gnu.org/g:f75806ec63ec1af2d76a194e5fa73e114b2b8857

commit r15-355-gf75806ec63ec1af2d76a194e5fa73e114b2b8857
Author: Xi Ruoyao 
Date:   Wed May 8 11:25:57 2024 +0800

driver: Move -fdiagnostics-urls= early like -fdiagnostics-color= [PR114980]

In GCC 14 we started to emit URLs for "command-line option  is
valid for  but not " and "-Werror= argument
'-Werror=' is not valid for " warnings.  So we should
have moved -fdiagnostics-urls= early like -fdiagnostics-color=, or
-fdiagnostics-urls= wouldn't be able to control URLs in these warnings.

No test cases are added because with TERM=xterm-256colors PR114980
already triggers some test failures.

gcc/ChangeLog:

PR driver/114980
* opts-common.cc (prune_options): Move -fdiagnostics-urls=
early like -fdiagnostics-color=.

Diff:
---
 gcc/opts-common.cc | 13 +
 1 file changed, 13 insertions(+)

diff --git a/gcc/opts-common.cc b/gcc/opts-common.cc
index 4a2dff243b0c..2d1e86ff94fa 100644
--- a/gcc/opts-common.cc
+++ b/gcc/opts-common.cc
@@ -1152,6 +1152,7 @@ prune_options (struct cl_decoded_option **decoded_options,
   unsigned int options_to_prepend = 0;
   unsigned int Wcomplain_wrong_lang_idx = 0;
   unsigned int fdiagnostics_color_idx = 0;
+  unsigned int fdiagnostics_urls_idx = 0;
 
   /* Remove arguments which are negated by others after them.  */
   new_decoded_options_count = 0;
@@ -1185,6 +1186,12 @@ prune_options (struct cl_decoded_option 
**decoded_options,
++options_to_prepend;
  fdiagnostics_color_idx = i;
  continue;
+   case OPT_fdiagnostics_urls_:
+ gcc_checking_assert (i != 0);
+ if (fdiagnostics_urls_idx == 0)
+   ++options_to_prepend;
+ fdiagnostics_urls_idx = i;
+ continue;
 
default:
  gcc_assert (opt_idx < cl_options_count);
@@ -1248,6 +1255,12 @@ keep:
= old_decoded_options[fdiagnostics_color_idx];
  new_decoded_options_count++;
}
+  if (fdiagnostics_urls_idx != 0)
+   {
+ new_decoded_options[argv_0 + options_prepended++]
+   = old_decoded_options[fdiagnostics_urls_idx];
+ new_decoded_options_count++;
+   }
   gcc_checking_assert (options_to_prepend == options_prepended);
 }

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Provide splitting guidance to combine to faciliate shNadd.uw generation

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:13d1b47251a94a67d698d4283caf754382ee27ea

commit 13d1b47251a94a67d698d4283caf754382ee27ea
Author: Jeff Law 
Date:   Thu May 9 21:07:06 2024 -0600

[committed] [RISC-V] Provide splitting guidance to combine to faciliate 
shNadd.uw generation

This fixes a minor code quality issue I found while comparing GCC and LLVM.
Essentially we want to do a bit of re-association to generate shNadd.uw
instructions.

Combine does the right thing and finds all the necessary instructions,
reassociates the operands, combines constants, etc.  Where is fails is 
finding
a good split point.  The backend can trivially provide guidance on how to 
split
via a define_split pattern.

This has survived both Ventana's internal CI system (rv64gcb) as well as my 
own
(rv64gc, rv32gcv).

I'll wait for the external CI system to give the all-clear before pushing.

gcc/
* config/riscv/bitmanip.md: Add splitter for shadd feeding another
add instruction.

gcc/testsuite/

* gcc.target/riscv/zba-shadduw.c: New test.

(cherry picked from commit bfb88b1406cdd8d3f97e280b0d63529aa925f18a)

Diff:
---
 gcc/config/riscv/bitmanip.md | 17 ++
 gcc/testsuite/gcc.target/riscv/zba-shadduw.c | 35 
 2 files changed, 52 insertions(+)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index ad3ad758959e..d76a72d30e02 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -184,6 +184,23 @@
   [(set_attr "type" "bitmanip")
(set_attr "mode" "DI")])
 
+;; Combine will reassociate the operands in the most useful way here.  We
+;; just have to give it guidance on where to split the result to facilitate
+;; shNadd.uw generation.
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+   (plus:DI (plus:DI (and:DI (ashift:DI (match_operand:DI 1 
"register_operand")
+(match_operand:QI 2 
"imm123_operand"))
+ (match_operand 3 
"consecutive_bits32_operand"))
+ (match_operand:DI 4 "register_operand"))
+(match_operand 5 "immediate_operand")))]
+  "TARGET_64BIT && TARGET_ZBA"
+  [(set (match_dup 0)
+   (plus:DI (and:DI (ashift:DI (match_dup 1) (match_dup 2))
+(match_dup 3))
+(match_dup 4)))
+   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 5)))])
+
 ;; ZBB extension.
 
 (define_expand "clzdi2"
diff --git a/gcc/testsuite/gcc.target/riscv/zba-shadduw.c 
b/gcc/testsuite/gcc.target/riscv/zba-shadduw.c
new file mode 100644
index ..5b77447e6813
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zba-shadduw.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zba -mabi=lp64" } */
+
+typedef struct simple_bitmap_def
+{
+  unsigned char *popcount;
+  unsigned int n_bits;
+  unsigned int size;
+  unsigned long elms[1];
+} *sbitmap;
+typedef const struct simple_bitmap_def *const_sbitmap;
+
+typedef unsigned long *sbitmap_ptr;
+typedef const unsigned long *const_sbitmap_ptr;
+static unsigned long sbitmap_elt_popcount (unsigned long);
+
+void
+sbitmap_a_or_b (sbitmap dst, const_sbitmap a, const_sbitmap b)
+{
+  unsigned int i, n = dst->size;
+  sbitmap_ptr dstp = dst->elms;
+  const_sbitmap_ptr ap = a->elms;
+  const_sbitmap_ptr bp = b->elms;
+  unsigned char has_popcount = dst->popcount != ((void *) 0);
+
+  for (i = 0; i < n; i++)
+{
+  const unsigned long tmp = *ap++ | *bp++;
+  *dstp++ = tmp;
+}
+}
+
+
+/* { dg-final { scan-assembler "sh3add.uw" } } */
+/* { dg-final { scan-assembler-not {\mslli.uw} } } */

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Make full-vec-move1.c test robust for optimization

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:788ed48d01b4fb85689ae1d7a0033cb05a48637f

commit 788ed48d01b4fb85689ae1d7a0033cb05a48637f
Author: Pan Li 
Date:   Thu May 9 10:56:46 2024 +0800

RISC-V: Make full-vec-move1.c test robust for optimization

During investigate the support of early break autovec, we notice
the test full-vec-move1.c will be optimized to 'return 0;' in main
function body.  Because somehow the value of V type is compiler
time constant,  and then the second loop will be considered as
assert (true).

Thus,  the ccp4 pass will eliminate these stmt and just return 0.

typedef int16_t V __attribute__((vector_size (128)));

int main ()
{
  V v;
  for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
(v)[i] = i;

  V res = v;
  for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
assert (res[i] == i); // will be optimized to assert (true)
}

This patch would like to introduce a extern function to use the res[i]
that get rid of the ccp4 optimization.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c:
Introduce extern func use to get rid of ccp4 optimization.

Signed-off-by: Pan Li 
(cherry picked from commit b1520d2260c5e0cfcd7a4354fab70f66e2912ff2)

Diff:
---
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
index d73bad4af6f7..fae2ae91572f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
@@ -2,11 +2,12 @@
 /* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d 
-fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include 
-#include 
 
 /* This would cause us to emit a vl1r.v for VNx4HImode even when
the hardware vector size vl > 64.  */
 
+extern int16_t test_element (int16_t);
+
 typedef int16_t V __attribute__((vector_size (128)));
 
 int main ()
@@ -14,9 +15,10 @@ int main ()
   V v;
   for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
 (v)[i] = i;
+
   V res = v;
   for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
-assert (res[i] == i);
+test_element (res[i]);
 }
 
 /* { dg-final { scan-assembler-not {vl[1248]r.v} } }  */

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add tests for cpymemsi expansion

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:2bb25f97841524649fef9d58ce84ca71748e2f2b

commit 2bb25f97841524649fef9d58ce84ca71748e2f2b
Author: Christoph Müllner 
Date:   Thu Apr 11 12:07:10 2024 +0200

RISC-V: Add tests for cpymemsi expansion

cpymemsi expansion was available for RISC-V since the initial port.
However, there are not tests to detect regression.
This patch adds such tests.

Three of the tests target the expansion requirements (known length and
alignment). One test reuses an existing memcpy test from the by-pieces
framework (gcc/testsuite/gcc.dg/torture/inline-mem-cpy-1.c).

gcc/testsuite/ChangeLog:

* gcc.target/riscv/cpymemsi-1.c: New test.
* gcc.target/riscv/cpymemsi-2.c: New test.
* gcc.target/riscv/cpymemsi-3.c: New test.
* gcc.target/riscv/cpymemsi.c: New test.

Signed-off-by: Christoph Müllner 
(cherry picked from commit 4d38e88227ea48e559a2f354c0e62d372e181b82)

Diff:
---
 gcc/testsuite/gcc.target/riscv/cpymemsi-1.c |  9 ++
 gcc/testsuite/gcc.target/riscv/cpymemsi-2.c | 42 
 gcc/testsuite/gcc.target/riscv/cpymemsi-3.c | 43 +
 gcc/testsuite/gcc.target/riscv/cpymemsi.c   | 22 +++
 4 files changed, 116 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c 
b/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
new file mode 100644
index ..983b564ccaf7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-march=rv32gc -save-temps -g0 -fno-lto" { target { rv32 } } } 
*/
+/* { dg-options "-march=rv64gc -save-temps -g0 -fno-lto" { target { rv64 } } } 
*/
+/* { dg-additional-options "-DRUN_FRACTION=11" { target simulator } } */
+/* { dg-timeout-factor 2 } */
+
+#include "../../gcc.dg/memcmp-1.c"
+/* Yeah, this memcmp test exercises plenty of memcpy, more than any of the
+   memcpy tests.  */
diff --git a/gcc/testsuite/gcc.target/riscv/cpymemsi-2.c 
b/gcc/testsuite/gcc.target/riscv/cpymemsi-2.c
new file mode 100644
index ..833d1c044876
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpymemsi-2.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" "-Oz" } } */
+
+#include 
+#define aligned32 __attribute__ ((aligned (32)))
+
+const char myconst15[] aligned32 = { 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7 };
+const char myconst23[] aligned32 = { 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7 };
+const char myconst31[] aligned32 = { 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7 };
+
+/* No expansion (unknown alignment) */
+#define MY_MEM_CPY_N(N)\
+void my_mem_cpy_##N (char *b1, const char *b2) \
+{  \
+  __builtin_memcpy (b1, b2, N);\
+}
+
+/* No expansion (unknown alignment) */
+#define MY_MEM_CPY_CONST_N(N)  \
+void my_mem_cpy_const_##N (char *b1)   \
+{  \
+  __builtin_memcpy (b1, myconst##N, sizeof(myconst##N));\
+}
+
+MY_MEM_CPY_N(15)
+MY_MEM_CPY_CONST_N(15)
+
+MY_MEM_CPY_N(23)
+MY_MEM_CPY_CONST_N(23)
+
+MY_MEM_CPY_N(31)
+MY_MEM_CPY_CONST_N(31)
+
+/* { dg-final { scan-assembler-times "\t(call|tail)\tmemcpy" 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cpymemsi-3.c 
b/gcc/testsuite/gcc.target/riscv/cpymemsi-3.c
new file mode 100644
index ..803765195b24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpymemsi-3.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" "-Oz" } } */
+
+#include 
+#define aligned32 __attribute__ ((aligned (32)))
+
+const char myconst15[] aligned32 = { 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7 };
+const char myconst23[] aligned32 = { 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7 };
+const char myconst31[] aligned32 = { 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7 };
+
+#define MY_MEM_CPY_ALIGNED_N(N)\
+void my_mem_cpy_aligned_##N(char *b1, const char *b2)  \
+{  

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:b59bc760740eccd8f7b76d218ed759d9ae6604c8

commit b59bc760740eccd8f7b76d218ed759d9ae6604c8
Author: Xiao Zeng 
Date:   Wed May 8 14:00:58 2024 -0600

[PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16

1 This patch implements the Nan-box of bf16.

2 Please refer to the Nan-box implementation of hf16 in:



3 The discussion about Nan-box can be found on the website:



4 Below test are passed for this patch
* The riscv fully regression test.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_legitimize_move): Expand movbf
with Nan-boxing value.
* config/riscv/riscv.md (*movbf_softfloat_boxing): New pattern.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/_Bfloat16-nanboxing.c: New test.

(cherry picked from commit ce51e6727c9d69bbab0e766c449e60fd41f5f2f9)

Diff:
---
 gcc/config/riscv/riscv.cc  | 52 --
 gcc/config/riscv/riscv.md  | 12 -
 .../gcc.target/riscv/_Bfloat16-nanboxing.c | 38 
 3 files changed, 77 insertions(+), 25 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 633b55f9707a..2eac67b0ce0a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3130,35 +3130,39 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx 
src)
 }
 
   /* In order to fit NaN boxing, expand
- (set FP_REG (reg:HF src))
+ (set FP_REG (reg:HF/BF src))
  to
  (set (reg:SI/DI mask) (const_int -65536)
- (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF src) 0)))
+ (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF/BF src) 0)))
  (set (reg:SI/DI temp) (ior:SI/DI (reg:SI/DI mask) (reg:SI/DI temp)))
- (set (reg:HF dest) (unspec:HF [ (reg:SI/DI temp) ] UNSPEC_FMV_SFP16_X))
+ (set (reg:HF/BF dest) (unspec:HF/BF[ (reg:SI/DI temp) ]
+   UNSPEC_FMV_SFP16_X/UNSPEC_FMV_SBF16_X))
  */
 
- if (TARGET_HARD_FLOAT
- && !TARGET_ZFHMIN && mode == HFmode
- && REG_P (dest) && FP_REG_P (REGNO (dest))
- && REG_P (src) && !FP_REG_P (REGNO (src))
- && can_create_pseudo_p ())
-   {
- rtx mask = force_reg (word_mode, gen_int_mode (-65536, word_mode));
- rtx temp = gen_reg_rtx (word_mode);
- emit_insn (gen_extend_insn (temp,
-simplify_gen_subreg (HImode, src, mode, 0),
-word_mode, HImode, 1));
- if (word_mode == SImode)
-   emit_insn (gen_iorsi3 (temp, mask, temp));
- else
-   emit_insn (gen_iordi3 (temp, mask, temp));
-
- riscv_emit_move (dest, gen_rtx_UNSPEC (HFmode, gen_rtvec (1, temp),
-   UNSPEC_FMV_SFP16_X));
-
- return true;
-   }
+  if (TARGET_HARD_FLOAT
+  && ((!TARGET_ZFHMIN && mode == HFmode)
+ || (!TARGET_ZFBFMIN && mode == BFmode))
+  && REG_P (dest) && FP_REG_P (REGNO (dest))
+  && REG_P (src) && !FP_REG_P (REGNO (src))
+  && can_create_pseudo_p ())
+{
+  rtx mask = force_reg (word_mode, gen_int_mode (-65536, word_mode));
+  rtx temp = gen_reg_rtx (word_mode);
+  emit_insn (gen_extend_insn (temp,
+ simplify_gen_subreg (HImode, src, mode, 0),
+ word_mode, HImode, 1));
+  if (word_mode == SImode)
+   emit_insn (gen_iorsi3 (temp, mask, temp));
+  else
+   emit_insn (gen_iordi3 (temp, mask, temp));
+
+  riscv_emit_move (dest,
+  gen_rtx_UNSPEC (mode, gen_rtvec (1, temp),
+  mode == HFmode ? UNSPEC_FMV_SFP16_X
+ : UNSPEC_FMV_SBF16_X));
+
+  return true;
+}
 
   /* We need to deal with constants that would be legitimate
  immediate_operands but aren't legitimate move_operands.  */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 620a1b3bd32f..4d6de9925572 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -86,8 +86,9 @@
   ;; String unspecs
   UNSPEC_STRLEN
 
-  ;; Workaround for HFmode without hardware extension
+  ;; Workaround for HFmode and BFmode without hardware extension
   UNSPEC_FMV_SFP16_X
+  UNSPEC_FMV_SBF16_X
 
   ;; XTheadFmv moves
   UNSPEC_XTHEADFMV
@@ -1926,6 +1927,15 @@
   [(set_attr "type" "fmove")
(set_attr "mode" "SF")])
 
+(define_insn "*movbf_softfloat_boxing"
+  [(set (match_operand:BF 0 "register_operand"   "=f")
+   (unspec:BF [(match_operand:X 1 "register_operand" " r")]
+UNSPEC_FMV_SBF16_X))]
+  "!TARGET_ZFBFMIN"
+  "fmv.w.x\t%0,%1"
+  [(set_attr "type" "fmove")
+   

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usage in constant synthesis

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:f273ad20d6b2b3f196a0c99a5a0c419cc13d862a

commit f273ad20d6b2b3f196a0c99a5a0c419cc13d862a
Author: Jeff Law 
Date:   Wed May 8 13:44:00 2024 -0600

[RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usage in constant 
synthesis

Reposting without the patch that ignores whitespace.  The CI system doesn't
like including both patches, that'll generate a failure to apply and none of
the tests actually get run.

So I managed to goof the if-then-else level of the bseti bits last week.  
They
were supposed to be a last ditch effort to improve the result, but ended up
inside a conditional where they don't really belong.  I almost always use 
Zba,
Zbb and Zbs together, so it slipped by.

So it's NFC if you always test with Zbb and Zbs enabled together.  But if 
you
enabled Zbs without Zbb you'd see a failure to use bseti.

gcc/
* config/riscv/riscv.cc (riscv_build_integer_1): Fix incorrect
if-then-else nesting of Zbs code.

(cherry picked from commit 1c234097487927a4388ddcc690b63597bb3a90dc)

Diff:
---
 gcc/config/riscv/riscv.cc | 81 ---
 1 file changed, 41 insertions(+), 40 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 62207b6b2273..633b55f9707a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -878,50 +878,51 @@ riscv_build_integer_1 (struct riscv_integer_op 
codes[RISCV_MAX_INTEGER_OPS],
  codes[1].use_uw = false;
  cost = 2;
}
-  /* Final cases, particularly focused on bseti.  */
-  else if (cost > 2 && TARGET_ZBS)
-   {
- int i = 0;
+}
 
- /* First handle any bits set by LUI.  Be careful of the
-SImode sign bit!.  */
- if (value & 0x7800)
-   {
- alt_codes[i].code = (i == 0 ? UNKNOWN : IOR);
- alt_codes[i].value = value & 0x7800;
- alt_codes[i].use_uw = false;
- value &= ~0x7800;
- i++;
-   }
+  /* Final cases, particularly focused on bseti.  */
+  if (cost > 2 && TARGET_ZBS)
+{
+  int i = 0;
 
- /* Next, any bits we can handle with addi.  */
- if (value & 0x7ff)
-   {
- alt_codes[i].code = (i == 0 ? UNKNOWN : PLUS);
- alt_codes[i].value = value & 0x7ff;
- alt_codes[i].use_uw = false;
- value &= ~0x7ff;
- i++;
-   }
+  /* First handle any bits set by LUI.  Be careful of the
+SImode sign bit!.  */
+  if (value & 0x7800)
+   {
+ alt_codes[i].code = (i == 0 ? UNKNOWN : IOR);
+ alt_codes[i].value = value & 0x7800;
+ alt_codes[i].use_uw = false;
+ value &= ~0x7800;
+  i++;
+   }
 
- /* And any residuals with bseti.  */
- while (i < cost && value)
-   {
- HOST_WIDE_INT bit = ctz_hwi (value);
- alt_codes[i].code = (i == 0 ? UNKNOWN : IOR);
- alt_codes[i].value = 1UL << bit;
- alt_codes[i].use_uw = false;
- value &= ~(1ULL << bit);
- i++;
-   }
+  /* Next, any bits we can handle with addi.  */
+  if (value & 0x7ff)
+   {
+ alt_codes[i].code = (i == 0 ? UNKNOWN : PLUS);
+ alt_codes[i].value = value & 0x7ff;
+ alt_codes[i].use_uw = false;
+ value &= ~0x7ff;
+ i++;
+   }
 
- /* If LUI+ADDI+BSETI resulted in a more efficient
-sequence, then use it.  */
- if (i < cost)
-   {
- memcpy (codes, alt_codes, sizeof (alt_codes));
- cost = i;
-   }
+  /* And any residuals with bseti.  */
+  while (i < cost && value)
+   {
+ HOST_WIDE_INT bit = ctz_hwi (value);
+ alt_codes[i].code = (i == 0 ? UNKNOWN : IOR);
+ alt_codes[i].value = 1UL << bit;
+ alt_codes[i].use_uw = false;
+ value &= ~(1ULL << bit);
+ i++;
+   }
+
+  /* If LUI+ADDI+BSETI resulted in a more efficient
+sequence, then use it.  */
+  if (i < cost)
+   {
+ memcpy (codes, alt_codes, sizeof (alt_codes));
+ cost = i;
}
 }

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cover sign-extensions in lshr3_zero_extend_4

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:b6dc4a54639ee85a425f46b86e152d99d209ffa4

commit b6dc4a54639ee85a425f46b86e152d99d209ffa4
Author: Christoph Müllner 
Date:   Tue May 7 22:23:26 2024 +0200

RISC-V: Cover sign-extensions in lshr3_zero_extend_4

The lshr3_zero_extend_4 pattern targets bit extraction
with zero-extension. This pattern represents the canonical form
of zero-extensions of a logical right shift.

The same optimization can be applied to sign-extensions.
Given the two optimizations are so similar, this patch converts
the existing one to also cover the sign-extension case as well.

gcc/ChangeLog:

* config/riscv/iterators.md (ashiftrt): New code attribute
'extract_shift' and adding extractions to optab.
* config/riscv/riscv.md (*lshr3_zero_extend_4): Rename 
to...
(*3):...this and add support for
sign-extensions.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/extend-shift-helpers.h: Add helpers for
sign-extension.
* gcc.target/riscv/sign-extend-rshift-32.c: New test.
* gcc.target/riscv/sign-extend-rshift-64.c: New test.
* gcc.target/riscv/sign-extend-rshift.c: New test.

Signed-off-by: Christoph Müllner 
(cherry picked from commit 3ee30d7981987b86bd6a9a2675e26fadec48e5cd)

Diff:
---
 gcc/config/riscv/iterators.md  |   4 +
 gcc/config/riscv/riscv.md  |  25 +++--
 .../gcc.target/riscv/extend-shift-helpers.h|  20 
 .../gcc.target/riscv/sign-extend-rshift-32.c   |  17 +++
 .../gcc.target/riscv/sign-extend-rshift-64.c   |  17 +++
 .../gcc.target/riscv/sign-extend-rshift.c  | 123 +
 6 files changed, 198 insertions(+), 8 deletions(-)

diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index c5ca01f382a9..8a9d1986b4ae 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -155,6 +155,8 @@
 (define_code_iterator any_extract [sign_extract zero_extract])
 (define_code_attr extract_sidi_shift [(sign_extract "sraiw")
  (zero_extract "srliw")])
+(define_code_attr extract_shift [(sign_extract "ashiftrt")
+(zero_extract "lshiftrt")])
 
 ;; This code iterator allows the two right shift instructions to be
 ;; generated from the same template.
@@ -261,6 +263,8 @@
 (us_minus "ussub")
 (sign_extend "extend")
 (zero_extend "zero_extend")
+(sign_extract "extract")
+(zero_extract "zero_extract")
 (fix "fix_trunc")
 (unsigned_fix "fixuns_trunc")])
 
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 58bf77122779..620a1b3bd32f 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2793,24 +2793,33 @@
   [(set_attr "type" "shift")
(set_attr "mode" "SI")])
 
-;; Canonical form for a zero-extend of a logical right shift.
-;; Special cases are handled above.
-;; Skip for single-bit extraction (Zbs/XTheadBs) and th.extu (XTheadBb)
-(define_insn_and_split "*lshr3_zero_extend_4"
+;; Canonical form for a extend of a logical shift right (sign/zero extraction).
+;; Special cases, that are ignored (handled elsewhere):
+;; * Single-bit extraction (Zbs/XTheadBs)
+;; * Single-bit extraction (Zicondops/XVentanaCondops)
+;; * Single-bit extraction (SFB)
+;; * Extraction instruction th.ext(u) (XTheadBb)
+;; * lshrsi3_extend_2 (see above)
+(define_insn_and_split "*3"
   [(set (match_operand:GPR 0 "register_operand" "=r")
-(zero_extract:GPR
+(any_extract:GPR
(match_operand:GPR 1 "register_operand" " r")
(match_operand 2 "const_int_operand")
(match_operand 3 "const_int_operand")))
(clobber (match_scratch:GPR  4 "="))]
-  "!((TARGET_ZBS || TARGET_XTHEADBS) && (INTVAL (operands[2]) == 1))
-   && !TARGET_XTHEADBB"
+  "!((TARGET_ZBS || TARGET_XTHEADBS || TARGET_ZICOND
+  || TARGET_XVENTANACONDOPS || TARGET_SFB_ALU)
+ && (INTVAL (operands[2]) == 1))
+   && !TARGET_XTHEADBB
+   && !(TARGET_64BIT
+&& (INTVAL (operands[3]) > 0)
+&& (INTVAL (operands[2]) + INTVAL (operands[3]) == 32))"
   "#"
   "&& reload_completed"
   [(set (match_dup 4)
  (ashift:GPR (match_dup 1) (match_dup 2)))
(set (match_dup 0)
- (lshiftrt:GPR (match_dup 4) (match_dup 3)))]
+ (:GPR (match_dup 4) (match_dup 3)))]
 {
   int regbits = GET_MODE_BITSIZE (GET_MODE (operands[0])).to_constant ();
   int sizebits = INTVAL (operands[2]);
diff --git a/gcc/testsuite/gcc.target/riscv/extend-shift-helpers.h 
b/gcc/testsuite/gcc.target/riscv/extend-shift-helpers.h
index 4853fe490d8e..720672de2426 100644
--- a/gcc/testsuite/gcc.target/riscv/extend-shift-helpers.h
+++ 

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add zero_extract support for rv64gc

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:38fc117452afa21fac0ca3f743fc09d35c3f8c5c

commit 38fc117452afa21fac0ca3f743fc09d35c3f8c5c
Author: Christoph Müllner 
Date:   Mon May 6 12:33:32 2024 +0200

RISC-V: Add zero_extract support for rv64gc

The combiner attempts to optimize a zero-extension of a logical right shift
using zero_extract. We already utilize this optimization for those cases
that result in a single instructions.  Let's add a insn_and_split
pattern that also matches the generic case, where we can emit an
optimized sequence of a slli/srli.

Tested with SPEC CPU 2017 (rv64gc).

PR target/111501

gcc/ChangeLog:

* config/riscv/riscv.md (*lshr3_zero_extend_4): New
pattern for zero-extraction.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/extend-shift-helpers.h: New test.
* gcc.target/riscv/pr111501.c: New test.
* gcc.target/riscv/zero-extend-rshift-32.c: New test.
* gcc.target/riscv/zero-extend-rshift-64.c: New test.
* gcc.target/riscv/zero-extend-rshift.c: New test.

Signed-off-by: Christoph Müllner 
(cherry picked from commit 3b9c760072c7792cbae6f38894756d2b96c2fd8c)

Diff:
---
 gcc/config/riscv/riscv.md  |  30 ++
 .../gcc.target/riscv/extend-shift-helpers.h|  26 +
 gcc/testsuite/gcc.target/riscv/pr111501.c  |  21 
 .../gcc.target/riscv/zero-extend-rshift-32.c   |  13 +++
 .../gcc.target/riscv/zero-extend-rshift-64.c   |  17 +++
 .../gcc.target/riscv/zero-extend-rshift.c  | 115 +
 6 files changed, 222 insertions(+)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b7fc13e4e611..58bf77122779 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2793,6 +2793,36 @@
   [(set_attr "type" "shift")
(set_attr "mode" "SI")])
 
+;; Canonical form for a zero-extend of a logical right shift.
+;; Special cases are handled above.
+;; Skip for single-bit extraction (Zbs/XTheadBs) and th.extu (XTheadBb)
+(define_insn_and_split "*lshr3_zero_extend_4"
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+(zero_extract:GPR
+   (match_operand:GPR 1 "register_operand" " r")
+   (match_operand 2 "const_int_operand")
+   (match_operand 3 "const_int_operand")))
+   (clobber (match_scratch:GPR  4 "="))]
+  "!((TARGET_ZBS || TARGET_XTHEADBS) && (INTVAL (operands[2]) == 1))
+   && !TARGET_XTHEADBB"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 4)
+ (ashift:GPR (match_dup 1) (match_dup 2)))
+   (set (match_dup 0)
+ (lshiftrt:GPR (match_dup 4) (match_dup 3)))]
+{
+  int regbits = GET_MODE_BITSIZE (GET_MODE (operands[0])).to_constant ();
+  int sizebits = INTVAL (operands[2]);
+  int startbits = INTVAL (operands[3]);
+  int lshamt = regbits - sizebits - startbits;
+  int rshamt = lshamt + startbits;
+  operands[2] = GEN_INT (lshamt);
+  operands[3] = GEN_INT (rshamt);
+}
+  [(set_attr "type" "shift")
+   (set_attr "mode" "")])
+
 ;; Handle AND with 2^N-1 for N from 12 to XLEN.  This can be split into
 ;; two logical shifts.  Otherwise it requires 3 instructions: lui,
 ;; xor/addi/srli, and.
diff --git a/gcc/testsuite/gcc.target/riscv/extend-shift-helpers.h 
b/gcc/testsuite/gcc.target/riscv/extend-shift-helpers.h
new file mode 100644
index ..4853fe490d8e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/extend-shift-helpers.h
@@ -0,0 +1,26 @@
+#ifndef EXTEND_SHIFT_HELPERS_H
+#define EXTEND_SHIFT_HELPERS_H
+
+#define RT_EXT_CT_RSHIFT_N_AT(RTS,RT,CTS,CT,N,ATS,AT)  \
+RTS RT \
+RTS##_##RT##_ext_##CTS##_##CT##_rshift_##N##_##ATS##_##AT(ATS AT v)\
+{  \
+return (CTS CT)(v >> N);   \
+}
+
+#define ULONG_EXT_USHORT_RSHIFT_N_ULONG(N) \
+   RT_EXT_CT_RSHIFT_N_AT(unsigned,long,unsigned,short,N,unsigned,long)
+
+#define ULONG_EXT_UINT_RSHIFT_N_ULONG(N) \
+   RT_EXT_CT_RSHIFT_N_AT(unsigned,long,unsigned,int,N,unsigned,long)
+
+#define UINT_EXT_USHORT_RSHIFT_N_UINT(N) \
+   RT_EXT_CT_RSHIFT_N_AT(unsigned,int,unsigned,short,N,unsigned,int)
+
+#define UINT_EXT_USHORT_RSHIFT_N_ULONG(N) \
+   RT_EXT_CT_RSHIFT_N_AT(unsigned,int,unsigned,short,N,unsigned,long)
+
+#define ULONG_EXT_USHORT_RSHIFT_N_UINT(N) \
+   RT_EXT_CT_RSHIFT_N_AT(unsigned,long,unsigned,short,N,unsigned,int)
+
+#endif /* EXTEND_SHIFT_HELPERS_H */
diff --git a/gcc/testsuite/gcc.target/riscv/pr111501.c 
b/gcc/testsuite/gcc.target/riscv/pr111501.c
new file mode 100644
index ..db48c34ce9af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr111501.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-options "-march=rv64gc" { target { rv64 } } } */
+/* { dg-skip-if "" { 

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:9041a047fe957232d9f9127791a08643b1087a36

commit 9041a047fe957232d9f9127791a08643b1087a36
Author: Christoph Müllner 
Date:   Tue May 7 23:26:02 2024 +0200

RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2

The pattern lshrsi3_zero_extend_2 extracts the MSB bits of the lower
32-bit word and zero-extends it back to DImode.
This is realized using srliw, which operates on 32-bit registers.

The same optimziation can be applied to sign-extensions when emitting
a sraiw instead of the srliw.

Given these two optimizations are so similar, this patch simply
converts the existing one to also cover the sign-extension case as well.

gcc/ChangeLog:

* config/riscv/iterators.md (sraiw): New code iterator 
'any_extract'.
New code attribute 'extract_sidi_shift'.
* config/riscv/riscv.md (*lshrsi3_zero_extend_2): Rename to...
(*lshrsi3_extend_2):...this and add support for sign-extensions.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sign-extend-1.c: Test sraiw 24 and sraiw 16.

Signed-off-by: Christoph Müllner 
(cherry picked from commit 4e46a3537ff57938a0d98fa524ac2fff8b08ae6d)

Diff:
---
 gcc/config/riscv/iterators.md  |  6 ++
 gcc/config/riscv/riscv.md  |  9 +
 gcc/testsuite/gcc.target/riscv/sign-extend-1.c | 14 ++
 3 files changed, 25 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 32e1b1403051..c5ca01f382a9 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -150,6 +150,12 @@
 ;; to use the same template.
 (define_code_iterator any_extend [sign_extend zero_extend])
 
+;; These code iterators allow unsigned and signed extraction to be generated
+;; from the same template.
+(define_code_iterator any_extract [sign_extract zero_extract])
+(define_code_attr extract_sidi_shift [(sign_extract "sraiw")
+ (zero_extract "srliw")])
+
 ;; This code iterator allows the two right shift instructions to be
 ;; generated from the same template.
 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 24558682eb8f..b7fc13e4e611 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2765,16 +2765,17 @@
   [(set_attr "type" "shift")
(set_attr "mode" "SI")])
 
-;; Canonical form for a zero-extend of a logical right shift.
-(define_insn "*lshrsi3_zero_extend_2"
+;; Canonical form for a sign/zero-extend of a logical right shift.
+;; Special case: extract MSB bits of lower 32-bit word
+(define_insn "*lshrsi3_extend_2"
   [(set (match_operand:DI   0 "register_operand" "=r")
-   (zero_extract:DI (match_operand:DI  1 "register_operand" " r")
+   (any_extract:DI (match_operand:DI  1 "register_operand" " r")
 (match_operand 2 "const_int_operand")
 (match_operand 3 "const_int_operand")))]
   "(TARGET_64BIT && (INTVAL (operands[3]) > 0)
 && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32))"
 {
-  return "srliw\t%0,%1,%3";
+  return "\t%0,%1,%3";
 }
   [(set_attr "type" "shift")
(set_attr "mode" "SI")])
diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend-1.c 
b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
index e9056ec0d424..d8c18dd1aaa7 100644
--- a/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
+++ b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
@@ -9,6 +9,20 @@ foo1 (int i)
 }
 /* { dg-final { scan-assembler "sraiw\ta\[0-9\],a\[0-9\],31" } } */
 
+signed char
+sub2 (long i)
+{
+  return i >> 24;
+}
+/* { dg-final { scan-assembler "sraiw\ta\[0-9\],a\[0-9\],24" } } */
+
+signed short
+sub3 (long i)
+{
+  return i >> 16;
+}
+/* { dg-final { scan-assembler "sraiw\ta\[0-9\],a\[0-9\],16" } } */
+
 /* { dg-final { scan-assembler-not "srai\t" } } */
 /* { dg-final { scan-assembler-not "srli\t" } } */
 /* { dg-final { scan-assembler-not "srliw\t" } } */

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add test for sraiw-31 special case

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:9a81321828844a7b663c78a9415770a247980e71

commit 9a81321828844a7b663c78a9415770a247980e71
Author: Christoph Müllner 
Date:   Tue May 7 22:59:44 2024 +0200

RISC-V: Add test for sraiw-31 special case

We already optimize a sign-extension of a right-shift by 31 in
si3_extend.  Let's add a test for that (similar to
zero-extend-1.c).

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sign-extend-1.c: New test.

Signed-off-by: Christoph Müllner 
(cherry picked from commit dd388198b8be52ab378c935fc517a269e0ba741c)

Diff:
---
 gcc/testsuite/gcc.target/riscv/sign-extend-1.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend-1.c 
b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
new file mode 100644
index ..e9056ec0d424
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
+
+signed long
+foo1 (int i)
+{
+  return i >> 31;
+}
+/* { dg-final { scan-assembler "sraiw\ta\[0-9\],a\[0-9\],31" } } */
+
+/* { dg-final { scan-assembler-not "srai\t" } } */
+/* { dg-final { scan-assembler-not "srli\t" } } */
+/* { dg-final { scan-assembler-not "srliw\t" } } */

[gcc r15-354] [committed] [RISC-V] Provide splitting guidance to combine to faciliate shNadd.uw generation

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:bfb88b1406cdd8d3f97e280b0d63529aa925f18a

commit r15-354-gbfb88b1406cdd8d3f97e280b0d63529aa925f18a
Author: Jeff Law 
Date:   Thu May 9 21:07:06 2024 -0600

[committed] [RISC-V] Provide splitting guidance to combine to faciliate 
shNadd.uw generation

This fixes a minor code quality issue I found while comparing GCC and LLVM.
Essentially we want to do a bit of re-association to generate shNadd.uw
instructions.

Combine does the right thing and finds all the necessary instructions,
reassociates the operands, combines constants, etc.  Where is fails is 
finding
a good split point.  The backend can trivially provide guidance on how to 
split
via a define_split pattern.

This has survived both Ventana's internal CI system (rv64gcb) as well as my 
own
(rv64gc, rv32gcv).

I'll wait for the external CI system to give the all-clear before pushing.

gcc/
* config/riscv/bitmanip.md: Add splitter for shadd feeding another
add instruction.

gcc/testsuite/

* gcc.target/riscv/zba-shadduw.c: New test.

Diff:
---
 gcc/config/riscv/bitmanip.md | 17 ++
 gcc/testsuite/gcc.target/riscv/zba-shadduw.c | 35 
 2 files changed, 52 insertions(+)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index ad3ad758959e..d76a72d30e02 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -184,6 +184,23 @@
   [(set_attr "type" "bitmanip")
(set_attr "mode" "DI")])
 
+;; Combine will reassociate the operands in the most useful way here.  We
+;; just have to give it guidance on where to split the result to facilitate
+;; shNadd.uw generation.
+(define_split
+  [(set (match_operand:DI 0 "register_operand")
+   (plus:DI (plus:DI (and:DI (ashift:DI (match_operand:DI 1 
"register_operand")
+(match_operand:QI 2 
"imm123_operand"))
+ (match_operand 3 
"consecutive_bits32_operand"))
+ (match_operand:DI 4 "register_operand"))
+(match_operand 5 "immediate_operand")))]
+  "TARGET_64BIT && TARGET_ZBA"
+  [(set (match_dup 0)
+   (plus:DI (and:DI (ashift:DI (match_dup 1) (match_dup 2))
+(match_dup 3))
+(match_dup 4)))
+   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 5)))])
+
 ;; ZBB extension.
 
 (define_expand "clzdi2"
diff --git a/gcc/testsuite/gcc.target/riscv/zba-shadduw.c 
b/gcc/testsuite/gcc.target/riscv/zba-shadduw.c
new file mode 100644
index ..5b77447e6813
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zba-shadduw.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zba -mabi=lp64" } */
+
+typedef struct simple_bitmap_def
+{
+  unsigned char *popcount;
+  unsigned int n_bits;
+  unsigned int size;
+  unsigned long elms[1];
+} *sbitmap;
+typedef const struct simple_bitmap_def *const_sbitmap;
+
+typedef unsigned long *sbitmap_ptr;
+typedef const unsigned long *const_sbitmap_ptr;
+static unsigned long sbitmap_elt_popcount (unsigned long);
+
+void
+sbitmap_a_or_b (sbitmap dst, const_sbitmap a, const_sbitmap b)
+{
+  unsigned int i, n = dst->size;
+  sbitmap_ptr dstp = dst->elms;
+  const_sbitmap_ptr ap = a->elms;
+  const_sbitmap_ptr bp = b->elms;
+  unsigned char has_popcount = dst->popcount != ((void *) 0);
+
+  for (i = 0; i < n; i++)
+{
+  const unsigned long tmp = *ap++ | *bp++;
+  *dstp++ = tmp;
+}
+}
+
+
+/* { dg-final { scan-assembler "sh3add.uw" } } */
+/* { dg-final { scan-assembler-not {\mslli.uw} } } */

[gcc r15-353] Revert: "Enable prange support." [PR114985]

[Aldy Hernandez via Gcc-cvs]

https://gcc.gnu.org/g:d7bb8eaade3cd3aa70715c8567b4d7b08098e699

commit r15-353-gd7bb8eaade3cd3aa70715c8567b4d7b08098e699
Author: Aldy Hernandez 
Date:   Fri May 10 00:29:13 2024 +0200

Revert: "Enable prange support." [PR114985]

This reverts commit 36e877996936abd8bd08f8b1d983c8d1023a5842 until the IPA
pass is fixed with regards to POINTER = POINTER  POINTER.

Diff:
---
 gcc/gimple-range-cache.cc |  4 ++--
 gcc/gimple-range-fold.cc  |  4 ++--
 gcc/gimple-range-fold.h   |  2 +-
 gcc/gimple-range-infer.cc |  2 +-
 gcc/gimple-range-op.cc|  2 +-
 gcc/gimple-range-path.cc  |  2 +-
 gcc/gimple-ssa-warn-access.cc |  2 +-
 gcc/ipa-cp.h  |  2 +-
 gcc/range-op-ptr.cc   |  4 
 gcc/range-op.cc   | 18 ++
 gcc/tree-ssa-structalias.cc   |  2 +-
 gcc/value-range.cc|  1 -
 gcc/value-range.h |  4 ++--
 13 files changed, 31 insertions(+), 18 deletions(-)

diff --git a/gcc/gimple-range-cache.cc b/gcc/gimple-range-cache.cc
index bdd2832873aa..72ac25523117 100644
--- a/gcc/gimple-range-cache.cc
+++ b/gcc/gimple-range-cache.cc
@@ -274,10 +274,10 @@ sbr_sparse_bitmap::sbr_sparse_bitmap (tree t, 
vrange_allocator *allocator,
   // Pre-cache zero and non-zero values for pointers.
   if (POINTER_TYPE_P (t))
 {
-  prange nonzero;
+  int_range<2> nonzero;
   nonzero.set_nonzero (t);
   m_range[1] = m_range_allocator->clone (nonzero);
-  prange zero;
+  int_range<2> zero;
   zero.set_zero (t);
   m_range[2] = m_range_allocator->clone (zero);
 }
diff --git a/gcc/gimple-range-fold.cc b/gcc/gimple-range-fold.cc
index a9c8c4d03e63..9c4ad1ee7b91 100644
--- a/gcc/gimple-range-fold.cc
+++ b/gcc/gimple-range-fold.cc
@@ -597,7 +597,7 @@ fold_using_range::fold_stmt (vrange , gimple *s, 
fur_source , tree name)
   // Process addresses.
   if (gimple_code (s) == GIMPLE_ASSIGN
   && gimple_assign_rhs_code (s) == ADDR_EXPR)
-return range_of_address (as_a  (r), s, src);
+return range_of_address (as_a  (r), s, src);
 
   gimple_range_op_handler handler (s);
   if (handler)
@@ -757,7 +757,7 @@ fold_using_range::range_of_range_op (vrange ,
 // If a range cannot be calculated, set it to VARYING and return true.
 
 bool
-fold_using_range::range_of_address (prange , gimple *stmt, fur_source )
+fold_using_range::range_of_address (irange , gimple *stmt, fur_source )
 {
   gcc_checking_assert (gimple_code (stmt) == GIMPLE_ASSIGN);
   gcc_checking_assert (gimple_assign_rhs_code (stmt) == ADDR_EXPR);
diff --git a/gcc/gimple-range-fold.h b/gcc/gimple-range-fold.h
index c7c599bfc939..7cbe15d05e53 100644
--- a/gcc/gimple-range-fold.h
+++ b/gcc/gimple-range-fold.h
@@ -157,7 +157,7 @@ protected:
  fur_source );
   bool range_of_call (vrange , gcall *call, fur_source );
   bool range_of_cond_expr (vrange , gassign* cond, fur_source );
-  bool range_of_address (prange , gimple *s, fur_source );
+  bool range_of_address (irange , gimple *s, fur_source );
   bool range_of_phi (vrange , gphi *phi, fur_source );
   void range_of_ssa_name_with_loop_info (vrange &, tree, class loop *, gphi *,
 fur_source );
diff --git a/gcc/gimple-range-infer.cc b/gcc/gimple-range-infer.cc
index d5e1aa142758..c8e8b9b60ac1 100644
--- a/gcc/gimple-range-infer.cc
+++ b/gcc/gimple-range-infer.cc
@@ -123,7 +123,7 @@ gimple_infer_range::add_nonzero (tree name)
 {
   if (!gimple_range_ssa_p (name))
 return;
-  prange nz;
+  int_range<2> nz;
   nz.set_nonzero (TREE_TYPE (name));
   add_range (name, nz);
 }
diff --git a/gcc/gimple-range-op.cc b/gcc/gimple-range-op.cc
index ddd13ec55942..55dfbb23ce22 100644
--- a/gcc/gimple-range-op.cc
+++ b/gcc/gimple-range-op.cc
@@ -1120,7 +1120,7 @@ class cfn_strlen : public range_operator
 {
 public:
   using range_operator::fold_range;
-  virtual bool fold_range (irange , tree type, const prange &,
+  virtual bool fold_range (irange , tree type, const irange &,
   const irange &, relation_trio) const
   {
 wide_int max = irange_val_max (ptrdiff_type_node);
diff --git a/gcc/gimple-range-path.cc b/gcc/gimple-range-path.cc
index f1a12f76144c..96c6ac6b6a50 100644
--- a/gcc/gimple-range-path.cc
+++ b/gcc/gimple-range-path.cc
@@ -443,7 +443,7 @@ path_range_query::compute_ranges_in_block (basic_block bb)
 void
 path_range_query::adjust_for_non_null_uses (basic_block bb)
 {
-  prange r;
+  int_range_max r;
   bitmap_iterator bi;
   unsigned i;
 
diff --git a/gcc/gimple-ssa-warn-access.cc b/gcc/gimple-ssa-warn-access.cc
index 0cd5b6d6ef48..2c10d19e7f36 100644
--- a/gcc/gimple-ssa-warn-access.cc
+++ b/gcc/gimple-ssa-warn-access.cc
@@ -4213,7 +4213,7 @@ pass_waccess::check_pointer_uses (gimple *stmt, tree ptr,
 where the realloc call is known to have failed are valid.
 Ignore pointers that nothing is known about.  Those could
 have escaped along with their 

[gcc r15-352] Constant fold {-1,-1} << 1 in simplify-rtx.cc

[Roger Sayle via Gcc-cvs]

https://gcc.gnu.org/g:f2449b55fb2d32fc4200667ba79847db31f6530d

commit r15-352-gf2449b55fb2d32fc4200667ba79847db31f6530d
Author: Roger Sayle 
Date:   Thu May 9 22:45:54 2024 +0100

Constant fold {-1,-1} << 1 in simplify-rtx.cc

This patch addresses a missed optimization opportunity in the RTL
optimization passes.  The function simplify_const_binary_operation
will constant fold binary operators with two CONST_INT operands,
and those with two CONST_VECTOR operands, but is missing compile-time
evaluation of binary operators with a CONST_VECTOR and a CONST_INT,
such as vector shifts and rotates.

The first version of this patch didn't contain a switch statement to
explicitly check for valid binary opcodes, which bootstrapped and
regression tested fine, but my paranoia has got the better of me,
so this version now checks that VEC_SELECT or some funky (future)
rtx_code doesn't cause problems.

2024-05-09  Roger Sayle  

gcc/ChangeLog
* simplify-rtx.cc (simplify_const_binary_operation): Constant
fold binary operations where the LHS is CONST_VECTOR and the
RHS is CONST_INT (or CONST_DOUBLE) such as vector shifts.

Diff:
---
 gcc/simplify-rtx.cc | 54 +
 1 file changed, 54 insertions(+)

diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc
index dceaa1ca..53f54d1d3928 100644
--- a/gcc/simplify-rtx.cc
+++ b/gcc/simplify-rtx.cc
@@ -5021,6 +5021,60 @@ simplify_const_binary_operation (enum rtx_code code, 
machine_mode mode,
   return gen_rtx_CONST_VECTOR (mode, v);
 }
 
+  if (VECTOR_MODE_P (mode)
+  && GET_CODE (op0) == CONST_VECTOR
+  && (CONST_SCALAR_INT_P (op1) || CONST_DOUBLE_AS_FLOAT_P (op1))
+  && (CONST_VECTOR_DUPLICATE_P (op0)
+ || CONST_VECTOR_NUNITS (op0).is_constant ()))
+{
+  switch (code)
+   {
+   case PLUS:
+   case MINUS:
+   case MULT:
+   case DIV:
+   case MOD:
+   case UDIV:
+   case UMOD:
+   case AND:
+   case IOR:
+   case XOR:
+   case SMIN:
+   case SMAX:
+   case UMIN:
+   case UMAX:
+   case LSHIFTRT:
+   case ASHIFTRT:
+   case ASHIFT:
+   case ROTATE:
+   case ROTATERT:
+   case SS_PLUS:
+   case US_PLUS:
+   case SS_MINUS:
+   case US_MINUS:
+   case SS_ASHIFT:
+   case US_ASHIFT:
+   case COPYSIGN:
+ break;
+   default:
+ return NULL_RTX;
+   }
+
+  unsigned int npatterns = (CONST_VECTOR_DUPLICATE_P (op0)
+   ? CONST_VECTOR_NPATTERNS (op0)
+   : CONST_VECTOR_NUNITS (op0).to_constant ());
+  rtx_vector_builder builder (mode, npatterns, 1);
+  for (unsigned i = 0; i < npatterns; i++)
+   {
+ rtx x = simplify_binary_operation (code, GET_MODE_INNER (mode),
+CONST_VECTOR_ELT (op0, i), op1);
+ if (!x || !valid_for_const_vector_p (mode, x))
+   return 0;
+ builder.quick_push (x);
+   }
+  return builder.build ();
+}
+
   if (SCALAR_FLOAT_MODE_P (mode)
   && CONST_DOUBLE_AS_FLOAT_P (op0) 
   && CONST_DOUBLE_AS_FLOAT_P (op1)

[gcc r15-351] c++: failure to suppress -Wsizeof-array-div in template [PR114983]

[Marek Polacek via Gcc-cvs]

https://gcc.gnu.org/g:646db3d30bd071a1b671b4f91c9ea2ab7f2be21c

commit r15-351-g646db3d30bd071a1b671b4f91c9ea2ab7f2be21c
Author: Marek Polacek 
Date:   Wed May 8 17:02:49 2024 -0400

c++: failure to suppress -Wsizeof-array-div in template [PR114983]

-Wsizeof-array-div offers a way to suppress the warning by wrapping
the second operand of the division in parens:

  sizeof (samplesBuffer) / (sizeof(unsigned char))

but this doesn't work in a template, because we fail to propagate
the suppression bits.  Do it, then.

The finish_parenthesized_expr hunk is not needed because suppress_warning
isn't very fine-grained.  But I think it makes sense to be explicit and
not rely on OPT_Wparentheses also suppressing OPT_Wsizeof_array_div.

PR c++/114983

gcc/cp/ChangeLog:

* pt.cc (tsubst_expr) : Use copy_warning.
* semantics.cc (finish_parenthesized_expr): Also suppress
-Wsizeof-array-div.

gcc/testsuite/ChangeLog:

* g++.dg/warn/Wsizeof-array-div3.C: New test.

Diff:
---
 gcc/cp/pt.cc   |  1 +
 gcc/cp/semantics.cc|  2 ++
 gcc/testsuite/g++.dg/warn/Wsizeof-array-div3.C | 27 ++
 3 files changed, 30 insertions(+)

diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index 8787eabb9fdb..a7d9fcf930e2 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -20570,6 +20570,7 @@ tsubst_expr (tree t, tree args, tsubst_flags_t 
complain, tree in_decl)
TREE_READONLY (r) = 1;
  }
SET_EXPR_LOCATION (r, EXPR_LOCATION (t));
+   copy_warning (r, t);
  }
RETURN (r);
   }
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index b8c2bf8771fc..71520dcd4fa9 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -2306,6 +2306,8 @@ finish_parenthesized_expr (cp_expr expr)
   /* This inhibits warnings in maybe_warn_unparenthesized_assignment
 and c_common_truthvalue_conversion.  */
   suppress_warning (STRIP_REFERENCE_REF (*expr), OPT_Wparentheses);
+  /* And maybe_warn_sizeof_array_div.  */
+  suppress_warning (STRIP_REFERENCE_REF (*expr), OPT_Wsizeof_array_div);
 }
 
   if (TREE_CODE (expr) == OFFSET_REF
diff --git a/gcc/testsuite/g++.dg/warn/Wsizeof-array-div3.C 
b/gcc/testsuite/g++.dg/warn/Wsizeof-array-div3.C
new file mode 100644
index ..bfd690325e51
--- /dev/null
+++ b/gcc/testsuite/g++.dg/warn/Wsizeof-array-div3.C
@@ -0,0 +1,27 @@
+// PR c++/114983
+// { dg-do compile { target c++11 } }
+// { dg-options "-Wsizeof-array-div" }
+
+using size_t = decltype (sizeof (0));
+unsigned int samplesBuffer[40];
+
+template 
+constexpr inline size_t fn1()
+{
+  return ((sizeof(samplesBuffer)) / (sizeof(T))); // { dg-bogus "expression 
does not compute" }
+}
+
+template 
+constexpr inline size_t fn2()
+{
+  return ((sizeof(samplesBuffer)) / sizeof(T)); // { dg-warning "expression 
does not compute" }
+}
+
+size_t
+g ()
+{
+  auto sz = sizeof (samplesBuffer) / (sizeof(unsigned char));
+  sz += fn1();
+  sz += fn2(); // { dg-message "required from here" }
+  return sz;
+}

[gcc r15-350] testsuite: Fix up pr84508* tests [PR84508]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:e02b5683e77c2b4317b23be72e43b6e6cc6c8e5b

commit r15-350-ge02b5683e77c2b4317b23be72e43b6e6cc6c8e5b
Author: Jakub Jelinek 
Date:   Thu May 9 20:59:05 2024 +0200

testsuite: Fix up pr84508* tests [PR84508]

The tests FAIL on x86_64-linux with
/usr/bin/ld: cannot find -lubsan
collect2: error: ld returned 1 exit status
compiler exited with status 1
FAIL: gcc.target/i386/pr84508-1.c (test for excess errors)
Excess errors:
/usr/bin/ld: cannot find -lubsan

The problem is that only *.dg/ubsan/ubsan.exp calls ubsan_init
which adds the needed search paths to libubsan library.
So, link/run tests for -fsanitize=undefined need to go into
gcc.dg/ubsan/ or g++.dg/ubsan/, even when they are target specific.

2024-05-09  Jakub Jelinek  

PR target/84508
* gcc.target/i386/pr84508-1.c: Move to ...
* gcc.dg/ubsan/pr84508-1.c: ... here.  Restrict to i?86/x86_64
non-ia32 targets.
* gcc.target/i386/pr84508-2.c: Move to ...
* gcc.dg/ubsan/pr84508-2.c: ... here.  Restrict to i?86/x86_64
non-ia32 targets.

Diff:
---
 gcc/testsuite/{gcc.target/i386 => gcc.dg/ubsan}/pr84508-1.c | 3 ++-
 gcc/testsuite/{gcc.target/i386 => gcc.dg/ubsan}/pr84508-2.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/i386/pr84508-1.c 
b/gcc/testsuite/gcc.dg/ubsan/pr84508-1.c
similarity index 74%
rename from gcc/testsuite/gcc.target/i386/pr84508-1.c
rename to gcc/testsuite/gcc.dg/ubsan/pr84508-1.c
index bb3e28d017e9..d781e01c 100644
--- a/gcc/testsuite/gcc.target/i386/pr84508-1.c
+++ b/gcc/testsuite/gcc.dg/ubsan/pr84508-1.c
@@ -1,5 +1,6 @@
-/* { dg-do run { target { ! ia32 } } } */
+/* { dg-do run { target { { i?86-*-* x86_64-*-* } && { ! ia32 } } } } */
 /* { dg-options "-fsanitize=undefined" } */
+
 #include 
 
 int main()
diff --git a/gcc/testsuite/gcc.target/i386/pr84508-2.c 
b/gcc/testsuite/gcc.dg/ubsan/pr84508-2.c
similarity index 73%
rename from gcc/testsuite/gcc.target/i386/pr84508-2.c
rename to gcc/testsuite/gcc.dg/ubsan/pr84508-2.c
index 32a8f20a5364..cf9c7db1d159 100644
--- a/gcc/testsuite/gcc.target/i386/pr84508-2.c
+++ b/gcc/testsuite/gcc.dg/ubsan/pr84508-2.c
@@ -1,5 +1,6 @@
-/* { dg-do run { target { ! ia32 } } } */
+/* { dg-do run { target { { i?86-*-* x86_64-*-* } && { ! ia32 } } } } */
 /* { dg-options "-fsanitize=undefined" } */
+
 #include 
 
 int main()

[gcc(refs/users/meissner/heads/work165-test)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:70bb25934207ac25ce21bb135b506c6ff7beaf74

commit 70bb25934207ac25ce21bb135b506c6ff7beaf74
Author: Michael Meissner 
Date:   Thu May 9 14:50:29 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.test | 99 +-
 1 file changed, 98 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index 6f9db4396158..fdf5f736b47d 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,6 +1,103 @@
+ Branch work165-test, patch #400 
+
+Limit SPR registers to hold only small integer modes.
+
+2024-05-08  Michael Meissner  
+
+   * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Limit
+   SPR registers to only hold only small integer modes.
+
+ Branch work165-tar, patch #203 
+
+Limit SPR registers to hold only DImode/SImode.
+
+2024-05-08  Michael Meissner  
+
+   * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Limit
+   SPR registers to only hold SImode/DImode.
+
+ Branch work165-tar, patch #202 
+
+Add -mfspr option.
+
+2024-05-08  Michael Meissner  
+
+   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add -mfspr
+   support.
+   (POWERPC_MASKS): Likewise.
+   * config/rs6000/rs6000.cc (rs6000_register_move_cost): Likewise.
+   * config/rs6000/rs6000.opt (-mfspr): Likewise.
+
+ Branch work165-tar, patch #201 
+
+Fix tests if -mtar is used.
+
+2024-05-06  Michael Meissner  
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/ppc-switch-1.c: Add support for using the TAR
+   register.
+   * gcc.target/powerpc/pr51513.c: Likewise.
+   * gcc.target/powerpc/safe-indirect-jump-3.c: Likewise.
+
+ Branch work165-tar, patch #200 
+
+Add support for -mtar
+
+2024-05-03  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/constraints.md (h constraint): Add tar register to
+   documentation.
+   (wt constraint): New constraint.
+   * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add -mtar.
+   (POWERPC_MASKS): Likewise.
+   * config/rs6000/rs6000.cc (rs6000_reg_names): Add new tar register.
+   (alt_reg_names): Likewise.
+   (rs6000_debug_reg_global): Likewise.
+   (rs6000_init_hard_regno_mode_ok): Likewise.
+   (rs6000_option_override_internal): Likewise.
+   (rs6000_conditional_register_usage): Likewise.
+   (print_operand): Likewise.
+   (rs6000_debugger_regno): Likewise.
+   (rs6000_opt_masks): Likewise.
+   * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Likewise.
+   (FiXED_REGISTERS): Likewise.
+   (CALL_REALLY_USED_REGISTERS): Likewise.
+   (REG_ALLOC_ORDER): Likewise.
+   (reg_class): Add new TAR_REGS register class.
+   (REG_CLASS_NAMES): Likewise.
+   (REG_CLASS_CONTENTS): Likewise.
+   (r6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.
+   (REG_NAMES): Add tar register.
+   * config/rs6000/rs6000.md (TAR_REGNO): New constant.
+   (mov_internal): Add support for tar register.
+   (movcc_): Likewise.
+   (movsf_hardfloat): Likewise.
+   (movsd_hardfloat): Likewise.
+   (mov_softfloat): Likewise.
+   (mov_hardfloat64): Likewise.
+   (mov_softfloat64): Likewise.
+   (@tablejump_insn_normal); Likewise.
+   (@tablejump_insn_nospec); Likewise.
+   * config/rs6000/rs6000.opt (-mtar): New option.
+   * doc/invoke.texi (RS/6000 options): Document -mtar.
+   * lra-constraints.md (lra_constraints): Print out insn that we can't
+   generate reloads for.
+
  Branch work165-test, baseline 
 
+Add ChangeLog.test and update REVISION.
+
+2024-05-02  Michael Meissner  
+
+gcc/
+
+   * ChangeLog.test: New file for branch.
+   * REVISION: Update.
+
 2024-05-02   Michael Meissner  
 
Clone branch
-

[gcc(refs/users/meissner/heads/work165-test)] Limit SPR registers to hold only small integer modes.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:dbb0bf3c552de9cfb09cd52c4136ffcca044e56b

commit dbb0bf3c552de9cfb09cd52c4136ffcca044e56b
Author: Michael Meissner 
Date:   Thu May 9 14:48:20 2024 -0400

Limit SPR registers to hold only small integer modes.

2024-05-08  Michael Meissner  

* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): 
Limit
SPR registers to only hold only small integer modes.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6bfcfdfb22c5..9f9f942a7860 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1930,8 +1930,11 @@ rs6000_hard_regno_mode_ok_uncached (int regno, 
machine_mode mode)
   if (CR_REGNO_P (regno))
 return GET_MODE_CLASS (mode) == MODE_CC;
 
+  if (CA_REGNO_P (regno))
+return mode == Pmode || mode == SImode;
+
   /* Limit SPR registers to integer modes that can fit in a single register.
- Do not allow complex modes or modes that need sign/zero extension.  */
+ Do not allow complex modes.  */
   switch (regno)
 {
 case LR_REGNO:
@@ -1939,8 +1942,10 @@ rs6000_hard_regno_mode_ok_uncached (int regno, 
machine_mode mode)
 case TAR_REGNO:
 case VRSAVE_REGNO:
 case VSCR_REGNO:
-case CA_REGNO:
-  return (orig_mode == Pmode || orig_mode == SImode);
+  return (orig_mode == Pmode
+ || orig_mode == SImode
+ || orig_mode == HImode
+ || orig_mode == QImode);
 
 default:
   break;

[gcc r15-349] PR modula2/115003 exporting a symbol to outer scope with a name clash causes ICE

[Gaius Mulley via Gcc-cvs]

https://gcc.gnu.org/g:bc5afdf14ccf8375f7fb3de2be1121aaf550f8aa

commit r15-349-gbc5afdf14ccf8375f7fb3de2be1121aaf550f8aa
Author: Gaius Mulley 
Date:   Thu May 9 19:35:20 2024 +0100

PR modula2/115003 exporting a symbol to outer scope with a name clash 
causes ICE

An ICE will occur if an unknown symbol is exported and causes a name
clash.  The error mechanism attempts to find the scope of an unknown
symbol.  This patch adds a missing case clause to GetScope and returns
NulSym if the scope is an unknown symbol.

gcc/m2/ChangeLog:

PR modula2/115003
* gm2-compiler/SymbolTable.mod (GetScope): Add UndefinedSym
case clause and return NulSym.

Signed-off-by: Gaius Mulley 

Diff:
---
 gcc/m2/gm2-compiler/SymbolTable.mod | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/m2/gm2-compiler/SymbolTable.mod 
b/gcc/m2/gm2-compiler/SymbolTable.mod
index f5890ec684fe..f206a47dff78 100644
--- a/gcc/m2/gm2-compiler/SymbolTable.mod
+++ b/gcc/m2/gm2-compiler/SymbolTable.mod
@@ -12449,6 +12449,7 @@ BEGIN
   ConstLitSym: RETURN( ConstLit.Scope ) |
   ConstStringSym : RETURN( ConstString.Scope ) |
   ConstVarSym: RETURN( ConstVar.Scope ) |
+  UndefinedSym   : RETURN( NulSym ) |
   PartialUnboundedSym: InternalError ('should not be requesting the scope 
of a PartialUnbounded symbol')
 
   ELSE

[gcc r14-10191] Fortran: fix issues with class(*) assignment [PR114827]

[Harald Anlauf via Gcc-cvs]

https://gcc.gnu.org/g:a5046235509caa10a4dc309ca0a8e67892b27750

commit r14-10191-ga5046235509caa10a4dc309ca0a8e67892b27750
Author: Harald Anlauf 
Date:   Mon Apr 29 19:52:52 2024 +0200

Fortran: fix issues with class(*) assignment [PR114827]

gcc/fortran/ChangeLog:

PR fortran/114827
* trans-array.cc (gfc_alloc_allocatable_for_assignment): Take into
account _len of unlimited polymorphic entities when calculating
the effective element size for allocation size and array span.
Set _len of lhs to _len of rhs.
* trans-expr.cc (trans_class_assignment): Take into account _len
of unlimited polymorphic entities for allocation size.

gcc/testsuite/ChangeLog:

PR fortran/114827
* gfortran.dg/asan/unlimited_polymorphic_34.f90: New test.

(cherry picked from commit 21e7aa5f3ea44ca2fef8deb8788edffc04901b5c)

Diff:
---
 gcc/fortran/trans-array.cc |  16 +++
 gcc/fortran/trans-expr.cc  |  13 ++
 .../gfortran.dg/asan/unlimited_polymorphic_34.f90  | 135 +
 3 files changed, 164 insertions(+)

diff --git a/gcc/fortran/trans-array.cc b/gcc/fortran/trans-array.cc
index 30b84762346d..7ec33fb15986 100644
--- a/gcc/fortran/trans-array.cc
+++ b/gcc/fortran/trans-array.cc
@@ -11278,6 +11278,19 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo 
*loop,
gfc_add_modify (, linfo->delta[dim], tmp);
 }
 
+  /* Take into account _len of unlimited polymorphic entities, so that span
+ for array descriptors and allocation sizes are computed correctly.  */
+  if (UNLIMITED_POLY (expr2))
+{
+  tree len = gfc_class_len_get (TREE_OPERAND (desc2, 0));
+  len = fold_build2_loc (input_location, MAX_EXPR, size_type_node,
+fold_convert (size_type_node, len),
+size_one_node);
+  elemsize2 = fold_build2_loc (input_location, MULT_EXPR,
+  gfc_array_index_type, elemsize2,
+  fold_convert (gfc_array_index_type, len));
+}
+
   if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (desc)))
 gfc_conv_descriptor_span_set (, desc, elemsize2);
 
@@ -11324,6 +11337,9 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo 
*loop,
gfc_add_modify (, tmp,
fold_convert (TREE_TYPE (tmp),
  TYPE_SIZE_UNIT (type)));
+ else if (UNLIMITED_POLY (expr2))
+   gfc_add_modify (, tmp,
+   gfc_class_len_get (TREE_OPERAND (desc2, 0)));
  else
gfc_add_modify (, tmp,
build_int_cst (TREE_TYPE (tmp), 0));
diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index 0280c441ced3..bc8eb419cffe 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -11991,6 +11991,19 @@ trans_class_assignment (stmtblock_t *block, gfc_expr 
*lhs, gfc_expr *rhs,
old_vptr = build_int_cst (TREE_TYPE (vptr), 0);
 
   size = gfc_vptr_size_get (rhs_vptr);
+
+  /* Take into account _len of unlimited polymorphic entities.
+TODO: handle class(*) allocatable function results on rhs.  */
+  if (UNLIMITED_POLY (rhs) && rhs->expr_type == EXPR_VARIABLE)
+   {
+ tree len = trans_get_upoly_len (block, rhs);
+ len = fold_build2_loc (input_location, MAX_EXPR, size_type_node,
+fold_convert (size_type_node, len),
+size_one_node);
+ size = fold_build2_loc (input_location, MULT_EXPR, TREE_TYPE (size),
+ size, fold_convert (TREE_TYPE (size), len));
+   }
+
   tmp = lse->expr;
   class_han = GFC_CLASS_TYPE_P (TREE_TYPE (tmp))
  ? gfc_class_data_get (tmp) : tmp;
diff --git a/gcc/testsuite/gfortran.dg/asan/unlimited_polymorphic_34.f90 
b/gcc/testsuite/gfortran.dg/asan/unlimited_polymorphic_34.f90
new file mode 100644
index ..c69158a1b55f
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/asan/unlimited_polymorphic_34.f90
@@ -0,0 +1,135 @@
+! { dg-do run }
+! PR fortran/114827 - issues with class(*) assignment found by valgrind
+!
+! Contributed by Neil Carlson 
+
+program main
+  implicit none
+  call run
+  call run1
+  call run2
+contains
+  ! Scalar tests
+  subroutine run ()
+character(*),parameter :: c = 'fubarfubarfubarfubarfubarfu'
+character(*,kind=4), parameter :: d = 4_"abcdef"
+complex, parameter :: z = (1.,2.)
+class(*),  allocatable :: y
+
+call foo (c, y)
+select type (y)
+type is (character(*))
+!  print *, y(5:6)  ! ICE (-> pr114874)
+   if (y /= c) stop 1
+class default
+   stop 2
+end select
+
+call foo (z, y)
+select type (y)
+type is (complex)
+   if (y /= z) stop 3
+class default

[gcc(refs/users/meissner/heads/work165-test)] Limit SPR registers to hold only DImode/SImode.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:787995064c01ec26ce551cd27a5c6abd1604caf5

commit 787995064c01ec26ce551cd27a5c6abd1604caf5
Author: Michael Meissner 
Date:   Thu May 9 14:13:37 2024 -0400

Limit SPR registers to hold only DImode/SImode.

2024-05-08  Michael Meissner  

* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): 
Limit
SPR registers to only hold SImode/DImode.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index bfc207fb5f55..6bfcfdfb22c5 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1848,6 +1848,7 @@ static int
 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
 {
   int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
+  machine_mode orig_mode = mode;
 
   if (COMPLEX_MODE_P (mode))
 mode = GET_MODE_INNER (mode);
@@ -1929,8 +1930,21 @@ rs6000_hard_regno_mode_ok_uncached (int regno, 
machine_mode mode)
   if (CR_REGNO_P (regno))
 return GET_MODE_CLASS (mode) == MODE_CC;
 
-  if (CA_REGNO_P (regno))
-return mode == Pmode || mode == SImode;
+  /* Limit SPR registers to integer modes that can fit in a single register.
+ Do not allow complex modes or modes that need sign/zero extension.  */
+  switch (regno)
+{
+case LR_REGNO:
+case CTR_REGNO:
+case TAR_REGNO:
+case VRSAVE_REGNO:
+case VSCR_REGNO:
+case CA_REGNO:
+  return (orig_mode == Pmode || orig_mode == SImode);
+
+default:
+  break;
+}
 
   /* AltiVec only in AldyVec registers.  */
   if (ALTIVEC_REGNO_P (regno))

[gcc(refs/users/meissner/heads/work165-test)] Add support for -mtar

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:bddaa9720d6f1a9652cf77d596d71156405b8537

commit bddaa9720d6f1a9652cf77d596d71156405b8537
Author: Michael Meissner 
Date:   Thu May 9 14:10:15 2024 -0400

Add support for -mtar

2024-05-08  Michael Meissner  

* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add -mfspr
support.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_register_move_cost): Likewise.
* config/rs6000/rs6000.opt (-mfspr): Likewise.

2024-05-06  Michael Meissner  

gcc/testsuite/

* gcc.target/powerpc/ppc-switch-1.c: Add support for using the TAR
register.
* gcc.target/powerpc/pr51513.c: Likewise.
* gcc.target/powerpc/safe-indirect-jump-3.c: Likewise.
2024-05-03  Michael Meissner  

gcc/

* config/rs6000/constraints.md (h constraint): Add tar register to
documentation.
(wt constraint): New constraint.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add -mtar.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_reg_names): Add new tar register.
(alt_reg_names): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_conditional_register_usage): Likewise.
(print_operand): Likewise.
(rs6000_debugger_regno): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Likewise.
(FiXED_REGISTERS): Likewise.
(CALL_REALLY_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(reg_class): Add new TAR_REGS register class.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(r6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.
(REG_NAMES): Add tar register.
* config/rs6000/rs6000.md (TAR_REGNO): New constant.
(mov_internal): Add support for tar register.
(movcc_): Likewise.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
(mov_softfloat): Likewise.
(mov_hardfloat64): Likewise.
(mov_softfloat64): Likewise.
(@tablejump_insn_normal); Likewise.
(@tablejump_insn_nospec); Likewise.
* config/rs6000/rs6000.opt (-mtar): New option.
* doc/invoke.texi (RS/6000 options): Document -mtar.
* lra-constraints.md (lra_constraints): Print out insn that we can't
generate reloads for.

Diff:
---
 gcc/config/rs6000/constraints.md   |  5 +-
 gcc/config/rs6000/rs6000-cpus.def  |  6 ++-
 gcc/config/rs6000/rs6000.cc| 53 +++---
 gcc/config/rs6000/rs6000.h | 31 -
 gcc/config/rs6000/rs6000.md| 23 +-
 gcc/config/rs6000/rs6000.opt   |  8 
 gcc/doc/invoke.texi| 12 -
 gcc/lra-constraints.cc |  9 ++--
 gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c|  4 +-
 gcc/testsuite/gcc.target/powerpc/pr51513.c |  4 +-
 .../gcc.target/powerpc/safe-indirect-jump-3.c  |  2 +-
 11 files changed, 116 insertions(+), 41 deletions(-)

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 369a7b75042d..14f0465d7ae5 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -57,7 +57,7 @@
   "@internal A compatibility alias for @code{wa}.")
 
 (define_register_constraint "h" "SPECIAL_REGS"
-  "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).")
+  "@internal A special register (@code{vrsave}, @code{ctr}, @code{lr} or 
@code{tar}).")
 
 (define_register_constraint "c" "CTR_REGS"
   "The count register, @code{ctr}.")
@@ -91,6 +91,9 @@
   "@internal Like @code{r}, if @option{-mpowerpc64} is used; otherwise,
@code{NO_REGS}.")
 
+(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
+  "The tar register, @code{tar}.")
+
 (define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
   "@internal Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise,
@code{NO_REGS}.")
diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index d625dbeb91fd..f53bd3e7dcba 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -51,8 +51,10 @@
 | OPTION_MASK_P8_VECTOR\
 | OPTION_MASK_CRYPTO   \
 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX  \
+| 

[gcc r13-8761] diagnostics: fix corrupt json/SARIF on stderr [PR114348]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:b7a2697733d19a093cbdd0e200ffce069a4bc812

commit r13-8761-gb7a2697733d19a093cbdd0e200ffce069a4bc812
Author: David Malcolm 
Date:   Thu May 9 13:09:33 2024 -0400

diagnostics: fix corrupt json/SARIF on stderr [PR114348]

Various values of -fdiagnostics-format= request machine-readable output
on stderr, using JSON, but in various places we use fnotice to write
free-form text to stderr, such as "compilation terminated", leading to
corrupt JSON.

Fix by having fnotice skip the output for such cases.

Backported from r14-9554-g0bf99b1b7eda2f (using a variable rather
than a vfunc of class diagnostic_output_format, since the latter
was added in gcc 14)

gcc/ChangeLog:
PR middle-end/114348
* diagnostic.cc (output_format): New variable.
(fnotice): Bail out if the user requested one of the
machine-readable diagnostic output formats on stderr.
(diagnostic_output_format_init): Set output_format.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/diagnostic.cc | 24 
 1 file changed, 24 insertions(+)

diff --git a/gcc/diagnostic.cc b/gcc/diagnostic.cc
index 0f093081161a..a3d84cf0bfae 100644
--- a/gcc/diagnostic.cc
+++ b/gcc/diagnostic.cc
@@ -2175,6 +2175,9 @@ internal_error_no_backtrace (const char *gmsgid, ...)
   gcc_unreachable ();
 }
 
+
+static enum diagnostics_output_format output_format;
+
 /* Special case error functions.  Most are implemented in terms of the
above, or should be.  */
 
@@ -2183,6 +2186,25 @@ internal_error_no_backtrace (const char *gmsgid, ...)
 void
 fnotice (FILE *file, const char *cmsgid, ...)
 {
+  /* If the user requested one of the machine-readable diagnostic output
+ formats on stderr (e.g. -fdiagnostics-format=sarif-stderr), then
+ emitting free-form text on stderr will lead to corrupt output.
+ Skip the message for such cases.  */
+  if (file == stderr && global_dc)
+switch (output_format)
+  {
+  default:
+   gcc_unreachable ();
+  case DIAGNOSTICS_OUTPUT_FORMAT_TEXT:
+  case DIAGNOSTICS_OUTPUT_FORMAT_JSON_FILE:
+  case DIAGNOSTICS_OUTPUT_FORMAT_SARIF_FILE:
+   break;
+  case DIAGNOSTICS_OUTPUT_FORMAT_JSON_STDERR:
+  case DIAGNOSTICS_OUTPUT_FORMAT_SARIF_STDERR:
+   /* stderr is meant to machine-readable; skip.  */
+   return;
+  }
+
   va_list ap;
 
   va_start (ap, cmsgid);
@@ -2290,6 +2312,8 @@ diagnostic_output_format_init (diagnostic_context 
*context,
   const char *base_file_name,
   enum diagnostics_output_format format)
 {
+  output_format = format;
+
   switch (format)
 {
 default:

[gcc r13-8760] Fix ICE in -fdiagnostics-generate-patch [PR112684]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:2a6f99aef7c8522471967b171180d9ba4136da90

commit r13-8760-g2a6f99aef7c8522471967b171180d9ba4136da90
Author: David Malcolm 
Date:   Thu May 9 13:09:32 2024 -0400

Fix ICE in -fdiagnostics-generate-patch [PR112684]

Backported from r14-8255-ge254d1224df306.

gcc/ChangeLog:
PR middle-end/112684
* toplev.cc (toplev::main): Don't ICE in
-fdiagnostics-generate-patch when exiting after options,
since no edit context will have been created.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/toplev.cc | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/gcc/toplev.cc b/gcc/toplev.cc
index 109c9d58cbd1..19391208eac2 100644
--- a/gcc/toplev.cc
+++ b/gcc/toplev.cc
@@ -2292,10 +2292,8 @@ toplev::main (int argc, char **argv)
  emit some diagnostics here.  */
   invoke_plugin_callbacks (PLUGIN_FINISH, NULL);
 
-  if (flag_diagnostics_generate_patch)
+  if (global_dc->edit_context_ptr)
 {
-  gcc_assert (global_dc->edit_context_ptr);
-
   pretty_printer pp;
   pp_show_color () = pp_show_color (global_dc->printer);
   global_dc->edit_context_ptr->print_diff (, true);

[gcc r13-8754] analyzer: fix skipping of debug stmts [PR113253]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:2c688f6afce4cbb414f5baab1199cd525f309fca

commit r13-8754-g2c688f6afce4cbb414f5baab1199cd525f309fca
Author: David Malcolm 
Date:   Thu May 9 13:09:30 2024 -0400

analyzer: fix skipping of debug stmts [PR113253]

PR analyzer/113253 reports a case where the analyzer output varied
with and without -g enabled.

The root cause was that debug stmts were in the
FOR_EACH_IMM_USE_FAST list for SSA names, leading to the analyzer's
state purging logic differing between the -g and non-debugging cases,
and thus leading to differences in the exploration of the user's code.

Fix by skipping such stmts in the state-purging logic, and removing
debug stmts when constructing the supergraph.

gcc/analyzer/ChangeLog:
PR analyzer/113253
* region-model.cc (region_model::on_stmt_pre): Add gcc_unreachable
for debug statements.
* state-purge.cc
(state_purge_per_ssa_name::state_purge_per_ssa_name): Skip any
debug stmts in the FOR_EACH_IMM_USE_FAST list.
* supergraph.cc (supergraph::supergraph): Don't add debug stmts
to the supernodes.

gcc/testsuite/ChangeLog:
PR analyzer/113253
* gcc.dg/analyzer/deref-before-check-pr113253.c: New test.

(cherry picked from commit r14-8670-gcc7aebff74d896)

Signed-off-by: David Malcolm 

Diff:
---
 gcc/analyzer/region-model.cc   |   5 +
 gcc/analyzer/state-purge.cc|   9 ++
 gcc/analyzer/supergraph.cc |   4 +
 .../gcc.dg/analyzer/deref-before-check-pr113253.c  | 154 +
 4 files changed, 172 insertions(+)

diff --git a/gcc/analyzer/region-model.cc b/gcc/analyzer/region-model.cc
index c98b09d5322e..7e42fcdfd551 100644
--- a/gcc/analyzer/region-model.cc
+++ b/gcc/analyzer/region-model.cc
@@ -1237,6 +1237,11 @@ region_model::on_stmt_pre (const gimple *stmt,
   /* No-op for now.  */
   break;
 
+case GIMPLE_DEBUG:
+  /* We should have stripped these out when building the supergraph.  */
+  gcc_unreachable ();
+  break;
+
 case GIMPLE_ASSIGN:
   {
const gassign *assign = as_a  (stmt);
diff --git a/gcc/analyzer/state-purge.cc b/gcc/analyzer/state-purge.cc
index 3a73146d928b..31a207436f09 100644
--- a/gcc/analyzer/state-purge.cc
+++ b/gcc/analyzer/state-purge.cc
@@ -329,6 +329,15 @@ state_purge_per_ssa_name::state_purge_per_ssa_name (const 
state_purge_map ,
  map.log ("used by stmt: %s", pp_formatted_text ());
}
 
+ if (is_gimple_debug (use_stmt))
+   {
+ /* We skipped debug stmts when building the supergraph,
+so ignore them now.  */
+ if (map.get_logger ())
+   map.log ("skipping debug stmt");
+ continue;
+   }
+
  const supernode *snode
= map.get_sg ().get_supernode_for_stmt (use_stmt);
 
diff --git a/gcc/analyzer/supergraph.cc b/gcc/analyzer/supergraph.cc
index a23ff15ece45..f07d68c60b8d 100644
--- a/gcc/analyzer/supergraph.cc
+++ b/gcc/analyzer/supergraph.cc
@@ -182,6 +182,10 @@ supergraph::supergraph (logger *logger)
  for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next ())
{
  gimple *stmt = gsi_stmt (gsi);
+ /* Discard debug stmts here, so we don't have to check for
+them anywhere within the analyzer.  */
+ if (is_gimple_debug (stmt))
+   continue;
  node_for_stmts->m_stmts.safe_push (stmt);
  m_stmt_to_node_t.put (stmt, node_for_stmts);
  m_stmt_uids.make_uid_unique (stmt);
diff --git a/gcc/testsuite/gcc.dg/analyzer/deref-before-check-pr113253.c 
b/gcc/testsuite/gcc.dg/analyzer/deref-before-check-pr113253.c
new file mode 100644
index ..d9015accd6ab
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/analyzer/deref-before-check-pr113253.c
@@ -0,0 +1,154 @@
+/* Regression test for PR analyzer/113253 which was showing analyzer
+   differences with and without -g.
+
+   C only: reduced reproducer doesn't easily work with C++.  */
+
+/* { dg-additional-options "-O2 -g" } */
+
+typedef long int ptrdiff_t;
+typedef unsigned long int uintptr_t;
+typedef long int EMACS_INT;
+enum
+{
+  EMACS_INT_WIDTH = 64,
+  VALBITS = EMACS_INT_WIDTH - 3,
+};
+typedef struct Lisp_X* Lisp_Word;
+enum Lisp_Type
+{
+  Lisp_Symbol = 0,
+  Lisp_Vectorlike = 5,
+};
+typedef Lisp_Word Lisp_Object;
+static inline EMACS_INT(XLI)(Lisp_Object o)
+{
+  return ((EMACS_INT)(o));
+}
+static inline void*(XLP)(Lisp_Object o)
+{
+  return ((void*)(o));
+}
+struct Lisp_Symbol
+{};
+typedef uintptr_t Lisp_Word_tag;
+extern struct Lisp_Symbol lispsym[1608];
+union vectorlike_header
+{
+  ptrdiff_t size;
+};
+enum pvec_type
+{
+  PVEC_MARKER,
+};
+enum More_Lisp_Bits
+{
+  PSEUDOVECTOR_SIZE_BITS = 12,
+  PSEUDOVECTOR_REST_BITS = 12,
+  

[gcc r13-8757] analyzer: fix ICE due to type mismatch when replaying call summary [PR114473]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:810d35a7e054bcbb5b66d2e5924428e445f5fba9

commit r13-8757-g810d35a7e054bcbb5b66d2e5924428e445f5fba9
Author: David Malcolm 
Date:   Thu May 9 13:09:31 2024 -0400

analyzer: fix ICE due to type mismatch when replaying call summary 
[PR114473]

gcc/analyzer/ChangeLog:
PR analyzer/114473
* call-summary.cc
(call_summary_replay::convert_svalue_from_summary): Assert that
the types match.
(call_summary_replay::convert_region_from_summary): Likewise.
(call_summary_replay::convert_region_from_summary_1): Add missing
cast for the deref of RK_SYMBOLIC case.

gcc/testsuite/ChangeLog:
PR analyzer/114473
* gcc.dg/analyzer/call-summaries-pr114473.c: New test.

(cherry picked from commit r14-9697-gfdd59818e2abf6)

Signed-off-by: David Malcolm 

Diff:
---
 gcc/analyzer/call-summary.cc   | 12 +
 .../gcc.dg/analyzer/call-summaries-pr114473.c  | 31 ++
 2 files changed, 43 insertions(+)

diff --git a/gcc/analyzer/call-summary.cc b/gcc/analyzer/call-summary.cc
index a18a1b1b40a7..836dcd4318d4 100644
--- a/gcc/analyzer/call-summary.cc
+++ b/gcc/analyzer/call-summary.cc
@@ -234,6 +234,11 @@ call_summary_replay::convert_svalue_from_summary (const 
svalue *summary_sval)
 
   const svalue *caller_sval = convert_svalue_from_summary_1 (summary_sval);
 
+  if (caller_sval)
+if (summary_sval->get_type () && caller_sval->get_type ())
+  gcc_assert (types_compatible_p (summary_sval->get_type (),
+ caller_sval->get_type ()));
+
   /* Add to cache.  */
   add_svalue_mapping (summary_sval, caller_sval);
 
@@ -551,6 +556,11 @@ call_summary_replay::convert_region_from_summary (const 
region *summary_reg)
 
   const region *caller_reg = convert_region_from_summary_1 (summary_reg);
 
+  if (caller_reg)
+if (summary_reg->get_type () && caller_reg->get_type ())
+  gcc_assert (types_compatible_p (summary_reg->get_type (),
+ caller_reg->get_type ()));
+
   /* Add to cache.  */
   add_region_mapping (summary_reg, caller_reg);
 
@@ -601,6 +611,8 @@ call_summary_replay::convert_region_from_summary_1 (const 
region *summary_reg)
  = get_caller_model ()->deref_rvalue (caller_ptr_sval,
   NULL_TREE,
   get_ctxt ());
+   caller_reg = mgr->get_cast_region (caller_reg,
+  summary_reg->get_type ());
return caller_reg;
   }
   break;
diff --git a/gcc/testsuite/gcc.dg/analyzer/call-summaries-pr114473.c 
b/gcc/testsuite/gcc.dg/analyzer/call-summaries-pr114473.c
new file mode 100644
index ..4598840f0dff
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/analyzer/call-summaries-pr114473.c
@@ -0,0 +1,31 @@
+/* { dg-additional-options "-fanalyzer-call-summaries" } */
+
+int a;
+extern int *q[];
+
+int *
+baz (int *src)
+{
+  while (a)
+{
+  src && a;
+  return src;
+}
+}
+
+void
+bar (int **src)
+{
+  for (unsigned j = 0; j;)
+a = 0;
+  while (a)
+baz (src[0]);
+}
+
+void
+foo (void)
+{
+  bar (q);
+  baz ();
+  bar (q);
+}

[gcc r13-8751] analyzer: fix deref-before-check false positives due to inlining [PR112790]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:994477c41049d45b60a4d6db7f624fe5c89860fe

commit r13-8751-g994477c41049d45b60a4d6db7f624fe5c89860fe
Author: David Malcolm 
Date:   Thu May 9 13:09:29 2024 -0400

analyzer: fix deref-before-check false positives due to inlining [PR112790]

Backported from commit r14-6918-g5743e1899d5964 (moving testcase from
c-c++-common to gcc.dg).

gcc/analyzer/ChangeLog:
PR analyzer/112790
* checker-event.cc (class inlining_info): Move to...
* inlining-iterator.h (class inlining_info): ...here.
* sm-malloc.cc: Include "analyzer/inlining-iterator.h".
(maybe_complain_about_deref_before_check): Reject stmts that were
inlined from another function.

gcc/testsuite/ChangeLog:
PR analyzer/112790
* gcc.dg/analyzer/deref-before-check-pr112790.c: New test.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/analyzer/checker-event.cc  | 40 --
 gcc/analyzer/inlining-iterator.h   | 40 ++
 gcc/analyzer/sm-malloc.cc  | 10 ++
 .../gcc.dg/analyzer/deref-before-check-pr112790.c  | 27 +++
 4 files changed, 77 insertions(+), 40 deletions(-)

diff --git a/gcc/analyzer/checker-event.cc b/gcc/analyzer/checker-event.cc
index 3612df7bd1d3..3cb2fb9175cd 100644
--- a/gcc/analyzer/checker-event.cc
+++ b/gcc/analyzer/checker-event.cc
@@ -106,46 +106,6 @@ event_kind_to_string (enum event_kind ek)
 }
 }
 
-/* A class for fixing up fndecls and stack depths in checker_event, based
-   on inlining records.
-
-   The early inliner runs before the analyzer, which can lead to confusing
-   output.
-
-   Tne base fndecl and depth within a checker_event are from call strings
-   in program_points, which reflect the call strings after inlining.
-   This class lets us offset the depth and fix up the reported fndecl and
-   stack depth to better reflect the user's original code.  */
-
-class inlining_info
-{
-public:
-  inlining_info (location_t loc)
-  {
-inlining_iterator iter (loc);
-m_inner_fndecl = iter.get_fndecl ();
-int num_frames = 0;
-while (!iter.done_p ())
-  {
-   m_outer_fndecl = iter.get_fndecl ();
-   num_frames++;
-   iter.next ();
-  }
-if (num_frames > 1)
-  m_extra_frames = num_frames - 1;
-else
-  m_extra_frames = 0;
-  }
-
-  tree get_inner_fndecl () const { return m_inner_fndecl; }
-  int get_extra_frames () const { return m_extra_frames; }
-
-private:
-  tree m_outer_fndecl;
-  tree m_inner_fndecl;
-  int m_extra_frames;
-};
-
 /* class checker_event : public diagnostic_event.  */
 
 /* checker_event's ctor.  */
diff --git a/gcc/analyzer/inlining-iterator.h b/gcc/analyzer/inlining-iterator.h
index 7d4798ce6ea5..76ba1dc3cf4a 100644
--- a/gcc/analyzer/inlining-iterator.h
+++ b/gcc/analyzer/inlining-iterator.h
@@ -106,4 +106,44 @@ private:
   tree m_next_abstract_origin;
 };
 
+/* A class for fixing up fndecls and stack depths in checker_event, based
+   on inlining records.
+
+   The early inliner runs before the analyzer, which can lead to confusing
+   output.
+
+   Tne base fndecl and depth within a checker_event are from call strings
+   in program_points, which reflect the call strings after inlining.
+   This class lets us offset the depth and fix up the reported fndecl and
+   stack depth to better reflect the user's original code.  */
+
+class inlining_info
+{
+public:
+  inlining_info (location_t loc)
+  {
+inlining_iterator iter (loc);
+m_inner_fndecl = iter.get_fndecl ();
+int num_frames = 0;
+while (!iter.done_p ())
+  {
+   m_outer_fndecl = iter.get_fndecl ();
+   num_frames++;
+   iter.next ();
+  }
+if (num_frames > 1)
+  m_extra_frames = num_frames - 1;
+else
+  m_extra_frames = 0;
+  }
+
+  tree get_inner_fndecl () const { return m_inner_fndecl; }
+  int get_extra_frames () const { return m_extra_frames; }
+
+private:
+  tree m_outer_fndecl;
+  tree m_inner_fndecl;
+  int m_extra_frames;
+};
+
 #endif /* GCC_ANALYZER_INLINING_ITERATOR_H */
diff --git a/gcc/analyzer/sm-malloc.cc b/gcc/analyzer/sm-malloc.cc
index 74701375409d..64295cfb66e7 100644
--- a/gcc/analyzer/sm-malloc.cc
+++ b/gcc/analyzer/sm-malloc.cc
@@ -47,6 +47,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "analyzer/program-state.h"
 #include "analyzer/checker-event.h"
 #include "analyzer/exploded-graph.h"
+#include "analyzer/inlining-iterator.h"
 
 #if ENABLE_ANALYZER
 
@@ -2147,6 +2148,15 @@ maybe_complain_about_deref_before_check (sm_context 
*sm_ctxt,
   if (checked_in_frame->get_index () > assumed_nonnull_in_frame->get_index ())
 return;
 
+  /* Don't complain if STMT was inlined from another function, to avoid
+ similar false positives involving shared helper functions.  */
+  if (stmt->location)
+{
+  inlining_info info (stmt->location);
+  if 

[gcc r13-8748] testsuite, analyzer: add test case [PR108171]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:44968a0e00f656e9bb3e504bb2fa1a8282002015

commit r13-8748-g44968a0e00f656e9bb3e504bb2fa1a8282002015
Author: David Malcolm 
Date:   Thu May 9 13:09:28 2024 -0400

testsuite, analyzer: add test case [PR108171]

The ICE in PR analyzer/108171 appears to be a dup of the recently fixed
PR analyzer/110882 and is likewise fixed by it; adding this test case.

gcc/testsuite/ChangeLog:
PR analyzer/108171
* gcc.dg/analyzer/pr108171.c: New test.

(cherry picked from commit r14-2957-gf80efa49b7a163)

Signed-off-by: David Malcolm 

Diff:
---
 gcc/testsuite/gcc.dg/analyzer/pr108171.c | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/gcc/testsuite/gcc.dg/analyzer/pr108171.c 
b/gcc/testsuite/gcc.dg/analyzer/pr108171.c
new file mode 100644
index ..5f7b9fd78754
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/analyzer/pr108171.c
@@ -0,0 +1,31 @@
+struct nl_context {
+  void *cmd_private;
+};
+
+struct sfeatures_context {
+  int a;
+  int req_mask[0];
+};
+
+int set_sf_req_mask_idx;
+
+extern void fill_legacy_flag();
+
+void
+fill_sfeatures_bitmap(struct nl_context *nlctx) {
+  while (nlctx) {
+fill_legacy_flag();
+struct nl_context __trans_tmp_1 = *nlctx;
+struct sfeatures_context *sfctx = __trans_tmp_1.cmd_private;
+sfctx->req_mask[set_sf_req_mask_idx] |= 1;
+  }
+}
+
+void
+nl_sfeatures() {
+  struct nl_context nlctx;
+  struct sfeatures_context *sfctx;
+  nlctx.cmd_private = 
+  sfctx = 0;
+  fill_sfeatures_bitmap();
+}

[gcc r13-8756] analyzer: fix -Wanalyzer-deref-before-check false positive seen in loop header macro [PR109251]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:ed026106ce420c7d9dd4d89caac017b6f235e219

commit r13-8756-ged026106ce420c7d9dd4d89caac017b6f235e219
Author: David Malcolm 
Date:   Thu May 9 13:09:31 2024 -0400

analyzer: fix -Wanalyzer-deref-before-check false positive seen in loop 
header macro [PR109251]

Backported from commit r14-9586-g9093f275e0a343 (moving tests from
c-c++-common to gcc.dg)

gcc/analyzer/ChangeLog:
PR analyzer/109251
* sm-malloc.cc (deref_before_check::emit): Reject cases where the
check is in a loop header within a macro expansion.
(deref_before_check::loop_header_p): New.

gcc/testsuite/ChangeLog:
PR analyzer/109251
* gcc.dg/analyzer/deref-before-check-pr109251-1.c: New test.
* gcc.dg/analyzer/deref-before-check-pr109251-2.c: New test.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/analyzer/sm-malloc.cc  | 30 +++
 .../analyzer/deref-before-check-pr109251-1.c   | 60 ++
 .../analyzer/deref-before-check-pr109251-2.c   | 37 +
 3 files changed, 127 insertions(+)

diff --git a/gcc/analyzer/sm-malloc.cc b/gcc/analyzer/sm-malloc.cc
index 64295cfb66e7..e9384a14dead 100644
--- a/gcc/analyzer/sm-malloc.cc
+++ b/gcc/analyzer/sm-malloc.cc
@@ -1565,6 +1565,21 @@ public:
 if (linemap_location_from_macro_definition_p (line_table, check_loc))
   return false;
 
+/* Reject warning if the check is in a loop header within a
+   macro expansion.  This rejects cases like:
+   |  deref of x;
+   |  [...snip...]
+   |  FOR_EACH(x) {
+   |[...snip...]
+   |  }
+   where the FOR_EACH macro tests for non-nullness of x, since
+   the user is hoping to encapsulate the details of iteration
+   in the macro, and the extra check on the first iteration
+   would just be noise if we reported it.  */
+if (loop_header_p (m_check_enode->get_point ())
+   && linemap_location_from_macro_expansion_p (line_table, check_loc))
+  return false;
+
 /* Reject if m_deref_expr is sufficiently different from m_arg
for cases where the dereference is spelled differently from
the check, which is probably two different ways to get the
@@ -1621,6 +1636,21 @@ public:
   }
 
 private:
+  static bool loop_header_p (const program_point )
+  {
+const supernode *snode = point.get_supernode ();
+if (!snode)
+  return false;
+for (auto _edge : snode->m_preds)
+  {
+   if (const cfg_superedge *cfg_in_edge
+ = in_edge->dyn_cast_cfg_superedge ())
+ if (cfg_in_edge->back_edge_p ())
+   return true;
+  }
+return false;
+  }
+
   static bool sufficiently_similar_p (tree expr_a, tree expr_b)
   {
 pretty_printer *pp_a = global_dc->printer->clone ();
diff --git a/gcc/testsuite/gcc.dg/analyzer/deref-before-check-pr109251-1.c 
b/gcc/testsuite/gcc.dg/analyzer/deref-before-check-pr109251-1.c
new file mode 100644
index ..769cffae6d74
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/analyzer/deref-before-check-pr109251-1.c
@@ -0,0 +1,60 @@
+/* Reduced from linux-5.10.162's kernel/sched/fair.c,
+   with !CONFIG_FAIR_GROUP_SCHED.  */
+
+#define NULL ((void*)0)
+
+struct load_weight
+{
+  unsigned long weight;
+  /* [...snip...] */
+};
+
+struct sched_entity
+{
+  struct load_weight load;
+  /* [...snip...] */
+  unsigned int on_rq;
+  /* [...snip...] */
+};
+
+struct cfs_rq
+{
+  /* [...snip...] */
+  unsigned int nr_running;
+  /* [...snip...] */
+};
+
+extern int
+__calc_delta(int delta_exec, unsigned long weight /* [...snip...] */);
+
+/* !CONFIG_FAIR_GROUP_SCHED */
+#define for_each_sched_entity(se) \
+  for (; se; se = (struct sched_entity *)NULL)
+
+extern struct cfs_rq*
+cfs_rq_of(struct sched_entity* se);
+
+extern int
+__sched_period(unsigned long nr_running);
+
+int
+sched_slice(struct cfs_rq* cfs_rq, struct sched_entity* se)
+{
+  unsigned int nr_running = cfs_rq->nr_running;
+  int slice;
+
+  /* [...snip...] */
+
+  slice = __sched_period(nr_running + !se->on_rq);
+
+  for_each_sched_entity(se) {
+/* [...snip...] */
+cfs_rq = cfs_rq_of(se);
+/* [...snip...] */
+slice = __calc_delta(slice, se->load.weight);
+  }
+
+  /* [...snip...] */
+
+  return slice;
+}
diff --git a/gcc/testsuite/gcc.dg/analyzer/deref-before-check-pr109251-2.c 
b/gcc/testsuite/gcc.dg/analyzer/deref-before-check-pr109251-2.c
new file mode 100644
index ..8e85a47d315e
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/analyzer/deref-before-check-pr109251-2.c
@@ -0,0 +1,37 @@
+struct node
+{
+  struct node *next;
+  int val;
+};
+
+int test_loop_1 (struct node *n)
+{
+  int total = 0;
+  if (n->val = 42)
+return -1;
+  for (struct node *iter = n; iter; iter=iter->next)
+total += iter->val;
+  return total;
+}
+
+int test_loop_2 (struct node *n)
+{
+  int total = 0;
+  if (n->val = 42)
+return -1;
+  for (; n; n=n->next)
+total 

[gcc r13-8758] analyzer: fix ICE and false positive with -Wanalyzer-deref-before-check [PR114408]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:96f7a3694c3e4c72af6258cc9b38bce30e609bee

commit r13-8758-g96f7a3694c3e4c72af6258cc9b38bce30e609bee
Author: David Malcolm 
Date:   Thu May 9 13:09:32 2024 -0400

analyzer: fix ICE and false positive with -Wanalyzer-deref-before-check 
[PR114408]

Backported from commit r14-9646-g80a0cb37456c49 (moving testcase to gcc.dg
and handling conflict in kf.cc)

gcc/analyzer/ChangeLog:
PR analyzer/114408
* engine.cc (impl_run_checkers): Free up any dominance info that
we may have created.
* kf.cc (class kf_ubsan_handler): New.
(register_sanitizer_builtins): New.
(register_known_functions): Call register_sanitizer_builtins.

gcc/testsuite/ChangeLog:
PR analyzer/114408
* gcc.dg/analyzer/deref-before-check-pr114408.c: New test.
* c-c++-common/ubsan/analyzer-ice-pr114408.c: New test.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/analyzer/engine.cc |  7 +++
 gcc/analyzer/kf.cc | 22 ++
 .../c-c++-common/ubsan/analyzer-ice-pr114408.c |  9 +
 .../gcc.dg/analyzer/deref-before-check-pr114408.c  | 22 ++
 4 files changed, 60 insertions(+)

diff --git a/gcc/analyzer/engine.cc b/gcc/analyzer/engine.cc
index a5965c2b8ff0..c5aadc41d114 100644
--- a/gcc/analyzer/engine.cc
+++ b/gcc/analyzer/engine.cc
@@ -6163,6 +6163,13 @@ impl_run_checkers (logger *logger)
 eng.get_model_manager ()->dump_untracked_regions ();
 
   delete purge_map;
+
+  /* Free up any dominance info that we may have created.  */
+  FOR_EACH_FUNCTION_WITH_GIMPLE_BODY (node)
+{
+  function *fun = node->get_fun ();
+  free_dominance_info (fun, CDI_DOMINATORS);
+}
 }
 
 /* Handle -fdump-analyzer and -fdump-analyzer-stderr.  */
diff --git a/gcc/analyzer/kf.cc b/gcc/analyzer/kf.cc
index 93c46630f361..4389ff917b8f 100644
--- a/gcc/analyzer/kf.cc
+++ b/gcc/analyzer/kf.cc
@@ -987,6 +987,27 @@ region_model::impl_deallocation_call (const call_details 
)
   kf.impl_call_post (cd);
 }
 
+/* Handle calls to the various __builtin___ubsan_handle_*.
+   These can return, but continuing after such a return
+   isn't likely to be interesting to the user of the analyzer.
+   Hence we terminate the analysis path at one of these calls.  */
+
+class kf_ubsan_handler : public internal_known_function
+{
+  void impl_call_post (const call_details ) const final override
+  {
+if (cd.get_ctxt ())
+  cd.get_ctxt ()->terminate_path ();
+  }
+};
+
+static void
+register_sanitizer_builtins (known_function_manager )
+{
+  kfm.add (BUILT_IN_UBSAN_HANDLE_NONNULL_ARG,
+  make_unique ());
+}
+
 /* Populate KFM with instances of known functions supported by the core of the
analyzer (as opposed to plugins).  */
 
@@ -1028,6 +1049,7 @@ register_known_functions (known_function_manager )
 kfm.add (BUILT_IN_STRNDUP, make_unique ());
 kfm.add (BUILT_IN_STRLEN, make_unique ());
 
+register_sanitizer_builtins (kfm);
 register_varargs_builtins (kfm);
   }
 
diff --git a/gcc/testsuite/c-c++-common/ubsan/analyzer-ice-pr114408.c 
b/gcc/testsuite/c-c++-common/ubsan/analyzer-ice-pr114408.c
new file mode 100644
index ..55f918726eed
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/ubsan/analyzer-ice-pr114408.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target analyzer } */
+/* { dg-options "-fanalyzer -fsanitize=undefined" } */
+
+int main(){}
+
+int HMAP_unset_copy(const char *key) {
+return __builtin_strcmp("a", key) + __builtin_strcmp("a", key);
+}
diff --git a/gcc/testsuite/gcc.dg/analyzer/deref-before-check-pr114408.c 
b/gcc/testsuite/gcc.dg/analyzer/deref-before-check-pr114408.c
new file mode 100644
index ..d55720271d0f
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/analyzer/deref-before-check-pr114408.c
@@ -0,0 +1,22 @@
+extern void unknown_returns (const char *p);
+extern void unknown_noreturn (const char *p) __attribute__((__noreturn__));
+
+void test_1 (const char *p)
+{
+  if (p)
+unknown_returns (p);
+  __builtin_strcmp ("a", p); /* { dg-message "pointer 'p' is dereferenced 
here" "" { target c } } */
+  if (p) /* { dg-warning "check of 'p' for NULL after already dereferencing 
it" "" { target c } } */
+unknown_returns (p);
+  __builtin_strcmp ("a", p);  
+}
+
+void test_2 (const char *p)
+{
+  if (p)
+unknown_noreturn (p);
+  __builtin_strcmp ("a", p);
+  if (p) /* { dg-bogus "check of 'p' for NULL after already dereferencing it" 
} */
+unknown_noreturn (p);
+  __builtin_strcmp ("a", p);  
+}

[gcc r13-8746] analyzer: fix ICE on division of tainted floating-point values [PR110700]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:0df1ee083434ac00ecb19582b1e5b25e105981b2

commit r13-8746-g0df1ee083434ac00ecb19582b1e5b25e105981b2
Author: David Malcolm 
Date:   Thu May 9 13:09:28 2024 -0400

analyzer: fix ICE on division of tainted floating-point values [PR110700]

gcc/analyzer/ChangeLog:
PR analyzer/110700
* region-model-manager.cc
(region_model_manager::get_or_create_int_cst): Assert that we have
an integral or pointer type.
* sm-taint.cc (taint_state_machine::check_for_tainted_divisor):
Don't check non-integral types.

gcc/testsuite/ChangeLog:
PR analyzer/110700
* gcc.dg/analyzer/taint-divisor-2.c: New test.

(cherry picked from commit r14-2658-gb86c0fe327a519)

Signed-off-by: David Malcolm 

Diff:
---
 gcc/analyzer/region-model-manager.cc|  3 ++-
 gcc/analyzer/sm-taint.cc|  6 ++
 gcc/testsuite/gcc.dg/analyzer/taint-divisor-2.c | 13 +
 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/gcc/analyzer/region-model-manager.cc 
b/gcc/analyzer/region-model-manager.cc
index fab5bba15d5f..1a9886fd83c2 100644
--- a/gcc/analyzer/region-model-manager.cc
+++ b/gcc/analyzer/region-model-manager.cc
@@ -233,7 +233,8 @@ const svalue *
 region_model_manager::get_or_create_int_cst (tree type, poly_int64 val)
 {
   gcc_assert (type);
-  tree tree_cst = build_int_cst (type, val);
+  gcc_assert (INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type));
+  tree tree_cst = wide_int_to_tree (type, val);
   return get_or_create_constant_svalue (tree_cst);
 }
 
diff --git a/gcc/analyzer/sm-taint.cc b/gcc/analyzer/sm-taint.cc
index f72f194460c2..7bce3ef79b2d 100644
--- a/gcc/analyzer/sm-taint.cc
+++ b/gcc/analyzer/sm-taint.cc
@@ -1344,6 +1344,12 @@ taint_state_machine::check_for_tainted_divisor 
(sm_context *sm_ctxt,
 return;
 
   tree divisor_expr = gimple_assign_rhs2 (assign);;
+
+  /* Until we track conditions on floating point values, we can't check to
+ see if they've been checked against zero.  */
+  if (!INTEGRAL_TYPE_P (TREE_TYPE (divisor_expr)))
+return;
+
   const svalue *divisor_sval = old_model->get_rvalue (divisor_expr, NULL);
 
   state_t state = sm_ctxt->get_state (assign, divisor_sval);
diff --git a/gcc/testsuite/gcc.dg/analyzer/taint-divisor-2.c 
b/gcc/testsuite/gcc.dg/analyzer/taint-divisor-2.c
new file mode 100644
index ..de9a1cb3a46f
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/analyzer/taint-divisor-2.c
@@ -0,0 +1,13 @@
+// TODO: remove need for this option:
+/* { dg-additional-options "-fanalyzer-checker=taint" } */
+
+#include "analyzer-decls.h"
+
+__attribute__ ((tainted_args))
+double pr110700 (double x, double y)
+{
+  /* Ideally we'd complain here with -Wanalyzer-tainted-divisor, but
+ until we track conditions on floating point values, we can't check to
+ see if they've been checked against zero.  */
+  return x / y;
+}

[gcc r13-8759] diagnostics: fix ICE on sarif output when source file is unreadable [PR111700]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:230f672b3ed0f64c9110ef9dba616c17d713816d

commit r13-8759-g230f672b3ed0f64c9110ef9dba616c17d713816d
Author: David Malcolm 
Date:   Thu May 9 13:09:32 2024 -0400

diagnostics: fix ICE on sarif output when source file is unreadable 
[PR111700]

Backported from r14-4474-g94caa6a6b4bd73.

gcc/ChangeLog:
PR driver/111700
* input.cc (file_cache::add_file): Update leading comment to
clarify that it can fail.
(file_cache::lookup_or_add_file): Likewise.
(get_source_file_content): Gracefully handle lookup_or_add_file
failing.

gcc/testsuite/ChangeLog:
PR driver/111700
* c-c++-common/diagnostic-format-sarif-file-pr111700.c: New test.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/input.cc | 12 ++--
 .../c-c++-common/diagnostic-format-sarif-file-pr111700.c | 12 
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/gcc/input.cc b/gcc/input.cc
index eaf301ec7c15..d1668ef5dcd5 100644
--- a/gcc/input.cc
+++ b/gcc/input.cc
@@ -443,7 +443,10 @@ file_cache::evicted_cache_tab_entry (unsigned 
*highest_use_count)
accessed by caret diagnostic.  This cache is added to an array of
cache and can be retrieved by lookup_file_in_cache_tab.  This
function returns the created cache.  Note that only the last
-   num_file_slots files are cached.  */
+   num_file_slots files are cached.
+
+   This can return nullptr if the FILE_PATH can't be opened for
+   reading, or if the content can't be converted to the input_charset.  */
 
 file_cache_slot*
 file_cache::add_file (const char *file_path)
@@ -547,7 +550,10 @@ file_cache::~file_cache ()
 /* Lookup the cache used for the content of a given file accessed by
caret diagnostic.  If no cached file was found, create a new cache
for this file, add it to the array of cached file and return
-   it.  */
+   it.
+
+   This can return nullptr on a cache miss if FILE_PATH can't be opened for
+   reading, or if the content can't be converted to the input_charset.  */
 
 file_cache_slot*
 file_cache::lookup_or_add_file (const char *file_path)
@@ -1071,6 +1077,8 @@ get_source_file_content (const char *file_path)
   diagnostic_file_cache_init ();
 
   file_cache_slot *c = global_dc->m_file_cache->lookup_or_add_file (file_path);
+  if (c == nullptr)
+return char_span (nullptr, 0);
   return c->get_full_file_content ();
 }
 
diff --git a/gcc/testsuite/c-c++-common/diagnostic-format-sarif-file-pr111700.c 
b/gcc/testsuite/c-c++-common/diagnostic-format-sarif-file-pr111700.c
new file mode 100644
index ..06605accf6e0
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/diagnostic-format-sarif-file-pr111700.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-fdiagnostics-format=sarif-file" } */
+
+# 0 "this-file-does-not-exist.c"
+#warning message
+
+/* Verify that some JSON was written to a file with the expected name.  */
+/* { dg-final { verify-sarif-file } } */
+
+/* ...and that it at least includes the warning
+   { dg-final { scan-sarif-file "\"message\": " } }
+ { dg-final { scan-sarif-file "\"text\": \"#warning message" } } */

[gcc r13-8755] analyzer: fix -Wanalyzer-va-arg-type-mismatch false +ve on int types [PR111289]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:67d104f3a032ee64bae335269bf1b8434785cc63

commit r13-8755-g67d104f3a032ee64bae335269bf1b8434785cc63
Author: David Malcolm 
Date:   Thu May 9 13:09:31 2024 -0400

analyzer: fix -Wanalyzer-va-arg-type-mismatch false +ve on int types 
[PR111289]

Backported from commit r14-9076-g5651ad62b08096 (moving new tests from
c-c++-common to gcc.dg).

gcc/analyzer/ChangeLog:
PR analyzer/111289
* varargs.cc (representable_in_integral_type_p): New.
(va_arg_compatible_types_p): Add "arg_sval" param.  Handle integer
types.
(kf_va_arg::impl_call_pre): Pass arg_sval to
va_arg_compatible_types_p.

gcc/testsuite/ChangeLog:
PR analyzer/111289
* gcc.dg/analyzer/stdarg-pr111289-int.c: New test.
* gcc.dg/analyzer/stdarg-pr111289-ptr.c: New test.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/analyzer/varargs.cc| 38 ++--
 .../gcc.dg/analyzer/stdarg-pr111289-int.c  | 69 ++
 .../gcc.dg/analyzer/stdarg-pr111289-ptr.c  | 39 
 3 files changed, 142 insertions(+), 4 deletions(-)

diff --git a/gcc/analyzer/varargs.cc b/gcc/analyzer/varargs.cc
index aeea73a3899e..6e13271969a4 100644
--- a/gcc/analyzer/varargs.cc
+++ b/gcc/analyzer/varargs.cc
@@ -961,13 +961,43 @@ public:
   }
 };
 
-/* Return true if it's OK to copy a value from ARG_TYPE to LHS_TYPE via
+static bool
+representable_in_integral_type_p (const svalue , const_tree type)
+{
+  gcc_assert (INTEGRAL_TYPE_P (type));
+
+  if (tree cst = sval.maybe_get_constant ())
+return wi::fits_to_tree_p (wi::to_wide (cst), type);
+
+  return true;
+}
+
+/* Return true if it's OK to copy ARG_SVAL from ARG_TYPE to LHS_TYPE via
va_arg (where argument promotion has already happened).  */
 
 static bool
-va_arg_compatible_types_p (tree lhs_type, tree arg_type)
+va_arg_compatible_types_p (tree lhs_type, tree arg_type, const svalue 
_sval)
 {
-  return compat_types_p (arg_type, lhs_type);
+  if (compat_types_p (arg_type, lhs_type))
+return true;
+
+  /* It's OK if both types are integer types, where one is signed and the
+ other type the corresponding unsigned type, when the value is
+ representable in both types.  */
+  if (INTEGRAL_TYPE_P (lhs_type)
+  && INTEGRAL_TYPE_P (arg_type)
+  && TYPE_UNSIGNED (lhs_type) != TYPE_UNSIGNED (arg_type)
+  && TYPE_PRECISION (lhs_type) == TYPE_PRECISION (arg_type)
+  && representable_in_integral_type_p (arg_sval, lhs_type)
+  && representable_in_integral_type_p (arg_sval, arg_type))
+return true;
+
+  /* It's OK if one type is a pointer to void and the other is a
+ pointer to a character type.
+ This is handled by compat_types_p.  */
+
+  /* Otherwise the types are not compatible.  */
+  return false;
 }
 
 /* If AP_SVAL is a pointer to a var_arg_region, return that var_arg_region.
@@ -1031,7 +1061,7 @@ kf_va_arg::impl_call_pre (const call_details ) const
{
  tree lhs_type = cd.get_lhs_type ();
  tree arg_type = arg_sval->get_type ();
- if (va_arg_compatible_types_p (lhs_type, arg_type))
+ if (va_arg_compatible_types_p (lhs_type, arg_type, *arg_sval))
cd.maybe_set_lhs (arg_sval);
  else
{
diff --git a/gcc/testsuite/gcc.dg/analyzer/stdarg-pr111289-int.c 
b/gcc/testsuite/gcc.dg/analyzer/stdarg-pr111289-int.c
new file mode 100644
index ..33d83169c3e0
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/analyzer/stdarg-pr111289-int.c
@@ -0,0 +1,69 @@
+#include 
+#include 
+#include 
+
+typedef unsigned int mode_t;
+
+extern void openat (int, const char *, int, mode_t);
+
+/* Signed vs unsigned of same integral type.  */
+
+static void
+test_1 (char const *name, ...)
+{
+  va_list arg;
+  va_start (arg, name);
+
+  mode_t mode = va_arg (arg, mode_t); /* { dg-bogus 
"-Wanalyzer-va-arg-type-mismatch" } */
+
+  va_end (arg);
+  openat (-42, name, 0, mode);
+}
+
+void
+call_test_1 ()
+{
+  test_1 ("nonexist.ent/", 0600);
+}
+
+/* Not the same size: small enough for int promotion.  */
+
+int16_t global_2;
+
+static void
+test_2 (char const *name, ...)
+{
+  va_list arg;
+  va_start (arg, name);
+
+  global_2 = va_arg (arg, int16_t); /* { dg-warning "promoted to 'int'" } */
+
+  va_end (arg);
+}
+
+void
+call_test_2 ()
+{
+  test_2 ("nonexist.ent/", 42);
+}
+
+/* Not the same size: too big for int promotion.  */
+
+long long global_3;
+
+static void
+test_3 (char const *name, ...)
+{
+  va_list arg;
+  va_start (arg, name);
+
+  global_3 = va_arg (arg, long long); /* { dg-warning "'va_arg' expected 'long 
long int' but received 'int' for variadic argument 1 of 'arg'" } */
+
+  va_end (arg);
+}
+
+void
+call_test_3 ()
+{
+  test_3 ("nonexist.ent/", 42);
+}
diff --git a/gcc/testsuite/gcc.dg/analyzer/stdarg-pr111289-ptr.c 

[gcc r13-8745] jit.exp: handle dwarf version mismatch in jit-check-debug-info [PR110466]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:60dcb710b6b4aa22ea96abc8df6dfe9067f3d7fe

commit r13-8745-g60dcb710b6b4aa22ea96abc8df6dfe9067f3d7fe
Author: David Malcolm 
Date:   Thu May 9 13:09:27 2024 -0400

jit.exp: handle dwarf version mismatch in jit-check-debug-info [PR110466]

gcc/testsuite/ChangeLog:
PR jit/110466
* jit.dg/jit.exp (jit-check-debug-info): Gracefully handle too
early versions of gdb that don't support our dwarf version, via
"unsupported".

(cherry picked from commit r14-2223-gc3c0ba5436170e)

Signed-off-by: David Malcolm 

Diff:
---
 gcc/testsuite/jit.dg/jit.exp | 4 
 1 file changed, 4 insertions(+)

diff --git a/gcc/testsuite/jit.dg/jit.exp b/gcc/testsuite/jit.dg/jit.exp
index 35d38cec5bc1..83fb6371fd24 100644
--- a/gcc/testsuite/jit.dg/jit.exp
+++ b/gcc/testsuite/jit.dg/jit.exp
@@ -440,6 +440,10 @@ proc jit-check-debug-info { obj_file cmds match } {
 send $cmd
 }
 expect {
+   -re "Dwarf Error: wrong version in compilation unit header" {
+   set testcase [testname-for-summary]
+   unsupported "$testcase: gdb does not support dwarf version"
+   }
 -re $match { pass OK }
 default { fail FAIL }
 }

[gcc r13-8749] jit: dump string literal initializers correctly

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:b8c772cae97b54386f7853edf0f9897012bfa90b

commit r13-8749-gb8c772cae97b54386f7853edf0f9897012bfa90b
Author: Vibhav Pant 
Date:   Thu May 9 13:09:28 2024 -0400

jit: dump string literal initializers correctly

Signed-off-by: David Malcolm 

gcc/jit/ChangeLog:
* jit-recording.cc (recording::global::write_to_dump): Fix
dump of string literal initializers.

(cherry picked from commit r14-4923-gac66744d94226a)

Signed-off-by: David Malcolm 

Diff:
---
 gcc/jit/jit-recording.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/jit/jit-recording.cc b/gcc/jit/jit-recording.cc
index df0368ff8f70..cf734cf7ef5f 100644
--- a/gcc/jit/jit-recording.cc
+++ b/gcc/jit/jit-recording.cc
@@ -4919,7 +4919,7 @@ recording::global::write_to_dump (dump )
   else if (m_rvalue_init)
 {
   d.write (" = ");
-  d.write (m_rvalue_init->get_debug_string ());
+  d.write ("%s", m_rvalue_init->get_debug_string ());
   d.write (";\n");
 }

[gcc r13-8753] analyzer: fix defaults in compound assignments from non-zero offsets [PR112969]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:0593151221ad21c2a67dfda597539c458ab731d8

commit r13-8753-g0593151221ad21c2a67dfda597539c458ab731d8
Author: David Malcolm 
Date:   Thu May 9 13:09:30 2024 -0400

analyzer: fix defaults in compound assignments from non-zero offsets 
[PR112969]

Confusion in binding_cluster::maybe_get_compound_binding about whether
offsets are relative to the start of the region or to the start of the
cluster was leading to incorrect handling of default values, leading
to false positives from -Wanalyzer-use-of-uninitialized-value, from
-Wanalyzer-exposure-through-uninit-copy, and other logic errors.

Fixed thusly.

Backported from commit r14-8428-g6426d466779fa8 (keeping tests
in gcc.dg, rather than c-c++-common).

gcc/analyzer/ChangeLog:
PR analyzer/112969
* store.cc (binding_cluster::maybe_get_compound_binding): When
populating default_map, express the bit-range of the default key
for REG relative to REG, rather than to the base region.

gcc/testsuite/ChangeLog:
PR analyzer/112969
* gcc.dg/analyzer/compound-assignment-5.c (test_3): Remove
xfails, reorder tests.
* gcc.dg/analyzer/compound-assignment-pr112969.c: New test.
* gcc.dg/plugin/infoleak-pr112969.c: New test.
* gcc.dg/plugin/plugin.exp: Add infoleak-pr112969.c to
analyzer_kernel_plugin.c tests.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/analyzer/store.cc  | 11 -
 .../gcc.dg/analyzer/compound-assignment-5.c| 29 +---
 .../gcc.dg/analyzer/compound-assignment-pr112969.c | 35 +++
 gcc/testsuite/gcc.dg/plugin/infoleak-pr112969.c| 52 ++
 gcc/testsuite/gcc.dg/plugin/plugin.exp |  1 +
 5 files changed, 109 insertions(+), 19 deletions(-)

diff --git a/gcc/analyzer/store.cc b/gcc/analyzer/store.cc
index e8c927b9fe9b..0acb0a2b1865 100644
--- a/gcc/analyzer/store.cc
+++ b/gcc/analyzer/store.cc
@@ -1718,7 +1718,16 @@ binding_cluster::maybe_get_compound_binding 
(store_manager *mgr,
   else
 default_sval = sval_mgr->get_or_create_initial_value (reg);
   const binding_key *default_key = binding_key::make (mgr, reg);
-  default_map.put (default_key, default_sval);
+
+  /* Express the bit-range of the default key for REG relative to REG,
+ rather than to the base region.  */
+  const concrete_binding *concrete_default_key
+= default_key->dyn_cast_concrete_binding ();
+  if (!concrete_default_key)
+return nullptr;
+  const concrete_binding *default_key_relative_to_reg
+ = mgr->get_concrete_binding (0, concrete_default_key->get_size_in_bits 
());
+  default_map.put (default_key_relative_to_reg, default_sval);
 
   for (map_t::iterator iter = m_map.begin (); iter != m_map.end (); ++iter)
 {
diff --git a/gcc/testsuite/gcc.dg/analyzer/compound-assignment-5.c 
b/gcc/testsuite/gcc.dg/analyzer/compound-assignment-5.c
index ccf8fe392bfa..e1f42177b08c 100644
--- a/gcc/testsuite/gcc.dg/analyzer/compound-assignment-5.c
+++ b/gcc/testsuite/gcc.dg/analyzer/compound-assignment-5.c
@@ -23,7 +23,7 @@ void test_1 (void)
 
 /* Copying from an on-stack array to a global array.  */
 
-struct coord glob_arr[16];
+struct coord glob_arr2[16];
 
 void test_2 (void)
 {
@@ -31,32 +31,29 @@ void test_2 (void)
   arr[3].x = 5;
   arr[3].y = 6;
 
-  glob_arr[7] = arr[3];
+  glob_arr2[7] = arr[3];
 
-  __analyzer_eval (glob_arr[7].x == 5); /* { dg-warning "TRUE" } */
-  __analyzer_eval (glob_arr[7].y == 6); /* { dg-warning "TRUE" } */
+  __analyzer_eval (glob_arr2[7].x == 5); /* { dg-warning "TRUE" } */
+  __analyzer_eval (glob_arr2[7].y == 6); /* { dg-warning "TRUE" } */
 }
 
 /* Copying from a partially initialized on-stack array to a global array.  */
 
-struct coord glob_arr[16];
+struct coord glob_arr3[16];
 
 void test_3 (void)
 {
   struct coord arr[16];
   arr[3].y = 6;
 
-  glob_arr[7] = arr[3]; // or should the uninit warning be here?
+  glob_arr3[7] = arr[3]; // or should the uninit warning be here?
 
-  __analyzer_eval (glob_arr[7].x); /* { dg-warning "uninitialized" "uninit" { 
xfail *-*-* } } */
-  /* { dg-bogus "UNKNOWN" "unknown" { xfail *-*-* } .-1 } */
-  __analyzer_eval (glob_arr[7].y == 6); /* { dg-warning "TRUE" } */
+  __analyzer_eval (glob_arr3[7].y == 6); /* { dg-warning "TRUE" } */
+  __analyzer_eval (glob_arr3[7].x); /* { dg-warning "uninitialized" "uninit" } 
*/
 }
 
 /* Symbolic bindings: copying from one array to another.  */
 
-struct coord glob_arr[16];
-
 void test_4 (int i)
 {
   struct coord arr_a[16];
@@ -77,8 +74,6 @@ void test_4 (int i)
 
 /* Symbolic bindings: copying within an array: symbolic src and dest  */
 
-struct coord glob_arr[16];
-
 void test_5a (int i, int j)
 {
   struct coord arr[16];
@@ -95,8 +90,6 @@ void test_5a (int i, int j)
 
 /* Symbolic bindings: copying within an array: symbolic src, concrete dest.  */
 

[gcc r13-8747] analyzer: fix ICE on zero-sized arrays [PR110882]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:a0b13d0860848dd5f2876897ada1e22e4e681e91

commit r13-8747-ga0b13d0860848dd5f2876897ada1e22e4e681e91
Author: David Malcolm 
Date:   Thu May 9 13:09:28 2024 -0400

analyzer: fix ICE on zero-sized arrays [PR110882]

gcc/analyzer/ChangeLog:
PR analyzer/110882
* region.cc (int_size_in_bits): Fail on zero-sized types.

gcc/testsuite/ChangeLog:
PR analyzer/110882
* gcc.dg/analyzer/pr110882.c: New test.

(cherry picked from commit r14-2955-gc62f93d1e0383d)

Signed-off-by: David Malcolm 

Diff:
---
 gcc/analyzer/region.cc   |  6 +-
 gcc/testsuite/gcc.dg/analyzer/pr110882.c | 18 ++
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/gcc/analyzer/region.cc b/gcc/analyzer/region.cc
index f982ce67509e..c1bfecabd158 100644
--- a/gcc/analyzer/region.cc
+++ b/gcc/analyzer/region.cc
@@ -395,7 +395,11 @@ int_size_in_bits (const_tree type, bit_size_t *out)
 }
 
   tree sz = TYPE_SIZE (type);
-  if (sz && tree_fits_uhwi_p (sz))
+  if (sz
+  && tree_fits_uhwi_p (sz)
+  /* If the size is zero, then we may have a zero-sized
+array; handle such cases by returning false.  */
+  && !integer_zerop (sz))
 {
   *out = TREE_INT_CST_LOW (sz);
   return true;
diff --git a/gcc/testsuite/gcc.dg/analyzer/pr110882.c 
b/gcc/testsuite/gcc.dg/analyzer/pr110882.c
new file mode 100644
index ..80027184053e
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/analyzer/pr110882.c
@@ -0,0 +1,18 @@
+/* { dg-additional-options "-Wno-analyzer-too-complex" } */
+
+struct csv_row {
+  char *columns[0];
+};
+
+void
+parse_csv_line (int n_columns, const char *columns[])
+{
+  for (int n = 0; n < n_columns; n++) {
+  columns[n] = ((void *)0);
+  }
+}
+
+void parse_csv_data (int n_columns, struct csv_row *entry)
+{
+  parse_csv_line(n_columns, (const char **)entry->columns);
+}

[gcc r13-8750] analyzer: fix ICE for 2 bits before the start of base region [PR112889]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:a1cb188cb2ca2ad3f4e837dba2967f323669d36e

commit r13-8750-ga1cb188cb2ca2ad3f4e837dba2967f323669d36e
Author: David Malcolm 
Date:   Thu May 9 13:09:29 2024 -0400

analyzer: fix ICE for 2 bits before the start of base region [PR112889]

Cncrete bindings were using -1 and -2 in the offset field to signify
deleted and empty hash slots, but these are valid values, leading to
assertion failures inside hash_map::put on a debug build, and probable
bugs in a release build.

(gdb) call k.dump(true)
start: -2, size: 1, next: -1

(gdb) p k.is_empty()
$6 = true

Fix by using the size field rather than the offset.

Backported from commit r14-6297-g775aeabcb870b7 (moving the testcase
from c-c++-common to gcc.dg).

gcc/analyzer/ChangeLog:
PR analyzer/112889
* store.h (concrete_binding::concrete_binding): Strengthen
assertion to require size to be be positive, rather than just
non-zero.
(concrete_binding::mark_deleted): Use size rather than start bit
offset.
(concrete_binding::mark_empty): Likewise.
(concrete_binding::is_deleted): Likewise.
(concrete_binding::is_empty): Likewise.

gcc/testsuite/ChangeLog:
PR analyzer/112889
* gcc.dg/analyzer/ice-pr112889.c: New test.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/analyzer/store.h | 10 +-
 gcc/testsuite/gcc.dg/analyzer/ice-pr112889.c | 17 +
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/gcc/analyzer/store.h b/gcc/analyzer/store.h
index 7ded650b6088..6b06be29d8f6 100644
--- a/gcc/analyzer/store.h
+++ b/gcc/analyzer/store.h
@@ -368,7 +368,7 @@ public:
   concrete_binding (bit_offset_t start_bit_offset, bit_size_t size_in_bits)
   : m_bit_range (start_bit_offset, size_in_bits)
   {
-gcc_assert (!m_bit_range.empty_p ());
+gcc_assert (m_bit_range.m_size_in_bits > 0);
   }
   bool concrete_p () const final override { return true; }
 
@@ -409,10 +409,10 @@ public:
 
   static int cmp_ptr_ptr (const void *, const void *);
 
-  void mark_deleted () { m_bit_range.m_start_bit_offset = -1; }
-  void mark_empty () { m_bit_range.m_start_bit_offset = -2; }
-  bool is_deleted () const { return m_bit_range.m_start_bit_offset == -1; }
-  bool is_empty () const { return m_bit_range.m_start_bit_offset == -2; }
+  void mark_deleted () { m_bit_range.m_size_in_bits = -1; }
+  void mark_empty () { m_bit_range.m_size_in_bits = -2; }
+  bool is_deleted () const { return m_bit_range.m_size_in_bits == -1; }
+  bool is_empty () const { return m_bit_range.m_size_in_bits == -2; }
 
 private:
   bit_range m_bit_range;
diff --git a/gcc/testsuite/gcc.dg/analyzer/ice-pr112889.c 
b/gcc/testsuite/gcc.dg/analyzer/ice-pr112889.c
new file mode 100644
index ..e90a53e79baf
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/analyzer/ice-pr112889.c
@@ -0,0 +1,17 @@
+typedef unsigned char __u8;
+struct sk_buff
+{
+  unsigned char *data;
+};
+struct cpl_pass_accept_req
+{
+  __u8 : 6;
+  __u8 sack : 1;
+};
+void build_cpl_pass_accept_req(struct sk_buff* skb)
+{
+  struct cpl_pass_accept_req* req;
+  skb->data -= sizeof(*req);
+  req = (struct cpl_pass_accept_req *)skb->data;
+  req->sack = 1;
+}

[gcc r13-8752] analyzer: casting all zeroes should give all zeroes [PR113333]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:132eb1a210bc7806c4cf188ecac6c08339c94384

commit r13-8752-g132eb1a210bc7806c4cf188ecac6c08339c94384
Author: David Malcolm 
Date:   Thu May 9 13:09:29 2024 -0400

analyzer: casting all zeroes should give all zeroes [PR11]

In particular, accessing the result of *calloc (1, SZ) (if non-NULL)
should be known to be all zeroes.

(backported from commit r14-7265-gd235bf2e807c5f)

gcc/analyzer/ChangeLog:
PR analyzer/11
* region-model-manager.cc
(region_model_manager::maybe_fold_unaryop): Casting all zeroes
should give all zeroes.

gcc/testsuite/ChangeLog:
PR analyzer/11
* gcc.dg/analyzer/calloc-1.c: Add tests.
* gcc.dg/analyzer/data-model-9.c: Update expected results.
* gcc.dg/analyzer/pr96639.c: Update expected results.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/analyzer/region-model-manager.cc |  6 +
 gcc/testsuite/gcc.dg/analyzer/calloc-1.c | 34 
 gcc/testsuite/gcc.dg/analyzer/data-model-9.c |  6 ++---
 gcc/testsuite/gcc.dg/analyzer/pr96639.c  |  2 +-
 4 files changed, 43 insertions(+), 5 deletions(-)

diff --git a/gcc/analyzer/region-model-manager.cc 
b/gcc/analyzer/region-model-manager.cc
index 1a9886fd83c2..51a2d8b029f2 100644
--- a/gcc/analyzer/region-model-manager.cc
+++ b/gcc/analyzer/region-model-manager.cc
@@ -422,6 +422,12 @@ region_model_manager::maybe_fold_unaryop (tree type, enum 
tree_code op,
  && region_sval->get_type ()
  && POINTER_TYPE_P (region_sval->get_type ()))
return get_ptr_svalue (type, region_sval->get_pointee ());
+
+   /* Casting all zeroes should give all zeroes.  */
+   if (type
+   && arg->all_zeroes_p ()
+   && (INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)))
+ return get_or_create_int_cst (type, 0);
   }
   break;
 case TRUTH_NOT_EXPR:
diff --git a/gcc/testsuite/gcc.dg/analyzer/calloc-1.c 
b/gcc/testsuite/gcc.dg/analyzer/calloc-1.c
index bc28128671f9..efb1a24c96a7 100644
--- a/gcc/testsuite/gcc.dg/analyzer/calloc-1.c
+++ b/gcc/testsuite/gcc.dg/analyzer/calloc-1.c
@@ -25,3 +25,37 @@ char *test_1 (size_t sz)
 
   return p;
 }
+
+char **
+test_pr11_1 (void)
+{
+  char **p = (char **)calloc (1, sizeof(char *));
+  if (p)
+{
+  __analyzer_eval (*p == 0); /* { dg-warning "TRUE" } */
+  __analyzer_eval (p[0] == 0); /* { dg-warning "TRUE" } */
+}
+  return p;
+}
+
+char **
+test_pr11_2 (void)
+{
+  char **p = (char **)calloc (2, sizeof(char *));
+  if (p)
+{
+  __analyzer_eval (*p == 0); /* { dg-warning "TRUE" } */
+  __analyzer_eval (p[0] == 0); /* { dg-warning "TRUE" } */
+  __analyzer_eval (p[1] == 0); /* { dg-warning "TRUE" } */
+}
+  return p;
+}
+
+char **
+test_pr11_3 (void)
+{
+  char **vec = (char **)calloc (1, sizeof(char *));
+  if (vec)
+for (char **p=vec ; *p ; p++); /* { dg-bogus "heap-based buffer over-read" 
} */
+  return vec;
+}
diff --git a/gcc/testsuite/gcc.dg/analyzer/data-model-9.c 
b/gcc/testsuite/gcc.dg/analyzer/data-model-9.c
index 159bc612576c..2121f20c4f02 100644
--- a/gcc/testsuite/gcc.dg/analyzer/data-model-9.c
+++ b/gcc/testsuite/gcc.dg/analyzer/data-model-9.c
@@ -14,8 +14,7 @@ void test_1 (void)
   struct foo *f = calloc (1, sizeof (struct foo));
   if (f == NULL)
 return;
-  __analyzer_eval (f->i == 0); /* { dg-warning "TRUE" "desired" { xfail *-*-* 
} } */
-  /* { dg-bogus "UNKNOWN" "status quo" { xfail *-*-* } .-1 } */
+  __analyzer_eval (f->i == 0); /* { dg-warning "TRUE" } */
   free (f);
 }
 
@@ -27,7 +26,6 @@ void test_2 (void)
   if (f == NULL)
 return;
   memset (f, 0, sizeof (struct foo));
-  __analyzer_eval (f->i == 0); /* { dg-warning "TRUE" "desired" { xfail *-*-* 
} } */
-  /* { dg-bogus "UNKNOWN" "status quo" { xfail *-*-* } .-1 } */
+  __analyzer_eval (f->i == 0); /* { dg-warning "TRUE" } */
   free (f);
 }
diff --git a/gcc/testsuite/gcc.dg/analyzer/pr96639.c 
b/gcc/testsuite/gcc.dg/analyzer/pr96639.c
index aedf0464dc93..c06a5c02f795 100644
--- a/gcc/testsuite/gcc.dg/analyzer/pr96639.c
+++ b/gcc/testsuite/gcc.dg/analyzer/pr96639.c
@@ -6,5 +6,5 @@ x7 (void)
   int **md = calloc (1, sizeof (void *));
 
   return md[0][0]; /* { dg-warning "possibly-NULL" "unchecked deref" } */
-  /* { dg-warning "leak of 'md'" "leak" { target *-*-* } .-1 } */
+  /* { dg-warning "Wanalyzer-null-dereference" "deref of NULL" { target *-*-* 
} .-1 } */
 }

[gcc r13-8744] jit: avoid using __vector in testcase [PR110466]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:b38472ffc1e631bd357573b44d956ce16d94e666

commit r13-8744-gb38472ffc1e631bd357573b44d956ce16d94e666
Author: David Malcolm 
Date:   Thu May 9 13:09:27 2024 -0400

jit: avoid using __vector in testcase [PR110466]

r13-4531-gd2e782cb99c311 added test coverage to libgccjit's vector
support, but used __vector, which doesn't work on Power.  Additionally
the size param to gcc_jit_type_get_vector was wrong.

Fixed thusly.

gcc/testsuite/ChangeLog:
PR jit/110466
* jit.dg/test-expressions.c (run_test_of_comparison): Fix size
param to gcc_jit_type_get_vector.
(verify_comparisons): Use a typedef rather than __vector.

(cherry picked from commit r14--g6735d660839533)

Co-authored-by: Marek Polacek 
Signed-off-by: David Malcolm 

Diff:
---
 gcc/testsuite/jit.dg/test-expressions.c | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/gcc/testsuite/jit.dg/test-expressions.c 
b/gcc/testsuite/jit.dg/test-expressions.c
index 13b3baf79ea5..2337b01907ec 100644
--- a/gcc/testsuite/jit.dg/test-expressions.c
+++ b/gcc/testsuite/jit.dg/test-expressions.c
@@ -417,7 +417,7 @@ static void run_test_of_comparison(gcc_jit_context *ctxt,
 const char *expected)
 {
   gcc_jit_type *vec_type =
-gcc_jit_type_get_vector (type, 4);
+gcc_jit_type_get_vector (type, 2);
 
   CHECK_STRING_VALUE (
 make_test_of_comparison (ctxt,
@@ -560,17 +560,17 @@ verify_comparisons (gcc_jit_result *result)
   CHECK_VALUE (test_COMPARISON_GE_on_int (1, 2), 0);
   CHECK_VALUE (test_COMPARISON_GE_on_int (2, 1), 1);
 
-  typedef int __vector __attribute__ ((__vector_size__ (sizeof(int) * 2)));
-  typedef __vector (*test_vec_fn) (__vector, __vector);
+  typedef int v2si __attribute__ ((__vector_size__ (sizeof(int) * 2)));
+  typedef v2si (*test_vec_fn) (v2si, v2si);
 
-  __vector zero_zero = {0, 0};
-  __vector zero_one = {0, 1};
-  __vector one_zero = {1, 0};
+  v2si zero_zero = {0, 0};
+  v2si zero_one = {0, 1};
+  v2si one_zero = {1, 0};
 
-  __vector true_true = {-1, -1};
-  __vector false_true = {0, -1};
-  __vector true_false = {-1, 0};
-  __vector false_false = {0, 0};
+  v2si true_true = {-1, -1};
+  v2si false_true = {0, -1};
+  v2si true_false = {-1, 0};
+  v2si false_false = {0, 0};
 
   test_vec_fn test_COMPARISON_EQ_on_vec_int =
 (test_vec_fn)gcc_jit_result_get_code (result,
@@ -615,7 +615,7 @@ verify_comparisons (gcc_jit_result *result)
   CHECK_VECTOR_VALUE (2, test_COMPARISON_GE_on_vec_int (zero_one, one_zero), 
false_true);
 
   typedef float __vector_f __attribute__ ((__vector_size__ (sizeof(float) * 
2)));
-  typedef __vector (*test_vec_f_fn) (__vector_f, __vector_f);
+  typedef v2si (*test_vec_f_fn) (__vector_f, __vector_f);
 
   __vector_f zero_zero_f = {0, 0};
   __vector_f zero_one_f = {0, 1};

[gcc r13-8743] testsuite: Add more allocation size tests for conjured svalues [PR110014]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:e0c52905f666e3d23881f82dbf39466a24f009f4

commit r13-8743-ge0c52905f666e3d23881f82dbf39466a24f009f4
Author: Tim Lange 
Date:   Thu May 9 13:09:26 2024 -0400

testsuite: Add more allocation size tests for conjured svalues [PR110014]

This patch adds the reproducers reported in PR 110014 as test cases. The
false positives in those cases are already fixed with PR 109577.

2023-06-09  Tim Lange  

PR analyzer/110014

gcc/testsuite/ChangeLog:

* gcc.dg/analyzer/realloc-pr110014.c: New tests.

(cherry picked from commit 
r14-1685-g39adc5eebd61fd276f3f1ef9d7228756a35bd0cb)

Signed-off-by: David Malcolm 

Diff:
---
 gcc/testsuite/gcc.dg/analyzer/realloc-pr110014.c | 25 
 1 file changed, 25 insertions(+)

diff --git a/gcc/testsuite/gcc.dg/analyzer/realloc-pr110014.c 
b/gcc/testsuite/gcc.dg/analyzer/realloc-pr110014.c
new file mode 100644
index ..d76b87814136
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/analyzer/realloc-pr110014.c
@@ -0,0 +1,25 @@
+void *realloc (void *, unsigned long)
+  __attribute__((__nothrow__, __leaf__))
+  __attribute__((__warn_unused_result__)) __attribute__((__alloc_size__ (2)));
+
+long *
+slurp (long *buffer, unsigned long file_size)
+{
+  unsigned long cc;
+  if (!__builtin_add_overflow (file_size - file_size % sizeof (long),
+  2 * sizeof (long), ))
+buffer = realloc (buffer, cc);
+  return buffer;
+}
+
+long *
+slurp1 (long *buffer, unsigned long file_size)
+{
+  return realloc (buffer, file_size - file_size % sizeof (long));
+}
+
+long *
+slurp2 (long *buffer, unsigned long file_size)
+{
+  return realloc (buffer, (file_size / sizeof (long)) * sizeof (long));
+}

[gcc r13-8742] analyzer: Fix allocation size false positive on conjured svalue [PR109577]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:ccf8d3e3d26c6ba3d5e11fffeed8d64018e9c060

commit r13-8742-gccf8d3e3d26c6ba3d5e11fffeed8d64018e9c060
Author: Tim Lange 
Date:   Thu May 9 13:09:26 2024 -0400

analyzer: Fix allocation size false positive on conjured svalue [PR109577]

Currently, the analyzer tries to prove that the allocation size is a
multiple of the pointee's type size.  This patch reverses the behavior
to try to prove that the expression is not a multiple of the pointee's
type size.  With this change, each unhandled case should be gracefully
considered as correct.  This fixes the bug reported in PR 109577 by
Paul Eggert.

Regression-tested on Linux x86-64 with -m32 and -m64.

2023-06-09  Tim Lange  

PR analyzer/109577

gcc/analyzer/ChangeLog:

* constraint-manager.cc (class sval_finder): Visitor to find
childs in svalue trees.
(constraint_manager::sval_constrained_p): Add new function to
check whether a sval might be part of an constraint.
* constraint-manager.h: Add sval_constrained_p function.
* region-model.cc (class size_visitor): Reverse behavior to not
emit a warning on not explicitly considered cases.
(region_model::check_region_size):
Adapt to size_visitor changes.

gcc/testsuite/ChangeLog:

* gcc.dg/analyzer/allocation-size-2.c: Change expected output
and add new test case.
* gcc.dg/analyzer/pr109577.c: New test.

(cherry picked from commit 
r14-1684-g1d57a2232575913ad1085bac0ba5e22b58185179)

Signed-off-by: David Malcolm 

Diff:
---
 gcc/analyzer/constraint-manager.cc| 131 ++
 gcc/analyzer/constraint-manager.h |   1 +
 gcc/analyzer/region-model.cc  |  80 +
 gcc/testsuite/gcc.dg/analyzer/allocation-size-2.c |  24 ++--
 gcc/testsuite/gcc.dg/analyzer/pr109577.c  |  16 +++
 5 files changed, 194 insertions(+), 58 deletions(-)

diff --git a/gcc/analyzer/constraint-manager.cc 
b/gcc/analyzer/constraint-manager.cc
index 2c9c435527ea..9211366fb7c4 100644
--- a/gcc/analyzer/constraint-manager.cc
+++ b/gcc/analyzer/constraint-manager.cc
@@ -2218,6 +2218,137 @@ constraint_manager::get_equiv_class_by_svalue (const 
svalue *sval,
   return false;
 }
 
+/* Tries to find a svalue inside another svalue.  */
+
+class sval_finder : public visitor
+{
+public:
+  sval_finder (const svalue *query) : m_query (query), m_found (false)
+  {
+  }
+
+  bool found_query_p ()
+  {
+return m_found;
+  }
+
+  void visit_region_svalue (const region_svalue *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_constant_svalue (const constant_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_unknown_svalue (const unknown_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_poisoned_svalue (const poisoned_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_setjmp_svalue (const setjmp_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_initial_svalue (const initial_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_unaryop_svalue (const unaryop_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_binop_svalue (const binop_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_sub_svalue (const sub_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_repeated_svalue (const repeated_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_bits_within_svalue (const bits_within_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_unmergeable_svalue (const unmergeable_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_placeholder_svalue (const placeholder_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_widening_svalue (const widening_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_compound_svalue (const compound_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_conjured_svalue (const conjured_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_asm_output_svalue (const asm_output_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+  void visit_const_fn_result_svalue (const const_fn_result_svalue  *sval)
+  {
+m_found |= m_query == sval;
+  }
+
+private:
+  const svalue *m_query;
+  bool m_found;
+};
+
+/* Returns true if SVAL is constrained.  */
+
+bool
+constraint_manager::sval_constrained_p (const svalue *sval) const
+{
+  int i;
+  equiv_class *ec;
+  sval_finder finder (sval);
+  FOR_EACH_VEC_ELT (m_equiv_classes, i, ec)
+{
+  int j;
+  const svalue *iv;
+  FOR_EACH_VEC_ELT (ec->m_vars, j, iv)
+   {
+ iv->accept ();
+ if 

[gcc r13-8741] analyzer: add caching to globals with initializers [PR110112]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:89feb3557a018893cfe50c2e07f91559bd3cde2b

commit r13-8741-g89feb3557a018893cfe50c2e07f91559bd3cde2b
Author: David Malcolm 
Date:   Thu May 9 13:09:26 2024 -0400

analyzer: add caching to globals with initializers [PR110112]

PR analyzer/110112 notes that -fanalyzer is extremely slow on a source
file with large read-only static arrays, repeatedly building the
same compound_svalue representing the full initializer, and repeatedly
building svalues representing parts of the the full initialiazer.

This patch adds caches for both of these; together they reduce the time
taken by -fanalyzer -O2 on the testcase in the bug for an optimized
build:
  91.2s : no caches (status quo)
  32.4s : cache in decl_region::get_svalue_for_constructor
   3.7s : cache in region::get_initial_value_at_main
   3.1s : both caches (this patch)

gcc/analyzer/ChangeLog:
PR analyzer/110112
* region-model.cc (region_model::get_initial_value_for_global):
Move code to region::calc_initial_value_at_main.
* region.cc (region::get_initial_value_at_main): New function.
(region::calc_initial_value_at_main): New function, based on code
in region_model::get_initial_value_for_global.
(region::region): Initialize m_cached_init_sval_at_main.
(decl_region::get_svalue_for_constructor): Add a cache, splitting
out body to...
(decl_region::calc_svalue_for_constructor): ...this new function.
* region.h (region::get_initial_value_at_main): New decl.
(region::calc_initial_value_at_main): New decl.
(region::m_cached_init_sval_at_main): New field.
(decl_region::decl_region): Initialize m_ctor_svalue.
(decl_region::calc_svalue_for_constructor): New decl.
(decl_region::m_ctor_svalue): New field.

(cherry picked from commit r14-1664-gfe9771b59f576f)

Signed-off-by: David Malcolm 

Diff:
---
 gcc/analyzer/region-model.cc | 25 +---
 gcc/analyzer/region.cc   | 71 
 gcc/analyzer/region.h| 14 -
 3 files changed, 79 insertions(+), 31 deletions(-)

diff --git a/gcc/analyzer/region-model.cc b/gcc/analyzer/region-model.cc
index fb81d43f91b2..18996c5e5e85 100644
--- a/gcc/analyzer/region-model.cc
+++ b/gcc/analyzer/region-model.cc
@@ -2355,30 +2355,7 @@ region_model::get_initial_value_for_global (const region 
*reg) const
  the initial value of REG can be taken from the initialization value
  of the decl.  */
   if (called_from_main_p () || TREE_READONLY (decl))
-{
-  /* Attempt to get the initializer value for base_reg.  */
-  if (const svalue *base_reg_init
-   = base_reg->get_svalue_for_initializer (m_mgr))
-   {
- if (reg == base_reg)
-   return base_reg_init;
- else
-   {
- /* Get the value for REG within base_reg_init.  */
- binding_cluster c (base_reg);
- c.bind (m_mgr->get_store_manager (), base_reg, base_reg_init);
- const svalue *sval
-   = c.get_any_binding (m_mgr->get_store_manager (), reg);
- if (sval)
-   {
- if (reg->get_type ())
-   sval = m_mgr->get_or_create_cast (reg->get_type (),
- sval);
- return sval;
-   }
-   }
-   }
-}
+return reg->get_initial_value_at_main (m_mgr);
 
   /* Otherwise, return INIT_VAL(REG).  */
   return m_mgr->get_or_create_initial_value (reg);
diff --git a/gcc/analyzer/region.cc b/gcc/analyzer/region.cc
index a18bfa50d09b..f982ce67509e 100644
--- a/gcc/analyzer/region.cc
+++ b/gcc/analyzer/region.cc
@@ -272,6 +272,51 @@ region::can_have_initial_svalue_p () const
 }
 }
 
+/* For regions within a global decl, get the svalue for the initial
+   value of this region when the program starts, caching the result.  */
+
+const svalue *
+region::get_initial_value_at_main (region_model_manager *mgr) const
+{
+  if (!m_cached_init_sval_at_main)
+m_cached_init_sval_at_main = calc_initial_value_at_main (mgr);
+  return m_cached_init_sval_at_main;
+}
+
+/* Implementation of region::get_initial_value_at_main.  */
+
+const svalue *
+region::calc_initial_value_at_main (region_model_manager *mgr) const
+{
+  const decl_region *base_reg = get_base_region ()->dyn_cast_decl_region ();
+  gcc_assert (base_reg);
+
+  /* Attempt to get the initializer value for base_reg.  */
+  if (const svalue *base_reg_init
+  = base_reg->get_svalue_for_initializer (mgr))
+{
+  if (this == base_reg)
+   return base_reg_init;
+  else
+   {
+ /* Get the value for REG within base_reg_init.  */
+ binding_cluster c (base_reg);
+ c.bind (mgr->get_store_manager (), base_reg, 

[gcc r15-348] c++: lambda capturing structured bindings [PR85889]

[Marek Polacek via Gcc-cvs]

https://gcc.gnu.org/g:46bafd9a6b9b776142e0b1424a6ac02e3a2fd300

commit r15-348-g46bafd9a6b9b776142e0b1424a6ac02e3a2fd300
Author: Marek Polacek 
Date:   Fri Mar 1 17:13:02 2024 -0500

c++: lambda capturing structured bindings [PR85889]

 clarifies that it's OK to capture structured
bindings.

[expr.prim.lambda.capture]/4 says "The identifier in a simple-capture shall
denote a local entity" and [basic.pre]/3: "An entity is a [...] structured
binding".

It doesn't appear that this was made a DR, so, strictly speaking, we
should have a -Wc++20-extensions warning, like clang++.

PR c++/85889

gcc/cp/ChangeLog:

* lambda.cc (add_capture): Add a pedwarn for capturing structured
bindings.

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/decomp3.C: Use -Wno-c++20-extensions.
* g++.dg/cpp1z/decomp60.C: New test.

Diff:
---
 gcc/cp/lambda.cc  | 10 ++
 gcc/testsuite/g++.dg/cpp1z/decomp60.C | 12 
 gcc/testsuite/g++.dg/cpp2a/decomp3.C  |  2 +-
 3 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/gcc/cp/lambda.cc b/gcc/cp/lambda.cc
index 4b1f9391fee1..630cc4eade14 100644
--- a/gcc/cp/lambda.cc
+++ b/gcc/cp/lambda.cc
@@ -607,6 +607,16 @@ add_capture (tree lambda, tree id, tree orig_init, bool 
by_reference_p,
 TCTX_CAPTURE_BY_COPY, type))
return error_mark_node;
}
+
+  if (cxx_dialect < cxx20)
+   {
+ auto_diagnostic_group d;
+ tree stripped_init = tree_strip_any_location_wrapper (initializer);
+ if (DECL_DECOMPOSITION_P (stripped_init)
+ && pedwarn (input_location, OPT_Wc__20_extensions,
+ "captured structured bindings are a C++20 extension"))
+   inform (DECL_SOURCE_LOCATION (stripped_init), "declared here");
+   }
 }
 
   /* Add __ to the beginning of the field name so that user code
diff --git a/gcc/testsuite/g++.dg/cpp1z/decomp60.C 
b/gcc/testsuite/g++.dg/cpp1z/decomp60.C
new file mode 100644
index ..b6117f3af583
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp1z/decomp60.C
@@ -0,0 +1,12 @@
+// PR c++/85889
+// { dg-do compile { target c++17 } }
+// { dg-options "" }
+
+struct X { int i, j; };
+void f() {
+  X x{};
+  auto [i, j] = x;
+  []() { }; // { dg-warning "captured structured bindings" "" { target 
c++17_only } }
+  [i]() { }; // { dg-warning "captured structured bindings" "" { target 
c++17_only } }
+}
+
diff --git a/gcc/testsuite/g++.dg/cpp2a/decomp3.C 
b/gcc/testsuite/g++.dg/cpp2a/decomp3.C
index 5e77973d41f7..25ab83199757 100644
--- a/gcc/testsuite/g++.dg/cpp2a/decomp3.C
+++ b/gcc/testsuite/g++.dg/cpp2a/decomp3.C
@@ -1,6 +1,6 @@
 // P1381R1
 // { dg-do compile { target c++11 } }
-// { dg-options "" }
+// { dg-options "-Wno-c++20-extensions" }
 
 struct Foo { int a : 1; int b; };

[gcc r13-8740] [PR114415][scheduler]: Fixing wrong code generation

[Vladimir Makarov via Gcc-cvs]

https://gcc.gnu.org/g:e30211cb0b3a2b88959e9bc40626a17461de52de

commit r13-8740-ge30211cb0b3a2b88959e9bc40626a17461de52de
Author: Vladimir N. Makarov 
Date:   Thu Apr 4 16:04:04 2024 -0400

[PR114415][scheduler]: Fixing wrong code generation

  For the test case, the insn scheduler (working for live range
shrinkage) moves insns modifying stack memory before an insn reserving
the stack memory. Comments in the patch contains more details about
the problem and its solution.

gcc/ChangeLog:

PR rtl-optimization/114415
* sched-deps.cc (add_insn_mem_dependence): Add memory check for mem 
argument.
(sched_analyze_1): Treat stack pointer modification as memory read.
(sched_analyze_2, sched_analyze_insn): Add memory guard for 
processing pending_read_mems.
* sched-int.h (deps_desc): Add comment to pending_read_mems.

gcc/testsuite/ChangeLog:

PR rtl-optimization/114415
* gcc.target/i386/pr114415.c: New test.

Diff:
---
 gcc/sched-deps.cc| 49 +---
 gcc/sched-int.h  |  4 ++-
 gcc/testsuite/gcc.target/i386/pr114415.c | 47 ++
 3 files changed, 83 insertions(+), 17 deletions(-)

diff --git a/gcc/sched-deps.cc b/gcc/sched-deps.cc
index 2aa6623ad2ea..2104895f3009 100644
--- a/gcc/sched-deps.cc
+++ b/gcc/sched-deps.cc
@@ -1735,7 +1735,7 @@ add_insn_mem_dependence (class deps_desc *deps, bool 
read_p,
   insn_node = alloc_INSN_LIST (insn, *insn_list);
   *insn_list = insn_node;
 
-  if (sched_deps_info->use_cselib)
+  if (sched_deps_info->use_cselib && MEM_P (mem))
 {
   mem = shallow_copy_rtx (mem);
   XEXP (mem, 0) = cselib_subst_to_values_from_insn (XEXP (mem, 0),
@@ -2458,6 +2458,25 @@ sched_analyze_1 (class deps_desc *deps, rtx x, rtx_insn 
*insn)
   FIRST_STACK_REG);
}
 #endif
+  if (!deps->readonly && regno == STACK_POINTER_REGNUM)
+   {
+ /* Please see PR114115.  We have insn modifying memory on the stack
+and not addressed by stack pointer and we have insn reserving the
+stack space.  If we move the insn modifying memory before insn
+reserving the stack space, we can change memory out of the red
+zone.  Even worse, some optimizations (e.g. peephole) can add
+insns using temporary stack slots before insn reserving the stack
+space but after the insn modifying memory.  This will corrupt the
+modified memory.  Therefore we treat insn changing the stack as
+reading unknown memory.  This will create anti-dependence.  We
+don't need to treat the insn as writing memory because GCC by
+itself does not generate code reading undefined stack memory.  */
+ if ((deps->pending_read_list_length + deps->pending_write_list_length)
+ >= param_max_pending_list_length
+ && !DEBUG_INSN_P (insn))
+   flush_pending_lists (deps, insn, true, true);
+ add_insn_mem_dependence (deps, true, insn, dest);
+   }
 }
   else if (MEM_P (dest))
 {
@@ -2498,10 +2517,11 @@ sched_analyze_1 (class deps_desc *deps, rtx x, rtx_insn 
*insn)
  pending_mem = deps->pending_read_mems;
  while (pending)
{
- if (anti_dependence (pending_mem->element (), t)
- && ! sched_insns_conditions_mutex_p (insn, pending->insn ()))
-   note_mem_dep (t, pending_mem->element (), pending->insn (),
- DEP_ANTI);
+ rtx mem = pending_mem->element ();
+ if (REG_P (mem)
+ || (anti_dependence (mem, t)
+ && ! sched_insns_conditions_mutex_p (insn, pending->insn 
(
+   note_mem_dep (t, mem, pending->insn (), DEP_ANTI);
 
  pending = pending->next ();
  pending_mem = pending_mem->next ();
@@ -2637,12 +2657,10 @@ sched_analyze_2 (class deps_desc *deps, rtx x, rtx_insn 
*insn)
pending_mem = deps->pending_read_mems;
while (pending)
  {
-   if (read_dependence (pending_mem->element (), t)
-   && ! sched_insns_conditions_mutex_p (insn,
-pending->insn ()))
- note_mem_dep (t, pending_mem->element (),
-   pending->insn (),
-   DEP_ANTI);
+   rtx mem = pending_mem->element ();
+   if (MEM_P (mem) && read_dependence (mem, t)
+   && ! sched_insns_conditions_mutex_p (insn, pending->insn 
()))
+ note_mem_dep (t, mem, pending->insn (), DEP_ANTI);
 
pending = pending->next ();
pending_mem = pending_mem->next ();
@@ -3026,8 +3044,7 @@ sched_analyze_insn (class 

[gcc r15-347] Add myself to DCO

[H.J. Lu via Gcc-cvs]

https://gcc.gnu.org/g:80d1e2ec4d394111ebd50d2e8928f7596b7b5c7e

commit r15-347-g80d1e2ec4d394111ebd50d2e8928f7596b7b5c7e
Author: H.J. Lu 
Date:   Thu May 9 07:59:50 2024 -0700

Add myself to DCO

ChangeLog:

* MAINTAINERS: Add myself to DCO.

Signed-off-by: H.J. Lu 

Diff:
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 27e3872ef936..71e02abc4263 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -769,6 +769,7 @@ Tim Lange   

 Jeff Law   
 Jeff Law   
 Jeff Law   
+H.J. Lu
 Immad Mir  
 Gaius Mulley   
 Andrew Pinski  

[gcc r15-346] sra: Do not leave work for DSE (that it can sometimes not perform)

[Martin Jambor via Gcc-cvs]

https://gcc.gnu.org/g:f6743695b4d2bd4da96e56a19157372f93b800bd

commit r15-346-gf6743695b4d2bd4da96e56a19157372f93b800bd
Author: Martin Jambor 
Date:   Thu May 9 16:39:44 2024 +0200

sra: Do not leave work for DSE (that it can sometimes not perform)

When looking again at the g++.dg/tree-ssa/pr109849.C testcase we
discovered that it generates terrible store-to-load forwarding stalls
because SRA was leaving behind aggregate loads but all the stores were
by scalar parts and DSE failed to remove the useless load.  SRA has
all the knowledge to remove the statement even now, so this small
patch makes it do so.

With this patch, the g++.dg/tree-ssa/pr109849.C micro-benchmark runs 9
times faster (on an AMD EPYC 75F3 machine).

gcc/ChangeLog:

2024-04-18  Martin Jambor  

* tree-sra.cc (sra_modify_assign): Remove the original statement
also when dealing with a store to a fully covered aggregate from a
non-candidate.

gcc/testsuite/ChangeLog:

2024-04-23  Martin Jambor  

* g++.dg/tree-ssa/pr109849.C: Also check that the aggeegate store
to cur disappears.
* gcc.dg/tree-ssa/ssa-dse-26.c: Instead of relying on DSE,
check that the unwanted stores were removed at early SRA time.

Diff:
---
 gcc/testsuite/g++.dg/tree-ssa/pr109849.C   |  3 ++-
 gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-26.c |  6 +++---
 gcc/tree-sra.cc| 14 --
 3 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/gcc/testsuite/g++.dg/tree-ssa/pr109849.C 
b/gcc/testsuite/g++.dg/tree-ssa/pr109849.C
index cd348c0f5906..d06dbb104829 100644
--- a/gcc/testsuite/g++.dg/tree-ssa/pr109849.C
+++ b/gcc/testsuite/g++.dg/tree-ssa/pr109849.C
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fdump-tree-sra" } */
+/* { dg-options "-O2 -fdump-tree-sra -fdump-tree-optimized" } */
 
 #include 
 typedef unsigned int uint32_t;
@@ -29,3 +29,4 @@ main()
 }
 
 /* { dg-final { scan-tree-dump "Created a replacement for stack offset" "sra"} 
} */
+/* { dg-final { scan-tree-dump-not "cur = MEM" "optimized"} } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-26.c 
b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-26.c
index 43152de56163..1d01392c5957 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-26.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-26.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fdump-tree-dse1-details -fno-short-enums -fno-tree-fre" 
} */
+/* { dg-options "-O2 -fdump-tree-esra -fno-short-enums -fno-tree-fre" } */
 /* { dg-skip-if "we want a BIT_FIELD_REF from fold_truth_andor" { ! lp64 } } */
 /* { dg-skip-if "temporary variable names are not x and y" { 
mmix-knuth-mmixware } } */
 
@@ -31,5 +31,5 @@ constraint_equal (struct constraint a, struct constraint b)
 && constraint_expr_equal (a.rhs, b.rhs);
 }
 
-/* { dg-final { scan-tree-dump-times "Deleted dead store: x = " 2 "dse1" } } */
-/* { dg-final { scan-tree-dump-times "Deleted dead store: y = " 2 "dse1" } } */
+/* { dg-final { scan-tree-dump-not "x = " "esra" } } */
+/* { dg-final { scan-tree-dump-not "y = " "esra" } } */
diff --git a/gcc/tree-sra.cc b/gcc/tree-sra.cc
index 32fa28911f2d..8040b0c56451 100644
--- a/gcc/tree-sra.cc
+++ b/gcc/tree-sra.cc
@@ -4854,8 +4854,18 @@ sra_modify_assign (gimple *stmt, gimple_stmt_iterator 
*gsi)
 But use the RHS aggregate to load from to expose more
 optimization opportunities.  */
  if (access_has_children_p (lacc))
-   generate_subtree_copies (lacc->first_child, rhs, lacc->offset,
-0, 0, gsi, true, true, loc);
+   {
+ generate_subtree_copies (lacc->first_child, rhs, lacc->offset,
+  0, 0, gsi, true, true, loc);
+ if (lacc->grp_covered)
+   {
+ unlink_stmt_vdef (stmt);
+ gsi_remove (& orig_gsi, true);
+ release_defs (stmt);
+ sra_stats.deleted++;
+ return SRA_AM_REMOVED;
+   }
+   }
}
 
   return SRA_AM_NONE;

[gcc r13-8739] Fix range-ops operator_addr.

[Andrew Macleod via Gcc-cvs]

https://gcc.gnu.org/g:421311a31a12b96143eb901fde0e020771fe71d4

commit r13-8739-g421311a31a12b96143eb901fde0e020771fe71d4
Author: Andrew MacLeod 
Date:   Wed May 8 10:22:23 2024 -0400

Fix range-ops operator_addr.

Lack of symbolic information prevents op1_range from being able to draw
the same conclusions as fold_range can.

PR tree-optimization/111009
gcc/
* range-op.cc (operator_addr_expr::op1_range): Be more restrictive.
* value-range.h (contains_zero_p): New.

gcc/testsuite/
* gcc.dg/pr111009.c: New.

Diff:
---
 gcc/range-op.cc | 12 +++-
 gcc/testsuite/gcc.dg/pr111009.c | 38 ++
 gcc/value-range.h   | 10 ++
 3 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/gcc/range-op.cc b/gcc/range-op.cc
index f90e78dcfbc9..97a88dc7efa4 100644
--- a/gcc/range-op.cc
+++ b/gcc/range-op.cc
@@ -4357,7 +4357,17 @@ operator_addr_expr::op1_range (irange , tree type,
   const irange ,
   relation_trio) const
 {
-  return operator_addr_expr::fold_range (r, type, lhs, op2);
+   if (empty_range_varying (r, type, lhs, op2))
+return true;
+
+  // Return a non-null pointer of the LHS type (passed in op2), but only
+  // if we cant overflow, eitherwise a no-zero offset could wrap to zero.
+  // See PR 111009.
+  if (!contains_zero_p (lhs) && TYPE_OVERFLOW_UNDEFINED (type))
+r = range_nonzero (type);
+  else
+r.set_varying (type);
+  return true;
 }
 
 
diff --git a/gcc/testsuite/gcc.dg/pr111009.c b/gcc/testsuite/gcc.dg/pr111009.c
new file mode 100644
index ..3accd9ac0630
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr111009.c
@@ -0,0 +1,38 @@
+/* PR tree-optimization/111009 */
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-strict-overflow" } */
+
+struct dso {
+ struct dso * next;
+ int maj;
+};
+
+__attribute__((noipa)) static void __dso_id__cmp_(void) {}
+
+__attribute__((noipa))
+static int bug(struct dso * d, struct dso *dso)
+{
+ struct dso **p = 
+ struct dso *curr = 0;
+
+ while (*p) {
+  curr = *p;
+  // prevent null deref below
+  if (!dso) return 1;
+  if (dso == curr) return 1;
+
+  int *a = >maj;
+  // null deref
+  if (!(a && *a)) __dso_id__cmp_();
+
+  p = >next;
+ }
+ return 0;
+}
+
+__attribute__((noipa))
+int main(void) {
+struct dso d = { 0, 0, };
+bug(, 0);
+}
+
diff --git a/gcc/value-range.h b/gcc/value-range.h
index 96e59ecfa72f..0284d6cedf4c 100644
--- a/gcc/value-range.h
+++ b/gcc/value-range.h
@@ -,6 +,16 @@ irange::normalize_kind ()
 }
 }
 
+inline bool
+contains_zero_p (const irange )
+{
+  if (r.undefined_p ())
+return false;
+
+  tree zero = build_zero_cst (r.type ());
+  return r.contains_p (zero);
+}
+
 // Return the maximum value for TYPE.
 
 inline tree

[gcc r15-345] Manually update entries for the Revert Revert commits.

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:2790195500ec523cad9c7292816540e2fc19f456

commit r15-345-g2790195500ec523cad9c7292816540e2fc19f456
Author: Jakub Jelinek 
Date:   Thu May 9 13:09:06 2024 +0200

Manually update entries for the Revert Revert commits.

Diff:
---
 gcc/ChangeLog   | 12 
 gcc/testsuite/ChangeLog | 11 +++
 2 files changed, 23 insertions(+)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 12a7d754b232..fff1592f837f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -477,6 +477,18 @@
(Specific, *-*-solaris2*): Document Solaris 11.3 removal.  Remove
11.3 references and caveats.  Update for 11.4.
 
+2024-05-07  Richard Biener  
+
+   Revert:
+   2024-04-10  Richard Biener  
+
+   Revert:
+   2024-03-27  Segher Boessenkool  
+
+   PR rtl-optimization/101523
+   * combine.cc (try_combine): Don't do a 2-insn combination if
+   it does not in fact change I2.
+
 2024-05-07  Andrew Pinski  
 
PR middle-end/97263
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index fa115f8fd425..9f87260fa17d 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -94,6 +94,17 @@
 
* gcc.target/i386/cmov6.c: Fixed.
 
+2024-05-08  Hans-Peter Nilsson  
+
+   Revert:
+   2024-04-10  Hans-Peter Nilsson  
+
+   Revert:
+   2024-04-05  Hans-Peter Nilsson  
+
+   * gcc.target/cris/pr93372-2.c: Tweak scan-assembler
+   checks to cover recent combine improvement.
+
 2024-05-07  Nathaniel Shead  
 
PR c++/114856

[gcc r15-344] contrib: Add 109f1b28fc94c93096506e3df0c25e331cef19d0 to ignored commits

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:5fe40f2c651af84b1a4ff6527ef4307591228a1b

commit r15-344-g5fe40f2c651af84b1a4ff6527ef4307591228a1b
Author: Jakub Jelinek 
Date:   Thu May 9 13:01:31 2024 +0200

contrib: Add 109f1b28fc94c93096506e3df0c25e331cef19d0 to ignored commits

2024-05-09  Jakub Jelinek  

* gcc-changelog/git_update_version.py: Replace
9dbff9c05520a74e6cd337578f27b56c941f64f3 with
39f81924d88e3cc197fc3df74204c9b5e01e12f7 and
109f1b28fc94c93096506e3df0c25e331cef19d0 in IGNORED_COMMITS.

Diff:
---
 contrib/gcc-changelog/git_update_version.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/contrib/gcc-changelog/git_update_version.py 
b/contrib/gcc-changelog/git_update_version.py
index 3d9a28ccbdf3..24f6c43d0b25 100755
--- a/contrib/gcc-changelog/git_update_version.py
+++ b/contrib/gcc-changelog/git_update_version.py
@@ -40,7 +40,8 @@ IGNORED_COMMITS = (
 '1957bedf29a1b2cc231972aba680fe80199d5498',
 '040e5b0edbca861196d9e2ea2af5e805769c8d5d',
 '8057f9aa1f7e70490064de796d7a8d42d446caf8',
-'9dbff9c05520a74e6cd337578f27b56c941f64f3')
+'109f1b28fc94c93096506e3df0c25e331cef19d0',
+'39f81924d88e3cc197fc3df74204c9b5e01e12f7')
 
 FORMAT = '%(asctime)s:%(levelname)s:%(name)s:%(message)s'
 logging.basicConfig(level=logging.INFO, format=FORMAT,

[gcc r15-342] RISC-V: Make full-vec-move1.c test robust for optimization

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:b1520d2260c5e0cfcd7a4354fab70f66e2912ff2

commit r15-342-gb1520d2260c5e0cfcd7a4354fab70f66e2912ff2
Author: Pan Li 
Date:   Thu May 9 10:56:46 2024 +0800

RISC-V: Make full-vec-move1.c test robust for optimization

During investigate the support of early break autovec, we notice
the test full-vec-move1.c will be optimized to 'return 0;' in main
function body.  Because somehow the value of V type is compiler
time constant,  and then the second loop will be considered as
assert (true).

Thus,  the ccp4 pass will eliminate these stmt and just return 0.

typedef int16_t V __attribute__((vector_size (128)));

int main ()
{
  V v;
  for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
(v)[i] = i;

  V res = v;
  for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
assert (res[i] == i); // will be optimized to assert (true)
}

This patch would like to introduce a extern function to use the res[i]
that get rid of the ccp4 optimization.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c:
Introduce extern func use to get rid of ccp4 optimization.

Signed-off-by: Pan Li 

Diff:
---
 .../gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
index d73bad4af6f7..fae2ae91572f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
@@ -2,11 +2,12 @@
 /* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d 
-fno-vect-cost-model -mrvv-vector-bits=zvl" } */
 
 #include 
-#include 
 
 /* This would cause us to emit a vl1r.v for VNx4HImode even when
the hardware vector size vl > 64.  */
 
+extern int16_t test_element (int16_t);
+
 typedef int16_t V __attribute__((vector_size (128)));
 
 int main ()
@@ -14,9 +15,10 @@ int main ()
   V v;
   for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
 (v)[i] = i;
+
   V res = v;
   for (int i = 0; i < sizeof (v) / sizeof (v[0]); i++)
-assert (res[i] == i);
+test_element (res[i]);
 }
 
 /* { dg-final { scan-assembler-not {vl[1248]r.v} } }  */

[gcc r15-341] contrib: Add 9dbff9c05520a74e6cd337578f27b56c941f64f3 to ignored commits

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:de0b40ac5be8977a6bee8860f67d45011642f1a2

commit r15-341-gde0b40ac5be8977a6bee8860f67d45011642f1a2
Author: Jakub Jelinek 
Date:   Thu May 9 12:15:51 2024 +0200

contrib: Add 9dbff9c05520a74e6cd337578f27b56c941f64f3 to ignored commits

2024-05-09  Jakub Jelinek  

* gcc-changelog/git_update_version.py: Add
9dbff9c05520a74e6cd337578f27b56c941f64f3 to IGNORED_COMMITS.

Diff:
---
 contrib/gcc-changelog/git_update_version.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/contrib/gcc-changelog/git_update_version.py 
b/contrib/gcc-changelog/git_update_version.py
index f194757b0cb7..3d9a28ccbdf3 100755
--- a/contrib/gcc-changelog/git_update_version.py
+++ b/contrib/gcc-changelog/git_update_version.py
@@ -39,7 +39,8 @@ IGNORED_COMMITS = (
 'e4cba49413ca429dc82f6aa2e88129ecb3fdd943',
 '1957bedf29a1b2cc231972aba680fe80199d5498',
 '040e5b0edbca861196d9e2ea2af5e805769c8d5d',
-'8057f9aa1f7e70490064de796d7a8d42d446caf8')
+'8057f9aa1f7e70490064de796d7a8d42d446caf8',
+'9dbff9c05520a74e6cd337578f27b56c941f64f3')
 
 FORMAT = '%(asctime)s:%(levelname)s:%(name)s:%(message)s'
 logging.basicConfig(level=logging.INFO, format=FORMAT,

[gcc r11-11423] testsuite: Fix up vector-subaccess-1.C test for ia32 [PR89224]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:e6c869372f0ca8b28ac63c7eb26fde35b53aba37

commit r11-11423-ge6c869372f0ca8b28ac63c7eb26fde35b53aba37
Author: Jakub Jelinek 
Date:   Thu May 9 11:18:21 2024 +0200

testsuite: Fix up vector-subaccess-1.C test for ia32 [PR89224]

The test FAILs on i686-linux due to
.../gcc/testsuite/g++.dg/torture/vector-subaccess-1.C:16:6: warning: SSE 
vector argument without SSE enabled changes the ABI [-Wpsabi]
excess warnings.

This fixes it by adding -Wno-psabi, like commonly done in other tests.

2024-05-09  Jakub Jelinek  

PR c++/89224
* g++.dg/torture/vector-subaccess-1.C: Add -Wno-psabi as additional
options.

(cherry picked from commit 8fb65ec816ff8f0d529b6d30821abace4328c9a2)

Diff:
---
 gcc/testsuite/g++.dg/torture/vector-subaccess-1.C | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C 
b/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
index 0c8958a4e034..4b909dae4926 100644
--- a/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
+++ b/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
@@ -1,4 +1,5 @@
 /* PR c++/89224 */
+/* { dg-additional-options "-Wno-psabi" } */
 
 /* The access of `vector[i]` has the same qualifiers as the original
vector which was missing. */

[gcc r12-10435] testsuite: Fix up vector-subaccess-1.C test for ia32 [PR89224]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:ffa41c65a375746fd26c2d620e634fb162726dfc

commit r12-10435-gffa41c65a375746fd26c2d620e634fb162726dfc
Author: Jakub Jelinek 
Date:   Thu May 9 11:18:21 2024 +0200

testsuite: Fix up vector-subaccess-1.C test for ia32 [PR89224]

The test FAILs on i686-linux due to
.../gcc/testsuite/g++.dg/torture/vector-subaccess-1.C:16:6: warning: SSE 
vector argument without SSE enabled changes the ABI [-Wpsabi]
excess warnings.

This fixes it by adding -Wno-psabi, like commonly done in other tests.

2024-05-09  Jakub Jelinek  

PR c++/89224
* g++.dg/torture/vector-subaccess-1.C: Add -Wno-psabi as additional
options.

(cherry picked from commit 8fb65ec816ff8f0d529b6d30821abace4328c9a2)

Diff:
---
 gcc/testsuite/g++.dg/torture/vector-subaccess-1.C | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C 
b/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
index 0c8958a4e034..4b909dae4926 100644
--- a/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
+++ b/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
@@ -1,4 +1,5 @@
 /* PR c++/89224 */
+/* { dg-additional-options "-Wno-psabi" } */
 
 /* The access of `vector[i]` has the same qualifiers as the original
vector which was missing. */

[gcc r13-8737] testsuite: Fix up vector-subaccess-1.C test for ia32 [PR89224]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:6f7674a558aaa0c7b16657c35666ad9b12e1c219

commit r13-8737-g6f7674a558aaa0c7b16657c35666ad9b12e1c219
Author: Jakub Jelinek 
Date:   Thu May 9 11:18:21 2024 +0200

testsuite: Fix up vector-subaccess-1.C test for ia32 [PR89224]

The test FAILs on i686-linux due to
.../gcc/testsuite/g++.dg/torture/vector-subaccess-1.C:16:6: warning: SSE 
vector argument without SSE enabled changes the ABI [-Wpsabi]
excess warnings.

This fixes it by adding -Wno-psabi, like commonly done in other tests.

2024-05-09  Jakub Jelinek  

PR c++/89224
* g++.dg/torture/vector-subaccess-1.C: Add -Wno-psabi as additional
options.

(cherry picked from commit 8fb65ec816ff8f0d529b6d30821abace4328c9a2)

Diff:
---
 gcc/testsuite/g++.dg/torture/vector-subaccess-1.C | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C 
b/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
index 0c8958a4e034..4b909dae4926 100644
--- a/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
+++ b/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
@@ -1,4 +1,5 @@
 /* PR c++/89224 */
+/* { dg-additional-options "-Wno-psabi" } */
 
 /* The access of `vector[i]` has the same qualifiers as the original
vector which was missing. */

[gcc r14-10189] testsuite: Fix up vector-subaccess-1.C test for ia32 [PR89224]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:726e7a64edc22a33a5f495698722ba797793edca

commit r14-10189-g726e7a64edc22a33a5f495698722ba797793edca
Author: Jakub Jelinek 
Date:   Thu May 9 11:18:21 2024 +0200

testsuite: Fix up vector-subaccess-1.C test for ia32 [PR89224]

The test FAILs on i686-linux due to
.../gcc/testsuite/g++.dg/torture/vector-subaccess-1.C:16:6: warning: SSE 
vector argument without SSE enabled changes the ABI [-Wpsabi]
excess warnings.

This fixes it by adding -Wno-psabi, like commonly done in other tests.

2024-05-09  Jakub Jelinek  

PR c++/89224
* g++.dg/torture/vector-subaccess-1.C: Add -Wno-psabi as additional
options.

(cherry picked from commit 8fb65ec816ff8f0d529b6d30821abace4328c9a2)

Diff:
---
 gcc/testsuite/g++.dg/torture/vector-subaccess-1.C | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C 
b/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
index 0c8958a4e034..4b909dae4926 100644
--- a/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
+++ b/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
@@ -1,4 +1,5 @@
 /* PR c++/89224 */
+/* { dg-additional-options "-Wno-psabi" } */
 
 /* The access of `vector[i]` has the same qualifiers as the original
vector which was missing. */

[gcc r15-340] testsuite: Fix up vector-subaccess-1.C test for ia32 [PR89224]

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:8fb65ec816ff8f0d529b6d30821abace4328c9a2

commit r15-340-g8fb65ec816ff8f0d529b6d30821abace4328c9a2
Author: Jakub Jelinek 
Date:   Thu May 9 11:18:21 2024 +0200

testsuite: Fix up vector-subaccess-1.C test for ia32 [PR89224]

The test FAILs on i686-linux due to
.../gcc/testsuite/g++.dg/torture/vector-subaccess-1.C:16:6: warning: SSE 
vector argument without SSE enabled changes the ABI [-Wpsabi]
excess warnings.

This fixes it by adding -Wno-psabi, like commonly done in other tests.

2024-05-09  Jakub Jelinek  

PR c++/89224
* g++.dg/torture/vector-subaccess-1.C: Add -Wno-psabi as additional
options.

Diff:
---
 gcc/testsuite/g++.dg/torture/vector-subaccess-1.C | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C 
b/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
index 0c8958a4e034..4b909dae4926 100644
--- a/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
+++ b/gcc/testsuite/g++.dg/torture/vector-subaccess-1.C
@@ -1,4 +1,5 @@
 /* PR c++/89224 */
+/* { dg-additional-options "-Wno-psabi" } */
 
 /* The access of `vector[i]` has the same qualifiers as the original
vector which was missing. */

[gcc r14-10187] AVR: target/114975 - Add combine-pattern for __popcountqi2.

[Georg-Johann Lay via Gcc-cvs]

https://gcc.gnu.org/g:4ef09dd8ce8866e4f64dd918890c97a67af8fd15

commit r14-10187-g4ef09dd8ce8866e4f64dd918890c97a67af8fd15
Author: Georg-Johann Lay 
Date:   Tue May 7 19:39:55 2024 +0200

AVR: target/114975 - Add combine-pattern for __popcountqi2.

PR target/114975
gcc/
* config/avr/avr.md: Add combine pattern for
8-bit popcount detection.

gcc/testsuite/
* gcc.target/avr/pr114975-popcount.c: New test.

(cherry picked from commit c8f4bbb824fafecf021a802324cd79e64b03b947)

Diff:
---
 gcc/config/avr/avr.md| 13 +
 gcc/testsuite/gcc.target/avr/pr114975-popcount.c | 17 +
 2 files changed, 30 insertions(+)

diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 97f42be7729c..36fe384828f9 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -8527,6 +8527,19 @@
 operands[2] = gen_reg_rtx (HImode);
   })
 
+(define_insn_and_split "*popcounthi2.split8"
+  [(set (reg:HI 24)
+(zero_extend:HI (popcount:QI (match_operand:QI 0 
"register_operand"]
+  "! reload_completed"
+  { gcc_unreachable(); }
+  "&& 1"
+  [(set (reg:QI 24)
+(match_dup 0))
+   (set (reg:QI 24)
+(popcount:QI (reg:QI 24)))
+   (set (reg:QI 25)
+(const_int 0))])
+
 (define_insn_and_split "*popcounthi2.libgcc_split"
   [(set (reg:HI 24)
 (popcount:HI (reg:HI 24)))]
diff --git a/gcc/testsuite/gcc.target/avr/pr114975-popcount.c 
b/gcc/testsuite/gcc.target/avr/pr114975-popcount.c
new file mode 100644
index ..87eb56b56c5a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/pr114975-popcount.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-Os" } */
+
+typedef __UINT8_TYPE__ uint8_t;
+
+uint8_t use_pop1 (int y, uint8_t x)
+{
+return 1 + __builtin_popcount (x);
+}
+
+uint8_t use_pop2 (uint8_t x)
+{
+   x += 1;
+return 1 - __builtin_popcount (x);
+}
+
+/* { dg-final { scan-assembler-times "__popcountqi2" 2 } } */

[gcc r14-10188] AVR: target/114975 - Add combine-pattern for __parityqi2.

[Georg-Johann Lay via Gcc-cvs]

https://gcc.gnu.org/g:bbb76ac0a06ae3a469f2acc2d5d63e63160bd9e5

commit r14-10188-gbbb76ac0a06ae3a469f2acc2d5d63e63160bd9e5
Author: Georg-Johann Lay 
Date:   Tue May 7 19:42:30 2024 +0200

AVR: target/114975 - Add combine-pattern for __parityqi2.

PR target/114975
gcc/
* config/avr/avr.md: Add combine pattern for
8-bit parity detection.

gcc/testsuite/
* gcc.target/avr/pr114975-parity.c: New test.

(cherry picked from commit 41bc359c322d45ec1adfb51f7a45c7ef02ce6ca9)

Diff:
---
 gcc/config/avr/avr.md  | 17 -
 gcc/testsuite/gcc.target/avr/pr114975-parity.c | 17 +
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 36fe384828f9..d4fcff46123b 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -8418,7 +8418,22 @@
(set (match_dup 0)
 (reg:HI 24))])
 
-(define_insn_and_split "*parityqihi2"
+(define_insn_and_split "*parityqihi2.1"
+  [(set (match_operand:HI 0 "register_operand""=r")
+(zero_extend:HI
+ (parity:QI (match_operand:QI 1 "register_operand" "r"
+   (clobber (reg:HI 24))]
+  "!reload_completed"
+  { gcc_unreachable(); }
+  "&& 1"
+  [(set (reg:QI 24)
+(match_dup 1))
+   (set (reg:HI 24)
+(zero_extend:HI (parity:QI (reg:QI 24
+   (set (match_dup 0)
+(reg:HI 24))])
+
+(define_insn_and_split "*parityqihi2.2"
   [(set (match_operand:HI 0 "register_operand"   "=r")
 (parity:HI (match_operand:QI 1 "register_operand" "r")))
(clobber (reg:HI 24))]
diff --git a/gcc/testsuite/gcc.target/avr/pr114975-parity.c 
b/gcc/testsuite/gcc.target/avr/pr114975-parity.c
new file mode 100644
index ..767ced0a464d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/pr114975-parity.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-Os" } */
+
+typedef __UINT8_TYPE__ uint8_t;
+
+uint8_t use_pary1 (int y, uint8_t x)
+{
+return 1 + __builtin_parity (x);
+}
+
+uint8_t use_pary2 (uint8_t x)
+{
+   x += 1;
+return 1 - __builtin_parity (x);
+}
+
+/* { dg-final { scan-assembler-times "__parityqi2" 2 } } */

[gcc r14-10186] AVR: target/114981 - Support __builtin_powi[l] / __powidf2.

[Georg-Johann Lay via Gcc-cvs]

https://gcc.gnu.org/g:a9e313ed38775b3ffee650d5396419ce3e6ea389

commit r14-10186-ga9e313ed38775b3ffee650d5396419ce3e6ea389
Author: Georg-Johann Lay 
Date:   Wed May 8 17:56:05 2024 +0200

AVR: target/114981 - Support __builtin_powi[l] / __powidf2.

This supports __powidf2 by means of a double wrapper for already
existing f7_powi (renamed to __f7_powi by f7-renames.h).
It tweaks the implementation so that it does not perform trivial
multiplications with 1.0 any more, but instead uses a move.
It also fixes the last statement of f7_powi, which was wrong.
Notice that f7_powi was unused until now.

PR target/114981
libgcc/config/avr/libf7/
* libf7-common.mk (F7_ASM_PARTS): Add D_powi
* libf7-asm.sx (F7MOD_D_powi_, __powidf2): New module and function.
* libf7.c (f7_powi): Fix last (wrong) statement.
Tweak trivial multiplications with 1.0.

gcc/testsuite/
* gcc.target/avr/pr114981-powil.c: New test.

(cherry picked from commit de4eea7d7ea86e54843507c68d6672eca9d8c7bb)

Diff:
---
 gcc/testsuite/gcc.target/avr/pr114981-powil.c | 33 +++
 libgcc/config/avr/libf7/libf7-asm.sx  | 12 ++
 libgcc/config/avr/libf7/libf7-common.mk   |  2 +-
 libgcc/config/avr/libf7/libf7.c   | 29 +--
 4 files changed, 68 insertions(+), 8 deletions(-)

diff --git a/gcc/testsuite/gcc.target/avr/pr114981-powil.c 
b/gcc/testsuite/gcc.target/avr/pr114981-powil.c
new file mode 100644
index ..70f8e796c654
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/pr114981-powil.c
@@ -0,0 +1,33 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-Os" } */
+
+const long double vals[] =
+  {
+0.0625L, -0.125L, 0.25L, -0.5L,
+1.0L,
+-2.0L, 4.0L, -8.0L, 16.0L
+  };
+
+#define ARRAY_SIZE(X) ((int) (sizeof(X) / sizeof(*X)))
+
+__attribute__((noinline,noclone))
+void test1 (long double x)
+{
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (vals); ++i)
+{
+  long double val0 = vals[i];
+  long double val1 = __builtin_powil (x, i - 4);
+  __asm ("" : "+r" (val0));
+
+  if (val0 != val1)
+   __builtin_exit (__LINE__);
+}
+}
+
+int main (void)
+{
+  test1 (-2.0L);
+  return 0;
+}
diff --git a/libgcc/config/avr/libf7/libf7-asm.sx 
b/libgcc/config/avr/libf7/libf7-asm.sx
index 1ab91270cb2b..1f8f60ab2826 100644
--- a/libgcc/config/avr/libf7/libf7-asm.sx
+++ b/libgcc/config/avr/libf7/libf7-asm.sx
@@ -1877,4 +1877,16 @@ ENDF call_ddd
 
 #include "f7-wraps.h"
 
+;;; Some additional, singular wraps that don't match any pattern.
+
+;; double __powidf2 (double, int)  ; __builtin_powi
+#ifdef F7MOD_D_powi_
+_DEFUN __powidf2
+.global F7_NAME(powi)
+ldi ZH, hi8(gs(F7_NAME(powi)))
+ldi ZL, lo8(gs(F7_NAME(powi)))
+F7jmp   call_ddx
+_ENDF __powidf2
+#endif /* F7MOD_D_powi_ */
+
 #endif /* !AVR_TINY */
diff --git a/libgcc/config/avr/libf7/libf7-common.mk 
b/libgcc/config/avr/libf7/libf7-common.mk
index d541b48ff3ca..5d411071c8e4 100644
--- a/libgcc/config/avr/libf7/libf7-common.mk
+++ b/libgcc/config/avr/libf7/libf7-common.mk
@@ -22,7 +22,7 @@ F7_ASM_PARTS += addsub_mant_scaled store load
 F7_ASM_PARTS += to_integer to_unsigned clz normalize_with_carry normalize
 F7_ASM_PARTS += store_expo sqrt16 sqrt_approx div
 
-F7_ASM_PARTS += D_class D_fma
+F7_ASM_PARTS += D_class D_fma D_powi
 F7_ASM_PARTS += D_isnan D_isinf D_isfinite D_signbit D_copysign D_neg D_fabs
 
 F7_ASM_PARTS += call_dd call_ddd
diff --git a/libgcc/config/avr/libf7/libf7.c b/libgcc/config/avr/libf7/libf7.c
index 369dbe241039..375becb854c1 100644
--- a/libgcc/config/avr/libf7/libf7.c
+++ b/libgcc/config/avr/libf7/libf7.c
@@ -1752,20 +1752,33 @@ void f7_powi (f7_t *cc, const f7_t *aa, int ii)
 {
   uint16_t u16 = ii;
   f7_t xx27, *xx2 = 
+  bool cc_is_one = true;
+  bool expo_is_neg = false;
 
   if (ii < 0)
-u16 = -u16;
+{
+  u16 = -u16;
+  expo_is_neg = true;
+}
 
   f7_copy (xx2, aa);
 
-  f7_set_u16 (cc, 1);
-
   while (1)
 {
   if (u16 & 1)
-   f7_Imul (cc, xx2);
+   {
+ if (cc_is_one)
+   {
+ // C *= X2 simplifies to C = X2.
+ f7_copy (cc, xx2);
+ cc_is_one = false;
+   }
+ else
+   f7_Imul (cc, xx2);
+   }
 
-  if (! f7_is_nonzero (cc))
+  if (! cc_is_one
+ && ! f7_is_nonzero (cc))
break;
 
   u16 >>= 1;
@@ -1774,8 +1787,10 @@ void f7_powi (f7_t *cc, const f7_t *aa, int ii)
   f7_Isquare (xx2);
 }
 
-  if (ii < 0)
-f7_div1 (xx2, aa);
+  if (cc_is_one)
+f7_set_u16 (cc, 1);
+  else if (expo_is_neg)
+f7_div1 (cc, cc);
 }
 #endif // F7MOD_powi_

[gcc r13-8736] AVR: target/114981 - Support __builtin_powi[l] / __powidf2.

[Georg-Johann Lay via Gcc-cvs]

https://gcc.gnu.org/g:adba85bb63a45d7d668501c11bdf9772cc00b7b8

commit r13-8736-gadba85bb63a45d7d668501c11bdf9772cc00b7b8
Author: Georg-Johann Lay 
Date:   Wed May 8 17:56:05 2024 +0200

AVR: target/114981 - Support __builtin_powi[l] / __powidf2.

This supports __powidf2 by means of a double wrapper for already
existing f7_powi (renamed to __f7_powi by f7-renames.h).
It tweaks the implementation so that it does not perform trivial
multiplications with 1.0 any more, but instead uses a move.
It also fixes the last statement of f7_powi, which was wrong.
Notice that f7_powi was unused until now.

PR target/114981
libgcc/config/avr/libf7/
* libf7-common.mk (F7_ASM_PARTS): Add D_powi
* libf7-asm.sx (F7MOD_D_powi_, __powidf2): New module and function.
* libf7.c (f7_powi): Fix last (wrong) statement.
Tweak trivial multiplications with 1.0.

gcc/testsuite/
* gcc.target/avr/pr114981-powil.c: New test.

(cherry picked from commit de4eea7d7ea86e54843507c68d6672eca9d8c7bb)

Diff:
---
 gcc/testsuite/gcc.target/avr/pr114981-powil.c | 33 +++
 libgcc/config/avr/libf7/libf7-asm.sx  | 12 ++
 libgcc/config/avr/libf7/libf7-common.mk   |  2 +-
 libgcc/config/avr/libf7/libf7.c   | 29 +--
 4 files changed, 68 insertions(+), 8 deletions(-)

diff --git a/gcc/testsuite/gcc.target/avr/pr114981-powil.c 
b/gcc/testsuite/gcc.target/avr/pr114981-powil.c
new file mode 100644
index ..70f8e796c654
--- /dev/null
+++ b/gcc/testsuite/gcc.target/avr/pr114981-powil.c
@@ -0,0 +1,33 @@
+/* { dg-do run { target { ! avr_tiny } } } */
+/* { dg-additional-options "-Os" } */
+
+const long double vals[] =
+  {
+0.0625L, -0.125L, 0.25L, -0.5L,
+1.0L,
+-2.0L, 4.0L, -8.0L, 16.0L
+  };
+
+#define ARRAY_SIZE(X) ((int) (sizeof(X) / sizeof(*X)))
+
+__attribute__((noinline,noclone))
+void test1 (long double x)
+{
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (vals); ++i)
+{
+  long double val0 = vals[i];
+  long double val1 = __builtin_powil (x, i - 4);
+  __asm ("" : "+r" (val0));
+
+  if (val0 != val1)
+   __builtin_exit (__LINE__);
+}
+}
+
+int main (void)
+{
+  test1 (-2.0L);
+  return 0;
+}
diff --git a/libgcc/config/avr/libf7/libf7-asm.sx 
b/libgcc/config/avr/libf7/libf7-asm.sx
index b00f75994964..df315d35c73e 100644
--- a/libgcc/config/avr/libf7/libf7-asm.sx
+++ b/libgcc/config/avr/libf7/libf7-asm.sx
@@ -1877,4 +1877,16 @@ ENDF call_ddd
 
 #include "f7-wraps.h"
 
+;;; Some additional, singular wraps that don't match any pattern.
+
+;; double __powidf2 (double, int)  ; __builtin_powi
+#ifdef F7MOD_D_powi_
+_DEFUN __powidf2
+.global F7_NAME(powi)
+ldi ZH, hi8(gs(F7_NAME(powi)))
+ldi ZL, lo8(gs(F7_NAME(powi)))
+F7jmp   call_ddx
+_ENDF __powidf2
+#endif /* F7MOD_D_powi_ */
+
 #endif /* !AVR_TINY */
diff --git a/libgcc/config/avr/libf7/libf7-common.mk 
b/libgcc/config/avr/libf7/libf7-common.mk
index d541b48ff3ca..5d411071c8e4 100644
--- a/libgcc/config/avr/libf7/libf7-common.mk
+++ b/libgcc/config/avr/libf7/libf7-common.mk
@@ -22,7 +22,7 @@ F7_ASM_PARTS += addsub_mant_scaled store load
 F7_ASM_PARTS += to_integer to_unsigned clz normalize_with_carry normalize
 F7_ASM_PARTS += store_expo sqrt16 sqrt_approx div
 
-F7_ASM_PARTS += D_class D_fma
+F7_ASM_PARTS += D_class D_fma D_powi
 F7_ASM_PARTS += D_isnan D_isinf D_isfinite D_signbit D_copysign D_neg D_fabs
 
 F7_ASM_PARTS += call_dd call_ddd
diff --git a/libgcc/config/avr/libf7/libf7.c b/libgcc/config/avr/libf7/libf7.c
index fd7059d6c65a..a769f311d958 100644
--- a/libgcc/config/avr/libf7/libf7.c
+++ b/libgcc/config/avr/libf7/libf7.c
@@ -1749,20 +1749,33 @@ void f7_powi (f7_t *cc, const f7_t *aa, int ii)
 {
   uint16_t u16 = ii;
   f7_t xx27, *xx2 = 
+  bool cc_is_one = true;
+  bool expo_is_neg = false;
 
   if (ii < 0)
-u16 = -u16;
+{
+  u16 = -u16;
+  expo_is_neg = true;
+}
 
   f7_copy (xx2, aa);
 
-  f7_set_u16 (cc, 1);
-
   while (1)
 {
   if (u16 & 1)
-   f7_Imul (cc, xx2);
+   {
+ if (cc_is_one)
+   {
+ // C *= X2 simplifies to C = X2.
+ f7_copy (cc, xx2);
+ cc_is_one = false;
+   }
+ else
+   f7_Imul (cc, xx2);
+   }
 
-  if (! f7_is_nonzero (cc))
+  if (! cc_is_one
+ && ! f7_is_nonzero (cc))
break;
 
   u16 >>= 1;
@@ -1771,8 +1784,10 @@ void f7_powi (f7_t *cc, const f7_t *aa, int ii)
   f7_Isquare (xx2);
 }
 
-  if (ii < 0)
-f7_div1 (xx2, aa);
+  if (cc_is_one)
+f7_set_u16 (cc, 1);
+  else if (expo_is_neg)
+f7_div1 (cc, cc);
 }
 #endif // F7MOD_powi_

[gcc r15-339] MIPS: Support constraint 'w' for MSA instruction

[YunQiang Su via Gcc-cvs]

https://gcc.gnu.org/g:9ba01240864ac446052d97692e2199539b7c76d8

commit r15-339-g9ba01240864ac446052d97692e2199539b7c76d8
Author: YunQiang Su 
Date:   Wed May 8 19:04:33 2024 +0800

MIPS: Support constraint 'w' for MSA instruction

Support syntax like:
asm volatile ("fmadd.d %w0, %w1, %w2" : "+w"(a): "w"(b), "w"(c));

gcc
* config/mips/constraints.md: Add new constraint 'w'.

gcc/testsuite
* gcc.target/mips/msa-inline-asm.c: New test.

Diff:
---
 gcc/config/mips/constraints.md | 3 +++
 gcc/testsuite/gcc.target/mips/msa-inline-asm.c | 9 +
 2 files changed, 12 insertions(+)

diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md
index a96028dd7460..f5c881790382 100644
--- a/gcc/config/mips/constraints.md
+++ b/gcc/config/mips/constraints.md
@@ -29,6 +29,9 @@
 (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
   "A floating-point register (if available).")
 
+(define_register_constraint "w" "ISA_HAS_MSA ? FP_REGS : NO_REGS"
+  "A MIPS SIMD register (if available).")
+
 (define_register_constraint "h" "NO_REGS"
   "Formerly the @code{hi} register.  This constraint is no longer supported.")
 
diff --git a/gcc/testsuite/gcc.target/mips/msa-inline-asm.c 
b/gcc/testsuite/gcc.target/mips/msa-inline-asm.c
new file mode 100644
index ..bdf6816ab3b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/msa-inline-asm.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa" } */
+
+double
+f(double a, double b, double c) {
+  asm volatile ("fmadd.d %w0, %w1, %w2" : "+w"(a): "w"(b), "w"(c));
+  return a;
+}
+/* { dg-final { scan-assembler "fmadd.d \\\$w0, \\\$w\[0-9\]*, \\\$w\[0-9\]*" 
} }  */

[gcc r15-338] RISC-V: Add tests for cpymemsi expansion

[Christoph Mﾃｼllner via Gcc-cvs]

https://gcc.gnu.org/g:4d38e88227ea48e559a2f354c0e62d372e181b82

commit r15-338-g4d38e88227ea48e559a2f354c0e62d372e181b82
Author: Christoph Müllner 
Date:   Thu Apr 11 12:07:10 2024 +0200

RISC-V: Add tests for cpymemsi expansion

cpymemsi expansion was available for RISC-V since the initial port.
However, there are not tests to detect regression.
This patch adds such tests.

Three of the tests target the expansion requirements (known length and
alignment). One test reuses an existing memcpy test from the by-pieces
framework (gcc/testsuite/gcc.dg/torture/inline-mem-cpy-1.c).

gcc/testsuite/ChangeLog:

* gcc.target/riscv/cpymemsi-1.c: New test.
* gcc.target/riscv/cpymemsi-2.c: New test.
* gcc.target/riscv/cpymemsi-3.c: New test.
* gcc.target/riscv/cpymemsi.c: New test.

Signed-off-by: Christoph Müllner 

Diff:
---
 gcc/testsuite/gcc.target/riscv/cpymemsi-1.c |  9 ++
 gcc/testsuite/gcc.target/riscv/cpymemsi-2.c | 42 
 gcc/testsuite/gcc.target/riscv/cpymemsi-3.c | 43 +
 gcc/testsuite/gcc.target/riscv/cpymemsi.c   | 22 +++
 4 files changed, 116 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c 
b/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
new file mode 100644
index ..983b564ccaf7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-march=rv32gc -save-temps -g0 -fno-lto" { target { rv32 } } } 
*/
+/* { dg-options "-march=rv64gc -save-temps -g0 -fno-lto" { target { rv64 } } } 
*/
+/* { dg-additional-options "-DRUN_FRACTION=11" { target simulator } } */
+/* { dg-timeout-factor 2 } */
+
+#include "../../gcc.dg/memcmp-1.c"
+/* Yeah, this memcmp test exercises plenty of memcpy, more than any of the
+   memcpy tests.  */
diff --git a/gcc/testsuite/gcc.target/riscv/cpymemsi-2.c 
b/gcc/testsuite/gcc.target/riscv/cpymemsi-2.c
new file mode 100644
index ..833d1c044876
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpymemsi-2.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" "-Oz" } } */
+
+#include 
+#define aligned32 __attribute__ ((aligned (32)))
+
+const char myconst15[] aligned32 = { 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7 };
+const char myconst23[] aligned32 = { 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7 };
+const char myconst31[] aligned32 = { 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7 };
+
+/* No expansion (unknown alignment) */
+#define MY_MEM_CPY_N(N)\
+void my_mem_cpy_##N (char *b1, const char *b2) \
+{  \
+  __builtin_memcpy (b1, b2, N);\
+}
+
+/* No expansion (unknown alignment) */
+#define MY_MEM_CPY_CONST_N(N)  \
+void my_mem_cpy_const_##N (char *b1)   \
+{  \
+  __builtin_memcpy (b1, myconst##N, sizeof(myconst##N));\
+}
+
+MY_MEM_CPY_N(15)
+MY_MEM_CPY_CONST_N(15)
+
+MY_MEM_CPY_N(23)
+MY_MEM_CPY_CONST_N(23)
+
+MY_MEM_CPY_N(31)
+MY_MEM_CPY_CONST_N(31)
+
+/* { dg-final { scan-assembler-times "\t(call|tail)\tmemcpy" 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cpymemsi-3.c 
b/gcc/testsuite/gcc.target/riscv/cpymemsi-3.c
new file mode 100644
index ..803765195b24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/cpymemsi-3.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" "-Oz" } } */
+
+#include 
+#define aligned32 __attribute__ ((aligned (32)))
+
+const char myconst15[] aligned32 = { 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7 };
+const char myconst23[] aligned32 = { 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7 };
+const char myconst31[] aligned32 = { 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7,
+0, 1, 2, 3, 4, 5, 6, 7 };
+
+#define MY_MEM_CPY_ALIGNED_N(N)\
+void my_mem_cpy_aligned_##N(char *b1, const char *b2)  \
+{  \
+  b1 = 

[gcc r15-337] i386: Fix some intrinsics without alignment requirements.

[Hu via Gcc-cvs]

https://gcc.gnu.org/g:5967696c0f6300da4387fea5d102be5bc9f23233

commit r15-337-g5967696c0f6300da4387fea5d102be5bc9f23233
Author: Hu, Lin1 
Date:   Fri Jan 19 15:22:10 2024 +0800

i386: Fix some intrinsics without alignment requirements.

gcc/ChangeLog:

PR target/84508
* config/i386/emmintrin.h
(_mm_load_sd): Remove alignment requirement.
(_mm_store_sd): Ditto.
(_mm_loadh_pd): Ditto.
(_mm_loadl_pd): Ditto.
(_mm_storel_pd): Add alignment requirement.
* config/i386/xmmintrin.h
(_mm_loadh_pi): Remove alignment requirement.
(_mm_loadl_pi): Ditto.
(_mm_load_ss): Ditto.
(_mm_store_ss): Ditto.

gcc/testsuite/ChangeLog:

PR target/84508
* gcc.target/i386/pr84508-1.c: New test.
* gcc.target/i386/pr84508-2.c: Ditto.

Diff:
---
 gcc/config/i386/emmintrin.h   | 11 ++-
 gcc/config/i386/xmmintrin.h   |  9 +
 gcc/testsuite/gcc.target/i386/pr84508-1.c | 11 +++
 gcc/testsuite/gcc.target/i386/pr84508-2.c | 11 +++
 4 files changed, 33 insertions(+), 9 deletions(-)

diff --git a/gcc/config/i386/emmintrin.h b/gcc/config/i386/emmintrin.h
index 915a5234c38c..fa301103daf8 100644
--- a/gcc/config/i386/emmintrin.h
+++ b/gcc/config/i386/emmintrin.h
@@ -56,6 +56,7 @@ typedef double __m128d __attribute__ ((__vector_size__ (16), 
__may_alias__));
 /* Unaligned version of the same types.  */
 typedef long long __m128i_u __attribute__ ((__vector_size__ (16), 
__may_alias__, __aligned__ (1)));
 typedef double __m128d_u __attribute__ ((__vector_size__ (16), __may_alias__, 
__aligned__ (1)));
+typedef double double_u __attribute__ ((__may_alias__, __aligned__ (1)));
 
 /* Create a selector for use with the SHUFPD instruction.  */
 #define _MM_SHUFFLE2(fp1,fp0) \
@@ -145,7 +146,7 @@ _mm_load1_pd (double const *__P)
 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
 _mm_load_sd (double const *__P)
 {
-  return _mm_set_sd (*__P);
+  return __extension__ (__m128d) { *(double_u *)__P, 0.0 };
 }
 
 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
@@ -180,7 +181,7 @@ _mm_storeu_pd (double *__P, __m128d __A)
 extern __inline void __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
 _mm_store_sd (double *__P, __m128d __A)
 {
-  *__P = ((__v2df)__A)[0];
+  *(double_u *)__P = ((__v2df)__A)[0] ;
 }
 
 extern __inline double __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
@@ -192,7 +193,7 @@ _mm_cvtsd_f64 (__m128d __A)
 extern __inline void __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
 _mm_storel_pd (double *__P, __m128d __A)
 {
-  _mm_store_sd (__P, __A);
+  *__P = ((__v2df)__A)[0];
 }
 
 /* Stores the upper DPFP value.  */
@@ -973,13 +974,13 @@ _mm_unpacklo_pd (__m128d __A, __m128d __B)
 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
 _mm_loadh_pd (__m128d __A, double const *__B)
 {
-  return (__m128d)__builtin_ia32_loadhpd ((__v2df)__A, __B);
+  return __extension__ (__m128d) { ((__v2df)__A)[0], *(double_u*)__B };
 }
 
 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
 _mm_loadl_pd (__m128d __A, double const *__B)
 {
-  return (__m128d)__builtin_ia32_loadlpd ((__v2df)__A, __B);
+  return __extension__ (__m128d) { *(double_u*)__B, ((__v2df)__A)[1] };
 }
 
 extern __inline int __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
diff --git a/gcc/config/i386/xmmintrin.h b/gcc/config/i386/xmmintrin.h
index 71b9955b8438..9e20f262839b 100644
--- a/gcc/config/i386/xmmintrin.h
+++ b/gcc/config/i386/xmmintrin.h
@@ -73,6 +73,7 @@ typedef float __m128 __attribute__ ((__vector_size__ (16), 
__may_alias__));
 
 /* Unaligned version of the same type.  */
 typedef float __m128_u __attribute__ ((__vector_size__ (16), __may_alias__, 
__aligned__ (1)));
+typedef float float_u __attribute__ ((__may_alias__, __aligned__ (1)));
 
 /* Internal data types for implementing the intrinsics.  */
 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
@@ -774,7 +775,7 @@ _mm_unpacklo_ps (__m128 __A, __m128 __B)
 /* Sets the upper two SPFP values with 64-bits of data loaded from P;
the lower two values are passed through from A.  */
 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, 
__artificial__))
-_mm_loadh_pi (__m128 __A, __m64 const *__P)
+_mm_loadh_pi (__m128 __A, __m64_u const *__P)
 {
   return (__m128) __builtin_ia32_loadhps ((__v4sf)__A, (const __v2sf *)__P);
 }
@@ -803,7 +804,7 @@ _mm_movelh_ps (__m128 __A, __m128 __B)
 /* Sets the lower two SPFP values with 64-bits of data loaded from P;
the upper two values are passed through from A.  */
 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, 

[gcc r11-11422] Fix PR 110386: backprop vs ABSU_EXPR

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:dbfc2d075f10149bd94e16c1210ffe4bac7e60c3

commit r11-11422-gdbfc2d075f10149bd94e16c1210ffe4bac7e60c3
Author: Andrew Pinski 
Date:   Sat Sep 23 21:53:09 2023 -0700

Fix PR 110386: backprop vs ABSU_EXPR

The issue here is that when backprop tries to go
and strip sign ops, it skips over ABSU_EXPR but
ABSU_EXPR not only does an ABS, it also changes the
type to unsigned.
Since strip_sign_op_1 is only supposed to strip off
sign changing operands and not ones that change types,
removing ABSU_EXPR here is correct. We don't handle
nop conversions so this does cause any missed optimizations either.

OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.

PR tree-optimization/110386

gcc/ChangeLog:

* gimple-ssa-backprop.c (strip_sign_op_1): Remove ABSU_EXPR.

gcc/testsuite/ChangeLog:

* gcc.c-torture/compile/pr110386-1.c: New test.
* gcc.c-torture/compile/pr110386-2.c: New test.

(cherry picked from commit 2bbac12ea7bd8a3eef5382e1b13f6019df4ec03f)

Diff:
---
 gcc/gimple-ssa-backprop.c|  1 -
 gcc/testsuite/gcc.c-torture/compile/pr110386-1.c |  9 +
 gcc/testsuite/gcc.c-torture/compile/pr110386-2.c | 11 +++
 3 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/gcc/gimple-ssa-backprop.c b/gcc/gimple-ssa-backprop.c
index 4b62bb92a21d..8c0a37e6e97d 100644
--- a/gcc/gimple-ssa-backprop.c
+++ b/gcc/gimple-ssa-backprop.c
@@ -688,7 +688,6 @@ strip_sign_op_1 (tree rhs)
 switch (gimple_assign_rhs_code (assign))
   {
   case ABS_EXPR:
-  case ABSU_EXPR:
   case NEGATE_EXPR:
return gimple_assign_rhs1 (assign);
 
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr110386-1.c 
b/gcc/testsuite/gcc.c-torture/compile/pr110386-1.c
new file mode 100644
index ..4fcc977ad16f
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr110386-1.c
@@ -0,0 +1,9 @@
+
+int f(int a)
+{
+int c = c < 0 ? c : -c;
+c = -c;
+unsigned b =  c;
+unsigned t = b*a;
+return t*t;
+}
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr110386-2.c 
b/gcc/testsuite/gcc.c-torture/compile/pr110386-2.c
new file mode 100644
index ..c60e1b6994b7
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr110386-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-mavx" } */
+
+#include 
+
+__m128i do_stuff(__m128i XMM0) {
+   __m128i ABS0 = _mm_abs_epi32(XMM0);
+   __m128i MUL0 = _mm_mullo_epi32(ABS0, XMM0);
+   __m128i MUL1 = _mm_mullo_epi32(MUL0, MUL0);
+   return MUL1;
+}

[gcc r12-10434] Fix PR 110386: backprop vs ABSU_EXPR

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:f5c7306d7f039e5c74c5e82cf06610f0ae07a0e8

commit r12-10434-gf5c7306d7f039e5c74c5e82cf06610f0ae07a0e8
Author: Andrew Pinski 
Date:   Sat Sep 23 21:53:09 2023 -0700

Fix PR 110386: backprop vs ABSU_EXPR

The issue here is that when backprop tries to go
and strip sign ops, it skips over ABSU_EXPR but
ABSU_EXPR not only does an ABS, it also changes the
type to unsigned.
Since strip_sign_op_1 is only supposed to strip off
sign changing operands and not ones that change types,
removing ABSU_EXPR here is correct. We don't handle
nop conversions so this does cause any missed optimizations either.

OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.

PR tree-optimization/110386

gcc/ChangeLog:

* gimple-ssa-backprop.cc (strip_sign_op_1): Remove ABSU_EXPR.

gcc/testsuite/ChangeLog:

* gcc.c-torture/compile/pr110386-1.c: New test.
* gcc.c-torture/compile/pr110386-2.c: New test.

(cherry picked from commit 2bbac12ea7bd8a3eef5382e1b13f6019df4ec03f)

Diff:
---
 gcc/gimple-ssa-backprop.cc   |  1 -
 gcc/testsuite/gcc.c-torture/compile/pr110386-1.c |  9 +
 gcc/testsuite/gcc.c-torture/compile/pr110386-2.c | 11 +++
 3 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/gcc/gimple-ssa-backprop.cc b/gcc/gimple-ssa-backprop.cc
index 74f981112567..68ea403e847f 100644
--- a/gcc/gimple-ssa-backprop.cc
+++ b/gcc/gimple-ssa-backprop.cc
@@ -688,7 +688,6 @@ strip_sign_op_1 (tree rhs)
 switch (gimple_assign_rhs_code (assign))
   {
   case ABS_EXPR:
-  case ABSU_EXPR:
   case NEGATE_EXPR:
return gimple_assign_rhs1 (assign);
 
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr110386-1.c 
b/gcc/testsuite/gcc.c-torture/compile/pr110386-1.c
new file mode 100644
index ..4fcc977ad16f
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr110386-1.c
@@ -0,0 +1,9 @@
+
+int f(int a)
+{
+int c = c < 0 ? c : -c;
+c = -c;
+unsigned b =  c;
+unsigned t = b*a;
+return t*t;
+}
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr110386-2.c 
b/gcc/testsuite/gcc.c-torture/compile/pr110386-2.c
new file mode 100644
index ..c60e1b6994b7
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr110386-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-mavx" } */
+
+#include 
+
+__m128i do_stuff(__m128i XMM0) {
+   __m128i ABS0 = _mm_abs_epi32(XMM0);
+   __m128i MUL0 = _mm_mullo_epi32(ABS0, XMM0);
+   __m128i MUL1 = _mm_mullo_epi32(MUL0, MUL0);
+   return MUL1;
+}

gcc-wwwdocs branch master updated. 40cca6168d9bb98450b213de6126b536d244f490

[Gerald Pfeifer via Gcc-cvs-wwwdocs]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "gcc-wwwdocs".

The branch, master has been updated
   via  40cca6168d9bb98450b213de6126b536d244f490 (commit)
  from  b0f7297602476b09073d13d12782d817a0115367 (commit)

Those revisions listed above that are new to this repository have
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- Log -
commit 40cca6168d9bb98450b213de6126b536d244f490
Author: Gerald Pfeifer 
Date:   Thu May 9 08:23:46 2024 +0200

gcc-9: Various editorial changes

diff --git a/htdocs/gcc-9/changes.html b/htdocs/gcc-9/changes.html
index 89c20985..47d2f2a2 100644
--- a/htdocs/gcc-9/changes.html
+++ b/htdocs/gcc-9/changes.html
@@ -221,7 +221,7 @@ v.c:10:7: missed: statement clobbers memory: __asm__ 
__volatile__( :
   
   Inter-procedural propagation of stack alignment can now be controlled by
   https://gcc.gnu.org/onlinedocs/gcc-9.1.0/gcc/Optimize-Options.html#index-fipa-stack-alignment;>-fipa-stack-alignment.
-  Propagation of addressability, readonly and writeonly flags on
+  Propagation of addressability, readonly, and writeonly flags on
   static variables can now be controlled by
   https://gcc.gnu.org/onlinedocs/gcc-9.1.0/gcc/Optimize-Options.html#index-fipa-reference-addressable;>-fipa-reference-addressable.
 
@@ -277,8 +277,8 @@ foo (int how)
   
 Inter-procedural optimization improvements:
   
-   Inliner defaults was tuned to better suits modern C++ codebases
-   especially when built with link time optimizations.
+   Inliner defaults were tuned to better suit modern C++ codebases,
+   especially when built with link time-optimizations.
New parameters max-inline-insns-small,
max-inline-insns-size,
uninlined-function-insns,
@@ -295,27 +295,27 @@ foo (int how)
https://gcc.gnu.org/onlinedocs/gcc-9.1.0/gcc/Optimize-Options.html#index-floop-interchange;>-floop-interchange,
https://gcc.gnu.org/onlinedocs/gcc-9.1.0/gcc/Optimize-Options.html#index-floop-unroll-and-jam;>-floop-unroll-and-jam,
https://gcc.gnu.org/onlinedocs/gcc-9.1.0/gcc/Optimize-Options.html#index-ftree-loop-distribution;>-ftree-loop-distribution.
-Streaming of counter histograms was removed.  This reduces
-   the size of profile files.  Histogram is computed on the fly
-   with link-time optimization.
-Parameter hot-bb-count-ws-permille was reduced
+Streaming of counter histograms was removed, which reduces
+   the size of profile files. Histograms are computed on the fly
+   with link-time optimization.
+The parameter hot-bb-count-ws-permille was reduced
 from 999 to 990 to account for more precise histograms.
   
 Link-time optimization improvements:
   
-Types are now simplified prior streaming resulting in significant
-   reductions of the LTO object files, link-time memory use, and
-   improvements of link-time parallelism.
-Default number of partitions (--param lto-partitions) was
+Types are now simplified prior to streaming resulting in significant
+   reductions of LTO object file sizes and link-time memory use as well
+   as improvements of link-time parallelism.
+The default number of partitions (--param lto-partitions) 
was
increased from 32 to 128 enabling effective use of CPUs with more than
32 hyperthreads. --param lto-max-streaming-parallelism
-   can now be used to control number of streaming processes.
+   can now be used to control the number of streaming processes.
 Warnings on C++ One Decl Rule violations (-Wodr) are
now more informative and produce fewer redundant results.
   
   Overall compile time of Firefox 66 and LibreOffice 6.2.3 on an 8-core
   machine was reduced by about 5% compared to GCC 8.3, and the size of
-  LTO object files by 7%.  LTO link-time improves by 11% on an 8-core
+  LTO object files by 7%.  LTO link time improves by 11% on an 8-core
   machine and scales significantly better for more parallel build
   environments.  The serial stage of
   the link-time optimization is 28% faster consuming 20% less memory.
@@ -1039,7 +1039,7 @@ $ g++ typo.cc
 which provide the __fentry__ symbol and do not
 clobber r0 when resolving lazily bound functions.
 
--mfentry is only supported when generating 64 bit
+-mfentry is only supported when generating 64-bit
 code and does not work with nested C functions.
 
   The -mnop-mcount option can be used to emit NOP

---

Summary of changes:
 htdocs/gcc-9/changes.html | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)


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gcc-wwwdocs branch master updated. b0f7297602476b09073d13d12782d817a0115367

[Gerald Pfeifer via Gcc-cvs-wwwdocs]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "gcc-wwwdocs".

The branch, master has been updated
   via  b0f7297602476b09073d13d12782d817a0115367 (commit)
  from  10f71cf2e68da0589c15d52adf1177feb959861b (commit)

Those revisions listed above that are new to this repository have
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- Log -
commit b0f7297602476b09073d13d12782d817a0115367
Author: Gerald Pfeifer 
Date:   Thu May 9 08:16:57 2024 +0200

gcc-11: Use 64-bit instead of 64 bit

diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.html
index a00637c6..b4ecf3c0 100644
--- a/htdocs/gcc-11/changes.html
+++ b/htdocs/gcc-11/changes.html
@@ -1001,8 +1001,8 @@ You may also want to check out our
 
 AIX
 
-  GCC for AIX can be built as a 64 bit application and the runtime
-is built as FAT libraries containing both 32 bit and 64 bit objects.
+  GCC for AIX can be built as a 64-bit application and the runtime
+is built as FAT libraries containing both 32-bit and 64-bit objects.
   Support AIX Vector Extended ABI with -mabi=vec-extabi.
   Thread-Local uninitiated data placed in local common section.
   Use thread-safe access in ctype.

---

Summary of changes:
 htdocs/gcc-11/changes.html | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


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