[gcc r15-1393] rs6000: Shrink rs6000_init_generated_builtins size [PR115324]
https://gcc.gnu.org/g:e17114f99c9ea754787573679b3b4d2b52434b61
commit r15-1393-ge17114f99c9ea754787573679b3b4d2b52434b61
Author: Jakub Jelinek
Date: Tue Jun 18 08:32:37 2024 +0200
rs6000: Shrink rs6000_init_generated_builtins size [PR115324]
While my r15-1001-g4cf2de9b5268224 PCH PIE power fix change decreased the
.data section sizes (219792 -> 189336), it increased the size of already
huge rs6000_init_generated_builtins generated function, from 218328
to 228668 bytes. That is because there are thousands of array references
to global arrays and we keep constructing the addresses of the arrays
again and again.
Ideally some optimization would figure out we have a single function which
has
461 rs6000_overload_info
1257 rs6000_builtin_info_fntype
1768 rs6000_builtin_decls
2548 rs6000_instance_info_fntype
array references and that maybe it might be a good idea to just preload
the addresses of those arrays into some register if it decreases code size
and doesn't slow things down.
The function actually is called just once and is huge, so code size is even
more important than speed, which is dominated by all the GC allocations
anyway.
Until that is done, here is a slightly cleaner version of the hack, which
makes the function noipa (so that LTO doesn't undo it) for GCC 8.1+ and
passes the 4 arrays as arguments to the function from the caller.
This decreases the function size from 228668 bytes to 207572 bytes.
2024-06-18 Jakub Jelinek
PR target/115324
* config/rs6000/rs6000-gen-builtins.cc (write_decls): Change
declaration of rs6000_init_generated_builtins from no arguments
to 4 pointer arguments.
(write_init_bif_table): Change rs6000_builtin_info_fntype to
builtin_info_fntype and rs6000_builtin_decls to builtin_decls.
(write_init_ovld_table): Change rs6000_instance_info_fntype to
instance_info_fntype, rs6000_builtin_decls to builtin_decls and
rs6000_overload_info to overload_info.
(write_init_file): Add __noipa__ attribute to
rs6000_init_generated_builtins for GCC 8.1+ and change the function
from no arguments to 4 pointer arguments. Change
rs6000_builtin_decls
to builtin_decls.
* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Adjust
rs6000_init_generated_builtins caller.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 5 -
gcc/config/rs6000/rs6000-gen-builtins.cc | 36 ++--
2 files changed, 29 insertions(+), 12 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index e96d5157e4dd..bb9da68edc73 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -835,7 +835,10 @@ rs6000_init_builtins (void)
TYPE_QUAL_CONST));
/* Execute the autogenerated initialization code for builtins. */
- rs6000_init_generated_builtins ();
+ rs6000_init_generated_builtins (rs6000_builtin_info_fntype,
+ rs6000_instance_info_fntype,
+ rs6000_overload_info,
+ rs6000_builtin_decls);
if (TARGET_DEBUG_BUILTIN)
{
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc
b/gcc/config/rs6000/rs6000-gen-builtins.cc
index 7ae932220bb8..9af92cc5185d 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.cc
+++ b/gcc/config/rs6000/rs6000-gen-builtins.cc
@@ -2376,7 +2376,10 @@ write_decls (void)
"rs6000_instance_info_fntype[RS6000_INST_MAX];\n");
fprintf (header_file, "extern ovldrecord rs6000_overload_info[];\n\n");
- fprintf (header_file, "extern void rs6000_init_generated_builtins ();\n\n");
+ fprintf (header_file,
+ "extern void rs6000_init_generated_builtins (tree *, tree *,\n");
+ fprintf (header_file,
+ "\t\t\t\t\tovldrecord *, tree *);\n\n");
fprintf (header_file,
"extern bool rs6000_builtin_is_supported (rs6000_gen_builtins);\n");
fprintf (header_file,
@@ -2651,7 +2654,7 @@ write_init_bif_table (void)
for (int i = 0; i <= curr_bif; i++)
{
fprintf (init_file,
- " rs6000_builtin_info_fntype[RS6000_BIF_%s]"
+ " builtin_info_fntype[RS6000_BIF_%s]"
"\n= %s;\n",
bifs[i].idname, bifs[i].fndecl);
@@ -2678,7 +2681,7 @@ write_init_bif_table (void)
}
fprintf (init_file,
- " rs6000_builtin_decls[(int)RS6000_BIF_%s] = t\n",
+ " builtin_decls[(int)RS6000_BIF_%s] = t\n",
bifs[i].idname);
fprintf (init_file,
"= add_builtin_function (\"%s\",\n",
@@ -2719,7 +2722,7 @@ write_init_bif_table (void)
fprintf (init_file, "
[gcc r15-1392] tree-optimization/115493 - fix wrong code with SLP induction cond reduction
https://gcc.gnu.org/g:19258ca1b85bc15e3a49054eff209f4f0d1c5bee commit r15-1392-g19258ca1b85bc15e3a49054eff209f4f0d1c5bee Author: Richard Biener Date: Mon Jun 17 16:01:15 2024 +0200 tree-optimization/115493 - fix wrong code with SLP induction cond reduction The following fixes a bad final value being used when doing single-lane SLP integer induction cond reduction vectorization. PR tree-optimization/115493 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the first scalar result. Diff: --- gcc/tree-vect-loop.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc index d9a2ad694843..7c79e9da1060 100644 --- a/gcc/tree-vect-loop.cc +++ b/gcc/tree-vect-loop.cc @@ -6843,8 +6843,8 @@ vect_create_epilog_for_reduction (loop_vec_info loop_vinfo, with the original initial value, unless induc_val is the same as initial_def already. */ tree zcompare = make_ssa_name (boolean_type_node); - epilog_stmt = gimple_build_assign (zcompare, EQ_EXPR, new_temp, -induc_val); + epilog_stmt = gimple_build_assign (zcompare, EQ_EXPR, +scalar_results[0], induc_val); gsi_insert_before (&exit_gsi, epilog_stmt, GSI_SAME_STMT); tree initial_def = reduc_info->reduc_initial_values[0]; tree tmp = make_ssa_name (new_scalar_dest);
[gcc r15-1391] Enhance if-conversion for automatic arrays
https://gcc.gnu.org/g:4b75ed33fa5fd604897e7a30e79bd28d46598373
commit r15-1391-g4b75ed33fa5fd604897e7a30e79bd28d46598373
Author: Richard Biener
Date: Fri Jun 14 14:46:08 2024 +0200
Enhance if-conversion for automatic arrays
Automatic arrays that are not address-taken should not be subject to
store data races. This applies to OMP SIMD in-branch lowered
functions result array which for the testcase otherwise prevents
vectorization with SSE and for AVX and AVX512 ends up with spurious
.MASK_STORE to the stack surviving.
This inefficiency was noted in PR111793.
I've introduced ref_can_have_store_data_races, commonizing uses
of flag_store_data_races in if-conversion, cselim and store motion.
PR tree-optimization/111793
* tree-ssa-alias.h (ref_can_have_store_data_races): Declare.
* tree-ssa-alias.cc (ref_can_have_store_data_races): New
function.
* tree-if-conv.cc (ifcvt_memrefs_wont_trap): Use
ref_can_have_store_data_races to allow more unconditional
stores.
* tree-ssa-loop-im.cc (execute_sm): Likewise.
* tree-ssa-phiopt.cc (cond_store_replacement): Likewise.
* gcc.dg/vect/vect-simd-clone-21.c: New testcase.
Diff:
---
gcc/testsuite/gcc.dg/vect/vect-simd-clone-21.c | 16
gcc/tree-if-conv.cc| 11 +--
gcc/tree-ssa-alias.cc | 19 +++
gcc/tree-ssa-alias.h | 2 ++
gcc/tree-ssa-loop-im.cc| 2 +-
gcc/tree-ssa-phiopt.cc | 4 +---
6 files changed, 44 insertions(+), 10 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-21.c
b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-21.c
new file mode 100644
index ..49c52fb59bd1
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-21.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target vect_simd_clones } */
+/* { dg-additional-options "-fopenmp-simd" } */
+
+#pragma omp declare simd simdlen(4) inbranch
+__attribute__((noinline)) int
+foo (int a, int b)
+{
+ return a + b;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" { target
i?86-*-* x86_64-*-* } } } */
+/* if-conversion shouldn't need to resort to masked stores for the result
+ array created by OMP lowering since that's automatic and does not have
+ its address taken. */
+/* { dg-final { scan-tree-dump-not "MASK_STORE" "vect" } } */
diff --git a/gcc/tree-if-conv.cc b/gcc/tree-if-conv.cc
index c4c3ed41a447..57992b6decaf 100644
--- a/gcc/tree-if-conv.cc
+++ b/gcc/tree-if-conv.cc
@@ -936,12 +936,11 @@ ifcvt_memrefs_wont_trap (gimple *stmt,
vec drs)
/* an unconditionaly write won't trap if the base is written
to unconditionally. */
- if (base_master_dr
- && DR_BASE_W_UNCONDITIONALLY (*base_master_dr))
- return flag_store_data_races;
- /* or the base is known to be not readonly. */
- else if (base_object_writable (DR_REF (a)))
- return flag_store_data_races;
+ if ((base_master_dr
+ && DR_BASE_W_UNCONDITIONALLY (*base_master_dr))
+ /* or the base is known to be not readonly. */
+ || base_object_writable (DR_REF (a)))
+ return !ref_can_have_store_data_races (base);
}
return false;
diff --git a/gcc/tree-ssa-alias.cc b/gcc/tree-ssa-alias.cc
index 1a91d63a31ec..fab048b0b594 100644
--- a/gcc/tree-ssa-alias.cc
+++ b/gcc/tree-ssa-alias.cc
@@ -3704,6 +3704,25 @@ stmt_kills_ref_p (gimple *stmt, tree ref)
return stmt_kills_ref_p (stmt, &r);
}
+/* Return whether REF can be subject to store data races. */
+
+bool
+ref_can_have_store_data_races (tree ref)
+{
+ /* With -fallow-store-data-races do not care about them. */
+ if (flag_store_data_races)
+return false;
+
+ tree base = get_base_address (ref);
+ if (auto_var_p (base)
+ && ! may_be_aliased (base))
+/* Automatic variables not aliased are not subject to
+ data races. */
+return false;
+
+ return true;
+}
+
/* Walk the virtual use-def chain of VUSE until hitting the virtual operand
TARGET or a statement clobbering the memory reference REF in which
diff --git a/gcc/tree-ssa-alias.h b/gcc/tree-ssa-alias.h
index 5cd64e722955..5834533ae9cd 100644
--- a/gcc/tree-ssa-alias.h
+++ b/gcc/tree-ssa-alias.h
@@ -144,6 +144,8 @@ extern bool call_may_clobber_ref_p (gcall *, tree, bool =
true);
extern bool call_may_clobber_ref_p_1 (gcall *, ao_ref *, bool = true);
extern bool stmt_kills_ref_p (gimple *, tree);
extern bool stmt_kills_ref_p (gimple *, ao_ref *);
+extern bool ref_can_have_store_data_races (tree);
+
enum translate_flags
{ TR_TRANSLATE, TR_VALUEIZE_AND_DISAMBIGUATE, TR_DISAMBIGUATE };
extern tree get_continuation_for_phi (gimple *, ao_ref *, bool,
diff --git a/gcc/tree-ssa-loop-im.cc b/gcc/tree-ssa-loo
[gcc(refs/users/meissner/heads/work169-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:265d476e2940759ea23733e5eb57aecc05af495d commit 265d476e2940759ea23733e5eb57aecc05af495d Author: Michael Meissner Date: Tue Jun 18 01:27:43 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 9a2af6e5eaf0..4bd3e28874b9 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,8 +1,8 @@ - Branch work169-bugs, patch #400 + Branch work169-bugs, patch #401 Do not build IEEE 128-bit support for little endian power5. -2024-06-17 Michael Meissner +2024-06-18 Michael Meissner gcc/ @@ -11,9 +11,10 @@ gcc/ libgcc/ - * config.host (powerpc*-linux*): Do not build the IEEE 128-bit support - libraries unless GCC is configured for at least power8 by default. - * configure.ac (powerpc*-linux*): Likewise. + * config.host (powerpc*-linux*): Do not enable ieee 128-bit hardware + support unless ieee 128-bit basic support is provided. + * configure.ac (powerpc*-linux*): Disable building libgcc on legacy + 32-bit little endian systems which will never support VSX. * configure: Regenerate. libgfortran/ @@ -24,6 +25,8 @@ libgfortran/ * kinds-override.h: Do not enable IEEE 128-bit floating point support on little endian PowerPC that does not have VSX support. + Branch work169-bugs, patch #400 was reverted + Branch work169-bugs, patch #11 (work169 branch) Add -mcpu=future tuning support.
[gcc(refs/users/meissner/heads/work169-bugs)] Do not build IEEE 128-bit support for little endian power5.
https://gcc.gnu.org/g:92c13724e59b55c9b1c18082064a6889ac5fc06f
commit 92c13724e59b55c9b1c18082064a6889ac5fc06f
Author: Michael Meissner
Date: Tue Jun 18 01:26:07 2024 -0400
Do not build IEEE 128-bit support for little endian power5.
2024-06-18 Michael Meissner
gcc/
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Do not
allow IEEE 128-bit on little endian 32-bit systems.
libgcc/
* config.host (powerpc*-linux*): Do not enable ieee 128-bit hardware
support unless ieee 128-bit basic support is provided.
* configure.ac (powerpc*-linux*): Disable building libgcc on legacy
32-bit little endian systems which will never support VSX.
* configure: Regenerate.
libgfortran/
* configure.ac (powerpc64le*-linux*): Check to see that the compiler
uses VSX before enabling IEEE 128-bit support.
* configure: Regenerate.
* kinds-override.h: Do not enable IEEE 128-bit floating point
support on
little endian PowerPC that does not have VSX support.
Diff:
---
gcc/config/rs6000/rs6000.cc | 13 -
libgcc/config.host | 14 --
libgcc/configure | 19 +--
libgcc/configure.ac | 19 +--
libgfortran/configure| 7 +--
libgfortran/configure.ac | 3 +++
libgfortran/kinds-override.h | 2 +-
7 files changed, 55 insertions(+), 22 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c5c4191127e4..ea36e651b446 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4146,7 +4146,8 @@ rs6000_option_override_internal (bool global_init_p)
the keyword as well as the type. */
TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
- /* IEEE 128-bit floating point requires VSX support. */
+ /* IEEE 128-bit floating point requires VSX support. Disable IEEE 128-bit on
+ legacy 32-bit LE systems. */
if (TARGET_FLOAT128_KEYWORD)
{
if (!TARGET_VSX)
@@ -4154,6 +4155,16 @@ rs6000_option_override_internal (bool global_init_p)
if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
error ("%qs requires VSX support", "-mfloat128");
+ TARGET_FLOAT128_TYPE = 0;
+ rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
+ | OPTION_MASK_FLOAT128_HW);
+ }
+ else if (!TARGET_POWERPC64 && !BYTES_BIG_ENDIAN)
+ {
+ if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
+ error ("%qs requires 64-bit support on little endian systems",
+ "-mfloat128");
+
TARGET_FLOAT128_TYPE = 0;
rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
| OPTION_MASK_FLOAT128_HW);
diff --git a/libgcc/config.host b/libgcc/config.host
index 9fae51d4ce7d..9e3b21e98fdd 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1290,16 +1290,18 @@ powerpc*-*-linux*)
;;
esac
+ # If the compiler is not configured for IEEE 128-bit, do not include the
+ # power9 and power10 hardware support libraries
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
- fi
- if test $libgcc_cv_powerpc_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-hw"
- fi
+ if test $libgcc_cv_powerpc_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-hw"
- if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
+ if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+ tmake_file="${tmake_file}
rs6000/t-float128-p10-hw"
+ fi
+ fi
fi
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/configure b/libgcc/configure
index a69d314374a3..7ac132b71693 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -5180,13 +5180,14 @@ esac
esac
case ${host} in
-# At present, we cannot turn -mfloat128 on via #pragma GCC target, so just
-# check if we have VSX (ISA 2.06) support to build the software libraries, and
-# whether the assembler can handle xsaddqp for hardware support. Also check if
-# a new glibc is being used so that __builtin_cpu_supports can be used.
+# Determine if the system can support VSX, which is needed to support
+# __float128. Little endian 32-bit cannot be supported, since those systems do
+# not support VSX. All of the little endian 64-bit systems require VSX support
+# (power8 and above). With big endian, the default might not include VSX, but
+# we can build the libgcc __float128 support
[gcc(refs/users/meissner/heads/work169-bugs)] Revert changes
https://gcc.gnu.org/g:20308918164fce2de9c974514d2797cd4652cd12
commit 20308918164fce2de9c974514d2797cd4652cd12
Author: Michael Meissner
Date: Tue Jun 18 00:55:58 2024 -0400
Revert changes
Diff:
---
gcc/config/rs6000/rs6000.cc | 13 +
libgcc/config.host | 14 ++
libgcc/configure | 9 +
libgcc/configure.ac | 9 +
libgfortran/configure| 7 ++-
libgfortran/configure.ac | 3 ---
libgfortran/kinds-override.h | 2 +-
7 files changed, 12 insertions(+), 45 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index ea36e651b446..c5c4191127e4 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4146,8 +4146,7 @@ rs6000_option_override_internal (bool global_init_p)
the keyword as well as the type. */
TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
- /* IEEE 128-bit floating point requires VSX support. Disable IEEE 128-bit on
- legacy 32-bit LE systems. */
+ /* IEEE 128-bit floating point requires VSX support. */
if (TARGET_FLOAT128_KEYWORD)
{
if (!TARGET_VSX)
@@ -4155,16 +4154,6 @@ rs6000_option_override_internal (bool global_init_p)
if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
error ("%qs requires VSX support", "-mfloat128");
- TARGET_FLOAT128_TYPE = 0;
- rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
- | OPTION_MASK_FLOAT128_HW);
- }
- else if (!TARGET_POWERPC64 && !BYTES_BIG_ENDIAN)
- {
- if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
- error ("%qs requires 64-bit support on little endian systems",
- "-mfloat128");
-
TARGET_FLOAT128_TYPE = 0;
rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
| OPTION_MASK_FLOAT128_HW);
diff --git a/libgcc/config.host b/libgcc/config.host
index 9e3b21e98fdd..9fae51d4ce7d 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1290,18 +1290,16 @@ powerpc*-*-linux*)
;;
esac
- # If the compiler is not configured for IEEE 128-bit, do not include the
- # power9 and power10 hardware support libraries
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
+ fi
- if test $libgcc_cv_powerpc_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-hw"
+ if test $libgcc_cv_powerpc_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-hw"
+ fi
- if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
- tmake_file="${tmake_file}
rs6000/t-float128-p10-hw"
- fi
- fi
+ if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
fi
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/configure b/libgcc/configure
index f61c9c9b3937..a69d314374a3 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -5184,16 +5184,9 @@ case ${host} in
# check if we have VSX (ISA 2.06) support to build the software libraries, and
# whether the assembler can handle xsaddqp for hardware support. Also check if
# a new glibc is being used so that __builtin_cpu_supports can be used.
-#
-# Originally we added -mabi=altivec -mvsx to the tests to see if we could
-# support IEEE 128-bit. This would mean that even if the compiler was
-# configured for power5, it would build the IEEE 128-bit libraries by adding
-# -mvsx. Instead if you want IEEE 128-bit support, you have to configure the
-# compiler to build ISA 2.06 (power8) by default. We do add -mfloat128 to
-# cater to systems where IEEE 128-bit might not be enabled by default.
powerpc*-*-linux*)
saved_CFLAGS="$CFLAGS"
- CFLAGS="$CFLAGS -mfloat128"
+ CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128"
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for PowerPC ISA 2.06 to
build __float128 libraries" >&5
$as_echo_n "checking for PowerPC ISA 2.06 to build __float128 libraries... "
>&6; }
if ${libgcc_cv_powerpc_float128+:} false; then :
diff --git a/libgcc/configure.ac b/libgcc/configure.ac
index d9941c0b1a6a..c2749fe09584 100644
--- a/libgcc/configure.ac
+++ b/libgcc/configure.ac
@@ -407,16 +407,9 @@ case ${host} in
# check if we have VSX (ISA 2.06) support to build the software libraries, and
# whether the assembler can handle xsaddqp for hardware support. Also check if
# a new glibc is being used so that __builtin_cpu_supports can be used.
-#
-# Originally we added -mabi=altivec -mvsx to the tests to see if we could
-# support IEEE 128-bit. This would mean that even if the compiler was
-# configured for power5, it would
[gcc r15-1389] i386: Handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx
https://gcc.gnu.org/g:7c6f79eea9febce3b21c5783bac9b0a36e08f003
commit r15-1389-g7c6f79eea9febce3b21c5783bac9b0a36e08f003
Author: Hu, Lin1
Date: Wed Mar 20 16:01:45 2024 +0800
i386: Handle target of __builtin_ia32_cmp[p|s][s|d] from avx into
sse/sse2/avx
gcc/ChangeLog:
* config/i386/avxintrin.h: Move cmp[p|s][s|d] to [e|x]mmintrin.h,
and move macros to xmmintrin.h
* config/i386/emmintrin.h: Add cmp[p|s]s intrins.
* config/i386/i386-builtin.def: Modify __builtin_ia32_cmp[p|s][s|d].
* config/i386/i386-expand.cc
(ix86_expand_args_builtin): Raise error when imm is in range of
[8, 32] without avx.
* config/i386/predicates.md (cmpps_imm_operand): New predicate.
* config/i386/sse.md (avx_cmp3): Modefy define_insn.
(avx_vmcmp3): Ditto.
* config/i386/xmmintrin.h (_CMP_EQ_OQ): New macro for sse/sse2.
(_CMP_LT_OS): Ditto
(_CMP_LE_OS): Ditto
(_CMP_UNORD_Q): Ditto
(_CMP_NEQ_UQ): Ditto
(_CMP_NLT_US): Ditto
(_CMP_NLE_US): Ditto
(_CMP_ORD_Q): Ditto
(_mm_cmp_ps): Move intrin from avxintrin.h to xmmintrin.h
(_mm_cmp_ss): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/sse-cmp-1.c: New test.
* gcc.target/i386/sse-cmp-2.c: Ditto.
* gcc.target/i386/sse-cmp-error.c: Ditto.
Diff:
---
gcc/config/i386/avxintrin.h | 56
gcc/config/i386/emmintrin.h | 22 ++
gcc/config/i386/i386-builtin.def | 10 +--
gcc/config/i386/i386-expand.cc| 6 ++
gcc/config/i386/predicates.md | 5 ++
gcc/config/i386/sse.md| 42 +++-
gcc/config/i386/xmmintrin.h | 41
gcc/testsuite/gcc.target/i386/sse-cmp-1.c | 20 ++
gcc/testsuite/gcc.target/i386/sse-cmp-2.c | 96 +++
gcc/testsuite/gcc.target/i386/sse-cmp-error.c | 16 +
10 files changed, 236 insertions(+), 78 deletions(-)
diff --git a/gcc/config/i386/avxintrin.h b/gcc/config/i386/avxintrin.h
index 802145408881..ec9b9905b5f6 100644
--- a/gcc/config/i386/avxintrin.h
+++ b/gcc/config/i386/avxintrin.h
@@ -72,22 +72,6 @@ typedef double __m256d_u __attribute__ ((__vector_size__
(32),
/* Compare predicates for scalar and packed compare intrinsics. */
-/* Equal (ordered, non-signaling) */
-#define _CMP_EQ_OQ 0x00
-/* Less-than (ordered, signaling) */
-#define _CMP_LT_OS 0x01
-/* Less-than-or-equal (ordered, signaling) */
-#define _CMP_LE_OS 0x02
-/* Unordered (non-signaling) */
-#define _CMP_UNORD_Q 0x03
-/* Not-equal (unordered, non-signaling) */
-#define _CMP_NEQ_UQ0x04
-/* Not-less-than (unordered, signaling) */
-#define _CMP_NLT_US0x05
-/* Not-less-than-or-equal (unordered, signaling) */
-#define _CMP_NLE_US0x06
-/* Ordered (nonsignaling) */
-#define _CMP_ORD_Q 0x07
/* Equal (unordered, non-signaling) */
#define _CMP_EQ_UQ 0x08
/* Not-greater-than-or-equal (unordered, signaling) */
@@ -381,18 +365,6 @@ _mm256_xor_ps (__m256 __A, __m256 __B)
}
#ifdef __OPTIMIZE__
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__,
__artificial__))
-_mm_cmp_pd (__m128d __X, __m128d __Y, const int __P)
-{
- return (__m128d) __builtin_ia32_cmppd ((__v2df)__X, (__v2df)__Y, __P);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__,
__artificial__))
-_mm_cmp_ps (__m128 __X, __m128 __Y, const int __P)
-{
- return (__m128) __builtin_ia32_cmpps ((__v4sf)__X, (__v4sf)__Y, __P);
-}
-
extern __inline __m256d __attribute__((__gnu_inline__, __always_inline__,
__artificial__))
_mm256_cmp_pd (__m256d __X, __m256d __Y, const int __P)
{
@@ -406,27 +378,7 @@ _mm256_cmp_ps (__m256 __X, __m256 __Y, const int __P)
return (__m256) __builtin_ia32_cmpps256 ((__v8sf)__X, (__v8sf)__Y,
__P);
}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__,
__artificial__))
-_mm_cmp_sd (__m128d __X, __m128d __Y, const int __P)
-{
- return (__m128d) __builtin_ia32_cmpsd ((__v2df)__X, (__v2df)__Y, __P);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__,
__artificial__))
-_mm_cmp_ss (__m128 __X, __m128 __Y, const int __P)
-{
- return (__m128) __builtin_ia32_cmpss ((__v4sf)__X, (__v4sf)__Y, __P);
-}
#else
-#define _mm_cmp_pd(X, Y, P)\
- ((__m128d) __builtin_ia32_cmppd ((__v2df)(__m128d)(X), \
- (__v2df)(__m128d)(Y), (int)(P)))
-
-#define _mm_cmp_ps(X, Y, P)\
- ((__m128) __builtin_ia32_cmpps ((__v4sf)(__m128)(X), \
- (__v4sf)(__m128)(Y), (int)(P)))
-
#define _mm
[gcc r15-1387] aarch64: Add testcase for PR97405
https://gcc.gnu.org/g:17979deb15d34dd4f036ca93d2977d0fc4d556a7
commit r15-1387-g17979deb15d34dd4f036ca93d2977d0fc4d556a7
Author: Andrew Pinski
Date: Mon Jun 17 16:45:34 2024 -0700
aarch64: Add testcase for PR97405
This aarch64 sve specific code was fixed by r15-917-gc9842f99042454
which added a riscv specific testcase so adding an aarch64 one to test
the fix does not regress is a good idea.
Committed as obvious after testing the testcase for aarch64-linux-gnu.
PR tree-optimization/97405
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/pr97405-1.c: New test.
Signed-off-by: Andrew Pinski
Diff:
---
gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c
b/gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c
new file mode 100644
index ..5efa32c99280
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv8.2-a+sve -O2" }
+/* PR tree-optimization/97405 */
+#include "arm_sve.h"
+
+void
+a (svuint8x3_t b, unsigned char *p, int c) {
+ if (c)
+svst1_u8(svptrue_pat_b8(SV_VL16), p, svget3_u8(b, 1));
+ else
+svst1_u8(svwhilelt_b8(6, 6), p, svget3_u8(b, 1));
+}
+
[gcc r15-1386] [to-be-committed, RISC-V] Handle zero_extract destination for single bit insertions
https://gcc.gnu.org/g:67bc21af7ba35b773b5cf0e85107715f7c2240e4
commit r15-1386-g67bc21af7ba35b773b5cf0e85107715f7c2240e4
Author: Jeff Law
Date: Mon Jun 17 17:24:03 2024 -0600
[to-be-committed,RISC-V] Handle zero_extract destination for single bit
insertions
Combine will use zero_extract destinations for certain bitfield
insertions. If the bitfield is a single bit constant, then we can use
bset/bclr.
In this case we are only dealing with word_mode objects, so we don't
have to worry about the SI->DI extension issues for TARGET_64BIT.
The testcase was derived from 502.gcc in spec from the RAU team.
An earlier version of this (TARGET_64BIT only) went through Ventana's CI
system. This version has gone though mine after generalizing it to
handle rv32 as well. I'll wait for pre-commit CI to render its verdict
before moving forward.
gcc/
* config/riscv/bitmanip.md (bsetclr_zero_extract): New pattern.
gcc/testsuite/
* gcc.target/riscv/zbs-zext-3.c: New test.
Diff:
---
gcc/config/riscv/bitmanip.md| 17 +
gcc/testsuite/gcc.target/riscv/zbs-zext-3.c | 27 +++
2 files changed, 44 insertions(+)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 311f0d373c00..094bc2acf1c7 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -654,6 +654,23 @@
(any_or:DI (ashift:DI (const_int 1) (match_dup 1))
(match_dup 3)))])
+;; Yet another form of a bset/bclr that can be created by combine.
+(define_insn "*bsetclr_zero_extract"
+ [(set (zero_extract:X (match_operand:X 0 "register_operand" "+r")
+ (const_int 1)
+ (zero_extend:X
+ (match_operand:QI 1 "register_operand" "r")))
+ (match_operand 2 "immediate_operand" "n"))]
+ "TARGET_ZBS
+ && (operands[2] == CONST0_RTX (mode)
+ || operands[2] == CONST1_RTX (mode))"
+ {
+return (operands[2] == CONST0_RTX (mode)
+ ? "bclr\t%0,%0,%1"
+ : "bset\t%0,%0,%1");
+ }
+ [(set_attr "type" "bitmanip")])
+
(define_insn "*bclr"
[(set (match_operand:X 0 "register_operand" "=r")
(and:X (rotate:X (const_int -2)
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-zext-3.c
b/gcc/testsuite/gcc.target/riscv/zbs-zext-3.c
new file mode 100644
index ..0239014e06bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbs-zext-3.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba_zbb_zbs -mabi=lp64d" { target { rv64 } } }
*/
+/* { dg-options "-march=rv32gc_zba_zbb_zbs -mabi=ilp32" { target { rv32 } } }
*/
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+/* We need to adjust the constant so this works for rv32 and rv64. */
+#if __riscv_xlen == 32
+#define ONE 1U
+#else
+#define ONE 1ULL
+#endif
+
+void add_to_hard_reg_set(long long *a, unsigned int count) {
+ int i = 0;
+ while(i++ < count)
+*a |= (1U << i);
+}
+
+void remove_from_hard_reg_set(long long *a, unsigned int count) {
+ int i = 0;
+ while(i++ < count)
+*a &= ~(ONE << i);
+}
+
+
+/* { dg-final { scan-assembler-not "and\t" } } */
+/* { dg-final { scan-assembler-not "andn\t" } } */
[gcc(refs/users/meissner/heads/work169-bugs)] Update ChangeLog.*
https://gcc.gnu.org/g:63019645e9daae404e78d0696ecccdb49a794959 commit 63019645e9daae404e78d0696ecccdb49a794959 Author: Michael Meissner Date: Mon Jun 17 18:42:29 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.bugs | 26 ++ 1 file changed, 26 insertions(+) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index 0366545b17e8..9a2af6e5eaf0 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,3 +1,29 @@ + Branch work169-bugs, patch #400 + +Do not build IEEE 128-bit support for little endian power5. + +2024-06-17 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Do not + allow IEEE 128-bit on little endian 32-bit systems. + +libgcc/ + + * config.host (powerpc*-linux*): Do not build the IEEE 128-bit support + libraries unless GCC is configured for at least power8 by default. + * configure.ac (powerpc*-linux*): Likewise. + * configure: Regenerate. + +libgfortran/ + + * configure.ac (powerpc64le*-linux*): Check to see that the compiler + uses VSX before enabling IEEE 128-bit support. + * configure: Regenerate. + * kinds-override.h: Do not enable IEEE 128-bit floating point support on + little endian PowerPC that does not have VSX support. + Branch work169-bugs, patch #11 (work169 branch) Add -mcpu=future tuning support.
[gcc(refs/users/meissner/heads/work169-bugs)] Do not build IEEE 128-bit support for little endian power5.
https://gcc.gnu.org/g:d1a317cacda5fe14e90ef2beefd8d19923ec696a
commit d1a317cacda5fe14e90ef2beefd8d19923ec696a
Author: Michael Meissner
Date: Mon Jun 17 18:41:05 2024 -0400
Do not build IEEE 128-bit support for little endian power5.
2024-06-17 Michael Meissner
gcc/
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Do not
allow IEEE 128-bit on little endian 32-bit systems.
libgcc/
* config.host (powerpc*-linux*): Do not build the IEEE 128-bit
support
libraries unless GCC is configured for at least power8 by default.
* configure.ac (powerpc*-linux*): Likewise.
* configure: Regenerate.
libgfortran/
* configure.ac (powerpc64le*-linux*): Check to see that the compiler
uses VSX before enabling IEEE 128-bit support.
* configure: Regenerate.
* kinds-override.h: Do not enable IEEE 128-bit floating point
support on
little endian PowerPC that does not have VSX support.
Diff:
---
gcc/config/rs6000/rs6000.cc | 13 -
libgcc/config.host | 14 --
libgcc/configure | 9 -
libgcc/configure.ac | 9 -
libgfortran/configure| 7 +--
libgfortran/configure.ac | 3 +++
libgfortran/kinds-override.h | 2 +-
7 files changed, 45 insertions(+), 12 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c5c4191127e4..ea36e651b446 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4146,7 +4146,8 @@ rs6000_option_override_internal (bool global_init_p)
the keyword as well as the type. */
TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
- /* IEEE 128-bit floating point requires VSX support. */
+ /* IEEE 128-bit floating point requires VSX support. Disable IEEE 128-bit on
+ legacy 32-bit LE systems. */
if (TARGET_FLOAT128_KEYWORD)
{
if (!TARGET_VSX)
@@ -4154,6 +4155,16 @@ rs6000_option_override_internal (bool global_init_p)
if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
error ("%qs requires VSX support", "-mfloat128");
+ TARGET_FLOAT128_TYPE = 0;
+ rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
+ | OPTION_MASK_FLOAT128_HW);
+ }
+ else if (!TARGET_POWERPC64 && !BYTES_BIG_ENDIAN)
+ {
+ if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
+ error ("%qs requires 64-bit support on little endian systems",
+ "-mfloat128");
+
TARGET_FLOAT128_TYPE = 0;
rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
| OPTION_MASK_FLOAT128_HW);
diff --git a/libgcc/config.host b/libgcc/config.host
index 9fae51d4ce7d..9e3b21e98fdd 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1290,16 +1290,18 @@ powerpc*-*-linux*)
;;
esac
+ # If the compiler is not configured for IEEE 128-bit, do not include the
+ # power9 and power10 hardware support libraries
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
- fi
- if test $libgcc_cv_powerpc_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-hw"
- fi
+ if test $libgcc_cv_powerpc_float128_hw = yes; then
+ tmake_file="${tmake_file} rs6000/t-float128-hw"
- if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
- tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
+ if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+ tmake_file="${tmake_file}
rs6000/t-float128-p10-hw"
+ fi
+ fi
fi
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/configure b/libgcc/configure
index a69d314374a3..f61c9c9b3937 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -5184,9 +5184,16 @@ case ${host} in
# check if we have VSX (ISA 2.06) support to build the software libraries, and
# whether the assembler can handle xsaddqp for hardware support. Also check if
# a new glibc is being used so that __builtin_cpu_supports can be used.
+#
+# Originally we added -mabi=altivec -mvsx to the tests to see if we could
+# support IEEE 128-bit. This would mean that even if the compiler was
+# configured for power5, it would build the IEEE 128-bit libraries by adding
+# -mvsx. Instead if you want IEEE 128-bit support, you have to configure the
+# compiler to build ISA 2.06 (power8) by default. We do add -mfloat128 to
+# cater to systems where IEEE 128-bit might not be enabled by default.
powerpc*-*-linux*)
saved_CFLAGS="$CFLAGS"
- CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat12
[gcc(refs/users/meissner/heads/work169-vpair)] Update ChangeLog.*
https://gcc.gnu.org/g:6dc0e15fc0935124b120a799b4058bf5f936e69e commit 6dc0e15fc0935124b120a799b4058bf5f936e69e Author: Michael Meissner Date: Mon Jun 17 17:56:55 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.vpair | 161 +++- 1 file changed, 160 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair index 246a7b149737..b7f665e3fe63 100644 --- a/gcc/ChangeLog.vpair +++ b/gcc/ChangeLog.vpair @@ -1,6 +1,165 @@ + Branch work169-vpair, patch #11 (work169 branch) + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-06-17 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work169-vpair, patch #10 (work169 branch) + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-06-17 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + + Branch work169-vpair, patch #3 (work169 branch) + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-06-17 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): Add new + effective target. + + Branch work169-vpair, patch #2 (work169 branch) + +Add -mcpu=power11 tuning support. + +This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. + +2024-06-17 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add power11 as an + alternative to power10. + + Branch work169-vpair, patch #1 (work169 branch) + +Add -mcpu=power11 support. + +This patch adds the power11 option to the -mcpu= and -mtune= switches. + +This patch treats the power11 like a power10 in terms of costs and reassociation +width. + +This patch issues a ".machine power11" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. + +This patch allows GCC to be configured with the --with-cpu=power11 and +--with-tune=power11 options. + +This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. + +This patch adds support for using "power11" in the __builtin_cpu_is built-in +function. + +2024-06-17 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs60
[gcc(refs/users/meissner/heads/work169-test)] Update ChangeLog.*
https://gcc.gnu.org/g:27f1d6c76fdd5c4e9387210e9bc3ef0fa4565dbe commit 27f1d6c76fdd5c4e9387210e9bc3ef0fa4565dbe Author: Michael Meissner Date: Mon Jun 17 17:55:54 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.test | 161 - 1 file changed, 160 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test index 67de41285d7c..dc462c93955a 100644 --- a/gcc/ChangeLog.test +++ b/gcc/ChangeLog.test @@ -1,6 +1,165 @@ + Branch work169-test, patch #11 (work169 branch) + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-06-17 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work169-test, patch #10 (work169 branch) + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-06-17 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + + Branch work169-test, patch #3 (work169 branch) + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-06-17 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): Add new + effective target. + + Branch work169-test, patch #2 (work169 branch) + +Add -mcpu=power11 tuning support. + +This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. + +2024-06-17 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add power11 as an + alternative to power10. + + Branch work169-test, patch #1 (work169 branch) + +Add -mcpu=power11 support. + +This patch adds the power11 option to the -mcpu= and -mtune= switches. + +This patch treats the power11 like a power10 in terms of costs and reassociation +width. + +This patch issues a ".machine power11" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. + +This patch allows GCC to be configured with the --with-cpu=power11 and +--with-tune=power11 options. + +This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. + +This patch adds support for using "power11" in the __builtin_cpu_is built-in +function. + +2024-06-17 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.
[gcc(refs/users/meissner/heads/work169-tar)] Apply patches 1-3 and 10-11 from work169 branch
https://gcc.gnu.org/g:a220a21e0c96edd0831d888719f7dd92eceea25b commit a220a21e0c96edd0831d888719f7dd92eceea25b Author: Michael Meissner Date: Mon Jun 17 17:54:49 2024 -0400 Apply patches 1-3 and 10-11 from work169 branch Diff: --- gcc/ChangeLog.tar| 161 ++- gcc/config.gcc | 6 +- gcc/config/rs6000/aix71.h| 2 + gcc/config/rs6000/aix72.h| 2 + gcc/config/rs6000/aix73.h| 2 + gcc/config/rs6000/driver-rs6000.cc | 4 + gcc/config/rs6000/power10.md | 145 gcc/config/rs6000/ppc-auxv.h | 3 +- gcc/config/rs6000/rs6000-builtin.cc | 1 + gcc/config/rs6000/rs6000-c.cc| 4 + gcc/config/rs6000/rs6000-cpus.def| 10 ++ gcc/config/rs6000/rs6000-opts.h | 4 +- gcc/config/rs6000/rs6000-string.cc | 2 + gcc/config/rs6000/rs6000-tables.opt | 6 + gcc/config/rs6000/rs6000.cc | 46 ++-- gcc/config/rs6000/rs6000.h | 2 + gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 6 + gcc/doc/invoke.texi | 5 +- gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +++ gcc/testsuite/gcc.target/powerpc/power11-2.c | 20 gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++ gcc/testsuite/lib/target-supports.exp| 17 +++ 23 files changed, 384 insertions(+), 89 deletions(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index 3ce483b3c2d5..2f8c29d4203d 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,6 +1,165 @@ + Branch work169-tar, patch #11 (work169 branch) + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-06-17 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work169-tar, patch #10 (work169 branch) + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-06-17 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + + Branch work169-tar, patch #3 (work169 branch) + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-06-17 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): Add new
[gcc(refs/users/meissner/heads/work169-dmf)] Update ChangeLog.*
https://gcc.gnu.org/g:e5fc38552028cad4ad0640f27e3b108083f6f7fd commit e5fc38552028cad4ad0640f27e3b108083f6f7fd Author: Michael Meissner Date: Mon Jun 17 17:53:21 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.dmf | 161 +- 1 file changed, 160 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf index b32cf61e3942..dc052b6dff1e 100644 --- a/gcc/ChangeLog.dmf +++ b/gcc/ChangeLog.dmf @@ -1,6 +1,165 @@ + Branch work169-dmf, patch #11 (work169 branch) + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-06-17 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work169-dmf, patch #10 (work169 branch) + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-06-17 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + + Branch work169-dmf, patch #3 (work169 branch) + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-06-17 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): Add new + effective target. + + Branch work169-dmf, patch #2 (work169 branch) + +Add -mcpu=power11 tuning support. + +This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. + +2024-06-17 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add power11 as an + alternative to power10. + + Branch work169-dmf, patch #1 (work169 branch) + +Add -mcpu=power11 support. + +This patch adds the power11 option to the -mcpu= and -mtune= switches. + +This patch treats the power11 like a power10 in terms of costs and reassociation +width. + +This patch issues a ".machine power11" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. + +This patch allows GCC to be configured with the --with-cpu=power11 and +--with-tune=power11 options. + +This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. + +This patch adds support for using "power11" in the __builtin_cpu_is built-in +function. + +2024-06-17 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CP
[gcc(refs/users/meissner/heads/work169-test)] Apply patches 1-3 and 10-11 from work169 branch
https://gcc.gnu.org/g:71ed2dec27a429f2a10e47c5636493cf1021109c
commit 71ed2dec27a429f2a10e47c5636493cf1021109c
Author: Michael Meissner
Date: Mon Jun 17 17:51:05 2024 -0400
Apply patches 1-3 and 10-11 from work169 branch
Diff:
---
gcc/config.gcc | 6 +-
gcc/config/rs6000/aix71.h| 2 +
gcc/config/rs6000/aix72.h| 2 +
gcc/config/rs6000/aix73.h| 2 +
gcc/config/rs6000/driver-rs6000.cc | 4 +
gcc/config/rs6000/power10.md | 145 ++-
gcc/config/rs6000/ppc-auxv.h | 3 +-
gcc/config/rs6000/rs6000-builtin.cc | 1 +
gcc/config/rs6000/rs6000-c.cc| 4 +
gcc/config/rs6000/rs6000-cpus.def| 10 ++
gcc/config/rs6000/rs6000-opts.h | 4 +-
gcc/config/rs6000/rs6000-string.cc | 2 +
gcc/config/rs6000/rs6000-tables.opt | 6 ++
gcc/config/rs6000/rs6000.cc | 46 +++--
gcc/config/rs6000/rs6000.h | 2 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt | 6 ++
gcc/doc/invoke.texi | 5 +-
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +++
gcc/testsuite/gcc.target/powerpc/power11-2.c | 20
gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++
gcc/testsuite/lib/target-supports.exp| 17
22 files changed, 224 insertions(+), 88 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index e500ba63e322..b297f68dad26 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -533,7 +533,9 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+ xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
+ | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 |
xe500mc64 \
+ | xe5500 | xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5621,7 +5623,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power10 | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x |
future \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 24bc301e37d6..570ddcc451db 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,8 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index c43974f577af..242ca94bd065 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,8 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index b1572bde81f9..2bd6b4bb3c4f 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,8 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/driver-rs6000.cc
b/gcc/config/rs6000/driver-rs6000.cc
index 3ebbaa42622a..99791250be44 100644
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -441,6 +441,7 @@ struct asm_name {
static const struct asm_name asm_names[] = {
#if defined (_AIX)
+ { "future", "-mfuture" },
{ "power3", "-m620" },
{ "power4", "-mpwr4" },
{ "power5", "-mpwr5" },
@@ -451,6 +452,7 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpwr8" },
{ "power9", "-mpwr9" },
{ "power10", "-mpwr10" },
+ { "power11", "-mpwr11" },
{ "powerpc", "-mppc" },
{ "rs64","-mppc" },
{ "603", "-m603" },
@@ -469,6 +471,7 @@ static const struct asm_name asm_names[] = {
#else
{ "cell","-mcell" },
+ { "
[gcc(refs/users/meissner/heads/work169-vpair)] Apply patches 1-3 and 10-11 from work169 branch
https://gcc.gnu.org/g:079b34c85b145db48e4cc2ddb1f7f2f4d899981c
commit 079b34c85b145db48e4cc2ddb1f7f2f4d899981c
Author: Michael Meissner
Date: Mon Jun 17 17:50:46 2024 -0400
Apply patches 1-3 and 10-11 from work169 branch
Diff:
---
gcc/config.gcc | 6 +-
gcc/config/rs6000/aix71.h| 2 +
gcc/config/rs6000/aix72.h| 2 +
gcc/config/rs6000/aix73.h| 2 +
gcc/config/rs6000/driver-rs6000.cc | 4 +
gcc/config/rs6000/power10.md | 145 ++-
gcc/config/rs6000/ppc-auxv.h | 3 +-
gcc/config/rs6000/rs6000-builtin.cc | 1 +
gcc/config/rs6000/rs6000-c.cc| 4 +
gcc/config/rs6000/rs6000-cpus.def| 10 ++
gcc/config/rs6000/rs6000-opts.h | 4 +-
gcc/config/rs6000/rs6000-string.cc | 2 +
gcc/config/rs6000/rs6000-tables.opt | 6 ++
gcc/config/rs6000/rs6000.cc | 46 +++--
gcc/config/rs6000/rs6000.h | 2 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt | 6 ++
gcc/doc/invoke.texi | 5 +-
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +++
gcc/testsuite/gcc.target/powerpc/power11-2.c | 20
gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++
gcc/testsuite/lib/target-supports.exp| 17
22 files changed, 224 insertions(+), 88 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index e500ba63e322..b297f68dad26 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -533,7 +533,9 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+ xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
+ | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 |
xe500mc64 \
+ | xe5500 | xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5621,7 +5623,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power10 | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x |
future \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 24bc301e37d6..570ddcc451db 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,8 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index c43974f577af..242ca94bd065 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,8 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index b1572bde81f9..2bd6b4bb3c4f 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,8 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/driver-rs6000.cc
b/gcc/config/rs6000/driver-rs6000.cc
index 3ebbaa42622a..99791250be44 100644
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -441,6 +441,7 @@ struct asm_name {
static const struct asm_name asm_names[] = {
#if defined (_AIX)
+ { "future", "-mfuture" },
{ "power3", "-m620" },
{ "power4", "-mpwr4" },
{ "power5", "-mpwr5" },
@@ -451,6 +452,7 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpwr8" },
{ "power9", "-mpwr9" },
{ "power10", "-mpwr10" },
+ { "power11", "-mpwr11" },
{ "powerpc", "-mppc" },
{ "rs64","-mppc" },
{ "603", "-m603" },
@@ -469,6 +471,7 @@ static const struct asm_name asm_names[] = {
#else
{ "cell","-mcell" },
+ { "
[gcc(refs/users/meissner/heads/work169-dmf)] Apply patches 1-3 and 10-11 from work169 branch
https://gcc.gnu.org/g:e832ea3f54064142c7abb24e32db2881dfb72167
commit e832ea3f54064142c7abb24e32db2881dfb72167
Author: Michael Meissner
Date: Mon Jun 17 17:50:11 2024 -0400
Apply patches 1-3 and 10-11 from work169 branch
Diff:
---
gcc/config.gcc | 6 +-
gcc/config/rs6000/aix71.h| 2 +
gcc/config/rs6000/aix72.h| 2 +
gcc/config/rs6000/aix73.h| 2 +
gcc/config/rs6000/driver-rs6000.cc | 4 +
gcc/config/rs6000/power10.md | 145 ++-
gcc/config/rs6000/ppc-auxv.h | 3 +-
gcc/config/rs6000/rs6000-builtin.cc | 1 +
gcc/config/rs6000/rs6000-c.cc| 4 +
gcc/config/rs6000/rs6000-cpus.def| 10 ++
gcc/config/rs6000/rs6000-opts.h | 4 +-
gcc/config/rs6000/rs6000-string.cc | 2 +
gcc/config/rs6000/rs6000-tables.opt | 6 ++
gcc/config/rs6000/rs6000.cc | 46 +++--
gcc/config/rs6000/rs6000.h | 2 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt | 6 ++
gcc/doc/invoke.texi | 5 +-
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +++
gcc/testsuite/gcc.target/powerpc/power11-2.c | 20
gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++
gcc/testsuite/lib/target-supports.exp| 17
22 files changed, 224 insertions(+), 88 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index e500ba63e322..b297f68dad26 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -533,7 +533,9 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+ xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
+ | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 |
xe500mc64 \
+ | xe5500 | xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5621,7 +5623,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power10 | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x |
future \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 24bc301e37d6..570ddcc451db 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,8 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index c43974f577af..242ca94bd065 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,8 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
index b1572bde81f9..2bd6b4bb3c4f 100644
--- a/gcc/config/rs6000/aix73.h
+++ b/gcc/config/rs6000/aix73.h
@@ -79,6 +79,8 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
+ mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
mcpu=power8: -mpwr8; \
diff --git a/gcc/config/rs6000/driver-rs6000.cc
b/gcc/config/rs6000/driver-rs6000.cc
index 3ebbaa42622a..99791250be44 100644
--- a/gcc/config/rs6000/driver-rs6000.cc
+++ b/gcc/config/rs6000/driver-rs6000.cc
@@ -441,6 +441,7 @@ struct asm_name {
static const struct asm_name asm_names[] = {
#if defined (_AIX)
+ { "future", "-mfuture" },
{ "power3", "-m620" },
{ "power4", "-mpwr4" },
{ "power5", "-mpwr5" },
@@ -451,6 +452,7 @@ static const struct asm_name asm_names[] = {
{ "power8", "-mpwr8" },
{ "power9", "-mpwr9" },
{ "power10", "-mpwr10" },
+ { "power11", "-mpwr11" },
{ "powerpc", "-mppc" },
{ "rs64","-mppc" },
{ "603", "-m603" },
@@ -469,6 +471,7 @@ static const struct asm_name asm_names[] = {
#else
{ "cell","-mcell" },
+ { "
[gcc(refs/users/meissner/heads/work169-bugs)] Apply patches 1-3 and 10-11 from work169 branch
https://gcc.gnu.org/g:7bb2a57b5568d4d64c78d688e1ffe9da6ae40768 commit 7bb2a57b5568d4d64c78d688e1ffe9da6ae40768 Author: Michael Meissner Date: Mon Jun 17 17:49:02 2024 -0400 Apply patches 1-3 and 10-11 from work169 branch Diff: --- gcc/ChangeLog.bugs | 161 ++- gcc/config.gcc | 6 +- gcc/config/rs6000/aix71.h| 2 + gcc/config/rs6000/aix72.h| 2 + gcc/config/rs6000/aix73.h| 2 + gcc/config/rs6000/driver-rs6000.cc | 4 + gcc/config/rs6000/power10.md | 145 gcc/config/rs6000/ppc-auxv.h | 3 +- gcc/config/rs6000/rs6000-builtin.cc | 1 + gcc/config/rs6000/rs6000-c.cc| 4 + gcc/config/rs6000/rs6000-cpus.def| 10 ++ gcc/config/rs6000/rs6000-opts.h | 4 +- gcc/config/rs6000/rs6000-string.cc | 2 + gcc/config/rs6000/rs6000-tables.opt | 6 + gcc/config/rs6000/rs6000.cc | 46 ++-- gcc/config/rs6000/rs6000.h | 2 + gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 6 + gcc/doc/invoke.texi | 5 +- gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +++ gcc/testsuite/gcc.target/powerpc/power11-2.c | 20 gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++ gcc/testsuite/lib/target-supports.exp| 17 +++ 23 files changed, 384 insertions(+), 89 deletions(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index fde4db8e004f..0366545b17e8 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,6 +1,165 @@ + Branch work169-bugs, patch #11 (work169 branch) + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-06-17 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work169-bugs, patch #10 (work169 branch) + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-06-17 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + + Branch work169-bugs, patch #3 (work169 branch) + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-06-17 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): A
[gcc(refs/users/meissner/heads/work169)] Add -mcpu=power11 tests.
https://gcc.gnu.org/g:99d2f9ee130985bfddc5c289db8b0de5d378a022
commit 99d2f9ee130985bfddc5c289db8b0de5d378a022
Author: Michael Meissner
Date: Mon Jun 17 17:41:34 2024 -0400
Add -mcpu=power11 tests.
This patch adds some simple tests for -mcpu=power11 support. In order to
run
these tests, you need an assembler that supports the appropriate option for
supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under
AIX).
2024-06-17 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/power11-1.c: New test.
* gcc.target/powerpc/power11-2.c: Likewise.
* gcc.target/powerpc/power11-3.c: Likewise.
* lib/target-supports.exp (check_effective_target_power11_ok): Add
new
effective target.
Diff:
---
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +
gcc/testsuite/gcc.target/powerpc/power11-2.c | 20
gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++
gcc/testsuite/lib/target-supports.exp| 17 +
4 files changed, 60 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
new file mode 100644
index ..2dd0f64ead1a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=power11. */
+
+#ifndef _ARCH_PWR11
+#error "-mcpu=power11 is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
new file mode 100644
index ..6537e22e1a62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-2.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the power11 target via a target attribute. */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
new file mode 100644
index ..89b13c857d98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c
@@ -0,0 +1,10 @@
+/* { dg-do assemble { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Check if we can set the power11 target via a target_clones attribute. */
+
+__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index e307f4e69efb..9d0314afe59a 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7129,6 +7129,23 @@ proc check_effective_target_power10_ok { } {
}
}
+# Return 1 if this is a PowerPC target supporting -mcpu=power11.
+
+proc check_effective_target_power11_ok { } {
+if { ([istarget powerpc*-*-*]) } {
+ return [check_no_compiler_messages power11_ok object {
+ int main (void) {
+ #ifndef _ARCH_PWR11
+ #error "-mcpu=power11 is not supported"
+ #endif
+ return 0;
+ }
+ } "-mcpu=power11"]
+} else {
+ return 0
+}
+}
+
# Return 1 if this is a PowerPC target supporting -mfloat128 via either
# software emulation on power7/power8 systems or hardware support on power9.
[gcc(refs/users/meissner/heads/work169)] Revert changes
https://gcc.gnu.org/g:08beab29a07123d5b9d464f21dda2889445ff7a9
commit 08beab29a07123d5b9d464f21dda2889445ff7a9
Author: Michael Meissner
Date: Mon Jun 17 17:40:04 2024 -0400
Revert changes
Diff:
---
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 -
gcc/testsuite/gcc.target/powerpc/power11-2.c | 21 -
gcc/testsuite/gcc.target/powerpc/power11-3.c | 11 ---
gcc/testsuite/lib/target-supports.exp| 17 -
4 files changed, 62 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
deleted file mode 100644
index 2dd0f64ead1a..
--- a/gcc/testsuite/gcc.target/powerpc/power11-1.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-do assemble { target powerpc*-*-* } } */
-/* { dg-require-effective-target power11_ok } */
-/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
-
-/* Basic check to see if the compiler supports -mcpu=power11. */
-
-#ifndef _ARCH_PWR11
-#error "-mcpu=power11 is not supported"
-#endif
-
-void foo (void)
-{
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
deleted file mode 100644
index 625031e91465..
--- a/gcc/testsuite/gcc.target/powerpc/power11-2.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/* { dg-do assemble { target powerpc*-*-* } } */
-/* { dg-require-effective-target power11_ok } */
-/* { dg-require-effective-target target_clone } */
-/* { dg-options "-O2" } */
-
-/* Check if we can set the power11 target via a target attribute. */
-
-__attribute__((__target__("cpu=power9")))
-void foo_p9 (void)
-{
-}
-
-__attribute__((__target__("cpu=power10")))
-void foo_p10 (void)
-{
-}
-
-__attribute__((__target__("cpu=power11")))
-void foo_p11 (void)
-{
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
deleted file mode 100644
index b0f245eea035..
--- a/gcc/testsuite/gcc.target/powerpc/power11-3.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* { dg-do assemble { target powerpc*-*-* } } */
-/* { dg-require-effective-target power11_ok } */
-/* { dg-require-effective-target target_clone } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Check if we can set the power11 target via a target_clones attribute. */
-
-__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
-void foo (void)
-{
-}
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 9d0314afe59a..e307f4e69efb 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7129,23 +7129,6 @@ proc check_effective_target_power10_ok { } {
}
}
-# Return 1 if this is a PowerPC target supporting -mcpu=power11.
-
-proc check_effective_target_power11_ok { } {
-if { ([istarget powerpc*-*-*]) } {
- return [check_no_compiler_messages power11_ok object {
- int main (void) {
- #ifndef _ARCH_PWR11
- #error "-mcpu=power11 is not supported"
- #endif
- return 0;
- }
- } "-mcpu=power11"]
-} else {
- return 0
-}
-}
-
# Return 1 if this is a PowerPC target supporting -mfloat128 via either
# software emulation on power7/power8 systems or hardware support on power9.
[gcc r15-1385] Add minimal support for __bf16 to -fdump-ada-spec
https://gcc.gnu.org/g:d78694c238ccb0b530afe3fe5a7afbe7cda8ad4b
commit r15-1385-gd78694c238ccb0b530afe3fe5a7afbe7cda8ad4b
Author: Eric Botcazou
Date: Mon Jun 17 23:26:21 2024 +0200
Add minimal support for __bf16 to -fdump-ada-spec
gcc/c-family/
* c-ada-spec.cc (is_float16): New predicate.
(dump_ada_node) : Call it.
Diff:
---
gcc/c-family/c-ada-spec.cc | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/gcc/c-family/c-ada-spec.cc b/gcc/c-family/c-ada-spec.cc
index a41e93aeafb8..e1b1b2a4b73f 100644
--- a/gcc/c-family/c-ada-spec.cc
+++ b/gcc/c-family/c-ada-spec.cc
@@ -2077,6 +2077,22 @@ dump_ada_enum_type (pretty_printer *pp, tree node, tree
type, int spc)
}
}
+/* Return true if NODE is the __bf16 type. */
+
+static bool
+is_float16 (tree node)
+{
+ if (!TYPE_NAME (node) || TREE_CODE (TYPE_NAME (node)) != TYPE_DECL)
+return false;
+
+ tree name = DECL_NAME (TYPE_NAME (node));
+
+ if (IDENTIFIER_POINTER (name) [0] != '_')
+return false;
+
+ return id_equal (name, "__bf16");
+}
+
/* Return true if NODE is the _Float32/_Float32x type. */
static bool
@@ -2210,7 +2226,12 @@ dump_ada_node (pretty_printer *pp, tree node, tree type,
int spc,
break;
case REAL_TYPE:
- if (is_float32 (node))
+ if (is_float16 (node))
+ {
+ pp_string (pp, "Short_Float");
+ break;
+ }
+ else if (is_float32 (node))
{
pp_string (pp, "Float");
break;
[gcc(refs/users/meissner/heads/work169)] Update ChangeLog.*
https://gcc.gnu.org/g:f658db2e992a5db2206b519351836a76df864edb commit f658db2e992a5db2206b519351836a76df864edb Author: Michael Meissner Date: Mon Jun 17 16:16:20 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 72 +++--- 1 file changed, 68 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index df288b5cdf30..9e0d3f523da9 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,67 @@ + Branch work169, patch #11 + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-06-17 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work169, patch #10 + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-06-17 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + Branch work169, patch #3 Add -mcpu=power11 tests. @@ -6,7 +70,7 @@ This patch adds some simple tests for -mcpu=power11 support. In order to run these tests, you need an assembler that supports the appropriate option for supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). -2024-06-03 Michael Meissner +2024-06-17 Michael Meissner gcc/testsuite/ @@ -22,7 +86,7 @@ Add -mcpu=power11 tuning support. This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. -2024-06-03 Michael Meissner +2024-06-17 Michael Meissner gcc/ @@ -51,7 +115,7 @@ This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. This patch adds support for using "power11" in the __builtin_cpu_is built-in function. -2024-06-03 Michael Meissner +2024-06-17 Michael Meissner gcc/ @@ -89,7 +153,7 @@ gcc/ Add ChangeLog.meissner and REVISION. -2024-06-03 Michael Meissner +2024-06-17 Michael Meissner gcc/
[gcc(refs/users/meissner/heads/work169)] Add -mcpu=future tuning support.
https://gcc.gnu.org/g:2a14f1136021581890d55530eb115b53e7ea8baf commit 2a14f1136021581890d55530eb115b53e7ea8baf Author: Michael Meissner Date: Mon Jun 17 16:14:22 2024 -0400 Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=power11. 2024-06-17 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add future as an alterntive to power10 and power11. Diff: --- gcc/config/rs6000/power10.md | 145 ++- 1 file changed, 73 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index 90312643858e..1ec1bef07260 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,5 @@ -;; Scheduling description for the IBM POWER10 and POWER11 processors. +;; Scheduling description for the IBM POWER10 and POWER11 processors as well as +;; potential future processors. ;; Copyright (C) 2020-2024 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +98,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +111,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +125,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +133,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +149,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +179,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +192,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") ; Update fo
[gcc(refs/users/meissner/heads/work169)] Add -mcpu=future support.
https://gcc.gnu.org/g:5d5b20e7c7c8daa814bddea2403f4bfa1ac28584
commit 5d5b20e7c7c8daa814bddea2403f4bfa1ac28584
Author: Michael Meissner
Date: Mon Jun 17 16:13:39 2024 -0400
Add -mcpu=future support.
This patch adds the future option to the -mcpu= and -mtune= switches.
This patch treats the future like a power11 in terms of costs and
reassociation
width.
This patch issues a ".machine future" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.
This patch allows GCC to be configured with the --with-cpu=future and
--with-tune=future options.
This patch passes -mfuture to the assembler if the user uses -mcpu=future.
2024-06-17 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR_FUTURE if -mcpu=future.
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add future isa bit.
(power11 cpu): Add future definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future
processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
future
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add future.
* config/rs6000/rs6000.opt (-mpower11): Add internal future ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=future.
Diff:
---
gcc/config.gcc | 4 ++--
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 30 ++
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 2 +-
15 files changed, 48 insertions(+), 13 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 1364bc7b3611..b297f68dad26 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -534,7 +534,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
- | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 |
xe500mc64 \
| xe5500 | xe6500)
cpu_is_64bit=yes
;;
@@ -5623,7 +5623,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power1[01] | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x |
future \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d7..570ddcc451db 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b48..242ca94bd065 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {
[gcc(refs/users/meissner/heads/work169)] Update ChangeLog.*
https://gcc.gnu.org/g:e12fe322f319695b3aca784268fd0547b7378ba7 commit e12fe322f319695b3aca784268fd0547b7378ba7 Author: Michael Meissner Date: Mon Jun 17 16:12:24 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 121 - 1 file changed, 120 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index ef7eaa6f006f..df288b5cdf30 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,6 +1,125 @@ + Branch work169, patch #3 + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-06-03 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): Add new + effective target. + + Branch work169, patch #2 + +Add -mcpu=power11 tuning support. + +This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. + +2024-06-03 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add power11 as an + alternative to power10. + + Branch work169, patch #1 + +Add -mcpu=power11 support. + +This patch adds the power11 option to the -mcpu= and -mtune= switches. + +This patch treats the power11 like a power10 in terms of costs and reassociation +width. + +This patch issues a ".machine power11" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. + +This patch allows GCC to be configured with the --with-cpu=power11 and +--with-tune=power11 options. + +This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. + +This patch adds support for using "power11" in the __builtin_cpu_is built-in +function. + +2024-06-03 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define. + * config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR11 if -mcpu=power11. + * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New define. + (POWERPC_MASKS): Add power11 isa bit. + (power11 cpu): Add power11 definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11 + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add power11. + * config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11. + Branch work169, baseline +Add ChangeLog.meissner and REVISION. + +2024-06-03 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + 2024-06-17 Michael Meissner Clone branch -
[gcc r15-1384] diagnostics: Fix add_misspelling_candidates [PR115440]
https://gcc.gnu.org/g:96db57948b50f45235ae4af3b46db66cae7ea859
commit r15-1384-g96db57948b50f45235ae4af3b46db66cae7ea859
Author: Jakub Jelinek
Date: Mon Jun 17 22:02:46 2024 +0200
diagnostics: Fix add_misspelling_candidates [PR115440]
The option_map array for most entries contains just non-NULL opt0
{ "-Wno-", NULL, "-W", false, true },
{ "-fno-", NULL, "-f", false, true },
{ "-gno-", NULL, "-g", false, true },
{ "-mno-", NULL, "-m", false, true },
{ "--debug=", NULL, "-g", false, false },
{ "--machine-", NULL, "-m", true, false },
{ "--machine-no-", NULL, "-m", false, true },
{ "--machine=", NULL, "-m", false, false },
{ "--machine=no-", NULL, "-m", false, true },
{ "--machine", "", "-m", false, false },
{ "--machine", "no-", "-m", false, true },
{ "--optimize=", NULL, "-O", false, false },
{ "--std=", NULL, "-std=", false, false },
{ "--std", "", "-std=", false, false },
{ "--warn-", NULL, "-W", true, false },
{ "--warn-no-", NULL, "-W", false, true },
{ "--", NULL, "-f", true, false },
{ "--no-", NULL, "-f", false, true }
and so add_misspelling_candidates works correctly for it, but 3 out of
these,
{ "--machine", "", "-m", false, false },
{ "--machine", "no-", "-m", false, true },
and
{ "--std", "", "-std=", false, false },
use non-NULL opt1. That says that
--machine foo
should map to
-mfoo
and
--machine no-foo
should map to
-mno-foo
and
--std c++17
should map to
-std=c++17
add_misspelling_canidates was not handling this, so it hapilly
registered say
--stdc++17
or
--machineavx512
(twice) as spelling alternatives, when those options aren't recognized.
Instead we support
--std c++17
or
--machine avx512
--machine no-avx512
The following patch fixes that. On this particular testcase, we no longer
suggest anything, even when among the suggestion is say that
--std c++17
or
-std=c++17
etc.
2024-06-17 Jakub Jelinek
PR driver/115440
* opts-common.cc (add_misspelling_candidates): If opt1 is non-NULL,
add a space and opt1 to the alternative suggestion text.
* g++.dg/cpp1z/pr115440.C: New test.
Diff:
---
gcc/opts-common.cc| 6 --
gcc/testsuite/g++.dg/cpp1z/pr115440.C | 8
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/gcc/opts-common.cc b/gcc/opts-common.cc
index 14084d08b05a..fcabc27dd542 100644
--- a/gcc/opts-common.cc
+++ b/gcc/opts-common.cc
@@ -524,6 +524,7 @@ add_misspelling_candidates (auto_vec *candidates,
for (unsigned i = 0; i < ARRAY_SIZE (option_map); i++)
{
const char *opt0 = option_map[i].opt0;
+ const char *opt1 = option_map[i].opt1;
const char *new_prefix = option_map[i].new_prefix;
size_t new_prefix_len = strlen (new_prefix);
@@ -532,8 +533,9 @@ add_misspelling_candidates (auto_vec *candidates,
if (strncmp (opt_text, new_prefix, new_prefix_len) == 0)
{
- char *alternative = concat (opt0 + 1, opt_text + new_prefix_len,
- NULL);
+ char *alternative
+ = concat (opt0 + 1, opt1 ? " " : "", opt1 ? opt1 : "",
+ opt_text + new_prefix_len, NULL);
candidates->safe_push (alternative);
}
}
diff --git a/gcc/testsuite/g++.dg/cpp1z/pr115440.C
b/gcc/testsuite/g++.dg/cpp1z/pr115440.C
new file mode 100644
index ..788d4806fe2d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp1z/pr115440.C
@@ -0,0 +1,8 @@
+// PR driver/115440
+// { dg-do compile { target c++17_only } }
+// { dg-options "--c++17" }
+
+int i;
+
+// { dg-bogus "unrecognized command-line option '--c\\\+\\\+17'; did you mean
'--stdc\\\+\\\+17'" "" { target *-*-* } 0 }
+// { dg-error "unrecognized command-line option '--c\\\+\\\+17'" "" { target
*-*-* } 0 }
[gcc r15-1383] vshuf-mem.C: Make -march=z14 depend on s390_vxe
https://gcc.gnu.org/g:7e59f0c05da840ca13ba73d25947df8a4eaf199e
commit r15-1383-g7e59f0c05da840ca13ba73d25947df8a4eaf199e
Author: Andreas Krebbel
Date: Mon Jun 17 21:50:27 2024 +0200
vshuf-mem.C: Make -march=z14 depend on s390_vxe
gcc/testsuite/ChangeLog:
* g++.dg/torture/vshuf-mem.C: Use -march=z14 only, if the we are
on a machine which can actually run it.
Diff:
---
gcc/testsuite/g++.dg/torture/vshuf-mem.C | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/g++.dg/torture/vshuf-mem.C
b/gcc/testsuite/g++.dg/torture/vshuf-mem.C
index 6d892f876be5..1d828e33a140 100644
--- a/gcc/testsuite/g++.dg/torture/vshuf-mem.C
+++ b/gcc/testsuite/g++.dg/torture/vshuf-mem.C
@@ -1,6 +1,6 @@
// { dg-options "-std=c++11 -Wno-psabi" }
// { dg-do run }
-// { dg-additional-options "-march=z14" { target s390*-*-* } }
+// { dg-additional-options "-march=z14" { target s390_vxe } }
/* This used to trigger (2024-05-28) the vectorize_vec_perm_const
backend hook to be invoked with a MEM source operand. Extracted
[gcc r15-1382] c: Implement C2Y alignof on incomplete arrays
https://gcc.gnu.org/g:edf514f83fa41012e52aaef2faef5a649e4b3f6d
commit r15-1382-gedf514f83fa41012e52aaef2faef5a649e4b3f6d
Author: Joseph Myers
Date: Mon Jun 17 19:45:43 2024 +
c: Implement C2Y alignof on incomplete arrays
C2Y has adopted support for alignof applied to incomplete array types
(N3273). Add this support to GCC. As the relevant checks are in
c-family code that doesn't have access to functions such as
pedwarn_c23, this remains a hard error for older versions and isn't
handled by -Wc23-c2y-compat, although preferably it would work like
pedwarn_c23 (pedwarn-if-pedantic for older versions, warning with
-Wc23-c2y-compat in C2Y mode).
Bootstrapped with no regressions for x86_64-pc-linux-gnu.
gcc/c-family/
* c-common.cc (c_sizeof_or_alignof_type): Allow alignof on an
incomplete array type for C2Y.
gcc/testsuite/
* gcc.dg/c23-align-10.c, gcc.dg/c2y-align-1.c,
gcc.dg/c2y-align-2.c: New tests.
Diff:
---
gcc/c-family/c-common.cc| 4 +++-
gcc/testsuite/gcc.dg/c23-align-10.c | 6 ++
gcc/testsuite/gcc.dg/c2y-align-1.c | 6 ++
gcc/testsuite/gcc.dg/c2y-align-2.c | 8
4 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/gcc/c-family/c-common.cc b/gcc/c-family/c-common.cc
index 24335deeb582..7d752acd430c 100644
--- a/gcc/c-family/c-common.cc
+++ b/gcc/c-family/c-common.cc
@@ -3972,7 +3972,9 @@ c_sizeof_or_alignof_type (location_t loc,
value = size_one_node;
}
else if (!COMPLETE_TYPE_P (type)
- && (!c_dialect_cxx () || is_sizeof || type_code != ARRAY_TYPE))
+ && ((!c_dialect_cxx () && !flag_isoc2y)
+ || is_sizeof
+ || type_code != ARRAY_TYPE))
{
if (complain)
error_at (loc, "invalid application of %qs to incomplete type %qT",
diff --git a/gcc/testsuite/gcc.dg/c23-align-10.c
b/gcc/testsuite/gcc.dg/c23-align-10.c
new file mode 100644
index ..bd6b9c268c3a
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/c23-align-10.c
@@ -0,0 +1,6 @@
+/* Test C2Y alignof on an incomplete array type: not allowed in C23. */
+/* { dg-do compile } */
+/* { dg-options "-std=c23 -pedantic-errors" } */
+
+int a = alignof(int[]); /* { dg-error "incomplete" } */
+int b = alignof(int[][1]); /* { dg-error "incomplete" } */
diff --git a/gcc/testsuite/gcc.dg/c2y-align-1.c
b/gcc/testsuite/gcc.dg/c2y-align-1.c
new file mode 100644
index ..3f9ab18c5186
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/c2y-align-1.c
@@ -0,0 +1,6 @@
+/* Test C2Y alignof on an incomplete array type. */
+/* { dg-do compile } */
+/* { dg-options "-std=c2y -pedantic-errors" } */
+
+int a = alignof(int[]);
+int b = alignof(int[][1]);
diff --git a/gcc/testsuite/gcc.dg/c2y-align-2.c
b/gcc/testsuite/gcc.dg/c2y-align-2.c
new file mode 100644
index ..b7b871504137
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/c2y-align-2.c
@@ -0,0 +1,8 @@
+/* Test C2Y alignof on an incomplete array type: still not allowed for other
+ incomplete types. */
+/* { dg-do compile } */
+/* { dg-options "-std=c2y -pedantic-errors" } */
+
+int a = alignof(void); /* { dg-error "void" } */
+struct s;
+int b = alignof(struct s); /* { dg-error "incomplete" } */
[gcc(refs/users/meissner/heads/work169)] Add -mcpu=power11 tests.
https://gcc.gnu.org/g:cf9375b72fdcbfef6a10c0c5ba32f641a60005de
commit cf9375b72fdcbfef6a10c0c5ba32f641a60005de
Author: Michael Meissner
Date: Mon Jun 17 14:50:47 2024 -0400
Add -mcpu=power11 tests.
This patch adds some simple tests for -mcpu=power11 support. In order to
run
these tests, you need an assembler that supports the appropriate option for
supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under
AIX).
2024-06-17 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/power11-1.c: New test.
* gcc.target/powerpc/power11-2.c: Likewise.
* gcc.target/powerpc/power11-3.c: Likewise.
* lib/target-supports.exp (check_effective_target_power11_ok): Add
new
effective target.
Diff:
---
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +
gcc/testsuite/gcc.target/powerpc/power11-2.c | 21 +
gcc/testsuite/gcc.target/powerpc/power11-3.c | 11 +++
gcc/testsuite/lib/target-supports.exp| 17 +
4 files changed, 62 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
new file mode 100644
index ..2dd0f64ead1a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=power11. */
+
+#ifndef _ARCH_PWR11
+#error "-mcpu=power11 is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
new file mode 100644
index ..625031e91465
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-2.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-require-effective-target target_clone } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the power11 target via a target attribute. */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
new file mode 100644
index ..b0f245eea035
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c
@@ -0,0 +1,11 @@
+/* { dg-do assemble { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-require-effective-target target_clone } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Check if we can set the power11 target via a target_clones attribute. */
+
+__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index e307f4e69efb..9d0314afe59a 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7129,6 +7129,23 @@ proc check_effective_target_power10_ok { } {
}
}
+# Return 1 if this is a PowerPC target supporting -mcpu=power11.
+
+proc check_effective_target_power11_ok { } {
+if { ([istarget powerpc*-*-*]) } {
+ return [check_no_compiler_messages power11_ok object {
+ int main (void) {
+ #ifndef _ARCH_PWR11
+ #error "-mcpu=power11 is not supported"
+ #endif
+ return 0;
+ }
+ } "-mcpu=power11"]
+} else {
+ return 0
+}
+}
+
# Return 1 if this is a PowerPC target supporting -mfloat128 via either
# software emulation on power7/power8 systems or hardware support on power9.
[gcc(refs/users/meissner/heads/work169)] Add -mcpu=power11 support.
https://gcc.gnu.org/g:05dfc843bde7a9f828d6ab8993121f73ec4df5d4
commit 05dfc843bde7a9f828d6ab8993121f73ec4df5d4
Author: Michael Meissner
Date: Mon Jun 17 14:40:40 2024 -0400
Add -mcpu=power11 support.
This patch adds the power11 option to the -mcpu= and -mtune= switches.
This patch treats the power11 like a power10 in terms of costs and
reassociation
width.
This patch issues a ".machine power11" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
This patch allows GCC to be configured with the --with-cpu=power11 and
--with-tune=power11 options.
This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.
This patch adds support for using "power11" in the __builtin_cpu_is built-in
function.
2024-06-17 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
* config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR11 if -mcpu=power11.
* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add power11 isa bit.
(power11 cpu): Add power11 definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11
processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
power11
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add power11.
* config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=power11.
Diff:
---
gcc/config.gcc | 6 --
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/ppc-auxv.h| 3 +--
gcc/config/rs6000/rs6000-builtin.cc | 1 +
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 32
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 5 +++--
17 files changed, 56 insertions(+), 16 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index e500ba63e322..1364bc7b3611 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -533,7 +533,9 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+ xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
+ | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xe5500 | xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5621,7 +5623,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power10 | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 24bc301e37d6..41037b3852d7 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ d
[gcc(refs/users/meissner/heads/work169)] Add -mcpu=power11 tuning support.
https://gcc.gnu.org/g:9492c1b39d1cb415af28f36c09e3fbf0fc28c902 commit 9492c1b39d1cb415af28f36c09e3fbf0fc28c902 Author: Michael Meissner Date: Mon Jun 17 14:41:20 2024 -0400 Add -mcpu=power11 tuning support. This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. 2024-06-17 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add power11 as an alternative to power10. Diff: --- gcc/config/rs6000/power10.md | 144 +-- 1 file changed, 72 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index fcc2199ab291..90312643858e 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,4 @@ -;; Scheduling description for the IBM POWER10 processor. +;; Scheduling description for the IBM POWER10 and POWER11 processors. ;; Copyright (C) 2020-2024 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated addr reg (define_insn_reservation "power10-store-update" 2 (and (eq_attr "type" "store,fpstore") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_p
[gcc r13-8854] c-family: Fix -Warray-compare warning ICE [PR115290]
https://gcc.gnu.org/g:be14e6cf7f2dc23012dfced0a4aff0894fd6ff57
commit r13-8854-gbe14e6cf7f2dc23012dfced0a4aff0894fd6ff57
Author: Jakub Jelinek
Date: Mon Jun 17 19:24:05 2024 +0200
c-family: Fix -Warray-compare warning ICE [PR115290]
The warning code uses %D to print the ARRAY_REF first operands.
That works in the most common case where those operands are decls, but
as can be seen on the following testcase, they can be other expressions
with array type.
Just changing %D to %E isn't enough, because then the diagnostics can
suggest something like
note: use '&(x) != 0 ? (int (*)[32])&a : (int (*)[32])&b[0] == &(y) != 0 ?
(int (*)[32])&a : (int (*)[32])&b[0]' to compare the addresses
which is a bad suggestion, the %E printing doesn't know that the
warning code will want to add & before it and [0] after it.
So, the following patch adds ()s around the operand as well, but does
that only for non-decls, for decls keeps it as &arr[0] like before.
2024-06-17 Jakub Jelinek
PR c/115290
* c-warn.cc (do_warn_array_compare): Use %E rather than %D for
printing op0 and op1; if those operands aren't decls, also print
parens around them.
* c-c++-common/Warray-compare-3.c: New test.
(cherry picked from commit b63c7d92012f92e0517190cf263d29bbef8a06bf)
Diff:
---
gcc/c-family/c-warn.cc| 13 +
gcc/testsuite/c-c++-common/Warray-compare-3.c | 13 +
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/gcc/c-family/c-warn.cc b/gcc/c-family/c-warn.cc
index 9ac43a1af6ef..6ee96edfd239 100644
--- a/gcc/c-family/c-warn.cc
+++ b/gcc/c-family/c-warn.cc
@@ -3827,11 +3827,16 @@ do_warn_array_compare (location_t location, tree_code
code, tree op0, tree op1)
/* C doesn't allow +arr. */
if (c_dialect_cxx ())
inform (location, "use unary %<+%> which decays operands to pointers "
- "or %<&%D[0] %s &%D[0]%> to compare the addresses",
- op0, op_symbol_code (code), op1);
+ "or %<&%s%E%s[0] %s &%s%E%s[0]%> to compare the addresses",
+ DECL_P (op0) ? "" : "(", op0, DECL_P (op0) ? "" : ")",
+ op_symbol_code (code),
+ DECL_P (op1) ? "" : "(", op1, DECL_P (op1) ? "" : ")");
else
- inform (location, "use %<&%D[0] %s &%D[0]%> to compare the addresses",
- op0, op_symbol_code (code), op1);
+ inform (location,
+ "use %<&%s%E%s[0] %s &%s%E%s[0]%> to compare the addresses",
+ DECL_P (op0) ? "" : "(", op0, DECL_P (op0) ? "" : ")",
+ op_symbol_code (code),
+ DECL_P (op1) ? "" : "(", op1, DECL_P (op1) ? "" : ")");
}
}
diff --git a/gcc/testsuite/c-c++-common/Warray-compare-3.c
b/gcc/testsuite/c-c++-common/Warray-compare-3.c
new file mode 100644
index ..4725aa2b38bf
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/Warray-compare-3.c
@@ -0,0 +1,13 @@
+/* PR c/115290 */
+/* { dg-do compile } */
+/* { dg-options "-Warray-compare" } */
+
+int a[32][32], b[32][32];
+
+int
+foo (int x, int y)
+{
+ return (x ? a : b) == (y ? a : b); /* { dg-warning "comparison between two
arrays" } */
+/* { dg-message "use '&\\\(\[^\n\r]*\\\)\\\[0\\\] ==
&\\\(\[^\n\r]*\\\)\\\[0\\\]' to compare the addresses" "" { target c } .-1 } */
+/* { dg-message "use unary '\\\+' which decays operands to pointers or
'&\\\(\[^\n\r]*\\\)\\\[0\\\] == &\\\(\[^\n\r]*\\\)\\\[0\\\]' to compare the
addresses" "" { target c++ } .-2 } */
+}
[gcc r14-10322] c-family: Fix -Warray-compare warning ICE [PR115290]
https://gcc.gnu.org/g:922648759b034c356e7d5c1ae530bdb6f3d00c62
commit r14-10322-g922648759b034c356e7d5c1ae530bdb6f3d00c62
Author: Jakub Jelinek
Date: Mon Jun 17 19:24:05 2024 +0200
c-family: Fix -Warray-compare warning ICE [PR115290]
The warning code uses %D to print the ARRAY_REF first operands.
That works in the most common case where those operands are decls, but
as can be seen on the following testcase, they can be other expressions
with array type.
Just changing %D to %E isn't enough, because then the diagnostics can
suggest something like
note: use '&(x) != 0 ? (int (*)[32])&a : (int (*)[32])&b[0] == &(y) != 0 ?
(int (*)[32])&a : (int (*)[32])&b[0]' to compare the addresses
which is a bad suggestion, the %E printing doesn't know that the
warning code will want to add & before it and [0] after it.
So, the following patch adds ()s around the operand as well, but does
that only for non-decls, for decls keeps it as &arr[0] like before.
2024-06-17 Jakub Jelinek
PR c/115290
* c-warn.cc (do_warn_array_compare): Use %E rather than %D for
printing op0 and op1; if those operands aren't decls, also print
parens around them.
* c-c++-common/Warray-compare-3.c: New test.
(cherry picked from commit b63c7d92012f92e0517190cf263d29bbef8a06bf)
Diff:
---
gcc/c-family/c-warn.cc| 13 +
gcc/testsuite/c-c++-common/Warray-compare-3.c | 13 +
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/gcc/c-family/c-warn.cc b/gcc/c-family/c-warn.cc
index bff87be05ae3..8fc0d8a53b35 100644
--- a/gcc/c-family/c-warn.cc
+++ b/gcc/c-family/c-warn.cc
@@ -3830,11 +3830,16 @@ do_warn_array_compare (location_t location, tree_code
code, tree op0, tree op1)
/* C doesn't allow +arr. */
if (c_dialect_cxx ())
inform (location, "use unary %<+%> which decays operands to pointers "
- "or %<&%D[0] %s &%D[0]%> to compare the addresses",
- op0, op_symbol_code (code), op1);
+ "or %<&%s%E%s[0] %s &%s%E%s[0]%> to compare the addresses",
+ DECL_P (op0) ? "" : "(", op0, DECL_P (op0) ? "" : ")",
+ op_symbol_code (code),
+ DECL_P (op1) ? "" : "(", op1, DECL_P (op1) ? "" : ")");
else
- inform (location, "use %<&%D[0] %s &%D[0]%> to compare the addresses",
- op0, op_symbol_code (code), op1);
+ inform (location,
+ "use %<&%s%E%s[0] %s &%s%E%s[0]%> to compare the addresses",
+ DECL_P (op0) ? "" : "(", op0, DECL_P (op0) ? "" : ")",
+ op_symbol_code (code),
+ DECL_P (op1) ? "" : "(", op1, DECL_P (op1) ? "" : ")");
}
}
diff --git a/gcc/testsuite/c-c++-common/Warray-compare-3.c
b/gcc/testsuite/c-c++-common/Warray-compare-3.c
new file mode 100644
index ..4725aa2b38bf
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/Warray-compare-3.c
@@ -0,0 +1,13 @@
+/* PR c/115290 */
+/* { dg-do compile } */
+/* { dg-options "-Warray-compare" } */
+
+int a[32][32], b[32][32];
+
+int
+foo (int x, int y)
+{
+ return (x ? a : b) == (y ? a : b); /* { dg-warning "comparison between two
arrays" } */
+/* { dg-message "use '&\\\(\[^\n\r]*\\\)\\\[0\\\] ==
&\\\(\[^\n\r]*\\\)\\\[0\\\]' to compare the addresses" "" { target c } .-1 } */
+/* { dg-message "use unary '\\\+' which decays operands to pointers or
'&\\\(\[^\n\r]*\\\)\\\[0\\\] == &\\\(\[^\n\r]*\\\)\\\[0\\\]' to compare the
addresses" "" { target c++ } .-2 } */
+}
[gcc r15-1381] c-family: Fix -Warray-compare warning ICE [PR115290]
https://gcc.gnu.org/g:b63c7d92012f92e0517190cf263d29bbef8a06bf
commit r15-1381-gb63c7d92012f92e0517190cf263d29bbef8a06bf
Author: Jakub Jelinek
Date: Mon Jun 17 19:24:05 2024 +0200
c-family: Fix -Warray-compare warning ICE [PR115290]
The warning code uses %D to print the ARRAY_REF first operands.
That works in the most common case where those operands are decls, but
as can be seen on the following testcase, they can be other expressions
with array type.
Just changing %D to %E isn't enough, because then the diagnostics can
suggest something like
note: use '&(x) != 0 ? (int (*)[32])&a : (int (*)[32])&b[0] == &(y) != 0 ?
(int (*)[32])&a : (int (*)[32])&b[0]' to compare the addresses
which is a bad suggestion, the %E printing doesn't know that the
warning code will want to add & before it and [0] after it.
So, the following patch adds ()s around the operand as well, but does
that only for non-decls, for decls keeps it as &arr[0] like before.
2024-06-17 Jakub Jelinek
PR c/115290
* c-warn.cc (do_warn_array_compare): Use %E rather than %D for
printing op0 and op1; if those operands aren't decls, also print
parens around them.
* c-c++-common/Warray-compare-3.c: New test.
Diff:
---
gcc/c-family/c-warn.cc| 13 +
gcc/testsuite/c-c++-common/Warray-compare-3.c | 13 +
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/gcc/c-family/c-warn.cc b/gcc/c-family/c-warn.cc
index 7ddf6ea2ad8e..5e4fb7f0f0a9 100644
--- a/gcc/c-family/c-warn.cc
+++ b/gcc/c-family/c-warn.cc
@@ -3832,11 +3832,16 @@ do_warn_array_compare (location_t location, tree_code
code, tree op0, tree op1)
/* C doesn't allow +arr. */
if (c_dialect_cxx ())
inform (location, "use unary %<+%> which decays operands to pointers "
- "or %<&%D[0] %s &%D[0]%> to compare the addresses",
- op0, op_symbol_code (code), op1);
+ "or %<&%s%E%s[0] %s &%s%E%s[0]%> to compare the addresses",
+ DECL_P (op0) ? "" : "(", op0, DECL_P (op0) ? "" : ")",
+ op_symbol_code (code),
+ DECL_P (op1) ? "" : "(", op1, DECL_P (op1) ? "" : ")");
else
- inform (location, "use %<&%D[0] %s &%D[0]%> to compare the addresses",
- op0, op_symbol_code (code), op1);
+ inform (location,
+ "use %<&%s%E%s[0] %s &%s%E%s[0]%> to compare the addresses",
+ DECL_P (op0) ? "" : "(", op0, DECL_P (op0) ? "" : ")",
+ op_symbol_code (code),
+ DECL_P (op1) ? "" : "(", op1, DECL_P (op1) ? "" : ")");
}
}
diff --git a/gcc/testsuite/c-c++-common/Warray-compare-3.c
b/gcc/testsuite/c-c++-common/Warray-compare-3.c
new file mode 100644
index ..4725aa2b38bf
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/Warray-compare-3.c
@@ -0,0 +1,13 @@
+/* PR c/115290 */
+/* { dg-do compile } */
+/* { dg-options "-Warray-compare" } */
+
+int a[32][32], b[32][32];
+
+int
+foo (int x, int y)
+{
+ return (x ? a : b) == (y ? a : b); /* { dg-warning "comparison between two
arrays" } */
+/* { dg-message "use '&\\\(\[^\n\r]*\\\)\\\[0\\\] ==
&\\\(\[^\n\r]*\\\)\\\[0\\\]' to compare the addresses" "" { target c } .-1 } */
+/* { dg-message "use unary '\\\+' which decays operands to pointers or
'&\\\(\[^\n\r]*\\\)\\\[0\\\] == &\\\(\[^\n\r]*\\\)\\\[0\\\]' to compare the
addresses" "" { target c++ } .-2 } */
+}
[gcc r13-8853] c++: Fix up floating point conversion rank comparison for _Float32 and float if float/double are sam
https://gcc.gnu.org/g:6d0a0c547a6c8425d432129fc90869305fef7bc2
commit r13-8853-g6d0a0c547a6c8425d432129fc90869305fef7bc2
Author: Jakub Jelinek
Date: Mon Jun 17 18:53:21 2024 +0200
c++: Fix up floating point conversion rank comparison for _Float32 and
float if float/double are same size [PR115511]
On AVR and SH with some options sizeof (float) == sizeof (double) and
the 2 types have the same set of values.
http://eel.is/c++draft/conv.rank#2.2 for this says that double still
has bigger rank than float and http://eel.is/c++draft/conv.rank#2.2
says that extended type with the same set of values as more than one
standard floating point type shall have the same rank as double.
I've implemented the latter rule as
if (cnt > 1 && mv2 == long_double_type_node)
return -2;
with the _Float64/double/long double case having same mode case (various
targets with -mlong-double-64) in mind.
But never thought there are actually targets where float and double
are the same, that needs handling too, if cnt > 1 (that is the extended
type mv1 has same set of values as 2 or 3 of float/double/long double)
and mv2 is float, we need to return 2, because mv1 in that case should
have same rank as double and double has bigger rank than float.
2024-06-17 Jakub Jelinek
PR target/111343
PR c++/115511
* typeck.cc (cp_compare_floating_point_conversion_ranks): If an
extended floating point type mv1 has same set of values as more
than one standard floating point type and mv2 is float, return 2.
* g++.dg/cpp23/ext-floating18.C: New test.
(cherry picked from commit 8584c98f370cd91647c184ce58141508ca478a12)
Diff:
---
gcc/cp/typeck.cc| 3 +++
gcc/testsuite/g++.dg/cpp23/ext-floating18.C | 26 ++
2 files changed, 29 insertions(+)
diff --git a/gcc/cp/typeck.cc b/gcc/cp/typeck.cc
index 81bc9edd9551..470bb2ee5f71 100644
--- a/gcc/cp/typeck.cc
+++ b/gcc/cp/typeck.cc
@@ -393,6 +393,9 @@ cp_compare_floating_point_conversion_ranks (tree t1, tree
t2)
has higher rank. */
if (cnt > 1 && mv2 == long_double_type_node)
return -2;
+ /* And similarly if t2 is float, t2 has lower rank. */
+ if (cnt > 1 && mv2 == float_type_node)
+return 2;
/* Otherwise, they have equal rank, but extended types
(other than std::bfloat16_t) have higher subrank.
std::bfloat16_t shouldn't have equal rank to any standard
diff --git a/gcc/testsuite/g++.dg/cpp23/ext-floating18.C
b/gcc/testsuite/g++.dg/cpp23/ext-floating18.C
new file mode 100644
index ..ece25464bfdf
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp23/ext-floating18.C
@@ -0,0 +1,26 @@
+// P1467R9 - Extended floating-point types and standard names.
+// { dg-do compile { target c++23 } }
+// { dg-options "" }
+// { dg-add-options float32 }
+
+constexpr int foo (float) { return 1; }
+constexpr int foo (double) { return 2; }
+constexpr int foo (long double) { return 3; }
+
+#ifdef __STDCPP_FLOAT32_T__
+#if __FLT_MAX_EXP__ == __FLT32_MAX_EXP__ \
+&& __FLT_MAX_DIG__ == __FLT32_MAX_DIG__
+#if __FLT_MAX_EXP__ == __DBL_MAX_EXP__ \
+&& __FLT_MAX_DIG__ == __DBL_MAX_DIG__
+static_assert (foo (1.0f32) == 2);
+#else
+static_assert (foo (1.0f32) == 1);
+#endif
+#endif
+#endif
+#ifdef __STDCPP_FLOAT64_T__
+#if __DBL_MAX_EXP__ == __FLT64_MAX_EXP__ \
+&& __DBL_MAX_DIG__ == __FLT64_MAX_DIG__
+static_assert (foo (1.0f64) == 2);
+#endif
+#endif
[gcc r14-10321] c++: Fix up floating point conversion rank comparison for _Float32 and float if float/double are sam
https://gcc.gnu.org/g:5be6d9d2a9854c05f3c019deb9fe95eca7248140
commit r14-10321-g5be6d9d2a9854c05f3c019deb9fe95eca7248140
Author: Jakub Jelinek
Date: Mon Jun 17 18:53:21 2024 +0200
c++: Fix up floating point conversion rank comparison for _Float32 and
float if float/double are same size [PR115511]
On AVR and SH with some options sizeof (float) == sizeof (double) and
the 2 types have the same set of values.
http://eel.is/c++draft/conv.rank#2.2 for this says that double still
has bigger rank than float and http://eel.is/c++draft/conv.rank#2.2
says that extended type with the same set of values as more than one
standard floating point type shall have the same rank as double.
I've implemented the latter rule as
if (cnt > 1 && mv2 == long_double_type_node)
return -2;
with the _Float64/double/long double case having same mode case (various
targets with -mlong-double-64) in mind.
But never thought there are actually targets where float and double
are the same, that needs handling too, if cnt > 1 (that is the extended
type mv1 has same set of values as 2 or 3 of float/double/long double)
and mv2 is float, we need to return 2, because mv1 in that case should
have same rank as double and double has bigger rank than float.
2024-06-17 Jakub Jelinek
PR target/111343
PR c++/115511
* typeck.cc (cp_compare_floating_point_conversion_ranks): If an
extended floating point type mv1 has same set of values as more
than one standard floating point type and mv2 is float, return 2.
* g++.dg/cpp23/ext-floating18.C: New test.
(cherry picked from commit 8584c98f370cd91647c184ce58141508ca478a12)
Diff:
---
gcc/cp/typeck.cc| 3 +++
gcc/testsuite/g++.dg/cpp23/ext-floating18.C | 26 ++
2 files changed, 29 insertions(+)
diff --git a/gcc/cp/typeck.cc b/gcc/cp/typeck.cc
index a25f8622651d..42578beb85be 100644
--- a/gcc/cp/typeck.cc
+++ b/gcc/cp/typeck.cc
@@ -393,6 +393,9 @@ cp_compare_floating_point_conversion_ranks (tree t1, tree
t2)
has higher rank. */
if (cnt > 1 && mv2 == long_double_type_node)
return -2;
+ /* And similarly if t2 is float, t2 has lower rank. */
+ if (cnt > 1 && mv2 == float_type_node)
+return 2;
/* Otherwise, they have equal rank, but extended types
(other than std::bfloat16_t) have higher subrank.
std::bfloat16_t shouldn't have equal rank to any standard
diff --git a/gcc/testsuite/g++.dg/cpp23/ext-floating18.C
b/gcc/testsuite/g++.dg/cpp23/ext-floating18.C
new file mode 100644
index ..ece25464bfdf
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp23/ext-floating18.C
@@ -0,0 +1,26 @@
+// P1467R9 - Extended floating-point types and standard names.
+// { dg-do compile { target c++23 } }
+// { dg-options "" }
+// { dg-add-options float32 }
+
+constexpr int foo (float) { return 1; }
+constexpr int foo (double) { return 2; }
+constexpr int foo (long double) { return 3; }
+
+#ifdef __STDCPP_FLOAT32_T__
+#if __FLT_MAX_EXP__ == __FLT32_MAX_EXP__ \
+&& __FLT_MAX_DIG__ == __FLT32_MAX_DIG__
+#if __FLT_MAX_EXP__ == __DBL_MAX_EXP__ \
+&& __FLT_MAX_DIG__ == __DBL_MAX_DIG__
+static_assert (foo (1.0f32) == 2);
+#else
+static_assert (foo (1.0f32) == 1);
+#endif
+#endif
+#endif
+#ifdef __STDCPP_FLOAT64_T__
+#if __DBL_MAX_EXP__ == __FLT64_MAX_EXP__ \
+&& __DBL_MAX_DIG__ == __FLT64_MAX_DIG__
+static_assert (foo (1.0f64) == 2);
+#endif
+#endif
[gcc r15-1380] c++: Fix up floating point conversion rank comparison for _Float32 and float if float/double are sam
https://gcc.gnu.org/g:8584c98f370cd91647c184ce58141508ca478a12
commit r15-1380-g8584c98f370cd91647c184ce58141508ca478a12
Author: Jakub Jelinek
Date: Mon Jun 17 18:53:21 2024 +0200
c++: Fix up floating point conversion rank comparison for _Float32 and
float if float/double are same size [PR115511]
On AVR and SH with some options sizeof (float) == sizeof (double) and
the 2 types have the same set of values.
http://eel.is/c++draft/conv.rank#2.2 for this says that double still
has bigger rank than float and http://eel.is/c++draft/conv.rank#2.2
says that extended type with the same set of values as more than one
standard floating point type shall have the same rank as double.
I've implemented the latter rule as
if (cnt > 1 && mv2 == long_double_type_node)
return -2;
with the _Float64/double/long double case having same mode case (various
targets with -mlong-double-64) in mind.
But never thought there are actually targets where float and double
are the same, that needs handling too, if cnt > 1 (that is the extended
type mv1 has same set of values as 2 or 3 of float/double/long double)
and mv2 is float, we need to return 2, because mv1 in that case should
have same rank as double and double has bigger rank than float.
2024-06-17 Jakub Jelinek
PR target/111343
PR c++/115511
* typeck.cc (cp_compare_floating_point_conversion_ranks): If an
extended floating point type mv1 has same set of values as more
than one standard floating point type and mv2 is float, return 2.
* g++.dg/cpp23/ext-floating18.C: New test.
Diff:
---
gcc/cp/typeck.cc| 3 +++
gcc/testsuite/g++.dg/cpp23/ext-floating18.C | 26 ++
2 files changed, 29 insertions(+)
diff --git a/gcc/cp/typeck.cc b/gcc/cp/typeck.cc
index 5970ac3d3989..717eb63eb985 100644
--- a/gcc/cp/typeck.cc
+++ b/gcc/cp/typeck.cc
@@ -393,6 +393,9 @@ cp_compare_floating_point_conversion_ranks (tree t1, tree
t2)
has higher rank. */
if (cnt > 1 && mv2 == long_double_type_node)
return -2;
+ /* And similarly if t2 is float, t2 has lower rank. */
+ if (cnt > 1 && mv2 == float_type_node)
+return 2;
/* Otherwise, they have equal rank, but extended types
(other than std::bfloat16_t) have higher subrank.
std::bfloat16_t shouldn't have equal rank to any standard
diff --git a/gcc/testsuite/g++.dg/cpp23/ext-floating18.C
b/gcc/testsuite/g++.dg/cpp23/ext-floating18.C
new file mode 100644
index ..ece25464bfdf
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp23/ext-floating18.C
@@ -0,0 +1,26 @@
+// P1467R9 - Extended floating-point types and standard names.
+// { dg-do compile { target c++23 } }
+// { dg-options "" }
+// { dg-add-options float32 }
+
+constexpr int foo (float) { return 1; }
+constexpr int foo (double) { return 2; }
+constexpr int foo (long double) { return 3; }
+
+#ifdef __STDCPP_FLOAT32_T__
+#if __FLT_MAX_EXP__ == __FLT32_MAX_EXP__ \
+&& __FLT_MAX_DIG__ == __FLT32_MAX_DIG__
+#if __FLT_MAX_EXP__ == __DBL_MAX_EXP__ \
+&& __FLT_MAX_DIG__ == __DBL_MAX_DIG__
+static_assert (foo (1.0f32) == 2);
+#else
+static_assert (foo (1.0f32) == 1);
+#endif
+#endif
+#endif
+#ifdef __STDCPP_FLOAT64_T__
+#if __DBL_MAX_EXP__ == __FLT64_MAX_EXP__ \
+&& __DBL_MAX_DIG__ == __FLT64_MAX_DIG__
+static_assert (foo (1.0f64) == 2);
+#endif
+#endif
[gcc r15-1379] RISC-V: Add configure check for Zaamo/Zalrsc assembler support
https://gcc.gnu.org/g:4f18f75c5648d0b46a72f18e321bec279a6964be
commit r15-1379-g4f18f75c5648d0b46a72f18e321bec279a6964be
Author: Patrick O'Neill
Date: Mon Jun 17 09:46:05 2024 -0700
RISC-V: Add configure check for Zaamo/Zalrsc assembler support
Binutils 2.42 and before don't support Zaamo/Zalrsc. Add a configure
check to prevent emitting Zaamo/Zalrsc in the arch string when the
assember does not support it.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::to_string): Skip zaamo/zalrsc when not
supported by the assembler.
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Add zaamo/zalrsc assmeber check.
Signed-off-by: Patrick O'Neill
Acked-by: Palmer Dabbelt # RISC-V
Reviewed-by: Palmer Dabbelt # RISC-V
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 11 +++
gcc/config.in | 6 ++
gcc/configure | 31 +++
gcc/configure.ac| 5 +
4 files changed, 53 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 78dfd6b1470d..1dc1d9904c7b 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -916,6 +916,7 @@ riscv_subset_list::to_string (bool version_p) const
riscv_subset_t *subset;
bool skip_zifencei = false;
+ bool skip_zaamo_zalrsc = false;
bool skip_zicsr = false;
bool i2p0 = false;
@@ -943,6 +944,10 @@ riscv_subset_list::to_string (bool version_p) const
a mistake in that binutils 2.35 supports zicsr but not zifencei. */
skip_zifencei = true;
#endif
+#ifndef HAVE_AS_MARCH_ZAAMO_ZALRSC
+ /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc. */
+ skip_zaamo_zalrsc = true;
+#endif
for (subset = m_head; subset != NULL; subset = subset->next)
{
@@ -954,6 +959,12 @@ riscv_subset_list::to_string (bool version_p) const
subset->name == "zicsr")
continue;
+ if (skip_zaamo_zalrsc && subset->name == "zaamo")
+ continue;
+
+ if (skip_zaamo_zalrsc && subset->name == "zalrsc")
+ continue;
+
/* For !version_p, we only separate extension with underline for
multi-letter extension. */
if (!first &&
diff --git a/gcc/config.in b/gcc/config.in
index e41b6dc97cdd..acab3c0f1263 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -629,6 +629,12 @@
#endif
+/* Define if the assembler understands -march=rv*_zaamo_zalrsc. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_AS_MARCH_ZAAMO_ZALRSC
+#endif
+
+
/* Define if the assembler understands -march=rv*_zifencei. */
#ifndef USED_FOR_TARGET
#undef HAVE_AS_MARCH_ZIFENCEI
diff --git a/gcc/configure b/gcc/configure
index 94970e24051f..9dc0b65dfaac 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -30820,6 +30820,37 @@ if test $gcc_cv_as_riscv_march_zifencei = yes; then
$as_echo "#define HAVE_AS_MARCH_ZIFENCEI 1" >>confdefs.h
+fi
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for
-march=rv32i_zaamo_zalrsc support" >&5
+$as_echo_n "checking assembler for -march=rv32i_zaamo_zalrsc support... " >&6;
}
+if ${gcc_cv_as_riscv_march_zaamo_zalrsc+:} false; then :
+ $as_echo_n "(cached) " >&6
+else
+ gcc_cv_as_riscv_march_zaamo_zalrsc=no
+ if test x$gcc_cv_as != x; then
+$as_echo '' > conftest.s
+if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_zaamo_zalrsc -o
conftest.o conftest.s >&5'
+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; }; }
+then
+ gcc_cv_as_riscv_march_zaamo_zalrsc=yes
+else
+ echo "configure: failed program was" >&5
+ cat conftest.s >&5
+fi
+rm -f conftest.o conftest.s
+ fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result:
$gcc_cv_as_riscv_march_zaamo_zalrsc" >&5
+$as_echo "$gcc_cv_as_riscv_march_zaamo_zalrsc" >&6; }
+if test $gcc_cv_as_riscv_march_zaamo_zalrsc = yes; then
+
+$as_echo "#define HAVE_AS_MARCH_ZAAMO_ZALRSC 1" >>confdefs.h
+
fi
;;
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 35475cf5aae3..b2243e9954aa 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -5452,6 +5452,11 @@ configured with --enable-newlib-nano-formatted-io.])
[-march=rv32i_zifencei2p0],,,
[AC_DEFINE(HAVE_AS_MARCH_ZIFENCEI, 1,
[Define if the assembler understands -march=rv*_zifencei.])])
+gcc_GAS_CHECK_FEATURE([-march=rv32i_zaamo_zalrsc support],
+ gcc_cv_as_riscv_march_zaamo_zalrsc,
+ [-march=rv32i_zaamo_zalrsc],,,
+ [AC_DEFINE(HAVE_AS_MARCH_ZAAMO_ZALRSC, 1,
+[Define if the assembler understands
-march=rv*_zaamo_zalrsc.])])
;;
loongarch*-*-*)
gcc_GAS_CHECK_FEATURE
[gcc(refs/users/meissner/heads/work169-orig)] Add REVISION.
https://gcc.gnu.org/g:ec768042c12704f169cb00ae03761e9994d5654a commit ec768042c12704f169cb00ae03761e9994d5654a Author: Michael Meissner Date: Mon Jun 17 11:48:48 2024 -0400 Add REVISION. 2024-06-17 Michael Meissner gcc/ * REVISION: New file for branch. Diff: --- gcc/REVISION | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..0365d2073ef8 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work169-orig branch
[gcc] Created branch 'meissner/heads/work169-orig' in namespace 'refs/users'
The branch 'meissner/heads/work169-orig' was created in namespace 'refs/users' pointing to: dae93785c9eb... doc: Mark up __cxa_atexit as @code.
[gcc(refs/users/meissner/heads/work169-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:c9aa9cd85ffa61a688fe79c95a3c8845d38b62a4 commit c9aa9cd85ffa61a688fe79c95a3c8845d38b62a4 Author: Michael Meissner Date: Mon Jun 17 11:47:42 2024 -0400 Add ChangeLog.test and update REVISION. 2024-06-17 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 6 ++ gcc/REVISION | 1 + 2 files changed, 7 insertions(+) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index ..67de41285d7c --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,6 @@ + Branch work169-test, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..8f4847e3bd85 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work169-test branch
[gcc(refs/users/meissner/heads/work169-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:61022fbf801c643e14a0f398c68c548d7d98bfe3 commit 61022fbf801c643e14a0f398c68c548d7d98bfe3 Author: Michael Meissner Date: Mon Jun 17 11:46:47 2024 -0400 Add ChangeLog.bugs and update REVISION. 2024-06-17 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 6 ++ gcc/REVISION | 1 + 2 files changed, 7 insertions(+) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index ..fde4db8e004f --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,6 @@ + Branch work169-bugs, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..72d51349994b --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work169-bugs branch
[gcc] Created branch 'meissner/heads/work169-test' in namespace 'refs/users'
The branch 'meissner/heads/work169-test' was created in namespace 'refs/users' pointing to: dae93785c9eb... doc: Mark up __cxa_atexit as @code.
[gcc] Created branch 'meissner/heads/work169-bugs' in namespace 'refs/users'
The branch 'meissner/heads/work169-bugs' was created in namespace 'refs/users' pointing to: dae93785c9eb... doc: Mark up __cxa_atexit as @code.
[gcc(refs/users/meissner/heads/work169-tar)] Add ChangeLog.tar and update REVISION.
https://gcc.gnu.org/g:8b991c94aafee86453b3421ad2f1c39f1b433c5d commit 8b991c94aafee86453b3421ad2f1c39f1b433c5d Author: Michael Meissner Date: Mon Jun 17 11:45:43 2024 -0400 Add ChangeLog.tar and update REVISION. 2024-06-17 Michael Meissner gcc/ * ChangeLog.tar: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.tar | 6 ++ gcc/REVISION | 1 + 2 files changed, 7 insertions(+) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar new file mode 100644 index ..3ce483b3c2d5 --- /dev/null +++ b/gcc/ChangeLog.tar @@ -0,0 +1,6 @@ + Branch work169-tar, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..cedbf7602f2c --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work169-tar branch
[gcc] Created branch 'meissner/heads/work169-tar' in namespace 'refs/users'
The branch 'meissner/heads/work169-tar' was created in namespace 'refs/users' pointing to: dae93785c9eb... doc: Mark up __cxa_atexit as @code.
[gcc(refs/users/meissner/heads/work169-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:73f2080b2556c1e303c26a13ee981b8c2c0c652c commit 73f2080b2556c1e303c26a13ee981b8c2c0c652c Author: Michael Meissner Date: Mon Jun 17 11:44:46 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-06-17 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 6 ++ gcc/REVISION| 1 + 2 files changed, 7 insertions(+) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index ..246a7b149737 --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,6 @@ + Branch work169-vpair, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..cf4b0cc424aa --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work169-vpair branch
[gcc] Created branch 'meissner/heads/work169-vpair' in namespace 'refs/users'
The branch 'meissner/heads/work169-vpair' was created in namespace 'refs/users' pointing to: dae93785c9eb... doc: Mark up __cxa_atexit as @code.
[gcc(refs/users/meissner/heads/work169-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:1cb999869bf0cf2aae3ebd41e08d8bd366d0e4d7 commit 1cb999869bf0cf2aae3ebd41e08d8bd366d0e4d7 Author: Michael Meissner Date: Mon Jun 17 11:43:43 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-06-17 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 6 ++ gcc/REVISION | 1 + 2 files changed, 7 insertions(+) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index ..b32cf61e3942 --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,6 @@ + Branch work169-dmf, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..870d2cdcff25 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work169-dmf branch
[gcc] Created branch 'meissner/heads/work169-dmf' in namespace 'refs/users'
The branch 'meissner/heads/work169-dmf' was created in namespace 'refs/users' pointing to: dae93785c9eb... doc: Mark up __cxa_atexit as @code.
[gcc(refs/users/meissner/heads/work169)] Add ChangeLog.meissner and REVISION.
https://gcc.gnu.org/g:5576ea03a26b7c022e7df127aefb4bcd050fa0d3 commit 5576ea03a26b7c022e7df127aefb4bcd050fa0d3 Author: Michael Meissner Date: Mon Jun 17 11:42:43 2024 -0400 Add ChangeLog.meissner and REVISION. 2024-06-17 Michael Meissner gcc/ * REVISION: New file for branch. * ChangeLog.meissner: New file. gcc/c-family/ * ChangeLog.meissner: New file. gcc/c/ * ChangeLog.meissner: New file. gcc/cp/ * ChangeLog.meissner: New file. gcc/fortran/ * ChangeLog.meissner: New file. gcc/testsuite/ * ChangeLog.meissner: New file. libgcc/ * ChangeLog.meissner: New file. Diff: --- gcc/ChangeLog.meissner | 6 ++ gcc/REVISION | 1 + gcc/c-family/ChangeLog.meissner | 6 ++ gcc/c/ChangeLog.meissner | 6 ++ gcc/cp/ChangeLog.meissner| 6 ++ gcc/fortran/ChangeLog.meissner | 6 ++ gcc/testsuite/ChangeLog.meissner | 6 ++ libgcc/ChangeLog.meissner| 6 ++ libstdc++-v3/ChangeLog.meissner | 6 ++ 9 files changed, 49 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner new file mode 100644 index ..ef7eaa6f006f --- /dev/null +++ b/gcc/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index ..ac3c7025be66 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work169 branch diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner new file mode 100644 index ..ef7eaa6f006f --- /dev/null +++ b/gcc/c-family/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner new file mode 100644 index ..ef7eaa6f006f --- /dev/null +++ b/gcc/c/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner new file mode 100644 index ..ef7eaa6f006f --- /dev/null +++ b/gcc/cp/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner new file mode 100644 index ..ef7eaa6f006f --- /dev/null +++ b/gcc/fortran/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner new file mode 100644 index ..ef7eaa6f006f --- /dev/null +++ b/gcc/testsuite/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner new file mode 100644 index ..ef7eaa6f006f --- /dev/null +++ b/libgcc/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch + diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner new file mode 100644 index ..ef7eaa6f006f --- /dev/null +++ b/libstdc++-v3/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work169, baseline + +2024-06-17 Michael Meissner + + Clone branch +
[gcc] Created branch 'meissner/heads/work169' in namespace 'refs/users'
The branch 'meissner/heads/work169' was created in namespace 'refs/users' pointing to: dae93785c9eb... doc: Mark up __cxa_atexit as @code.
[gcc r14-10320] c++: undeclared identifier in requires-clause [PR99678]
https://gcc.gnu.org/g:20cda2e85c307096a3856f7f27215b8a28982fb6
commit r14-10320-g20cda2e85c307096a3856f7f27215b8a28982fb6
Author: Patrick Palka
Date: Thu Jun 13 10:16:10 2024 -0400
c++: undeclared identifier in requires-clause [PR99678]
Since the terms of a requires-clause are grammatically primary-expressions
and not e.g. postfix-expressions, it seems we need to explicitly handle
and diagnose the case where a term parses to a bare unresolved identifier,
like cp_parser_postfix_expression does, since cp_parser_primary_expression
leaves that up to its callers. Otherwise we incorrectly accept the first
three requires-clauses below.
Note that the only occurrences of primary-expression in the grammar are
postfix-expression and constraint-logical-and-expression, so it's not too
surprising that we need this special handling here.
PR c++/99678
gcc/cp/ChangeLog:
* parser.cc (cp_parser_constraint_primary_expression): Diagnose
a bare unresolved unqualified-id.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/concepts-requires38.C: New test.
Reviewed-by: Jason Merrill
(cherry picked from commit d387ecb2b2f44f33fd6a7c5ec7eadaf6dd70efc9)
Diff:
---
gcc/cp/parser.cc | 2 ++
gcc/testsuite/g++.dg/cpp2a/concepts-requires38.C | 14 ++
2 files changed, 16 insertions(+)
diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc
index 598380dda089..6b786ed8266f 100644
--- a/gcc/cp/parser.cc
+++ b/gcc/cp/parser.cc
@@ -31225,6 +31225,8 @@ cp_parser_constraint_primary_expression (cp_parser
*parser, bool lambda_p)
}
if (pce == pce_ok)
{
+ if (idk == CP_ID_KIND_UNQUALIFIED && identifier_p (expr))
+ expr = unqualified_name_lookup_error (expr);
cp_lexer_commit_tokens (parser->lexer);
return finish_constraint_primary_expr (expr);
}
diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-requires38.C
b/gcc/testsuite/g++.dg/cpp2a/concepts-requires38.C
new file mode 100644
index ..663195b79cc7
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/concepts-requires38.C
@@ -0,0 +1,14 @@
+// PR c++/99678
+// { dg-do compile { target c++20 } }
+
+template
+void f1() requires undeclared_identifier; // { dg-error "not declared" }
+
+template
+void f2() requires true && undeclared_identifier; // { dg-error "not declared"
}
+
+template
+void f3() requires false || undeclared_identifier; // { dg-error "not
declared" }
+
+template
+void f4() requires undeclared_identifier(T{}); // { dg-error "must be enclosed
in parentheses" }
[gcc r14-10319] c++: ICE w/ ambig and non-strictly-viable cands [PR115239]
https://gcc.gnu.org/g:4df86402990e2f45e02a367f1734a22ebc041e98
commit r14-10319-g4df86402990e2f45e02a367f1734a22ebc041e98
Author: Patrick Palka
Date: Thu Jun 13 10:02:43 2024 -0400
c++: ICE w/ ambig and non-strictly-viable cands [PR115239]
Here during overload resolution we have two strictly viable ambiguous
candidates #1 and #2, and two non-strictly viable candidates #3 and #4
which we hold on to ever since r14-6522. These latter candidates have
an empty second arg conversion since the first arg conversion was deemed
bad, and this trips up joust when called on #3 and #4 which assumes all
arg conversions are there.
We can fix this by making joust robust to empty arg conversions, but in
this situation we shouldn't need to compare #3 and #4 at all given that
we have a strictly viable candidate. To that end, this patch makes
tourney shortcut considering non-strictly viable candidates upon
encountering ambiguity between two strictly viable candidates (taking
advantage of the fact that the candidates list is sorted according to
viability via splice_viable).
PR c++/115239
gcc/cp/ChangeLog:
* call.cc (tourney): Don't consider a non-strictly viable
candidate as the champ if there was ambiguity between two
strictly viable candidates.
gcc/testsuite/ChangeLog:
* g++.dg/overload/error7.C: New test.
Reviewed-by: Jason Merrill
(cherry picked from commit 7fed7e9bbc57d502e141e079a6be2706bdbd4560)
Diff:
---
gcc/cp/call.cc | 3 ++-
gcc/testsuite/g++.dg/overload/error7.C | 10 ++
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/gcc/cp/call.cc b/gcc/cp/call.cc
index 38b9c4f08601..f5584c92efb8 100644
--- a/gcc/cp/call.cc
+++ b/gcc/cp/call.cc
@@ -13488,7 +13488,8 @@ tourney (struct z_candidate *candidates, tsubst_flags_t
complain)
{
previous_worse_champ = nullptr;
champ = &(*challenger)->next;
- if (!*champ || !(*champ)->viable)
+ if (!*champ || !(*champ)->viable
+ || (*champ)->viable < (*challenger)->viable)
{
champ = nullptr;
break;
diff --git a/gcc/testsuite/g++.dg/overload/error7.C
b/gcc/testsuite/g++.dg/overload/error7.C
new file mode 100644
index ..de50ce5f66e4
--- /dev/null
+++ b/gcc/testsuite/g++.dg/overload/error7.C
@@ -0,0 +1,10 @@
+// PR c++/115239
+
+bool foo(char *, long); // #1, strictly viable, ambig with #2
+bool foo(char *, unsigned); // #2, strictly viable, ambig with #1
+bool foo(char, long); // #3, non-strictly viable
+bool foo(char, unsigned); // #4, non-strictly viable
+
+int main() {
+ foo((char *)0, 0); // { dg-error "ambiguous" }
+}
[gcc r14-10318] c++: visibility wrt concept-id as targ [PR115283]
https://gcc.gnu.org/g:9583f781e17d4da881ee64db43af939402331413
commit r14-10318-g9583f781e17d4da881ee64db43af939402331413
Author: Patrick Palka
Date: Wed Jun 12 20:05:05 2024 -0400
c++: visibility wrt concept-id as targ [PR115283]
Like with alias templates, it seems we don't maintain visibility flags
for concepts either, so min_vis_expr_r should ignore them for now.
Otherwise after r14-6789 we may incorrectly give a function template that
uses a concept-id in its signature internal linkage.
PR c++/115283
gcc/cp/ChangeLog:
* decl2.cc (min_vis_expr_r) : Ignore
concepts.
gcc/testsuite/ChangeLog:
* g++.dg/template/linkage5.C: New test.
Reviewed-by: Jason Merrill
(cherry picked from commit b1fe718cbe0c8883af89f52e0aad3ebf913683de)
Diff:
---
gcc/cp/decl2.cc | 5 +++--
gcc/testsuite/g++.dg/template/linkage5.C | 14 ++
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/gcc/cp/decl2.cc b/gcc/cp/decl2.cc
index 806a2a4bc69d..88933be732db 100644
--- a/gcc/cp/decl2.cc
+++ b/gcc/cp/decl2.cc
@@ -2710,9 +2710,10 @@ min_vis_expr_r (tree *tp, int */*walk_subtrees*/, void
*data)
break;
case TEMPLATE_DECL:
- if (DECL_ALIAS_TEMPLATE_P (t))
+ if (DECL_ALIAS_TEMPLATE_P (t) || standard_concept_p (t))
/* FIXME: We don't maintain TREE_PUBLIC / DECL_VISIBILITY for
- alias templates so we can't trust it here (PR107906). */
+ alias templates so we can't trust it here (PR107906). Ditto
+ for concepts. */
break;
t = DECL_TEMPLATE_RESULT (t);
/* Fall through. */
diff --git a/gcc/testsuite/g++.dg/template/linkage5.C
b/gcc/testsuite/g++.dg/template/linkage5.C
new file mode 100644
index ..7e8f93f546f1
--- /dev/null
+++ b/gcc/testsuite/g++.dg/template/linkage5.C
@@ -0,0 +1,14 @@
+// PR c++/115283
+// { dg-final { scan-assembler "(weak|glob)\[^\n\]*_Z1fIiEv1AIX1CIT_EEE" } }
+// { dg-do compile { target c++20 } }
+
+template
+concept C = true;
+
+template
+struct A { };
+
+template
+void f(A>) { }
+
+template void f(A);
[gcc r15-1378] doc: Mark up __cxa_atexit as @code.
https://gcc.gnu.org/g:dae93785c9ebdaf6a0a4eeef51d399e2530679cd
commit r15-1378-gdae93785c9ebdaf6a0a4eeef51d399e2530679cd
Author: Gerald Pfeifer
Date: Mon Jun 17 15:16:49 2024 +0200
doc: Mark up __cxa_atexit as @code.
gcc:
* doc/install.texi (Configuration): Mark up __cxa_atexit as @code.
Diff:
---
gcc/doc/install.texi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 298031dc2de9..1774a010889a 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1779,12 +1779,12 @@ Produce code conforming to version 20191213.
In the absence of this configuration option the default version is 20191213.
@item --enable-__cxa_atexit
-Define if you want to use __cxa_atexit, rather than atexit, to
+Define if you want to use @code{__cxa_atexit}, rather than atexit, to
register C++ destructors for local statics and global objects.
This is essential for fully standards-compliant handling of
-destructors, but requires __cxa_atexit in libc. This option is currently
-only available on systems with GNU libc. When enabled, this will cause
-@option{-fuse-cxa-atexit} to be passed by default.
+destructors, but requires @code{__cxa_atexit} in libc. This option is
+currently only available on systems with GNU libc. When enabled, this
+will cause @option{-fuse-cxa-atexit} to be passed by default.
@item --enable-gnu-indirect-function
Define if you want to enable the @code{ifunc} attribute. This option is
[gcc r15-1377] rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]
https://gcc.gnu.org/g:c70eea0dba5f223d49c80cfb3e80e87b74330aac
commit r15-1377-gc70eea0dba5f223d49c80cfb3e80e87b74330aac
Author: Peter Bergner
Date: Fri Jun 14 14:36:20 2024 -0500
rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]
We currently only compute the offset for the ROP hash save location in
the stack frame for Altivec compiles. For non-Altivec compiles when we
emit ROP mitigation instructions, we use a default offset of zero which
corresponds to the backchain save location which will get clobbered on
any call. The fix is to compute the ROP hash save location for all
compiles.
2024-06-14 Peter Bergner
gcc/
PR target/115389
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Compute
rop_hash_save_offset for non-Altivec compiles.
gcc/testsuite
PR target/115389
* gcc.target/powerpc/pr115389.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-logue.cc | 9 -
gcc/testsuite/gcc.target/powerpc/pr115389.c | 17 +
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-logue.cc
b/gcc/config/rs6000/rs6000-logue.cc
index d61a25a51264..193e2122c0f9 100644
--- a/gcc/config/rs6000/rs6000-logue.cc
+++ b/gcc/config/rs6000/rs6000-logue.cc
@@ -817,17 +817,16 @@ rs6000_stack_info (void)
gcc_assert (info->altivec_size == 0
|| info->altivec_save_offset % 16 == 0);
- /* Adjust for AltiVec case. */
- info->ehrd_offset = info->altivec_save_offset - ehrd_size;
-
/* Adjust for ROP protection. */
info->rop_hash_save_offset
= info->altivec_save_offset - info->rop_hash_size;
- info->ehrd_offset -= info->rop_hash_size;
}
else
- info->ehrd_offset = info->gp_save_offset - ehrd_size;
+ /* Adjust for ROP protection. */
+ info->rop_hash_save_offset
+ = info->gp_save_offset - info->rop_hash_size;
+ info->ehrd_offset = info->rop_hash_save_offset - ehrd_size;
info->ehcr_offset = info->ehrd_offset - ehcr_size;
info->cr_save_offset = reg_size; /* first word when 64-bit. */
info->lr_save_offset = 2*reg_size;
diff --git a/gcc/testsuite/gcc.target/powerpc/pr115389.c
b/gcc/testsuite/gcc.target/powerpc/pr115389.c
new file mode 100644
index ..a091ee8a1be0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr115389.c
@@ -0,0 +1,17 @@
+/* PR target/115389 */
+/* { dg-do assemble } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -mrop-protect -mno-vsx -mno-altivec
-mabi=no-altivec -save-temps" } */
+/* { dg-require-effective-target rop_ok } */
+
+/* Verify we do not emit invalid offsets for our ROP insns. */
+
+extern void foo (void);
+long
+bar (void)
+{
+ foo ();
+ return 0;
+}
+
+/* { dg-final { scan-assembler-times {\mhashst\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mhashchk\M} 1 } } */
[gcc r15-1376] [to-be-committed, RISC-V] Improve variable bit set for rv64
https://gcc.gnu.org/g:83aad89fb99d0e82209734717c12f5aaca477970
commit r15-1376-g83aad89fb99d0e82209734717c12f5aaca477970
Author: Jeff Law
Date: Mon Jun 17 07:04:13 2024 -0600
[to-be-committed,RISC-V] Improve variable bit set for rv64
Another case of being able to safely use bset for 1 << n. In this case
the (1 << n) is explicitly zero extended from SI to DI. Two things to
keep in mind. The (1 << n) is done in SImode. So it doesn't directly
define bits 32..63 and those bits are cleared by the explicit zero
extension. Second if N is out of SImode's range, then the original
source level construct was undefined.
Thus we can use bset with x0 as our source input.
I think this testcase was from the RAU team. It doesn't immediately
look like something from SPEC, but that's where they were primarily focused.
This has been through Ventana's CI system in the past. I've also
recently added zbs testing to my own tester and naturally this passed
there as well. I'll wait for the pre-commit CI to do its thing before
moving forward. The plan would be to commit after passing.
gcc/
* config/riscv/bitmanip.md (bsetdi_2): New pattern.
gcc/testsuite/
* gcc.target/riscv/zbs-zext-2.c: New test.
Diff:
---
gcc/config/riscv/bitmanip.md| 12
gcc/testsuite/gcc.target/riscv/zbs-zext-2.c | 12
2 files changed, 24 insertions(+)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 0d35fb786e11..311f0d373c00 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -597,6 +597,18 @@
"bset\t%0,x0,%1"
[(set_attr "type" "bitmanip")])
+;; The result will always have bits 32..63 clear, so the zero-extend
+;; is redundant. We could split it to bset_1, but it seems
+;; unnecessary.
+(define_insn "*bsetdi_2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (ashift:SI (const_int 1)
+(match_operand:QI 1 "register_operand" "r"]
+ "TARGET_64BIT && TARGET_ZBS"
+ "bset\t%0,x0,%1"
+ [(set_attr "type" "bitmanip")])
+
(define_insn "*bset_1_mask"
[(set (match_operand:X 0 "register_operand" "=r")
(ashift:X (const_int 1)
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-zext-2.c
b/gcc/testsuite/gcc.target/riscv/zbs-zext-2.c
new file mode 100644
index ..ebd269d1695c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbs-zext-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */
+unsigned long long foo(long long symbol)
+{
+return 1u << symbol;
+}
+
+/* { dg-final { scan-assembler-times "bset\t" 1 } } */
+/* { dg-final { scan-assembler-not "li\t"} } */
+/* { dg-final { scan-assembler-not "sllw\t"} } */
+/* { dg-final { scan-assembler-not "zext.w\t"} } */
[gcc r15-1375] tree-optimization/115508 - fix ICE with SLP scheduling and extern vector
https://gcc.gnu.org/g:65e72b95c63a5501cf1482f3814ae8c8e672bf06
commit r15-1375-g65e72b95c63a5501cf1482f3814ae8c8e672bf06
Author: Richard Biener
Date: Mon Jun 17 14:36:56 2024 +0200
tree-optimization/115508 - fix ICE with SLP scheduling and extern vector
When there's a permute after an extern vector we can run into a case
that didn't consider the scheduled node being a permute which lacks
a representative.
PR tree-optimization/115508
* tree-vect-slp.cc (vect_schedule_slp_node): Guard check on
representative.
* gcc.target/i386/pr115508.c: New testcase.
Diff:
---
gcc/testsuite/gcc.target/i386/pr115508.c | 15 +++
gcc/tree-vect-slp.cc | 1 +
2 files changed, 16 insertions(+)
diff --git a/gcc/testsuite/gcc.target/i386/pr115508.c
b/gcc/testsuite/gcc.target/i386/pr115508.c
new file mode 100644
index ..a97b2007f7a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr115508.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=znver1" } */
+
+typedef long long v4di __attribute__((vector_size(4 * sizeof (long long;
+
+v4di vec_var;
+extern long long array1[];
+long long g(void)
+{
+ int total_error_4 = 0;
+ total_error_4 += array1 [0] + array1 [1] + array1 [2] + array1 [3];
+ v4di t = vec_var;
+ long long iorvar = t [1] | t [0] | t [2] | t [3];
+ return iorvar + total_error_4;
+}
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index 7e3d0107b4e7..7d18b5bfee5d 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -9669,6 +9669,7 @@ vect_schedule_slp_node (vec_info *vinfo,
si = gsi_after_labels (vinfo->bbs[0]);
}
else if (is_a (vinfo)
+ && SLP_TREE_CODE (node) != VEC_PERM_EXPR
&& gimple_bb (last_stmt) != gimple_bb (stmt_info->stmt)
&& gimple_could_trap_p (stmt_info->stmt))
{
[gcc r15-1374] Testcase for PR115492
https://gcc.gnu.org/g:95bfc6abf378a32e502dca0e2938f94d5b0ab094
commit r15-1374-g95bfc6abf378a32e502dca0e2938f94d5b0ab094
Author: Richard Biener
Date: Mon Jun 17 09:23:25 2024 +0200
Testcase for PR115492
This adds a testcase for the PR fixed with reversal of
r15-204-g7c469a9fc78550.
PR tree-optimization/115492
* gcc.dg/torture/pr115492.c: New testcase.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr115492.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/torture/pr115492.c
b/gcc/testsuite/gcc.dg/torture/pr115492.c
new file mode 100644
index ..4ecc060768c0
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr115492.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+
+int a = 2, b=0, *c = &a, *d = &a, e=0;
+[[gnu::noipa]]
+void f(int) {}
+[[gnu::noipa]]
+int h(int *k) {
+ int ***j;
+ if (b) {
+*j = &k; // Note the unintialized j is used here
+ // but since it is conditional and b is always zero, there should
no
+ // effect otherwise.
+***j;
+ }
+ f(*k);
+ *d = e;
+ return *k;
+}
+int main() { if (h(c)) __builtin_abort(); }
[gcc r15-1373] Revert "tree-optimization/100923 - re-do VN with contextual PTA info fix"
https://gcc.gnu.org/g:b100488bfca3c3ca67e9e807d6e4e03dd0e3f6db
commit r15-1373-gb100488bfca3c3ca67e9e807d6e4e03dd0e3f6db
Author: Richard Biener
Date: Mon Jun 17 09:21:17 2024 +0200
Revert "tree-optimization/100923 - re-do VN with contextual PTA info fix"
This reverts commit 7c469a9fc785505dc350aba60311812c2bb0c1b5.
Diff:
---
gcc/tree-ssa-sccvn.cc | 58 +--
1 file changed, 33 insertions(+), 25 deletions(-)
diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc
index 726e9d88b8f4..fbbfa5578339 100644
--- a/gcc/tree-ssa-sccvn.cc
+++ b/gcc/tree-ssa-sccvn.cc
@@ -1201,14 +1201,8 @@ ao_ref_init_from_vn_reference (ao_ref *ref,
case STRING_CST:
/* This can show up in ARRAY_REF bases. */
case INTEGER_CST:
- *op0_p = op->op0;
- op0_p = NULL;
- break;
-
case SSA_NAME:
- /* SSA names we have to get at one available since it contains
-flow-sensitive info. */
- *op0_p = vn_valueize (op->op0);
+ *op0_p = op->op0;
op0_p = NULL;
break;
@@ -2731,6 +2725,7 @@ vn_reference_lookup_3 (ao_ref *ref, tree vuse, void
*data_,
copy_reference_ops_from_ref (lhs, &lhs_ops);
valueize_refs_1 (&lhs_ops, &valueized_anything, true);
}
+ vn_context_bb = saved_rpo_bb;
ao_ref_init (&lhs_ref, lhs);
lhs_ref_ok = true;
if (valueized_anything
@@ -2739,11 +2734,9 @@ vn_reference_lookup_3 (ao_ref *ref, tree vuse, void
*data_,
ao_ref_base_alias_set (&lhs_ref), TREE_TYPE (lhs), lhs_ops)
&& !refs_may_alias_p_1 (ref, &lhs_ref, data->tbaa_p))
{
- vn_context_bb = saved_rpo_bb;
*disambiguate_only = TR_VALUEIZE_AND_DISAMBIGUATE;
return NULL;
}
- vn_context_bb = saved_rpo_bb;
/* When the def is a CLOBBER we can optimistically disambiguate
against it since any overlap it would be undefined behavior.
@@ -3641,19 +3634,13 @@ vn_reference_lookup_3 (ao_ref *ref, tree vuse, void
*data_,
/* Adjust *ref from the new operands. */
ao_ref rhs1_ref;
ao_ref_init (&rhs1_ref, rhs1);
- basic_block saved_rpo_bb = vn_context_bb;
- vn_context_bb = gimple_bb (def_stmt);
if (!ao_ref_init_from_vn_reference (&r,
force_no_tbaa ? 0
: ao_ref_alias_set (&rhs1_ref),
force_no_tbaa ? 0
: ao_ref_base_alias_set (&rhs1_ref),
vr->type, vr->operands))
- {
- vn_context_bb = saved_rpo_bb;
- return (void *)-1;
- }
- vn_context_bb = saved_rpo_bb;
+ return (void *)-1;
/* This can happen with bitfields. */
if (maybe_ne (ref->size, r.size))
{
@@ -3852,14 +3839,8 @@ vn_reference_lookup_3 (ao_ref *ref, tree vuse, void
*data_,
return data->finish (0, 0, val);
/* Adjust *ref from the new operands. */
- basic_block saved_rpo_bb = vn_context_bb;
- vn_context_bb = gimple_bb (def_stmt);
if (!ao_ref_init_from_vn_reference (&r, 0, 0, vr->type, vr->operands))
- {
- vn_context_bb = saved_rpo_bb;
- return (void *)-1;
- }
- vn_context_bb = saved_rpo_bb;
+ return (void *)-1;
/* This can happen with bitfields. */
if (maybe_ne (ref->size, r.size))
return (void *)-1;
@@ -3947,13 +3928,31 @@ vn_reference_lookup_pieces (tree vuse, alias_set_type
set,
unsigned limit = param_sccvn_max_alias_queries_per_access;
vn_walk_cb_data data (&vr1, NULL_TREE, NULL, kind, true, NULL_TREE,
false);
+ vec ops_for_ref;
+ if (!valueized_p)
+ ops_for_ref = vr1.operands;
+ else
+ {
+ /* For ao_ref_from_mem we have to ensure only available SSA names
+end up in base and the only convenient way to make this work
+for PRE is to re-valueize with that in mind. */
+ ops_for_ref.create (operands.length ());
+ ops_for_ref.quick_grow (operands.length ());
+ memcpy (ops_for_ref.address (),
+ operands.address (),
+ sizeof (vn_reference_op_s)
+ * operands.length ());
+ valueize_refs_1 (&ops_for_ref, &valueized_p, true);
+ }
if (ao_ref_init_from_vn_reference (&r, set, base_set, type,
-vr1.operands))
+ops_for_ref))
*vnresult
= ((vn_reference_t)
walk_non_aliased_vuses (&r, vr1.vuse, true, vn_reference_lookup_2,
vn_reference_lookup_3, vuse_valueize,
limit, &data));
+ if (ops_for_ref != shared_lookup_references)
+ ops_for_ref.release ();
[gcc r15-1372] Rename Value_Range to value_range.
https://gcc.gnu.org/g:3dedfad5a1edb14169a138492e486ee691387a53 commit r15-1372-g3dedfad5a1edb14169a138492e486ee691387a53 Author: Aldy Hernandez Date: Tue Jun 4 07:35:51 2024 +0200 Rename Value_Range to value_range. Now that all remaining users of value_range have been renamed to int_range<>, we can reclaim value_range as a temporary, thus removing the annoying CamelCase. gcc/ChangeLog: * data-streamer-in.cc (streamer_read_value_range): Rename Value_Range to value_range. * data-streamer.h (streamer_read_value_range): Same. * gimple-pretty-print.cc (dump_ssaname_info): Same. * gimple-range-cache.cc (ssa_block_ranges::dump): Same. (ssa_lazy_cache::merge): Same. (block_range_cache::dump): Same. (ssa_cache::merge_range): Same. (ssa_cache::dump): Same. (ranger_cache::edge_range): Same. (ranger_cache::propagate_cache): Same. (ranger_cache::fill_block_cache): Same. (ranger_cache::resolve_dom): Same. (ranger_cache::range_from_dom): Same. (ranger_cache::register_inferred_value): Same. * gimple-range-fold.cc (op1_range): Same. (op2_range): Same. (fold_relations): Same. (fold_using_range::range_of_range_op): Same. (fold_using_range::range_of_phi): Same. (fold_using_range::range_of_call): Same. (fold_using_range::condexpr_adjust): Same. (fold_using_range::range_of_cond_expr): Same. (fur_source::register_outgoing_edges): Same. * gimple-range-fold.h (gimple_range_type): Same. (gimple_range_ssa_p): Same. * gimple-range-gori.cc (gori_compute::compute_operand_range): Same. (gori_compute::logical_combine): Same. (gori_compute::refine_using_relation): Same. (gori_compute::compute_operand1_range): Same. (gori_compute::compute_operand2_range): Same. (gori_compute::compute_operand1_and_operand2_range): Same. (gori_calc_operands): Same. (gori_name_helper): Same. * gimple-range-infer.cc (gimple_infer_range::check_assume_func): Same. (gimple_infer_range::gimple_infer_range): Same. (infer_range_manager::maybe_adjust_range): Same. (infer_range_manager::add_range): Same. * gimple-range-infer.h: Same. * gimple-range-op.cc (gimple_range_op_handler::gimple_range_op_handler): Same. (gimple_range_op_handler::calc_op1): Same. (gimple_range_op_handler::calc_op2): Same. (gimple_range_op_handler::maybe_builtin_call): Same. * gimple-range-path.cc (path_range_query::internal_range_of_expr): Same. (path_range_query::ssa_range_in_phi): Same. (path_range_query::compute_ranges_in_phis): Same. (path_range_query::compute_ranges_in_block): Same. (path_range_query::add_to_exit_dependencies): Same. * gimple-range-trace.cc (debug_seed_ranger): Same. * gimple-range.cc (gimple_ranger::range_of_expr): Same. (gimple_ranger::range_on_entry): Same. (gimple_ranger::range_on_edge): Same. (gimple_ranger::range_of_stmt): Same. (gimple_ranger::prefill_stmt_dependencies): Same. (gimple_ranger::register_inferred_ranges): Same. (gimple_ranger::register_transitive_inferred_ranges): Same. (gimple_ranger::export_global_ranges): Same. (gimple_ranger::dump_bb): Same. (assume_query::calculate_op): Same. (assume_query::calculate_phi): Same. (assume_query::dump): Same. (dom_ranger::range_of_stmt): Same. * ipa-cp.cc (ipcp_vr_lattice::meet_with_1): Same. (ipa_vr_operation_and_type_effects): Same. (ipa_value_range_from_jfunc): Same. (propagate_bits_across_jump_function): Same. (propagate_vr_across_jump_function): Same. (ipcp_store_vr_results): Same. * ipa-cp.h: Same. * ipa-fnsummary.cc (evaluate_conditions_for_known_args): Same. (evaluate_properties_for_edge): Same. * ipa-prop.cc (struct ipa_vr_ggc_hash_traits): Same. (ipa_vr::get_vrange): Same. (ipa_vr::streamer_read): Same. (ipa_vr::streamer_write): Same. (ipa_vr::dump): Same. (ipa_set_jfunc_vr): Same. (ipa_compute_jump_functions_for_edge): Same. (ipcp_get_parm_bits): Same. (ipcp_update_vr): Same. (ipa_record_return_value_range): Same. (ipa_return_value_range): Same. * ipa-prop.h (ipa_return_value_range): Same. (ipa_record_return_value_range): Same. * range-op.h (range_cast)
[gcc r12-10562] libstdc++: Fix declaration of posix_memalign for freestanding
https://gcc.gnu.org/g:ea0aa9765d44baccce398ec92c30cb5f2e3e2e9d
commit r12-10562-gea0aa9765d44baccce398ec92c30cb5f2e3e2e9d
Author: Jonathan Wakely
Date: Fri Jun 14 12:10:48 2024 +0100
libstdc++: Fix declaration of posix_memalign for freestanding
Thanks to Jérôme Duval for noticing this.
libstdc++-v3/ChangeLog:
* libsupc++/new_opa.cc [!_GLIBCXX_HOSTED]: Fix declaration of
posix_memalign.
(cherry picked from commit 161efd677458f20d13ee1018a4d5e3964febd508)
Diff:
---
libstdc++-v3/libsupc++/new_opa.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libstdc++-v3/libsupc++/new_opa.cc
b/libstdc++-v3/libsupc++/new_opa.cc
index ae01166cae3b..def6c8de79d4 100644
--- a/libstdc++-v3/libsupc++/new_opa.cc
+++ b/libstdc++-v3/libsupc++/new_opa.cc
@@ -47,7 +47,7 @@ using std::size_t;
extern "C"
{
# if _GLIBCXX_HAVE_POSIX_MEMALIGN
- void *posix_memalign(void **, size_t alignment, size_t size);
+ int posix_memalign(void **, size_t alignment, size_t size);
# elif _GLIBCXX_HAVE_ALIGNED_ALLOC
void *aligned_alloc(size_t alignment, size_t size);
# elif _GLIBCXX_HAVE__ALIGNED_MALLOC
[gcc r15-1371] [APX ZU] Fix test for target-support check
https://gcc.gnu.org/g:4fbaac1f089f2236b5b1e79e18baba05239ad3b1
commit r15-1371-g4fbaac1f089f2236b5b1e79e18baba05239ad3b1
Author: Lingling Kong
Date: Mon Jun 17 16:11:09 2024 +0800
[APX ZU] Fix test for target-support check
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-zu-1.c: Add attribute for noinline,
and target apx.
* gcc.target/i386/apx-zu-2.c: Add target-support check.
Diff:
---
gcc/testsuite/gcc.target/i386/apx-zu-1.c | 6 ++
gcc/testsuite/gcc.target/i386/apx-zu-2.c | 3 +++
2 files changed, 9 insertions(+)
diff --git a/gcc/testsuite/gcc.target/i386/apx-zu-1.c
b/gcc/testsuite/gcc.target/i386/apx-zu-1.c
index 927a87673a7a..bc0e7fbb4dd6 100644
--- a/gcc/testsuite/gcc.target/i386/apx-zu-1.c
+++ b/gcc/testsuite/gcc.target/i386/apx-zu-1.c
@@ -9,26 +9,32 @@
/* { dg-final { scan-assembler-times "setzue" 1} } */
/* { dg-final { scan-assembler-times "setzuge" 1} } */
/* { dg-final { scan-assembler "imulzu"} } */
+
+__attribute__((noinline, noclone, target("apxf")))
long long foo0 (int a)
{
return a == 0 ? 0 : 1;
}
+__attribute__((noinline, noclone, target("apxf")))
long foo1 (int a, int b)
{
return a > b ? 0 : 1;
}
+__attribute__((noinline, noclone, target("apxf")))
int foo2 (int a, int b)
{
return a != b ? 0 : 1;
}
+__attribute__((noinline, noclone, target("apxf")))
short foo3 (int a, int b)
{
return a < b ? 0 : 1;
}
+__attribute__((noinline, noclone, target("apxf")))
unsigned long
f1(unsigned short x)
{
diff --git a/gcc/testsuite/gcc.target/i386/apx-zu-2.c
b/gcc/testsuite/gcc.target/i386/apx-zu-2.c
index 3ee04495d98a..7585492bd7c2 100644
--- a/gcc/testsuite/gcc.target/i386/apx-zu-2.c
+++ b/gcc/testsuite/gcc.target/i386/apx-zu-2.c
@@ -5,6 +5,9 @@
int main(void)
{
+ if (!__builtin_cpu_supports ("apxf"))
+return 0;
+
if (foo0 (0))
__builtin_abort ();
if (foo1 (3, 2))
[gcc r15-1370] i386: Refine all cvtt* instructions with UNSPEC instead of FIX/UNSIGNED_FIX.
https://gcc.gnu.org/g:b5d3ad256afdfd891d37d8fdb126d599f150e78b commit r15-1370-gb5d3ad256afdfd891d37d8fdb126d599f150e78b Author: Hu, Lin1 Date: Wed Jun 12 16:25:34 2024 +0800 i386: Refine all cvtt* instructions with UNSPEC instead of FIX/UNSIGNED_FIX. gcc/ChangeLog: PR target/115161 * config/i386/i386-builtin.def: Change CODE_FOR_* for cvtt*'s builtins. * config/i386/sse.md: (unspec_avx512fp16_fix _trunc2): Use UNSPEC instead of FIX/UNSIGNED_FIX. (unspec_avx512fp16_fix_trunc2): Ditto. (unspec_avx512fp16_fix_truncv2di2): Ditto. (unspec_avx512fp16_fix_trunc2): Ditto. (unspec_sse_cvttps2pi): Ditto. (unspec_sse_cvttss2si): Ditto. (unspec_fix_truncv16sfv16si2): Ditto. (unspec_fix_truncv8sfv8si2): Ditto. (unspec_fix_truncv4sfv4si2): Ditto. (unspec_sse2_cvttpd2pi): Ditto. (unspec_fixuns_truncv2dfv2si2): Ditto. (unspec_avx512f_vcvttss2usi): Ditto. (unspec_avx512f_vcvttsd2usi): Ditto. (unspec_sse2_cvttsd2si): Ditto. (unspec_fix_truncv8dfv8si2): Ditto. (*unspec_fixuns_truncv2dfv2si2): Ditto. (unspec_fixuns_truncv2dfv2si2_mask): Ditto. (unspec_fix_truncv4dfv4si2): Ditto. (unspec_fixuns_truncv4dfv4si2): Ditto. (unspec_fix _trunc2): Ditto. (unspec_fix _trunc2): Ditto. (unspec_avx512dq_fix_truncv2sfv2di2): Ditto. (unspec_fixuns_trunc2): Ditto. (unspec_sse2_cvttpd2dq): Ditto. gcc/testsuite/ChangeLog: PR target/115161 * gcc.target/i386/pr115161-1.c: New test. Diff: --- gcc/config/i386/i386-builtin.def | 128 +-- gcc/config/i386/sse.md | 335 + gcc/testsuite/gcc.target/i386/pr115161-1.c | 65 ++ 3 files changed, 464 insertions(+), 64 deletions(-) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index a28c48c75668..edb1d2f11b22 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -635,9 +635,9 @@ BDESC (OPTION_MASK_ISA_SSE, 0, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX, 0, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF) BDESC (OPTION_MASK_ISA_SSE, 0, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF) BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF) -BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX, 0, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF) -BDESC (OPTION_MASK_ISA_SSE, 0, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF) -BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF) +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX, 0, CODE_FOR_unspec_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF) +BDESC (OPTION_MASK_ISA_SSE, 0, CODE_FOR_unspec_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF) +BDESC (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_unspec_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF) BDESC (OPTION_MASK_ISA_SSE, 0, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT) @@ -729,19 +729,19 @@ BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2p BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF) BDESC (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF) BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF) -BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF) -BDESC (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF) +BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_unspec_sse2_cvttpd2dq
[gcc r15-1369] Fix ICE when compiling with -fcoarray=single, when derefing a non-array.
https://gcc.gnu.org/g:db75a6657e9de6ee7effe46cd2626d9bb946f2e6
commit r15-1369-gdb75a6657e9de6ee7effe46cd2626d9bb946f2e6
Author: Andre Vehreschild
Date: Tue Jun 11 15:24:55 2024 +0200
Fix ICE when compiling with -fcoarray=single, when derefing a non-array.
PR fortran/96418
PR fortran/103112
gcc/fortran/ChangeLog:
* trans.cc (gfc_deallocate_with_status): Check that object to deref
is an array, before applying array deref.
gcc/testsuite/ChangeLog:
* gfortran.dg/coarray_alloc_comp_3.f08: Moved to...
* gfortran.dg/coarray/alloc_comp_8.f90: ...here.
Should be tested for both -fcoarray=single and lib, resp.
* gfortran.dg/coarray_alloc_comp_4.f08: Fix program name.
Diff:
---
gcc/fortran/trans.cc | 3 ++-
.../gfortran.dg/{coarray_alloc_comp_3.f08 => coarray/alloc_comp_8.f90} | 3 +--
gcc/testsuite/gfortran.dg/coarray_alloc_comp_4.f08 | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/fortran/trans.cc b/gcc/fortran/trans.cc
index a208afe90ab0..1335b8cc48bb 100644
--- a/gcc/fortran/trans.cc
+++ b/gcc/fortran/trans.cc
@@ -1838,7 +1838,8 @@ gfc_deallocate_with_status (tree pointer, tree status,
tree errmsg,
else
caf_dereg_type = (enum gfc_coarray_deregtype) coarray_dealloc_mode;
}
- else if (flag_coarray == GFC_FCOARRAY_SINGLE)
+ else if (flag_coarray == GFC_FCOARRAY_SINGLE
+ && GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (pointer)))
pointer = gfc_conv_descriptor_data_get (pointer);
}
else if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (pointer)))
diff --git a/gcc/testsuite/gfortran.dg/coarray_alloc_comp_3.f08
b/gcc/testsuite/gfortran.dg/coarray/alloc_comp_8.f90
similarity index 95%
rename from gcc/testsuite/gfortran.dg/coarray_alloc_comp_3.f08
rename to gcc/testsuite/gfortran.dg/coarray/alloc_comp_8.f90
index e2037aa58093..8b1539251298 100644
--- a/gcc/testsuite/gfortran.dg/coarray_alloc_comp_3.f08
+++ b/gcc/testsuite/gfortran.dg/coarray/alloc_comp_8.f90
@@ -1,12 +1,11 @@
! { dg-do run }
-! { dg-options "-fcoarray=lib -lcaf_single" }
! { dg-additional-options "-latomic" { target libatomic_available } }
!
! Contributed by Andre Vehreschild
! Check that manually freeing components does not lead to a runtime crash,
! when the auto-deallocation is taking care.
-program coarray_alloc_comp_3
+program alloc_comp_6
implicit none
type dt
diff --git a/gcc/testsuite/gfortran.dg/coarray_alloc_comp_4.f08
b/gcc/testsuite/gfortran.dg/coarray_alloc_comp_4.f08
index 6586ec651ddf..4c71a90af8fa 100644
--- a/gcc/testsuite/gfortran.dg/coarray_alloc_comp_4.f08
+++ b/gcc/testsuite/gfortran.dg/coarray_alloc_comp_4.f08
@@ -5,7 +5,7 @@
! Contributed by Andre Vehreschild
! Check that sub-components are caf_deregistered and not freed.
-program coarray_alloc_comp_3
+program coarray_alloc_comp_4
implicit none
type dt
