[gcc r15-1466] build: Fix missing variable quotes and typo
https://gcc.gnu.org/g:bea447a2982f3094aa3423b5045cea929f4f4700 commit r15-1466-gbea447a2982f3094aa3423b5045cea929f4f4700 Author: Collin Funk Date: Wed Jun 19 16:36:50 2024 -0700 build: Fix missing variable quotes and typo When dlopen and pthread_create are in libc the variable is set to "none required", therefore running configure will show the following errors: ./configure: line 8997: test: too many arguments ./configure: line 8999: test: too many arguments ./configure: line 9003: test: too many arguments ./configure: line 9005: test: =: unary operator expected ChangeLog: PR bootstrap/115453 * configure.ac: Quote variable result of AC_SEARCH_LIBS. Fix typo ac_cv_search_pthread_crate. * configure: Regenerate. Signed-off-by: Collin Funk Diff: --- configure| 8 configure.ac | 8 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/configure b/configure index 51576a41f303..51bf1d1add18 100755 --- a/configure +++ b/configure @@ -8994,15 +8994,15 @@ if test "$ac_res" != no; then : fi -if test $ac_cv_search_dlopen = -ldl; then +if test "$ac_cv_search_dlopen" = -ldl; then CRAB1_LIBS="$CRAB1_LIBS -ldl" -elif test $ac_cv_search_dlopen = no; then +elif test "$ac_cv_search_dlopen" = no; then missing_rust_dynlibs="libdl" fi -if test $ac_cv_search_pthread_create = -lpthread; then +if test "$ac_cv_search_pthread_create" = -lpthread; then CRAB1_LIBS="$CRAB1_LIBS -lpthread" -elif test $ac_cv_search_pthread_crate = no; then +elif test "$ac_cv_search_pthread_create" = no; then missing_rust_dynlibs="$missing_rust_dynlibs, libpthread" fi diff --git a/configure.ac b/configure.ac index 5eda8dcdbf72..20457005e299 100644 --- a/configure.ac +++ b/configure.ac @@ -2045,15 +2045,15 @@ missing_rust_dynlibs=none AC_SEARCH_LIBS([dlopen], [dl]) AC_SEARCH_LIBS([pthread_create], [pthread]) -if test $ac_cv_search_dlopen = -ldl; then +if test "$ac_cv_search_dlopen" = -ldl; then CRAB1_LIBS="$CRAB1_LIBS -ldl" -elif test $ac_cv_search_dlopen = no; then +elif test "$ac_cv_search_dlopen" = no; then missing_rust_dynlibs="libdl" fi -if test $ac_cv_search_pthread_create = -lpthread; then +if test "$ac_cv_search_pthread_create" = -lpthread; then CRAB1_LIBS="$CRAB1_LIBS -lpthread" -elif test $ac_cv_search_pthread_crate = no; then +elif test "$ac_cv_search_pthread_create" = no; then missing_rust_dynlibs="$missing_rust_dynlibs, libpthread" fi
[gcc r15-1465] vect: Tighten an assertion for lane-reducing in transform
https://gcc.gnu.org/g:ecbc96bb2873e453b0bd33d602ce34ad0d9d9cfd
commit r15-1465-gecbc96bb2873e453b0bd33d602ce34ad0d9d9cfd
Author: Feng Xue
Date: Sun Jun 16 13:33:52 2024 +0800
vect: Tighten an assertion for lane-reducing in transform
According to logic of code nearby the assertion, all lane-reducing
operations
should not appear, not just DOT_PROD_EXPR. Since "use_mask_by_cond_expr_p"
treats SAD_EXPR same as DOT_PROD_EXPR, and WIDEN_SUM_EXPR should not be
allowed
by the following assertion "gcc_assert (commutative_binary_op_p (...))", so
tighten the assertion.
2024-06-16 Feng Xue
gcc/
* tree-vect-loop.cc (vect_transform_reduction): Change assertion to
cover all lane-reducing ops.
Diff:
---
gcc/tree-vect-loop.cc | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index 1d60ac47e553..347dac97e497 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -8618,7 +8618,8 @@ vect_transform_reduction (loop_vec_info loop_vinfo,
}
bool single_defuse_cycle = STMT_VINFO_FORCE_SINGLE_CYCLE (reduc_info);
- gcc_assert (single_defuse_cycle || lane_reducing_op_p (code));
+ bool lane_reducing = lane_reducing_op_p (code);
+ gcc_assert (single_defuse_cycle || lane_reducing);
/* Create the destination vector */
tree scalar_dest = gimple_get_lhs (stmt_info->stmt);
@@ -8674,8 +8675,9 @@ vect_transform_reduction (loop_vec_info loop_vinfo,
tree vop[3] = { vec_oprnds[0][i], vec_oprnds[1][i], NULL_TREE };
if (masked_loop_p && !mask_by_cond_expr)
{
- /* No conditional ifns have been defined for dot-product yet. */
- gcc_assert (code != DOT_PROD_EXPR);
+ /* No conditional ifns have been defined for lane-reducing op
+yet. */
+ gcc_assert (!lane_reducing);
/* Make sure that the reduction accumulator is vop[0]. */
if (reduc_index == 1)
[gcc r15-1464] vect: Use an array to replace 3 relevant variables
https://gcc.gnu.org/g:b9c369d900ccfbd2271028611af3f08b5cf6f998
commit r15-1464-gb9c369d900ccfbd2271028611af3f08b5cf6f998
Author: Feng Xue
Date: Sun Jun 16 13:21:13 2024 +0800
vect: Use an array to replace 3 relevant variables
It's better to place 3 relevant independent variables into array, since we
have requirement to access them via an index in the following patch. At the
same time, this change may get some duplicated code be more compact.
2024-06-16 Feng Xue
gcc/
* tree-vect-loop.cc (vect_transform_reduction): Replace
vec_oprnds0/1/2
with one new array variable vec_oprnds[3].
Diff:
---
gcc/tree-vect-loop.cc | 43 ++-
1 file changed, 18 insertions(+), 25 deletions(-)
diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index 27f77ed8b0b6..1d60ac47e553 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -8580,9 +8580,7 @@ vect_transform_reduction (loop_vec_info loop_vinfo,
/* Transform. */
tree new_temp = NULL_TREE;
- auto_vec vec_oprnds0;
- auto_vec vec_oprnds1;
- auto_vec vec_oprnds2;
+ auto_vec vec_oprnds[3];
if (dump_enabled_p ())
dump_printf_loc (MSG_NOTE, vect_location, "transform reduction.\n");
@@ -8630,14 +8628,15 @@ vect_transform_reduction (loop_vec_info loop_vinfo,
definition. */
if (!cond_fn_p)
{
+ gcc_assert (reduc_index >= 0 && reduc_index <= 2);
vect_get_vec_defs (loop_vinfo, stmt_info, slp_node, ncopies,
single_defuse_cycle && reduc_index == 0
-? NULL_TREE : op.ops[0], _oprnds0,
+? NULL_TREE : op.ops[0], _oprnds[0],
single_defuse_cycle && reduc_index == 1
-? NULL_TREE : op.ops[1], _oprnds1,
+? NULL_TREE : op.ops[1], _oprnds[1],
op.num_ops == 3
&& !(single_defuse_cycle && reduc_index == 2)
-? op.ops[2] : NULL_TREE, _oprnds2);
+? op.ops[2] : NULL_TREE, _oprnds[2]);
}
else
{
@@ -8645,12 +8644,12 @@ vect_transform_reduction (loop_vec_info loop_vinfo,
vectype. */
gcc_assert (single_defuse_cycle
&& (reduc_index == 1 || reduc_index == 2));
- vect_get_vec_defs (loop_vinfo, stmt_info, slp_node, ncopies,
-op.ops[0], truth_type_for (vectype_in), _oprnds0,
+ vect_get_vec_defs (loop_vinfo, stmt_info, slp_node, ncopies, op.ops[0],
+truth_type_for (vectype_in), _oprnds[0],
reduc_index == 1 ? NULL_TREE : op.ops[1],
-NULL_TREE, _oprnds1,
+NULL_TREE, _oprnds[1],
reduc_index == 2 ? NULL_TREE : op.ops[2],
-NULL_TREE, _oprnds2);
+NULL_TREE, _oprnds[2]);
}
/* For single def-use cycles get one copy of the vectorized reduction
@@ -8658,20 +8657,21 @@ vect_transform_reduction (loop_vec_info loop_vinfo,
if (single_defuse_cycle)
{
vect_get_vec_defs (loop_vinfo, stmt_info, slp_node, 1,
-reduc_index == 0 ? op.ops[0] : NULL_TREE, _oprnds0,
-reduc_index == 1 ? op.ops[1] : NULL_TREE, _oprnds1,
+reduc_index == 0 ? op.ops[0] : NULL_TREE,
+_oprnds[0],
+reduc_index == 1 ? op.ops[1] : NULL_TREE,
+_oprnds[1],
reduc_index == 2 ? op.ops[2] : NULL_TREE,
-_oprnds2);
+_oprnds[2]);
}
bool emulated_mixed_dot_prod = vect_is_emulated_mixed_dot_prod (stmt_info);
+ unsigned num = vec_oprnds[reduc_index == 0 ? 1 : 0].length ();
- unsigned num = (reduc_index == 0
- ? vec_oprnds1.length () : vec_oprnds0.length ());
for (unsigned i = 0; i < num; ++i)
{
gimple *new_stmt;
- tree vop[3] = { vec_oprnds0[i], vec_oprnds1[i], NULL_TREE };
+ tree vop[3] = { vec_oprnds[0][i], vec_oprnds[1][i], NULL_TREE };
if (masked_loop_p && !mask_by_cond_expr)
{
/* No conditional ifns have been defined for dot-product yet. */
@@ -8696,7 +8696,7 @@ vect_transform_reduction (loop_vec_info loop_vinfo,
else
{
if (op.num_ops >= 3)
- vop[2] = vec_oprnds2[i];
+ vop[2] = vec_oprnds[2][i];
if (masked_loop_p && mask_by_cond_expr)
{
@@ -8727,14 +8727,7 @@ vect_transform_reduction (loop_vec_info loop_vinfo,
}
if (single_defuse_cycle && i < num - 1)
- {
- if (reduc_index == 0)
- vec_oprnds0.safe_push (gimple_get_lhs (new_stmt));
- else if (reduc_index == 1)
- vec_oprnds1.safe_push (gimple_get_lhs (new_stmt));
- else if (reduc_index == 2)
-
[gcc r15-1463] vect: Use one reduction_type local variable
https://gcc.gnu.org/g:0726f1cde5459ccdbaa6af8c6904276a28d572ba
commit r15-1463-g0726f1cde5459ccdbaa6af8c6904276a28d572ba
Author: Feng Xue
Date: Sun Jun 16 12:17:26 2024 +0800
vect: Use one reduction_type local variable
Two local variables were defined to refer same STMT_VINFO_REDUC_TYPE, better
to keep only one.
2024-06-16 Feng Xue
gcc/
* tree-vect-loop.cc (vectorizable_reduction): Remove v_reduc_type,
and
replace it to another local variable reduction_type.
Diff:
---
gcc/tree-vect-loop.cc | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index aab408d1019d..27f77ed8b0b6 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -7868,10 +7868,10 @@ vectorizable_reduction (loop_vec_info loop_vinfo,
if (lane_reducing)
STMT_VINFO_REDUC_VECTYPE_IN (stmt_info) = vectype_in;
- enum vect_reduction_type v_reduc_type = STMT_VINFO_REDUC_TYPE (phi_info);
- STMT_VINFO_REDUC_TYPE (reduc_info) = v_reduc_type;
+ enum vect_reduction_type reduction_type = STMT_VINFO_REDUC_TYPE (phi_info);
+ STMT_VINFO_REDUC_TYPE (reduc_info) = reduction_type;
/* If we have a condition reduction, see if we can simplify it further. */
- if (v_reduc_type == COND_REDUCTION)
+ if (reduction_type == COND_REDUCTION)
{
if (slp_node && SLP_TREE_LANES (slp_node) != 1)
return false;
@@ -8038,7 +8038,7 @@ vectorizable_reduction (loop_vec_info loop_vinfo,
STMT_VINFO_REDUC_CODE (reduc_info) = orig_code;
- vect_reduction_type reduction_type = STMT_VINFO_REDUC_TYPE (reduc_info);
+ reduction_type = STMT_VINFO_REDUC_TYPE (reduc_info);
if (reduction_type == TREE_CODE_REDUCTION)
{
/* Check whether it's ok to change the order of the computation.
[gcc r15-1462] vect: Remove duplicated check on reduction operand
https://gcc.gnu.org/g:a944e57506fc64b8eede79c2405ba0b498461f0b commit r15-1462-ga944e57506fc64b8eede79c2405ba0b498461f0b Author: Feng Xue Date: Sun Jun 16 12:08:56 2024 +0800 vect: Remove duplicated check on reduction operand In vectorizable_reduction, one check on a reduction operand via index could be contained by another one check via pointer, so remove the former. 2024-06-16 Feng Xue gcc/ * tree-vect-loop.cc (vectorizable_reduction): Remove the duplicated check. Diff: --- gcc/tree-vect-loop.cc | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc index eeb75c09e91a..aab408d1019d 100644 --- a/gcc/tree-vect-loop.cc +++ b/gcc/tree-vect-loop.cc @@ -7815,11 +7815,9 @@ vectorizable_reduction (loop_vec_info loop_vinfo, "use not simple.\n"); return false; } - if (i == STMT_VINFO_REDUC_IDX (stmt_info)) - continue; - /* For an IFN_COND_OP we might hit the reduction definition operand -twice (once as definition, once as else). */ + /* Skip reduction operands, and for an IFN_COND_OP we might hit the +reduction operand twice (once as definition, once as else). */ if (op.ops[i] == op.ops[STMT_VINFO_REDUC_IDX (stmt_info)]) continue;
[gcc r15-1461] vect: Add a function to check lane-reducing stmt
https://gcc.gnu.org/g:70466e6f9d9fb87f78ffe2e397ca876b380cb493
commit r15-1461-g70466e6f9d9fb87f78ffe2e397ca876b380cb493
Author: Feng Xue
Date: Sat Jun 15 23:17:10 2024 +0800
vect: Add a function to check lane-reducing stmt
Add a utility function to check if a statement is lane-reducing operation,
which could simplify some existing code.
2024-06-16 Feng Xue
gcc/
* tree-vectorizer.h (lane_reducing_stmt_p): New function.
* tree-vect-slp.cc (vect_analyze_slp): Use new function
lane_reducing_stmt_p to check statement.
Diff:
---
gcc/tree-vect-slp.cc | 4 +---
gcc/tree-vectorizer.h | 12
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index 7d18b5bfee5d..a5665946a4eb 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -3919,7 +3919,6 @@ vect_analyze_slp (vec_info *vinfo, unsigned max_tree_size)
scalar_stmts.create (loop_vinfo->reductions.length ());
for (auto next_info : loop_vinfo->reductions)
{
- gassign *g;
next_info = vect_stmt_to_vectorize (next_info);
if ((STMT_VINFO_RELEVANT_P (next_info)
|| STMT_VINFO_LIVE_P (next_info))
@@ -3931,8 +3930,7 @@ vect_analyze_slp (vec_info *vinfo, unsigned max_tree_size)
{
/* Do not discover SLP reductions combining lane-reducing
ops, that will fail later. */
- if (!(g = dyn_cast (STMT_VINFO_STMT (next_info)))
- || !lane_reducing_op_p (gimple_assign_rhs_code (g)))
+ if (!lane_reducing_stmt_p (STMT_VINFO_STMT (next_info)))
scalar_stmts.quick_push (next_info);
else
{
diff --git a/gcc/tree-vectorizer.h b/gcc/tree-vectorizer.h
index 6bb0f5c3a56f..60224f4e2847 100644
--- a/gcc/tree-vectorizer.h
+++ b/gcc/tree-vectorizer.h
@@ -2169,12 +2169,24 @@ vect_apply_runtime_profitability_check_p (loop_vec_info
loop_vinfo)
&& th >= vect_vf_for_cost (loop_vinfo));
}
+/* Return true if CODE is a lane-reducing opcode. */
+
inline bool
lane_reducing_op_p (code_helper code)
{
return code == DOT_PROD_EXPR || code == WIDEN_SUM_EXPR || code == SAD_EXPR;
}
+/* Return true if STMT is a lane-reducing statement. */
+
+inline bool
+lane_reducing_stmt_p (gimple *stmt)
+{
+ if (auto *assign = dyn_cast (stmt))
+return lane_reducing_op_p (gimple_assign_rhs_code (assign));
+ return false;
+}
+
/* Source location + hotness information. */
extern dump_user_location_t vect_location;
[gcc r15-1459] Revert "build: Fix missing variable quotes"
https://gcc.gnu.org/g:6d6587bc37f2039225e4fba9acaf7b26e600e3d3
commit r15-1459-g6d6587bc37f2039225e4fba9acaf7b26e600e3d3
Author: YunQiang Su
Date: Thu Jun 20 07:02:47 2024 +0800
Revert "build: Fix missing variable quotes"
This reverts commit c6a9ab8c920f297c4efd289182aef9fbc73f5906.
Diff:
---
configure| 10 +-
configure.ac | 8
gcc/configure| 2 +-
gcc/configure.ac | 2 +-
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/configure b/configure
index 6e95b27d9df4..51576a41f303 100755
--- a/configure
+++ b/configure
@@ -8994,15 +8994,15 @@ if test "$ac_res" != no; then :
fi
-if test "$ac_cv_search_dlopen" = -ldl; then
+if test $ac_cv_search_dlopen = -ldl; then
CRAB1_LIBS="$CRAB1_LIBS -ldl"
-elif test "$ac_cv_search_dlopen" = no; then
+elif test $ac_cv_search_dlopen = no; then
missing_rust_dynlibs="libdl"
fi
-if test "$ac_cv_search_pthread_create" = -lpthread; then
+if test $ac_cv_search_pthread_create = -lpthread; then
CRAB1_LIBS="$CRAB1_LIBS -lpthread"
-elif test "$ac_cv_search_pthread_crate" = no; then
+elif test $ac_cv_search_pthread_crate = no; then
missing_rust_dynlibs="$missing_rust_dynlibs, libpthread"
fi
@@ -19746,7 +19746,7 @@ config.status
configured by $0, generated by GNU Autoconf 2.69,
with options \\"\$ac_cs_config\\"
-Copyright (C) Free Software Foundation, Inc.
+Copyright (C) 2012 Free Software Foundation, Inc.
This config.status script is free software; the Free Software Foundation
gives unlimited permission to copy, distribute and modify it."
diff --git a/configure.ac b/configure.ac
index 88576b31bfcd..5eda8dcdbf72 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2045,15 +2045,15 @@ missing_rust_dynlibs=none
AC_SEARCH_LIBS([dlopen], [dl])
AC_SEARCH_LIBS([pthread_create], [pthread])
-if test "$ac_cv_search_dlopen" = -ldl; then
+if test $ac_cv_search_dlopen = -ldl; then
CRAB1_LIBS="$CRAB1_LIBS -ldl"
-elif test "$ac_cv_search_dlopen" = no; then
+elif test $ac_cv_search_dlopen = no; then
missing_rust_dynlibs="libdl"
fi
-if test "$ac_cv_search_pthread_create" = -lpthread; then
+if test $ac_cv_search_pthread_create = -lpthread; then
CRAB1_LIBS="$CRAB1_LIBS -lpthread"
-elif test "$ac_cv_search_pthread_crate" = no; then
+elif test $ac_cv_search_pthread_crate = no; then
missing_rust_dynlibs="$missing_rust_dynlibs, libpthread"
fi
diff --git a/gcc/configure b/gcc/configure
index b536af664d3d..9dc0b65dfaac 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -30239,7 +30239,7 @@ else
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result:
$gcc_cv_as_mips_explicit_relocs_pcrel" >&5
$as_echo "$gcc_cv_as_mips_explicit_relocs_pcrel" >&6; }
-if test "x$gcc_cv_as_mips_explicit_relocs_pcrel" = "xyes"; then
+if test $gcc_cv_as_mips_explicit_relocs_pcrel = yes; then
$as_echo "#define MIPS_EXPLICIT_RELOCS MIPS_EXPLICIT_RELOCS_PCREL" >>confdefs.h
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 1501bf89c89d..b2243e9954aa 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -5317,7 +5317,7 @@ x:
AC_MSG_CHECKING(assembler and linker for explicit JALR relocation)
gcc_cv_as_ld_jalr_reloc=no
-if test "x$gcc_cv_as_mips_explicit_relocs" = "xyes"; then
+if test $gcc_cv_as_mips_explicit_relocs = yes; then
if test $in_tree_ld = yes ; then
if test "$gcc_cv_gld_major_version" -eq 2 -a
"$gcc_cv_gld_minor_version" -ge 20 -o "$gcc_cv_gld_major_version" -gt 2 \
&& test $in_tree_ld_is_elf = yes; then
[gcc r15-1458] Revert "Build: Fix typo ac_cv_search_pthread_crate"
https://gcc.gnu.org/g:a334189739e13f8de1f9af99f8d16970435cebc4 commit r15-1458-ga334189739e13f8de1f9af99f8d16970435cebc4 Author: YunQiang Su Date: Thu Jun 20 07:02:33 2024 +0800 Revert "Build: Fix typo ac_cv_search_pthread_crate" This reverts commit 8088374a868aacab4dff208ec3e3fde790a1d9a3. Diff: --- configure| 2 +- configure.ac | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 1469cd735392..6e95b27d9df4 100755 --- a/configure +++ b/configure @@ -9002,7 +9002,7 @@ fi if test "$ac_cv_search_pthread_create" = -lpthread; then CRAB1_LIBS="$CRAB1_LIBS -lpthread" -elif test "$ac_cv_search_pthread_create" = no; then +elif test "$ac_cv_search_pthread_crate" = no; then missing_rust_dynlibs="$missing_rust_dynlibs, libpthread" fi diff --git a/configure.ac b/configure.ac index 20457005e299..88576b31bfcd 100644 --- a/configure.ac +++ b/configure.ac @@ -2053,7 +2053,7 @@ fi if test "$ac_cv_search_pthread_create" = -lpthread; then CRAB1_LIBS="$CRAB1_LIBS -lpthread" -elif test "$ac_cv_search_pthread_create" = no; then +elif test "$ac_cv_search_pthread_crate" = no; then missing_rust_dynlibs="$missing_rust_dynlibs, libpthread" fi
[gcc r15-1457] [PATCH v2] RISC-V: Remove float vector eqne pattern
https://gcc.gnu.org/g:f0204ae3861e5f2e6099719c2cb1718e064c8c12
commit r15-1457-gf0204ae3861e5f2e6099719c2cb1718e064c8c12
Author: demin.han
Date: Wed Jun 19 16:21:13 2024 -0600
[PATCH v2] RISC-V: Remove float vector eqne pattern
We can unify eqne and other comparison operations.
Tested on RV32 and RV64
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond
* config/riscv/vector.md (@pred_eqne_scalar): Remove patterns
(*pred_eqne_scalar_merge_tie_mask): Ditto
(*pred_eqne_scalar): Ditto
(*pred_eqne_scalar_narrow): Ditto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cmp-eqne.c: New test.
Diff:
---
gcc/config/riscv/riscv-vector-builtins-bases.cc| 8 +-
gcc/config/riscv/vector.md | 86 --
.../riscv/rvv/base/float-point-cmp-eqne.c | 54 ++
3 files changed, 56 insertions(+), 92 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index b6f6e4ff37e7..596b88cc8a3c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1420,12 +1420,8 @@ public:
switch (e.op_info->op)
{
case OP_TYPE_vf: {
- if (CODE == EQ || CODE == NE)
- return e.use_compare_insn (CODE, code_for_pred_eqne_scalar (
- e.vector_mode ()));
- else
- return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
- e.vector_mode ()));
+ return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
+e.vector_mode ()));
}
case OP_TYPE_vv: {
return e.use_compare_insn (CODE,
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index fbcdf96f038b..f8fae6557d93 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7545,92 +7545,6 @@
(set_attr "mode" "")
(set_attr "spec_restriction" "none,thv,thv,none,none")])
-(define_expand "@pred_eqne_scalar"
- [(set (match_operand: 0 "register_operand")
- (if_then_else:
- (unspec:
- [(match_operand: 1 "vector_mask_operand")
-(match_operand 6 "vector_length_operand")
-(match_operand 7 "const_int_operand")
-(match_operand 8 "const_int_operand")
-(reg:SI VL_REGNUM)
-(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator: 3 "equality_operator"
-[(vec_duplicate:V_VLSF
- (match_operand: 5 "register_operand"))
- (match_operand:V_VLSF 4 "register_operand")])
- (match_operand: 2 "vector_merge_operand")))]
- "TARGET_VECTOR"
- {})
-
-(define_insn "*pred_eqne_scalar_merge_tie_mask"
- [(set (match_operand: 0 "register_operand" "=vm")
- (if_then_else:
- (unspec:
- [(match_operand: 1 "register_operand" " 0")
-(match_operand 5 "vector_length_operand" " rK")
-(match_operand 6 "const_int_operand" " i")
-(match_operand 7 "const_int_operand" " i")
-(reg:SI VL_REGNUM)
-(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator: 2 "equality_operator"
-[(vec_duplicate:V_VLSF
- (match_operand: 4 "register_operand" " f"))
- (match_operand:V_VLSF 3 "register_operand" " vr")])
- (match_dup 1)))]
- "TARGET_VECTOR"
- "vmf%B2.vf\t%0,%3,%4,v0.t"
- [(set_attr "type" "vfcmp")
- (set_attr "mode" "")
- (set_attr "merge_op_idx" "1")
- (set_attr "vl_op_idx" "5")
- (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type_idx") (const_int 7))])
-
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne_scalar"
- [(set (match_operand: 0 "register_operand""=vr, vr,
, ")
- (if_then_else:
- (unspec:
- [(match_operand: 1 "vector_mask_operand"
"vmWc1,vmWc1,vmWc1,vmWc1")
-(match_operand 6 "vector_length_operand" " rK, rK,
rK, rK")
-(match_operand 7 "const_int_operand" "i,i,
i,i")
-(match_operand 8 "const_int_operand" "i,i,
i,i")
-(reg:SI VL_REGNUM)
-(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator: 3 "equality_operator"
-[(vec_duplicate:V_VLSF
- (match_operand: 5 "register_operand" "f,f,
f,f"))
- (match_operand:V_VLSF 4 "register_operand" " vr, vr,
vr, vr")])
- (match_operand: 2 "vector_merge_operand"" vu,0,
[gcc r15-1456] RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils
https://gcc.gnu.org/g:e03583e7ee99552276a90a4094776fda55ab2e02
commit r15-1456-ge03583e7ee99552276a90a4094776fda55ab2e02
Author: Patrick O'Neill
Date: Tue Jun 18 14:40:15 2024 -0700
RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils
Binutils 2.42 and before don't support Zaamo/Zalrsc. When users specify
both Zaamo and Zalrsc, promote them to 'a' in the -march string.
This does not affect testsuite results for users with old versions of
binutils.
Testcases that failed due to 'call'/isa string continue to fail after this
PATCH
when using an old version of binutils.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add 'a' extension to
riscv_combine_info.
Signed-off-by: Patrick O'Neill
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 1dc1d9904c7b..410e673f5e01 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -401,6 +401,7 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
/* Combine extensions defined in this table */
static const struct riscv_ext_version riscv_combine_info[] =
{
+ {"a", ISA_SPEC_CLASS_20191213, 2, 1},
{"zk", ISA_SPEC_CLASS_NONE, 1, 0},
{"zkn", ISA_SPEC_CLASS_NONE, 1, 0},
{"zks", ISA_SPEC_CLASS_NONE, 1, 0},
[gcc r13-8857] Fortran: fix ALLOCATE with SOURCE=, zero-length character [PR83865]
https://gcc.gnu.org/g:0530884fbf49cc81119d66de7e4a48b47172ed4c
commit r13-8857-g0530884fbf49cc81119d66de7e4a48b47172ed4c
Author: Harald Anlauf
Date: Mon Jun 3 22:02:06 2024 +0200
Fortran: fix ALLOCATE with SOURCE=, zero-length character [PR83865]
gcc/fortran/ChangeLog:
PR fortran/83865
* trans-stmt.cc (gfc_trans_allocate): Restrict special case for
source-expression with zero-length character to rank 0, so that
the array shape is not discarded.
gcc/testsuite/ChangeLog:
PR fortran/83865
* gfortran.dg/allocate_with_source_32.f90: New test.
(cherry picked from commit 7f21aee0d4ef95eee7d9f7f42e9a056715836648)
Diff:
---
gcc/fortran/trans-stmt.cc | 3 +-
.../gfortran.dg/allocate_with_source_32.f90| 33 ++
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/gcc/fortran/trans-stmt.cc b/gcc/fortran/trans-stmt.cc
index 35eb1880539b..caa7b59e9129 100644
--- a/gcc/fortran/trans-stmt.cc
+++ b/gcc/fortran/trans-stmt.cc
@@ -6398,8 +6398,9 @@ gfc_trans_allocate (gfc_code * code)
else
gfc_add_block_to_block (, );
- /* Special case when string in expr3 is zero. */
+ /* Special case when string in expr3 is scalar and has length zero. */
if (code->expr3->ts.type == BT_CHARACTER
+ && code->expr3->rank == 0
&& integer_zerop (se.string_length))
{
gfc_init_se (, NULL);
diff --git a/gcc/testsuite/gfortran.dg/allocate_with_source_32.f90
b/gcc/testsuite/gfortran.dg/allocate_with_source_32.f90
new file mode 100644
index ..4a9bd46da4d5
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/allocate_with_source_32.f90
@@ -0,0 +1,33 @@
+! { dg-do run }
+!
+! PR fortran/83865
+!
+! Test ALLOCATE with SOURCE= of deferred length character, where
+! the source-expression is an array of character with length 0.
+
+program p
+ implicit none
+ character(:), allocatable :: z(:)
+ character(1) :: cc(4) = ""
+ allocate (z, source=[''])
+ if (len (z) /= 0 .or. size (z) /= 1) stop 1
+ deallocate (z)
+ allocate (z, source=['',''])
+ if (len (z) /= 0 .or. size (z) /= 2) stop 2
+ deallocate (z)
+ allocate (z, source=[ character(0) :: 'a','b','c'])
+ if (len (z) /= 0 .or. size (z) /= 3) stop 3
+ deallocate (z)
+ allocate (z, source=[ character(0) :: cc ])
+ if (len (z) /= 0 .or. size (z) /= 4) stop 4
+ deallocate (z)
+ associate (x => f())
+if (len (x) /= 0 .or. size (x) /= 1) stop 5
+if (x(1) /= '') stop 6
+ end associate
+contains
+ function f() result(z)
+character(:), allocatable :: z(:)
+allocate (z, source=[''])
+ end function f
+end
[gcc r15-1455] bitint: Fix up lowering of COMPLEX_EXPR [PR115544]
https://gcc.gnu.org/g:25860fd2a674373a6476af5ff0bd92354fc53d06
commit r15-1455-g25860fd2a674373a6476af5ff0bd92354fc53d06
Author: Jakub Jelinek
Date: Wed Jun 19 21:10:39 2024 +0200
bitint: Fix up lowering of COMPLEX_EXPR [PR115544]
We don't really support _Complex _BitInt(N), the only place we use
bitint complex types is for the .{ADD,SUB,MUL}_OVERFLOW internal function
results and COMPLEX_EXPR in the usual case should be either not present
yet because the ifns weren't folded and will be lowered, or optimized
into something simpler, because normally the complex bitint should be
used just for extracting the 2 subparts from it.
Still, with disabled optimizations it can occassionally happen that it
appears in the IL and that is why there is support for lowering those,
but it doesn't handle optimizing those too much, so if it uses SSA_NAME,
it relies on them having a backing VAR_DECL during the lowering.
This is normally achieves through the
&& ((is_gimple_assign (use_stmt)
&& (gimple_assign_rhs_code (use_stmt)
!= COMPLEX_EXPR))
|| gimple_code (use_stmt) == GIMPLE_COND)
hunk in gimple_lower_bitint, but as the following testcase shows, there
is one thing I've missed, the load optimization isn't guarded by the
above stuff. So, either we'd need to add support for loads to
lower_complexexpr_stmt, or because they should be really rare, this
patch just disables the load optimization if at least one load use is
a COMPLEX_EXPR (like we do already for PHIs, calls, asm).
2024-06-19 Jakub Jelinek
PR tree-optimization/115544
* gimple-lower-bitint.cc (gimple_lower_bitint): Disable optimizing
loads used by COMPLEX_EXPR operands.
* gcc.dg/bitint-107.c: New test.
Diff:
---
gcc/gimple-lower-bitint.cc| 5 -
gcc/testsuite/gcc.dg/bitint-107.c | 16
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/gcc/gimple-lower-bitint.cc b/gcc/gimple-lower-bitint.cc
index 56e5f826a8d9..f955f3eabd9b 100644
--- a/gcc/gimple-lower-bitint.cc
+++ b/gcc/gimple-lower-bitint.cc
@@ -6630,7 +6630,10 @@ gimple_lower_bitint (void)
continue;
if (gimple_code (use_stmt) == GIMPLE_PHI
|| is_gimple_call (use_stmt)
- || gimple_code (use_stmt) == GIMPLE_ASM)
+ || gimple_code (use_stmt) == GIMPLE_ASM
+ || (is_gimple_assign (use_stmt)
+ && (gimple_assign_rhs_code (use_stmt)
+ == COMPLEX_EXPR)))
{
optimizable_load = false;
break;
diff --git a/gcc/testsuite/gcc.dg/bitint-107.c
b/gcc/testsuite/gcc.dg/bitint-107.c
new file mode 100644
index ..a3f5f534088f
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/bitint-107.c
@@ -0,0 +1,16 @@
+/* PR tree-optimization/115544 */
+/* { dg-do compile { target bitint } } */
+/* { dg-options "-O -fno-tree-fre -fno-tree-ccp -fno-tree-forwprop" } */
+
+#if __BITINT_MAXWIDTH__ >= 129
+typedef _BitInt(129) B;
+#else
+typedef _BitInt(63) B;
+#endif
+B a, b;
+
+int
+foo (void)
+{
+ return __builtin_mul_overflow (a, 1, );
+}
[gcc r15-1454] i386: Zhaoxin shijidadao enablement
https://gcc.gnu.org/g:6f6ea27d17e9bbc917b94ffea1c933755e736bdc
commit r15-1454-g6f6ea27d17e9bbc917b94ffea1c933755e736bdc
Author: mayshao
Date: Wed Jun 19 16:03:25 2024 +0200
i386: Zhaoxin shijidadao enablement
This patch enables -march/-mtune=shijidadao, costs and tunings are set
according to the characteristics of the processor.
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Recognize
shijidadao.
* common/config/i386/i386-common.cc: Add shijidadao.
* common/config/i386/i386-cpuinfo.h (enum processor_subtypes):
Add ZHAOXIN_FAM7H_SHIJIDADAO.
* config.gcc: Add shijidadao.
* config/i386/driver-i386.cc (host_detect_local_cpu):
Let -march=native recognize shijidadao processors.
* config/i386/i386-c.cc (ix86_target_macros_internal): Add
shijidadao.
* config/i386/i386-options.cc (m_ZHAOXIN): Add m_SHIJIDADAO.
(m_SHIJIDADAO): New definition.
* config/i386/i386.h (enum processor_type): Add
PROCESSOR_SHIJIDADAO.
* config/i386/x86-tune-costs.h (struct processor_costs):
Add shijidadao_cost.
* config/i386/x86-tune-sched.cc (ix86_issue_rate): Add shijidadao.
(ix86_adjust_cost): Ditto.
* config/i386/x86-tune.def (X86_TUNE_USE_GATHER_2PARTS): Add
m_SHIJIDADAO.
(X86_TUNE_USE_GATHER_4PARTS): Ditto.
(X86_TUNE_USE_GATHER_8PARTS): Ditto.
(X86_TUNE_AVOID_128FMA_CHAINS): Ditto.
* doc/extend.texi: Add details about shijidadao.
* doc/invoke.texi: Ditto.
gcc/testsuite/ChangeLog:
* g++.target/i386/mv32.C: Handle new -march
* gcc.target/i386/funcspec-56.inc: Ditto.
Diff:
---
gcc/common/config/i386/cpuinfo.h | 8 +-
gcc/common/config/i386/i386-common.cc | 8 +-
gcc/common/config/i386/i386-cpuinfo.h | 1 +
gcc/config.gcc| 14 +++-
gcc/config/i386/driver-i386.cc| 11 ++-
gcc/config/i386/i386-c.cc | 7 ++
gcc/config/i386/i386-options.cc | 4 +-
gcc/config/i386/i386.h| 1 +
gcc/config/i386/x86-tune-costs.h | 116 ++
gcc/config/i386/x86-tune-sched.cc | 2 +
gcc/config/i386/x86-tune.def | 8 +-
gcc/doc/extend.texi | 3 +
gcc/doc/invoke.texi | 6 ++
gcc/testsuite/g++.target/i386/mv32.C | 6 ++
gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 +
15 files changed, 183 insertions(+), 14 deletions(-)
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 4610bf6d6a45..936039725ab6 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -667,12 +667,18 @@ get_zhaoxin_cpu (struct __processor_model *cpu_model,
reset_cpu_feature (cpu_model, cpu_features2, FEATURE_F16C);
cpu_model->__cpu_subtype = ZHAOXIN_FAM7H_LUJIAZUI;
}
- else if (model >= 0x5b)
+ else if (model == 0x5b)
{
cpu = "yongfeng";
CHECK___builtin_cpu_is ("yongfeng");
cpu_model->__cpu_subtype = ZHAOXIN_FAM7H_YONGFENG;
}
+ else if (model >= 0x6b)
+ {
+ cpu = "shijidadao";
+ CHECK___builtin_cpu_is ("shijidadao");
+ cpu_model->__cpu_subtype = ZHAOXIN_FAM7H_SHIJIDADAO;
+ }
break;
default:
break;
diff --git a/gcc/common/config/i386/i386-common.cc
b/gcc/common/config/i386/i386-common.cc
index 5d9c188c9c7d..e38b1b22ffb1 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -2066,6 +2066,7 @@ const char *const processor_names[] =
"intel",
"lujiazui",
"yongfeng",
+ "shijidadao",
"geode",
"k6",
"athlon",
@@ -2271,10 +2272,13 @@ const pta processor_alias_table[] =
| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
{"lujiazui", PROCESSOR_LUJIAZUI, CPU_LUJIAZUI,
PTA_LUJIAZUI,
- M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI), P_NONE},
+ M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI), P_PROC_BMI},
{"yongfeng", PROCESSOR_YONGFENG, CPU_YONGFENG,
PTA_YONGFENG,
- M_CPU_SUBTYPE (ZHAOXIN_FAM7H_YONGFENG), P_NONE},
+ M_CPU_SUBTYPE (ZHAOXIN_FAM7H_YONGFENG), P_PROC_AVX2},
+ {"shijidadao", PROCESSOR_SHIJIDADAO, CPU_YONGFENG,
+ PTA_YONGFENG,
+ M_CPU_SUBTYPE (ZHAOXIN_FAM7H_SHIJIDADAO), P_PROC_AVX2},
{"k8", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
diff --git a/gcc/common/config/i386/i386-cpuinfo.h
b/gcc/common/config/i386/i386-cpuinfo.h
index 3ec9e005a6ad..ccc6deb63853 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -104,6
[gcc r15-1453] xtensa: Eliminate double MEMW insertions for volatile memory
https://gcc.gnu.org/g:0982552bc4eeffb5520deba10dedecfb2390a8de
commit r15-1453-g0982552bc4eeffb5520deba10dedecfb2390a8de
Author: Takayuki 'January June' Suwa
Date: Wed Jun 19 13:59:54 2024 +0900
xtensa: Eliminate double MEMW insertions for volatile memory
This patch makes avoid inserting a MEMW instruction before a load/store
nstruction with volatile memory reference if there is already a MEMW
immediately before it.
gcc/ChangeLog:
* config/xtensa/xtensa.cc (print_operand):
When outputting MEMW before the instruction, check if the previous
instruction is already that.
Diff:
---
gcc/config/xtensa/xtensa.cc | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index bc127997ac6c..e2549de5df05 100644
--- a/gcc/config/xtensa/xtensa.cc
+++ b/gcc/config/xtensa/xtensa.cc
@@ -3078,7 +3078,17 @@ print_operand (FILE *file, rtx x, int letter)
/* For a volatile memory reference, emit a MEMW before the
load or store. */
if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE)
- fprintf (file, "memw\n\t");
+ {
+ rtx_insn *prev_insn
+ = prev_nonnote_nondebug_insn (current_output_insn);
+ rtx pat, src;
+
+ if (! (prev_insn && NONJUMP_INSN_P (prev_insn)
+&& GET_CODE (pat = PATTERN (prev_insn)) == SET
+&& GET_CODE (src = SET_SRC (pat)) == UNSPEC
+&& XINT (src, 1) == UNSPEC_MEMW))
+ fprintf (file, "memw\n\t");
+ }
}
else
output_operand_lossage ("invalid %%v value");
[gcc r15-1452] libstdc++: Consistently indent with tabs
https://gcc.gnu.org/g:bcb9dad9f6123c14ab8b14d2c3d360461dd5ee17
commit r15-1452-gbcb9dad9f6123c14ab8b14d2c3d360461dd5ee17
Author: Jonathan Wakely
Date: Wed Jun 19 14:16:27 2024 +0100
libstdc++: Consistently indent with tabs
libstdc++-v3/ChangeLog:
* include/std/future: Adjust whitespace to use tabs for
indentation.
Diff:
---
libstdc++-v3/include/std/future | 328
1 file changed, 164 insertions(+), 164 deletions(-)
diff --git a/libstdc++-v3/include/std/future b/libstdc++-v3/include/std/future
index d7be205af506..6ce7d89ca3ff 100644
--- a/libstdc++-v3/include/std/future
+++ b/libstdc++-v3/include/std/future
@@ -292,7 +292,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
{
using __allocator_type = __alloc_rebind<_Alloc, _Result_alloc>;
-explicit
+ explicit
_Result_alloc(const _Alloc& __a) : _Result<_Res>(), _Alloc(__a)
{ }
@@ -362,9 +362,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
}
template
-future_status
-wait_for(const chrono::duration<_Rep, _Period>& __rel)
-{
+ future_status
+ wait_for(const chrono::duration<_Rep, _Period>& __rel)
+ {
// First, check if the future has been made ready. Use acquire MO
// to synchronize with the thread that made it ready.
if (_M_status._M_load(memory_order_acquire) == _Status::__ready)
@@ -396,9 +396,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
}
template
-future_status
-wait_until(const chrono::time_point<_Clock, _Duration>& __abs)
-{
+ future_status
+ wait_until(const chrono::time_point<_Clock, _Duration>& __abs)
+ {
#if __cplusplus > 201703L
static_assert(chrono::is_clock_v<_Clock>);
#endif
@@ -430,8 +430,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
_M_set_result(function<_Ptr_type()> __res, bool __ignore_failure = false)
{
bool __did_set = false;
-// all calls to this function are serialized,
-// side-effects of invoking __res only happen once
+ // all calls to this function are serialized,
+ // side-effects of invoking __res only happen once
call_once(_M_once, &_State_baseV2::_M_do_set, this,
std::__addressof(__res), std::__addressof(__did_set));
if (__did_set)
@@ -439,7 +439,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
_M_status._M_store_notify_all(_Status::__ready,
memory_order_release);
else if (!__ignore_failure)
- __throw_future_error(int(future_errc::promise_already_satisfied));
+ __throw_future_error(int(future_errc::promise_already_satisfied));
}
// Provide a result to the shared state but delay making it ready
@@ -451,12 +451,12 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
{
bool __did_set = false;
unique_ptr<_Make_ready> __mr{new _Make_ready};
-// all calls to this function are serialized,
-// side-effects of invoking __res only happen once
+ // all calls to this function are serialized,
+ // side-effects of invoking __res only happen once
call_once(_M_once, &_State_baseV2::_M_do_set, this,
std::__addressof(__res), std::__addressof(__did_set));
if (!__did_set)
- __throw_future_error(int(future_errc::promise_already_satisfied));
+ __throw_future_error(int(future_errc::promise_already_satisfied));
__mr->_M_shared_state = std::move(__self);
__mr->_M_set();
__mr.release();
@@ -490,41 +490,41 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
}
template
-struct _Setter;
+ struct _Setter;
// set lvalues
template
-struct _Setter<_Res, _Arg&>
-{
- // check this is only used by promise::set_value(const R&)
- // or promise::set_value(R&)
- static_assert(is_same<_Res, _Arg&>::value // promise
- || is_same::value, // promise
- "Invalid specialisation");
+ struct _Setter<_Res, _Arg&>
+ {
+ // check this is only used by promise::set_value(const R&)
+ // or promise::set_value(R&)
+ static_assert(is_same<_Res, _Arg&>::value // promise
+ || is_same::value, // promise
+ "Invalid specialisation");
// Used by std::promise to copy construct the result.
- typename promise<_Res>::_Ptr_type operator()() const
- {
-_M_promise->_M_storage->_M_set(*_M_arg);
-return std::move(_M_promise->_M_storage);
- }
- promise<_Res>*_M_promise;
- _Arg* _M_arg;
-};
+ typename promise<_Res>::_Ptr_type operator()() const
+ {
+ _M_promise->_M_storage->_M_set(*_M_arg);
+ return std::move(_M_promise->_M_storage);
+ }
+
[gcc r15-1451] libstdc++: Add noexcept to some std::promise shared state internals
https://gcc.gnu.org/g:5d156a91853a7863d674ed35df87562e3a1eba0e
commit r15-1451-g5d156a91853a7863d674ed35df87562e3a1eba0e
Author: Jonathan Wakely
Date: Tue Jun 18 20:59:25 2024 +0100
libstdc++: Add noexcept to some std::promise shared state internals
Making the state ready for a std::promise only needs to move a
unique_ptr, which cannot throw. Make its call operator noexcept.
Similarly, making the state ready by storing an exception_ptr also can't
throw, so make that call operator noexcept too.
libstdc++-v3/ChangeLog:
* include/std/future (_State_baseV2::_Setter): Add
noexcept to call operator.
(_State_baseV2::_Setter): Likewise.
Diff:
---
libstdc++-v3/include/std/future | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/libstdc++-v3/include/std/future b/libstdc++-v3/include/std/future
index 9e75ae98b13d..d7be205af506 100644
--- a/libstdc++-v3/include/std/future
+++ b/libstdc++-v3/include/std/future
@@ -532,7 +532,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
{
static_assert(is_void<_Res>::value, "Only used for promise");
- typename promise<_Res>::_Ptr_type operator()() const
+ typename promise<_Res>::_Ptr_type operator()() const noexcept
{ return std::move(_M_promise->_M_storage); }
promise<_Res>*_M_promise;
@@ -545,7 +545,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
struct _Setter<_Res, __exception_ptr_tag>
{
// Used by std::promise to store an exception as the result.
- typename promise<_Res>::_Ptr_type operator()() const
+ typename promise<_Res>::_Ptr_type operator()() const noexcept
{
_M_promise->_M_storage->_M_error = *_M_ex;
return std::move(_M_promise->_M_storage);
[gcc r15-1450] libstdc++: Add conditional noexcept to std::pair default ctor
https://gcc.gnu.org/g:9651d6005f9c1ac60aecf7b36d6c0bd1ead8a63b commit r15-1450-g9651d6005f9c1ac60aecf7b36d6c0bd1ead8a63b Author: Jonathan Wakely Date: Tue Jun 18 20:57:24 2024 +0100 libstdc++: Add conditional noexcept to std::pair default ctor Most of std::pair constructors implemented using C++20 concepts have a conditional noexcept-specifier, but the default constructor doesn't. This fixes that. libstdc++-v3/ChangeLog: * include/bits/stl_pair.h [__cpp_lib_concepts] (pair()): Add conditional noexcept. Diff: --- libstdc++-v3/include/bits/stl_pair.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libstdc++-v3/include/bits/stl_pair.h b/libstdc++-v3/include/bits/stl_pair.h index 0c1e5719a1a3..0d60eaba1941 100644 --- a/libstdc++-v3/include/bits/stl_pair.h +++ b/libstdc++-v3/include/bits/stl_pair.h @@ -344,6 +344,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION explicit(__not_<__and_<__is_implicitly_default_constructible<_T1>, __is_implicitly_default_constructible<_T2>>>()) pair() + noexcept(is_nothrow_default_constructible_v<_T1> + && is_nothrow_default_constructible_v<_T2>) requires is_default_constructible_v<_T1> && is_default_constructible_v<_T2> : first(), second()
[gcc r15-1449] Fortran: fix for CHARACTER(len=*) dummies with bind(C) [PR115390]
https://gcc.gnu.org/g:954f9011c4923b72f42cc6ca8460333e7c7aad98
commit r15-1449-g954f9011c4923b72f42cc6ca8460333e7c7aad98
Author: Harald Anlauf
Date: Tue Jun 18 21:57:19 2024 +0200
Fortran: fix for CHARACTER(len=*) dummies with bind(C) [PR115390]
gcc/fortran/ChangeLog:
PR fortran/115390
* trans-decl.cc (gfc_conv_cfi_to_gfc): Move derivation of type sizes
for character via gfc_trans_vla_type_sizes to after character length
has been set.
gcc/testsuite/ChangeLog:
PR fortran/115390
* gfortran.dg/bind_c_char_11.f90: New test.
Diff:
---
gcc/fortran/trans-decl.cc| 4 +--
gcc/testsuite/gfortran.dg/bind_c_char_11.f90 | 45
2 files changed, 47 insertions(+), 2 deletions(-)
diff --git a/gcc/fortran/trans-decl.cc b/gcc/fortran/trans-decl.cc
index 88538713a02b..f7fb6eec336a 100644
--- a/gcc/fortran/trans-decl.cc
+++ b/gcc/fortran/trans-decl.cc
@@ -7063,8 +7063,8 @@ gfc_conv_cfi_to_gfc (stmtblock_t *init, stmtblock_t
*finally,
if (sym->ts.type == BT_CHARACTER
&& !INTEGER_CST_P (sym->ts.u.cl->backend_decl))
{
- gfc_conv_string_length (sym->ts.u.cl, NULL, init);
- gfc_trans_vla_type_sizes (sym, init);
+ gfc_conv_string_length (sym->ts.u.cl, NULL, );
+ gfc_trans_vla_type_sizes (sym, );
}
/* gfc->data = cfi->base_addr - or for scalars: gfc = cfi->base_addr.
diff --git a/gcc/testsuite/gfortran.dg/bind_c_char_11.f90
b/gcc/testsuite/gfortran.dg/bind_c_char_11.f90
new file mode 100644
index ..5ed8e82853bf
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/bind_c_char_11.f90
@@ -0,0 +1,45 @@
+! { dg-do compile }
+! { dg-additional-options "-Wuninitialized" }
+!
+! PR fortran/115390 - fixes for CHARACTER(len=*) dummies with bind(C)
+
+module test
+ implicit none
+contains
+ subroutine bar(s,t) bind(c)
+character(*), intent(in) :: s,t
+optional :: t
+call foo(s,t)
+ end
+ subroutine bar1(s,t) bind(c)
+character(*), intent(in) :: s(:),t(:)
+optional :: t
+call foo1(s,t)
+ end
+ subroutine bar4(s,t) bind(c)
+character(len=*,kind=4), intent(in) :: s,t
+optional:: t
+call foo4(s,t)
+ end
+ subroutine bar5(s,t) bind(c)
+character(len=*,kind=4), intent(in) :: s(:),t(:)
+optional:: t
+call foo5(s,t)
+ end
+ subroutine foo(s,t)
+character(*), intent(in) :: s,t
+optional :: t
+ end
+ subroutine foo1(s,t)
+character(*), intent(in) :: s(:),t(:)
+optional :: t
+ end
+ subroutine foo4(s,t)
+character(len=*,kind=4), intent(in) :: s,t
+optional:: t
+ end
+ subroutine foo5(s,t)
+character(len=*,kind=4), intent(in) :: s(:),t(:)
+optional:: t
+ end
+end
[gcc r15-1448] arm: Add support for MVE Tail-Predicated Low Overhead Loops
https://gcc.gnu.org/g:3dfc28dbbd21b1d708aa40064380ef4c42c994d7 commit r15-1448-g3dfc28dbbd21b1d708aa40064380ef4c42c994d7 Author: Andre Vieira Date: Wed Jun 19 17:05:55 2024 +0100 arm: Add support for MVE Tail-Predicated Low Overhead Loops This patch adds support for MVE Tail-Predicated Low Overhead Loops by using the doloop funcitonality added to support predicated vectorized hardware loops. gcc/ChangeLog: * config/arm/arm-protos.h (arm_target_bb_ok_for_lob): Change declaration to pass basic_block. (arm_attempt_dlstp_transform): New declaration. * config/arm/arm.cc (TARGET_LOOP_UNROLL_ADJUST): Define targethook. (TARGET_PREDICT_DOLOOP_P): Likewise. (arm_target_bb_ok_for_lob): Adapt condition. (arm_mve_get_vctp_lanes): New function. (arm_dl_usage_type): New internal enum. (arm_get_required_vpr_reg): New function. (arm_get_required_vpr_reg_param): New function. (arm_get_required_vpr_reg_ret_val): New function. (arm_mve_get_loop_vctp): New function. (arm_mve_insn_predicated_by): New function. (arm_mve_across_lane_insn_p): New function. (arm_mve_load_store_insn_p): New function. (arm_mve_impl_pred_on_outputs_p): New function. (arm_mve_impl_pred_on_inputs_p): New function. (arm_last_vect_def_insn): New function. (arm_mve_impl_predicated_p): New function. (arm_mve_check_reg_origin_is_num_elems): New function. (arm_mve_dlstp_check_inc_counter): New function. (arm_mve_dlstp_check_dec_counter): New function. (arm_mve_loop_valid_for_dlstp): New function. (arm_predict_doloop_p): New function. (arm_loop_unroll_adjust): New function. (arm_emit_mve_unpredicated_insn_to_seq): New function. (arm_attempt_dlstp_transform): New function. * config/arm/arm.opt (mdlstp): New option. * config/arm/iterators.md (dlstp_elemsize, letp_num_lanes, letp_num_lanes_neg, letp_num_lanes_minus_1): New attributes. (DLSTP, LETP): New iterators. * config/arm/mve.md (predicated_doloop_end_internal, dlstp_insn): New insn patterns. * config/arm/thumb2.md (doloop_end): Adapt to support tail-predicated loops. (doloop_begin): Likewise. * config/arm/types.md (mve_misc): New mve type to represent predicated_loop_end insn sequences. * config/arm/unspecs.md: (DLSTP8, DLSTP16, DLSTP32, DSLTP64, LETP8, LETP16, LETP32, LETP64): New unspecs for DLSTP and LETP. gcc/testsuite/ChangeLog: * gcc.target/arm/lob.h: Add new helpers. * gcc.target/arm/lob1.c: Use new helpers. * gcc.target/arm/lob6.c: Likewise. * gcc.target/arm/mve/dlstp-compile-asm-1.c: New test. * gcc.target/arm/mve/dlstp-compile-asm-2.c: New test. * gcc.target/arm/mve/dlstp-compile-asm-3.c: New test. * gcc.target/arm/mve/dlstp-int8x16.c: New test. * gcc.target/arm/mve/dlstp-int8x16-run.c: New test. * gcc.target/arm/mve/dlstp-int16x8.c: New test. * gcc.target/arm/mve/dlstp-int16x8-run.c: New test. * gcc.target/arm/mve/dlstp-int32x4.c: New test. * gcc.target/arm/mve/dlstp-int32x4-run.c: New test. * gcc.target/arm/mve/dlstp-int64x2.c: New test. * gcc.target/arm/mve/dlstp-int64x2-run.c: New test. * gcc.target/arm/mve/dlstp-invalid-asm.c: New test. Co-authored-by: Stam Markianos-Wright Diff: --- gcc/config/arm/arm-protos.h|4 +- gcc/config/arm/arm.cc | 1249 +++- gcc/config/arm/arm.opt |3 + gcc/config/arm/iterators.md| 15 + gcc/config/arm/mve.md | 50 + gcc/config/arm/thumb2.md | 138 ++- gcc/config/arm/types.md|6 +- gcc/config/arm/unspecs.md | 14 +- gcc/testsuite/gcc.target/arm/lob.h | 128 +- gcc/testsuite/gcc.target/arm/lob1.c| 23 +- gcc/testsuite/gcc.target/arm/lob6.c|8 +- .../gcc.target/arm/mve/dlstp-compile-asm-1.c | 146 +++ .../gcc.target/arm/mve/dlstp-compile-asm-2.c | 749 .../gcc.target/arm/mve/dlstp-compile-asm-3.c | 46 + .../gcc.target/arm/mve/dlstp-int16x8-run.c | 44 + gcc/testsuite/gcc.target/arm/mve/dlstp-int16x8.c | 31 + .../gcc.target/arm/mve/dlstp-int32x4-run.c | 45 + gcc/testsuite/gcc.target/arm/mve/dlstp-int32x4.c | 31 + .../gcc.target/arm/mve/dlstp-int64x2-run.c | 48 +
[gcc r15-1447] doloop: Add support for predicated vectorized loops
https://gcc.gnu.org/g:5d0c1b4e0d33c2d1077264636d0a65ce206d0d96
commit r15-1447-g5d0c1b4e0d33c2d1077264636d0a65ce206d0d96
Author: Andre Vieira
Date: Wed Jun 19 17:05:45 2024 +0100
doloop: Add support for predicated vectorized loops
This patch adds support in the target agnostic doloop pass for the
detection of
predicated vectorized hardware loops. Arm is currently the only target that
will make use of this feature.
gcc/ChangeLog:
* df-core.cc (df_bb_regno_only_def_find): New helper function.
* df.h (df_bb_regno_only_def_find): Declare new function.
* loop-doloop.cc (doloop_condition_get): Add support for detecting
predicated vectorized hardware loops.
(doloop_modify): Add support for GTU condition checks.
(doloop_optimize): Update costing computation to support
alterations to
desc->niter_expr by the backend.
Co-authored-by: Stam Markianos-Wright
Diff:
---
gcc/df-core.cc | 15 +
gcc/df.h | 1 +
gcc/loop-doloop.cc | 164 +++--
3 files changed, 113 insertions(+), 67 deletions(-)
diff --git a/gcc/df-core.cc b/gcc/df-core.cc
index f0eb4c93957f..b0e8a88d433b 100644
--- a/gcc/df-core.cc
+++ b/gcc/df-core.cc
@@ -1964,6 +1964,21 @@ df_bb_regno_last_def_find (basic_block bb, unsigned int
regno)
return NULL;
}
+/* Return the one and only def of REGNO within BB. If there is no def or
+ there are multiple defs, return NULL. */
+
+df_ref
+df_bb_regno_only_def_find (basic_block bb, unsigned int regno)
+{
+ df_ref temp = df_bb_regno_first_def_find (bb, regno);
+ if (!temp)
+return NULL;
+ else if (temp == df_bb_regno_last_def_find (bb, regno))
+return temp;
+ else
+return NULL;
+}
+
/* Finds the reference corresponding to the definition of REG in INSN.
DF is the dataflow object. */
diff --git a/gcc/df.h b/gcc/df.h
index 84e5aa8b524d..c4e690b40cf2 100644
--- a/gcc/df.h
+++ b/gcc/df.h
@@ -987,6 +987,7 @@ extern void df_check_cfg_clean (void);
#endif
extern df_ref df_bb_regno_first_def_find (basic_block, unsigned int);
extern df_ref df_bb_regno_last_def_find (basic_block, unsigned int);
+extern df_ref df_bb_regno_only_def_find (basic_block, unsigned int);
extern df_ref df_find_def (rtx_insn *, rtx);
extern bool df_reg_defined (rtx_insn *, rtx);
extern df_ref df_find_use (rtx_insn *, rtx);
diff --git a/gcc/loop-doloop.cc b/gcc/loop-doloop.cc
index 529e810e530c..8953e1de9609 100644
--- a/gcc/loop-doloop.cc
+++ b/gcc/loop-doloop.cc
@@ -85,10 +85,10 @@ doloop_condition_get (rtx_insn *doloop_pat)
forms:
1) (parallel [(set (pc) (if_then_else (condition)
- (label_ref (label))
- (pc)))
-(set (reg) (plus (reg) (const_int -1)))
-(additional clobbers and uses)])
+ (label_ref (label))
+ (pc)))
+(set (reg) (plus (reg) (const_int -1)))
+(additional clobbers and uses)])
The branch must be the first entry of the parallel (also required
by jump.cc), and the second entry of the parallel must be a set of
@@ -96,19 +96,33 @@ doloop_condition_get (rtx_insn *doloop_pat)
the loop counter in an if_then_else too.
2) (set (reg) (plus (reg) (const_int -1))
- (set (pc) (if_then_else (reg != 0)
-(label_ref (label))
-(pc))).
+(set (pc) (if_then_else (reg != 0)
+(label_ref (label))
+(pc))).
- Some targets (ARM) do the comparison before the branch, as in the
+ 3) Some targets (Arm) do the comparison before the branch, as in the
following form:
- 3) (parallel [(set (cc) (compare ((plus (reg) (const_int -1), 0)))
- (set (reg) (plus (reg) (const_int -1)))])
-(set (pc) (if_then_else (cc == NE)
-(label_ref (label))
-(pc))) */
-
+ (parallel [(set (cc) (compare (plus (reg) (const_int -1)) 0))
+ (set (reg) (plus (reg) (const_int -1)))])
+ (set (pc) (if_then_else (cc == NE)
+(label_ref (label))
+(pc)))
+
+ 4) This form supports a construct that is used to represent a vectorized
+ do loop with predication, however we do not need to care about the
+ details of the predication here.
+ Arm uses this construct to support MVE tail predication.
+
+ (parallel
+ [(set (pc)
+(if_then_else (gtu (plus (reg) (const_int -n))
+ (const_int n-1))
+ (label_ref)
+ (pc)))
+ (set (reg) (plus (reg)
[gcc r15-1446] Build: Fix typo ac_cv_search_pthread_crate
https://gcc.gnu.org/g:8088374a868aacab4dff208ec3e3fde790a1d9a3 commit r15-1446-g8088374a868aacab4dff208ec3e3fde790a1d9a3 Author: YunQiang Su Date: Wed Jun 19 22:30:22 2024 +0800 Build: Fix typo ac_cv_search_pthread_crate The correct variable name is ac_cv_search_pthread_create ChangeLog: PR bootstrap/115453 * configure.ac: Fix typo ac_cv_search_pthread_crate. * configure: Regnerate. Diff: --- configure| 2 +- configure.ac | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 6e95b27d9df4..1469cd735392 100755 --- a/configure +++ b/configure @@ -9002,7 +9002,7 @@ fi if test "$ac_cv_search_pthread_create" = -lpthread; then CRAB1_LIBS="$CRAB1_LIBS -lpthread" -elif test "$ac_cv_search_pthread_crate" = no; then +elif test "$ac_cv_search_pthread_create" = no; then missing_rust_dynlibs="$missing_rust_dynlibs, libpthread" fi diff --git a/configure.ac b/configure.ac index 88576b31bfcd..20457005e299 100644 --- a/configure.ac +++ b/configure.ac @@ -2053,7 +2053,7 @@ fi if test "$ac_cv_search_pthread_create" = -lpthread; then CRAB1_LIBS="$CRAB1_LIBS -lpthread" -elif test "$ac_cv_search_pthread_crate" = no; then +elif test "$ac_cv_search_pthread_create" = no; then missing_rust_dynlibs="$missing_rust_dynlibs, libpthread" fi
[gcc r15-1445] RISC-V: Add testcases for unsigned .SAT_SUB vector form 10
https://gcc.gnu.org/g:be18486825dd24533d320bf840bf95bd083487d1
commit r15-1445-gbe18486825dd24533d320bf840bf95bd083487d1
Author: Pan Li
Date: Wed Jun 19 21:14:31 2024 +0800
RISC-V: Add testcases for unsigned .SAT_SUB vector form 10
After the middle-end support the form 10 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 10:
#define DEF_VEC_SAT_U_SUB_FMT_10(T) \
void __attribute__((noinline))\
vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, );\
out[i] = !overflow ? ret : 0; \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test
macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 18 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-37.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-38.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-39.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-40.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c | 75 ++
9 files changed, 397 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index e231d1e66aa3..d5c81fbe5a9e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -265,6 +265,21 @@ vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_SUB_FMT_10(T) \
+void __attribute__((noinline))\
+vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \
+{ \
+ unsigned i; \
+ for (i = 0; i < limit; i++) \
+{ \
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ T ret; \
+ bool overflow = __builtin_sub_overflow (x, y, );\
+ out[i] = !overflow ? ret : 0; \
+} \
+}
+
#define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
@@ -292,4 +307,7 @@ vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_U_SUB_FMT_9(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_9(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) \
+ vec_sat_u_sub_##T##_fmt_10(out, op_1, op_2, N)
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
[gcc r15-1444] RISC-V: Add testcases for unsigned .SAT_SUB vector form 9
https://gcc.gnu.org/g:f1275820518772f4eece48bb3a578277cd7da138
commit r15-1444-gf1275820518772f4eece48bb3a578277cd7da138
Author: Pan Li
Date: Wed Jun 19 21:02:27 2024 +0800
RISC-V: Add testcases for unsigned .SAT_SUB vector form 9
After the middle-end support the form 9 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 9:
#define DEF_VEC_SAT_U_SUB_FMT_9(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, ); \
out[i] = overflow ? 0 : ret; \
}\
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test
macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-33.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-34.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-35.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-36.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c | 75 ++
9 files changed, 398 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 302fc4587086..e231d1e66aa3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -2,6 +2,7 @@
#define HAVE_VEC_SAT_ARITH
#include
+#include
/**/
/* Saturation Add (unsigned and signed)
*/
@@ -249,6 +250,21 @@ vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_SUB_FMT_9(T) \
+void __attribute__((noinline)) \
+vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ T ret; \
+ bool overflow = __builtin_sub_overflow (x, y, ); \
+ out[i] = overflow ? 0 : ret; \
+}\
+}
+
#define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
@@ -273,4 +289,7 @@ vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_U_SUB_FMT_8(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_8(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_SUB_FMT_9(T,
[gcc r15-1443] RISC-V: Add testcases for unsigned .SAT_SUB vector form 8
https://gcc.gnu.org/g:ff3729e94a114f5b24a5c3d0a6c3b7a9aeb8cbc9
commit r15-1443-gff3729e94a114f5b24a5c3d0a6c3b7a9aeb8cbc9
Author: Pan Li
Date: Wed Jun 19 20:38:43 2024 +0800
RISC-V: Add testcases for unsigned .SAT_SUB vector form 8
After the middle-end support the form 8 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 8:
#define DEF_VEC_SAT_U_SUB_FMT_8(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
T overflow = __builtin_sub_overflow (x, y, ); \
out[i] = ret & (T)-(!overflow);\
}\
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test
macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 18 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-29.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-30.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-31.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-32.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c | 75 ++
9 files changed, 397 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 69fbc6b52584..302fc4587086 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -234,6 +234,21 @@ vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_SUB_FMT_8(T) \
+void __attribute__((noinline)) \
+vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ T ret; \
+ T overflow = __builtin_sub_overflow (x, y, ); \
+ out[i] = ret & (T)-(!overflow);\
+}\
+}
+
#define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
@@ -255,4 +270,7 @@ vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_U_SUB_FMT_7(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_7(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_SUB_FMT_8(T, out, op_1, op_2, N) \
+ vec_sat_u_sub_##T##_fmt_8(out, op_1, op_2, N)
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
[gcc r15-1442] RISC-V: Add testcases for unsigned .SAT_SUB vector form 7
https://gcc.gnu.org/g:be8dc4bf3b25ca2600886f6e1d9ba7299e78b856
commit r15-1442-gbe8dc4bf3b25ca2600886f6e1d9ba7299e78b856
Author: Pan Li
Date: Wed Jun 19 20:28:11 2024 +0800
RISC-V: Add testcases for unsigned .SAT_SUB vector form 7
After the middle-end support the form 7 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 7:
#define DEF_VEC_SAT_U_SUB_FMT_7(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
T overflow = __builtin_sub_overflow (x, y, ); \
out[i] = ret & (T)(overflow - 1); \
}\
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test
macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 18 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-25.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-26.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-27.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-28.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c | 75 ++
9 files changed, 397 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index fd4d88e6f303..69fbc6b52584 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -219,6 +219,21 @@ vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_SUB_FMT_7(T) \
+void __attribute__((noinline)) \
+vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ T ret; \
+ T overflow = __builtin_sub_overflow (x, y, ); \
+ out[i] = ret & (T)(overflow - 1); \
+}\
+}
+
#define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
@@ -237,4 +252,7 @@ vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_U_SUB_FMT_6(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_6(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_SUB_FMT_7(T, out, op_1, op_2, N) \
+ vec_sat_u_sub_##T##_fmt_7(out, op_1, op_2, N)
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
[gcc r15-1441] RISC-V: Add testcases for unsigned .SAT_SUB vector form 6
https://gcc.gnu.org/g:337b21151135176b48d5cb6382e3f3258bc9a1db
commit r15-1441-g337b21151135176b48d5cb6382e3f3258bc9a1db
Author: Pan Li
Date: Wed Jun 19 20:15:27 2024 +0800
RISC-V: Add testcases for unsigned .SAT_SUB vector form 6
After the middle-end support the form 6 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 6:
#define DEF_VEC_SAT_U_SUB_FMT_6(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x <= y ? 0 : x - y; \
}\
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test
macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 16 +
.../riscv/rvv/autovec/binop/vec_sat_u_sub-21.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-22.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-23.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-24.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c | 75 ++
9 files changed, 395 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index b25215c10cb4..fd4d88e6f303 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -206,6 +206,19 @@ vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_SUB_FMT_6(T) \
+void __attribute__((noinline)) \
+vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ out[i] = x <= y ? 0 : x - y; \
+}\
+}
+
#define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
@@ -221,4 +234,7 @@ vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_U_SUB_FMT_5(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_5(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_SUB_FMT_6(T, out, op_1, op_2, N) \
+ vec_sat_u_sub_##T##_fmt_6(out, op_1, op_2, N)
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
new file mode 100644
index ..9799a1eb0c7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details
[gcc r15-1440] RISC-V: Add testcases for unsigned .SAT_SUB vector form 5
https://gcc.gnu.org/g:d5054ecca13b9f8f480f5534e40da3e931c4fa72
commit r15-1440-gd5054ecca13b9f8f480f5534e40da3e931c4fa72
Author: Pan Li
Date: Wed Jun 19 19:44:52 2024 +0800
RISC-V: Add testcases for unsigned .SAT_SUB vector form 5
After the middle-end support the form 5 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 5:
#define DEF_VEC_SAT_U_SUB_FMT_5(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x < y ? 0 : x - y;\
}\
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test
macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 16 +
.../riscv/rvv/autovec/binop/vec_sat_u_sub-17.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-18.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-19.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-20.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c | 75 ++
9 files changed, 395 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index a83f964df0c5..b25215c10cb4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -193,6 +193,19 @@ vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_SUB_FMT_5(T) \
+void __attribute__((noinline)) \
+vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ out[i] = x < y ? 0 : x - y;\
+}\
+}
+
#define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
@@ -205,4 +218,7 @@ vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_U_SUB_FMT_4(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_4(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_SUB_FMT_5(T, out, op_1, op_2, N) \
+ vec_sat_u_sub_##T##_fmt_5(out, op_1, op_2, N)
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
new file mode 100644
index ..8d50f5ff26c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details
[gcc r15-1439] RISC-V: Add testcases for unsigned .SAT_SUB vector form 4
https://gcc.gnu.org/g:0fe8c5f146178ac86468859f8c83039e88b73481
commit r15-1439-g0fe8c5f146178ac86468859f8c83039e88b73481
Author: Pan Li
Date: Wed Jun 19 19:19:23 2024 +0800
RISC-V: Add testcases for unsigned .SAT_SUB vector form 4
After the middle-end support the form 4 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 4:
#define DEF_VEC_SAT_U_SUB_FMT_4(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x >= y ? x - y : 0; \
}\
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test
macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 16 +
.../riscv/rvv/autovec/binop/vec_sat_u_sub-13.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-14.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-15.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-16.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c | 75 ++
9 files changed, 395 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 182cf2cf064f..a83f964df0c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -180,6 +180,19 @@ vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_SUB_FMT_4(T) \
+void __attribute__((noinline)) \
+vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ out[i] = x >= y ? x - y : 0; \
+}\
+}
+
#define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
@@ -189,4 +202,7 @@ vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_U_SUB_FMT_3(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_3(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_SUB_FMT_4(T, out, op_1, op_2, N) \
+ vec_sat_u_sub_##T##_fmt_4(out, op_1, op_2, N)
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
new file mode 100644
index ..d4d098f06232
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details
[gcc r15-1438] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3
https://gcc.gnu.org/g:b3a34469f3f94b8cde26976e87b61895e8111cd1
commit r15-1438-gb3a34469f3f94b8cde26976e87b61895e8111cd1
Author: Pan Li
Date: Wed Jun 19 18:56:51 2024 +0800
RISC-V: Add testcases for unsigned .SAT_SUB vector form 3
After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 3:
#define DEF_VEC_SAT_U_SUB_FMT_3(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x > y ? x - y : 0;\
}\
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test
macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 17 +
.../riscv/rvv/autovec/binop/vec_sat_u_sub-10.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-11.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-12.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-9.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c | 75 ++
9 files changed, 396 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 443f88261ba0..182cf2cf064f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -167,9 +167,26 @@ vec_sat_u_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_SUB_FMT_3(T) \
+void __attribute__((noinline)) \
+vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ out[i] = x > y ? x - y : 0;\
+}\
+}
+
#define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N)
+
#define RUN_VEC_SAT_U_SUB_FMT_2(T, out, op_1, op_2, N) \
vec_sat_u_sub_##T##_fmt_2(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_SUB_FMT_3(T, out, op_1, op_2, N) \
+ vec_sat_u_sub_##T##_fmt_3(out, op_1, op_2, N)
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
new file mode 100644
index ..e1c4020b36d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final {
[gcc r15-1437] libstdc++: Fix warning regressions in
https://gcc.gnu.org/g:8c52adcf5f9812ef66aeef357590fb2f148302f7
commit r15-1437-g8c52adcf5f9812ef66aeef357590fb2f148302f7
Author: Jonathan Wakely
Date: Tue Jun 18 20:53:53 2024 +0100
libstdc++: Fix warning regressions in
I caused some new warnings with -Wsystem-headers with my recent changes
to std::get_temporary_buffer and std::_Temporary_buffer. There's a
-Wsign-compare warning which can be avoided by casting the ptrdiff_t
argument to size_t (which also conveniently rejects negative values).
There's also a -Wdeprecated-declarations warning because I moved where
std::get_temporary_buffer is called, but didn't move the diagnostic
pragmas that suppress the warning for calling it.
libstdc++-v3/ChangeLog:
* include/bits/stl_tempbuf.h (__get_temporary_buffer): Cast
argument to size_t to handle negative values and suppress
-Wsign-compare warning.
(_Temporary_buffer): Move diagnostic pragmas to new location of
call to std::get_temporary_buffer.
Diff:
---
libstdc++-v3/include/bits/stl_tempbuf.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/libstdc++-v3/include/bits/stl_tempbuf.h
b/libstdc++-v3/include/bits/stl_tempbuf.h
index fa03fd277042..759c4937744b 100644
--- a/libstdc++-v3/include/bits/stl_tempbuf.h
+++ b/libstdc++-v3/include/bits/stl_tempbuf.h
@@ -82,7 +82,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
inline _Tp*
__get_temporary_buffer(ptrdiff_t __len) _GLIBCXX_NOTHROW
{
- if (__builtin_expect(__len > (size_t(-1) / sizeof(_Tp)), 0))
+ if (__builtin_expect(size_t(__len) > (size_t(-1) / sizeof(_Tp)), 0))
return 0;
#if __cpp_aligned_new
@@ -200,6 +200,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
size_type _M_original_len;
struct _Impl
{
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
explicit
_Impl(ptrdiff_t __original_len)
{
@@ -208,6 +210,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
_M_len = __p.second;
_M_buffer = __p.first;
}
+#pragma GCC diagnostic pop
~_Impl()
{ std::__detail::__return_temporary_buffer(_M_buffer, _M_len); }
@@ -315,8 +318,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
__ucr(__first, __last, __seed);
}
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
template
_Temporary_buffer<_ForwardIterator, _Tp>::
_Temporary_buffer(_ForwardIterator __seed, size_type __original_len)
@@ -324,7 +325,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
{
std::__uninitialized_construct_buf(begin(), end(), __seed);
}
-#pragma GCC diagnostic pop
_GLIBCXX_END_NAMESPACE_VERSION
} // namespace
[gcc r15-1436] build: Fix missing variable quotes
https://gcc.gnu.org/g:c6a9ab8c920f297c4efd289182aef9fbc73f5906
commit r15-1436-gc6a9ab8c920f297c4efd289182aef9fbc73f5906
Author: Collin Funk
Date: Thu Jun 13 17:53:55 2024 -0700
build: Fix missing variable quotes
When dlopen and pthread_create are in libc the variable is
set to "none required", therefore running configure will show
the following errors:
./configure: line 8997: test: too many arguments
./configure: line 8999: test: too many arguments
./configure: line 9003: test: too many arguments
./configure: line 9005: test: =: unary operator expected
gcc/configure also has a similar problem on
gcc_cv_as_mips_explicit_relocs:
./gcc/configure: line 30242: test: =: unary operator expected
ChangeLog:
* configure.ac: Quote variable result of AC_SEARCH_LIBS.
* configure: Regenerate.
gcc/ChangeLog:
* configure.ac: Add missing quotation of variable
gcc_cv_as_mips_explicit_relocs.
* configure: Regenerate.
Signed-off-by: Collin Funk
Diff:
---
configure| 10 +-
configure.ac | 8
gcc/configure| 2 +-
gcc/configure.ac | 2 +-
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/configure b/configure
index 51576a41f303..6e95b27d9df4 100755
--- a/configure
+++ b/configure
@@ -8994,15 +8994,15 @@ if test "$ac_res" != no; then :
fi
-if test $ac_cv_search_dlopen = -ldl; then
+if test "$ac_cv_search_dlopen" = -ldl; then
CRAB1_LIBS="$CRAB1_LIBS -ldl"
-elif test $ac_cv_search_dlopen = no; then
+elif test "$ac_cv_search_dlopen" = no; then
missing_rust_dynlibs="libdl"
fi
-if test $ac_cv_search_pthread_create = -lpthread; then
+if test "$ac_cv_search_pthread_create" = -lpthread; then
CRAB1_LIBS="$CRAB1_LIBS -lpthread"
-elif test $ac_cv_search_pthread_crate = no; then
+elif test "$ac_cv_search_pthread_crate" = no; then
missing_rust_dynlibs="$missing_rust_dynlibs, libpthread"
fi
@@ -19746,7 +19746,7 @@ config.status
configured by $0, generated by GNU Autoconf 2.69,
with options \\"\$ac_cs_config\\"
-Copyright (C) 2012 Free Software Foundation, Inc.
+Copyright (C) Free Software Foundation, Inc.
This config.status script is free software; the Free Software Foundation
gives unlimited permission to copy, distribute and modify it."
diff --git a/configure.ac b/configure.ac
index 5eda8dcdbf72..88576b31bfcd 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2045,15 +2045,15 @@ missing_rust_dynlibs=none
AC_SEARCH_LIBS([dlopen], [dl])
AC_SEARCH_LIBS([pthread_create], [pthread])
-if test $ac_cv_search_dlopen = -ldl; then
+if test "$ac_cv_search_dlopen" = -ldl; then
CRAB1_LIBS="$CRAB1_LIBS -ldl"
-elif test $ac_cv_search_dlopen = no; then
+elif test "$ac_cv_search_dlopen" = no; then
missing_rust_dynlibs="libdl"
fi
-if test $ac_cv_search_pthread_create = -lpthread; then
+if test "$ac_cv_search_pthread_create" = -lpthread; then
CRAB1_LIBS="$CRAB1_LIBS -lpthread"
-elif test $ac_cv_search_pthread_crate = no; then
+elif test "$ac_cv_search_pthread_crate" = no; then
missing_rust_dynlibs="$missing_rust_dynlibs, libpthread"
fi
diff --git a/gcc/configure b/gcc/configure
index 9dc0b65dfaac..b536af664d3d 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -30239,7 +30239,7 @@ else
fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result:
$gcc_cv_as_mips_explicit_relocs_pcrel" >&5
$as_echo "$gcc_cv_as_mips_explicit_relocs_pcrel" >&6; }
-if test $gcc_cv_as_mips_explicit_relocs_pcrel = yes; then
+if test "x$gcc_cv_as_mips_explicit_relocs_pcrel" = "xyes"; then
$as_echo "#define MIPS_EXPLICIT_RELOCS MIPS_EXPLICIT_RELOCS_PCREL" >>confdefs.h
diff --git a/gcc/configure.ac b/gcc/configure.ac
index b2243e9954aa..1501bf89c89d 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -5317,7 +5317,7 @@ x:
AC_MSG_CHECKING(assembler and linker for explicit JALR relocation)
gcc_cv_as_ld_jalr_reloc=no
-if test $gcc_cv_as_mips_explicit_relocs = yes; then
+if test "x$gcc_cv_as_mips_explicit_relocs" = "xyes"; then
if test $in_tree_ld = yes ; then
if test "$gcc_cv_gld_major_version" -eq 2 -a
"$gcc_cv_gld_minor_version" -ge 20 -o "$gcc_cv_gld_major_version" -gt 2 \
&& test $in_tree_ld_is_elf = yes; then
[gcc r15-1435] Improve gcc.dg/vect/bb-slp-32.c testcase
https://gcc.gnu.org/g:a73744a4f81e669d8ae72ed3bf529e1602858c88
commit r15-1435-ga73744a4f81e669d8ae72ed3bf529e1602858c88
Author: Richard Biener
Date: Wed Jun 19 11:39:51 2024 +0200
Improve gcc.dg/vect/bb-slp-32.c testcase
The following adds a correctness check to the combined store/reduce
vectorization.
* gcc.dg/vect/bb-slp-32.c: Add check for correctness.
Diff:
---
gcc/testsuite/gcc.dg/vect/bb-slp-32.c | 26 --
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-32.c
b/gcc/testsuite/gcc.dg/vect/bb-slp-32.c
index f10442e6d568..4f72727b6948 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-32.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-32.c
@@ -1,14 +1,15 @@
-/* { dg-do compile } */
/* { dg-require-effective-target vect_int } */
/* { dg-additional-options "-fvect-cost-model=dynamic" } */
-void bar (int *);
-int foo (int *p, int a, int b)
+#include "tree-vect.h"
+
+int __attribute__((noipa))
+foo (int * __restrict__ x, int *p, int a, int b)
{
- int x[4];
+ p = __builtin_assume_aligned (p, __BIGGEST_ALIGNMENT__);
+ x = __builtin_assume_aligned (x, __BIGGEST_ALIGNMENT__);
int tem0, tem1, tem2, tem3;
int sum = 0;
- p = __builtin_assume_aligned (p, __BIGGEST_ALIGNMENT__);
tem0 = p[0] + 1 + a;
sum += tem0;
x[0] = tem0;
@@ -21,6 +22,19 @@ int foo (int *p, int a, int b)
tem3 = p[3] + 4 + a;
sum += tem3;
x[3] = tem3;
- bar (x);
return sum;
}
+
+int x[4] __attribute__((aligned(__BIGGEST_ALIGNMENT__)));
+int p[4] __attribute__((aligned(__BIGGEST_ALIGNMENT__))) = { 0, 1, 2, 3 };
+
+int main()
+{
+ check_vect ();
+
+ if (foo (x, p, 7, 13) != 56)
+abort ();
+ if (x[0] != 8 || x[1] != 16 || x[2] != 18 || x[3] != 14)
+abort ();
+ return 0;
+}
[gcc r15-1434] Fortran: Set the vptr of a class typed result.
https://gcc.gnu.org/g:dbb718175d7df89b957b316ba2f5fbea5d21b2b1
commit r15-1434-gdbb718175d7df89b957b316ba2f5fbea5d21b2b1
Author: Andre Vehreschild
Date: Thu Jun 6 14:01:13 2024 +0200
Fortran: Set the vptr of a class typed result.
PR fortran/90076
gcc/fortran/ChangeLog:
* trans-decl.cc (gfc_generate_function_code): Set vptr for
results to declared class type.
* trans-expr.cc (gfc_reset_vptr): Allow to provide the typespec
instead of the expression.
* trans.h (gfc_reset_vptr): Same.
gcc/testsuite/ChangeLog:
* gfortran.dg/class_76.f90: Add declared vtab occurrence.
* gfortran.dg/class_78.f90: New test.
Diff:
---
gcc/fortran/trans-decl.cc | 11 ++-
gcc/fortran/trans-expr.cc | 10 ++
gcc/fortran/trans.h| 4 +++-
gcc/testsuite/gfortran.dg/class_76.f90 | 2 +-
gcc/testsuite/gfortran.dg/class_78.f90 | 29 +
5 files changed, 45 insertions(+), 11 deletions(-)
diff --git a/gcc/fortran/trans-decl.cc b/gcc/fortran/trans-decl.cc
index dca7779528bb..88538713a02b 100644
--- a/gcc/fortran/trans-decl.cc
+++ b/gcc/fortran/trans-decl.cc
@@ -7926,11 +7926,12 @@ gfc_generate_function_code (gfc_namespace * ns)
&& CLASS_DATA (sym)->attr.dimension == 0
&& sym->result == sym)
{
- tmp = CLASS_DATA (sym)->backend_decl;
- tmp = fold_build3_loc (input_location, COMPONENT_REF,
-TREE_TYPE (tmp), result, tmp, NULL_TREE);
- gfc_add_modify (, tmp, fold_convert (TREE_TYPE (tmp),
- null_pointer_node));
+ tmp = gfc_class_data_get (result);
+ gfc_add_modify (, tmp,
+ fold_convert (TREE_TYPE (tmp),
+ null_pointer_node));
+ gfc_reset_vptr (, nullptr, result,
+ CLASS_DATA (sym->result)->ts.u.derived);
}
else if (sym->ts.type == BT_DERIVED
&& !sym->attr.allocatable)
diff --git a/gcc/fortran/trans-expr.cc b/gcc/fortran/trans-expr.cc
index d6f4d6bfe457..558a73805169 100644
--- a/gcc/fortran/trans-expr.cc
+++ b/gcc/fortran/trans-expr.cc
@@ -530,13 +530,14 @@ gfc_find_and_cut_at_last_class_ref (gfc_expr *e, bool
is_mold,
return base_expr;
}
-
/* Reset the vptr to the declared type, e.g. after deallocation.
Use the variable in CLASS_CONTAINER if available. Otherwise, recreate
- one with E. The generated assignment code is added at the end of BLOCK. */
+ one with e or derived. At least one of the two has to be set. The
generated
+ assignment code is added at the end of BLOCK. */
void
-gfc_reset_vptr (stmtblock_t *block, gfc_expr *e, tree class_container)
+gfc_reset_vptr (stmtblock_t *block, gfc_expr *e, tree class_container,
+ gfc_symbol *derived)
{
tree vptr = NULL_TREE;
@@ -546,6 +547,7 @@ gfc_reset_vptr (stmtblock_t *block, gfc_expr *e, tree
class_container)
if (vptr == NULL_TREE)
{
gfc_se se;
+ gcc_assert (e);
/* Evaluate the expression and obtain the vptr from it. */
gfc_init_se (, NULL);
@@ -570,7 +572,7 @@ gfc_reset_vptr (stmtblock_t *block, gfc_expr *e, tree
class_container)
tree vtable;
/* Return the vptr to the address of the declared type. */
- vtab = gfc_find_derived_vtab (e->ts.u.derived);
+ vtab = gfc_find_derived_vtab (derived ? derived : e->ts.u.derived);
vtable = vtab->backend_decl;
if (vtable == NULL_TREE)
vtable = gfc_get_symbol_decl (vtab);
diff --git a/gcc/fortran/trans.h b/gcc/fortran/trans.h
index f94fa6014004..5e064af5ccbd 100644
--- a/gcc/fortran/trans.h
+++ b/gcc/fortran/trans.h
@@ -451,7 +451,9 @@ tree gfc_vptr_def_init_get (tree);
tree gfc_vptr_copy_get (tree);
tree gfc_vptr_final_get (tree);
tree gfc_vptr_deallocate_get (tree);
-void gfc_reset_vptr (stmtblock_t *, gfc_expr *, tree = NULL_TREE);
+void
+gfc_reset_vptr (stmtblock_t *, gfc_expr *, tree = NULL_TREE,
+ gfc_symbol * = nullptr);
void gfc_reset_len (stmtblock_t *, gfc_expr *);
tree gfc_get_class_from_gfc_expr (gfc_expr *);
tree gfc_get_class_from_expr (tree);
diff --git a/gcc/testsuite/gfortran.dg/class_76.f90
b/gcc/testsuite/gfortran.dg/class_76.f90
index 1ee1e1fc25f2..c9842a15feab 100644
--- a/gcc/testsuite/gfortran.dg/class_76.f90
+++ b/gcc/testsuite/gfortran.dg/class_76.f90
@@ -61,6 +61,6 @@ contains
end function newContainer
end program returned_memory_leak
-! { dg-final { scan-tree-dump-times "newabstract" 14 "original" } }
+! { dg-final { scan-tree-dump-times "newabstract" 15 "original" } }
! { dg-final { scan-tree-dump-times "__builtin_free" 8 "original" } }
diff --git a/gcc/testsuite/gfortran.dg/class_78.f90
[gcc r15-1433] xtensa: constantsynth: Reforge to fix some non-fatal issues
https://gcc.gnu.org/g:23141088e8fb50bf916ac0b2e364b1eef9f3569d
commit r15-1433-g23141088e8fb50bf916ac0b2e364b1eef9f3569d
Author: Takayuki 'January June' Suwa
Date: Wed Jun 19 11:55:57 2024 +0900
xtensa: constantsynth: Reforge to fix some non-fatal issues
The previous constant synthesis logic had some issues that were non-fatal
but worth considering:
- It didn't work with DFmode literals, because those were cast to SImode
rather SFmode when splitting into two natural-width words by
split_double().
- It didn't work with large literals when TARGET_AUTO_LITPOOLS was enabled,
because those were relaxed MOVI immediates rather references to literal
pool entries,
- It didn't take into account that when literals with the same RTL
representation are pooled multiple times within a function, those entries
are shared (especially important when optimizing for size).
This patch addresses the above issues by making appropriate tweaks to the
constant synthesis logic.
gcc/ChangeLog:
* config/xtensa/xtensa-protos.h (xtensa_constantsynth):
Change the second argument from HOST_WIDE_INT to rtx.
* config/xtensa/xtensa.cc (#include):
Add "context.h" and "pass_manager.h".
(machine_function): Add a new hash_map field "litpool_usage".
(xtensa_constantsynth): Make "src" (the second operand) accept
RTX literal instead of its value, and treat both bare and pooled
SI/SFmode literals equally by bit-exact canonicalization into
CONST_INT RTX internally. And then, make avoid synthesis if
such multiple identical canonicalized literals are found in same
function when optimizing for size. Finally, for literals where
synthesis is not possible or has been avoided, re-emit "move"
RTXes with canonicalized ones to increase the chances of sharing
literal pool entries.
* config/xtensa/xtensa.md (split patterns for constant synthesis):
Change to simply invoke xtensa_constantsynth() as mentioned above,
and add new patterns for when TARGET_AUTO_LITPOOLS is enabled.
Diff:
---
gcc/config/xtensa/xtensa-protos.h | 2 +-
gcc/config/xtensa/xtensa.cc | 75 +++
gcc/config/xtensa/xtensa.md | 56 +
3 files changed, 103 insertions(+), 30 deletions(-)
diff --git a/gcc/config/xtensa/xtensa-protos.h
b/gcc/config/xtensa/xtensa-protos.h
index 77553b0453f1..8f645e87de96 100644
--- a/gcc/config/xtensa/xtensa-protos.h
+++ b/gcc/config/xtensa/xtensa-protos.h
@@ -44,7 +44,7 @@ extern int xtensa_expand_scc (rtx *, machine_mode);
extern int xtensa_expand_block_move (rtx *);
extern int xtensa_expand_block_set (rtx *);
extern void xtensa_split_operand_pair (rtx *, machine_mode);
-extern int xtensa_constantsynth (rtx, HOST_WIDE_INT);
+extern int xtensa_constantsynth (rtx, rtx);
extern int xtensa_emit_move_sequence (rtx *, machine_mode);
extern rtx xtensa_copy_incoming_a7 (rtx);
extern void xtensa_expand_nonlocal_goto (rtx *);
diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index 45dc1be3ff52..bc127997ac6c 100644
--- a/gcc/config/xtensa/xtensa.cc
+++ b/gcc/config/xtensa/xtensa.cc
@@ -58,6 +58,8 @@ along with GCC; see the file COPYING3. If not see
#include "insn-attr.h"
#include "tree-pass.h"
#include "print-rtl.h"
+#include "context.h"
+#include "pass_manager.h"
#include
/* This file should be included last. */
@@ -107,6 +109,7 @@ struct GTY(()) machine_function
bool inhibit_logues_a1_adjusts;
rtx last_logues_a9_content;
HARD_REG_SET eliminated_callee_saved;
+ hash_map *litpool_usage;
};
static void xtensa_option_override (void);
@@ -1104,7 +1107,7 @@ xtensa_split_operand_pair (rtx operands[4], machine_mode
mode)
}
-/* Try to emit insns to load srcval (that cannot fit into signed 12-bit)
+/* Try to emit insns to load src (either naked or pooled SI/SF constant)
into dst with synthesizing a such constant value from a sequence of
load-immediate / arithmetic ones, instead of a L32R instruction
(plus a constant in litpool). */
@@ -1190,11 +1193,67 @@ xtensa_constantsynth_rtx_ADDSUBX (rtx reg,
HOST_WIDE_INT imm)
}
int
-xtensa_constantsynth (rtx dst, HOST_WIDE_INT srcval)
+xtensa_constantsynth (rtx dst, rtx src)
{
+ HOST_WIDE_INT srcval;
+ static opt_pass *pass_rtl_split2;
+ int *pv;
+
+ /* Derefer if src is litpool entry, and get integer constant value. */
+ src = avoid_constant_pool_reference (src);
+ if (CONST_INT_P (src))
+srcval = INTVAL (src);
+ else if (CONST_DOUBLE_P (src) && GET_MODE (src) == SFmode)
+{
+ long l;
+
+ REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (src), l);
+ srcval = (int32_t)l, src = GEN_INT (srcval);
+}
+ else
+return 0;
+
+ /* Force
gcc-wwwdocs branch master updated. 79ef2cb65d7876e71ea9560e2a92843070dc40d5
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via 79ef2cb65d7876e71ea9560e2a92843070dc40d5 (commit) via eafcdb152016eefd4e9f691f45437c284810ee5e (commit) from 320e118cfd9379bba6f08b57c7b4bfb118803e57 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log - commit 79ef2cb65d7876e71ea9560e2a92843070dc40d5 Author: Gerald Pfeifer Date: Wed Jun 19 08:17:31 2024 +0200 gcc-3.0: Avoid duplicate link to LAPACK There is already one such link pretty directly above, so avoid the second one. diff --git a/htdocs/gcc-3.0/criteria.html b/htdocs/gcc-3.0/criteria.html index 97be2e30..3e679d28 100644 --- a/htdocs/gcc-3.0/criteria.html +++ b/htdocs/gcc-3.0/criteria.html @@ -313,8 +313,7 @@ for measuring code quality: LAPACK Fortran -http://www.netlib.org/lapack/lapack.tgz;> -LAPACK 3.0 (timing programs) +LAPACK 3.0 (timing programs) commit eafcdb152016eefd4e9f691f45437c284810ee5e Author: Gerald Pfeifer Date: Tue Jun 18 11:04:26 2024 +0200 codingrationale: Fix spelling diff --git a/htdocs/codingrationale.html b/htdocs/codingrationale.html index c51c9da4..5e3d6b88 100644 --- a/htdocs/codingrationale.html +++ b/htdocs/codingrationale.html @@ -18,7 +18,7 @@ Inlining functions has a potential cost in object size, -working set size, compile time, and debuggablity. +working set size, compile time, and debugability. These costs should not be borne without some evidence that the inlining pays for itself. --- Summary of changes: htdocs/codingrationale.html | 2 +- htdocs/gcc-3.0/criteria.html | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) hooks/post-receive -- gcc-wwwdocs
[gcc r15-1432] RISC-V: Add testcases for unsigned .SAT_ADD vector form 8
https://gcc.gnu.org/g:eb549f13fcde079a7bbe27e5ba3d5e80abbffba1
commit r15-1432-geb549f13fcde079a7bbe27e5ba3d5e80abbffba1
Author: Pan Li
Date: Mon Jun 17 22:31:27 2024 +0800
RISC-V: Add testcases for unsigned .SAT_ADD vector form 8
After the middle-end support the form 8 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 8.
Form 8:
#define DEF_VEC_SAT_U_ADD_FMT_8(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x > (T)(x + y) ? -1 : (x + y);\
}\
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 16 +
.../riscv/rvv/autovec/binop/vec_sat_u_add-29.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-30.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-31.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-32.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c | 75 ++
9 files changed, 395 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 46fae4555be4..443f88261ba0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -101,6 +101,19 @@ vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_ADD_FMT_8(T) \
+void __attribute__((noinline)) \
+vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ out[i] = x > (T)(x + y) ? -1 : (x + y);\
+}\
+}
+
#define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
@@ -122,6 +135,9 @@ vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_U_ADD_FMT_7(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_7(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_ADD_FMT_8(T, out, op_1, op_2, N) \
+ vec_sat_u_add_##T##_fmt_8(out, op_1, op_2, N)
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
/**/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
new file mode 100644
index
[gcc r15-1431] RISC-V: Add testcases for unsigned .SAT_ADD vector form 7
https://gcc.gnu.org/g:ed94699eefc7cc8ac8fd79a6d8d81bf05d5a79ff
commit r15-1431-ged94699eefc7cc8ac8fd79a6d8d81bf05d5a79ff
Author: Pan Li
Date: Mon Jun 17 22:19:54 2024 +0800
RISC-V: Add testcases for unsigned .SAT_ADD vector form 7
After the middle-end support the form 7 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 7.
Form 7:
#define DEF_VEC_SAT_U_ADD_FMT_7(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = (T)(x + y) < x ? -1 : (x + y);\
}\
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 16 +
.../riscv/rvv/autovec/binop/vec_sat_u_add-25.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-26.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-27.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-28.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c | 75 ++
9 files changed, 395 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 0f08822cbeb7..46fae4555be4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -88,6 +88,19 @@ vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_ADD_FMT_7(T) \
+void __attribute__((noinline)) \
+vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ out[i] = (T)(x + y) < x ? -1 : (x + y);\
+}\
+}
+
#define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
@@ -106,6 +119,9 @@ vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_U_ADD_FMT_6(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_6(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_ADD_FMT_7(T, out, op_1, op_2, N) \
+ vec_sat_u_add_##T##_fmt_7(out, op_1, op_2, N)
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
/**/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
new file mode 100644
index
[gcc r15-1430] RISC-V: Add testcases for unsigned .SAT_ADD vector form 6
https://gcc.gnu.org/g:748b9f0a37c448cbe8585cfa8c1b380b4975ba9d
commit r15-1430-g748b9f0a37c448cbe8585cfa8c1b380b4975ba9d
Author: Pan Li
Date: Mon Jun 17 22:10:31 2024 +0800
RISC-V: Add testcases for unsigned .SAT_ADD vector form 6
After the middle-end support the form 6 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 6.
Form 6:
#define DEF_VEC_SAT_U_ADD_FMT_6(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x <= (T)(x + y) ? (x + y) : -1; \
}\
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 16 +
.../riscv/rvv/autovec/binop/vec_sat_u_add-21.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-22.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-23.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-24.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c | 75 ++
9 files changed, 395 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 1f2ee31577dc..0f08822cbeb7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -75,6 +75,19 @@ vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_ADD_FMT_6(T) \
+void __attribute__((noinline)) \
+vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ out[i] = x <= (T)(x + y) ? (x + y) : -1; \
+}\
+}
+
#define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
@@ -90,6 +103,9 @@ vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_U_ADD_FMT_5(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_5(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_ADD_FMT_6(T, out, op_1, op_2, N) \
+ vec_sat_u_add_##T##_fmt_6(out, op_1, op_2, N)
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
/**/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
new file mode 100644
index
[gcc r15-1429] RISC-V: Add testcases for unsigned .SAT_ADD vector form 5
https://gcc.gnu.org/g:1daf54aa7818519b5a1dcc441c8b235d15a8726e
commit r15-1429-g1daf54aa7818519b5a1dcc441c8b235d15a8726e
Author: Pan Li
Date: Mon Jun 17 16:31:26 2024 +0800
RISC-V: Add testcases for unsigned .SAT_ADD vector form 5
After the middle-end support the form 5 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 5.
Form 5:
#define DEF_VEC_SAT_U_ADD_FMT_5(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
out[i] = __builtin_add_overflow (x, y, ) == 0 ? ret : -1; \
}\
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 17 +
.../riscv/rvv/autovec/binop/vec_sat_u_add-17.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-18.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-19.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-20.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c | 75 ++
9 files changed, 396 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index e00769e35b60..1f2ee31577dc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -61,6 +61,20 @@ vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_ADD_FMT_5(T) \
+void __attribute__((noinline)) \
+vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ T ret; \
+ out[i] = __builtin_add_overflow (x, y, ) == 0 ? ret : -1; \
+}\
+}
+
#define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
@@ -73,6 +87,9 @@ vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned
limit) \
#define RUN_VEC_SAT_U_ADD_FMT_4(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_4(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_ADD_FMT_5(T, out, op_1, op_2, N) \
+ vec_sat_u_add_##T##_fmt_5(out, op_1, op_2, N)
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
/**/
diff --git
[gcc r15-1428] RISC-V: Add testcases for unsigned .SAT_ADD vector form 4
https://gcc.gnu.org/g:24ae0a0a3dea27d8c81f2f102d637cf09424b4b9
commit r15-1428-g24ae0a0a3dea27d8c81f2f102d637cf09424b4b9
Author: Pan Li
Date: Mon Jun 17 16:09:13 2024 +0800
RISC-V: Add testcases for unsigned .SAT_ADD vector form 4
After the middle-end support the form 4 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 4.
Form 4:
#define DEF_VEC_SAT_U_ADD_FMT_4(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
out[i] = __builtin_add_overflow (x, y, ) ? -1 : ret; \
}\
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 17 +
.../riscv/rvv/autovec/binop/vec_sat_u_add-13.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-14.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-15.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-16.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c | 75 ++
9 files changed, 396 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 76f393fffbd1..e00769e35b60 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -47,6 +47,20 @@ vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_ADD_FMT_4(T) \
+void __attribute__((noinline)) \
+vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ T ret; \
+ out[i] = __builtin_add_overflow (x, y, ) ? -1 : ret; \
+}\
+}
+
#define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
@@ -56,6 +70,9 @@ vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned
limit) \
#define RUN_VEC_SAT_U_ADD_FMT_3(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_3(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_ADD_FMT_4(T, out, op_1, op_2, N) \
+ vec_sat_u_add_##T##_fmt_4(out, op_1, op_2, N)
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
/**/
diff --git
[gcc r15-1427] RISC-V: Add testcases for unsigned .SAT_ADD vector form 3
https://gcc.gnu.org/g:1bdcac7aefdd2a170112e2c78e8e769f7caad0a2
commit r15-1427-g1bdcac7aefdd2a170112e2c78e8e769f7caad0a2
Author: Pan Li
Date: Mon Jun 17 14:53:12 2024 +0800
RISC-V: Add testcases for unsigned .SAT_ADD vector form 3
After the middle-end support the form 3 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 3.
Form 3:
#define DEF_VEC_SAT_U_ADD_FMT_3(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
T overflow = __builtin_add_overflow (x, y, ); \
out[i] = (T)(-overflow) | ret; \
}\
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 18 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-10.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-11.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-12.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-9.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c | 75 ++
9 files changed, 397 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 57b1bce4bd2c..76f393fffbd1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -32,12 +32,30 @@ vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_ADD_FMT_3(T) \
+void __attribute__((noinline)) \
+vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ T ret; \
+ T overflow = __builtin_add_overflow (x, y, ); \
+ out[i] = (T)(-overflow) | ret; \
+}\
+}
+
#define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
#define RUN_VEC_SAT_U_ADD_FMT_2(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_2(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_ADD_FMT_3(T, out, op_1, op_2, N) \
+ vec_sat_u_add_##T##_fmt_3(out, op_1, op_2, N)
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
[gcc r15-1426] RISC-V: Add testcases for unsigned .SAT_ADD vector form 2
https://gcc.gnu.org/g:a84945e521e5687cdc46fc1f963d64d0b7f26cdd
commit r15-1426-ga84945e521e5687cdc46fc1f963d64d0b7f26cdd
Author: Pan Li
Date: Mon Jun 17 14:39:10 2024 +0800
RISC-V: Add testcases for unsigned .SAT_ADD vector form 2
After the middle-end support the form 2 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 2.
Form 2:
#define DEF_VEC_SAT_U_ADD_FMT_2(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
{\
unsigned i;\
for (i = 0; i < limit; i++)\
{\
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = (T)(x + y) >= x ? (x + y) : -1; \
}\
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: New
test.
Signed-off-by: Pan Li
Diff:
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h| 16 +
.../riscv/rvv/autovec/binop/vec_sat_u_add-5.c | 19 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-6.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-7.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-8.c | 20 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c | 75 ++
.../riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c | 75 ++
9 files changed, 395 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index 450f0fbbc72c..57b1bce4bd2c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -19,9 +19,25 @@ vec_sat_u_add_##T##_fmt_1 (T *out, T *op_1, T *op_2,
unsigned limit) \
}\
}
+#define DEF_VEC_SAT_U_ADD_FMT_2(T) \
+void __attribute__((noinline)) \
+vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
+{\
+ unsigned i;\
+ for (i = 0; i < limit; i++)\
+{\
+ T x = op_1[i]; \
+ T y = op_2[i]; \
+ out[i] = (T)(x + y) >= x ? (x + y) : -1; \
+}\
+}
+
#define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N)
+#define RUN_VEC_SAT_U_ADD_FMT_2(T, out, op_1, op_2, N) \
+ vec_sat_u_add_##T##_fmt_2(out, op_1, op_2, N)
+
/**/
/* Saturation Sub (Unsigned and Signed)
*/
/**/
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
new file mode 100644
index ..a46a3c592c24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3
