[gcc r15-1562] [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests
https://gcc.gnu.org/g:77f3b3419d476e90a2b82dff2204466aba3b9c2c
commit r15-1562-g77f3b3419d476e90a2b82dff2204466aba3b9c2c
Author: Craig Blackmore
Date: Sat Jun 22 22:07:06 2024 -0600
[PATCH] RISC-V: Fix unresolved mcpu-[67].c tests
These tests check the sched2 dump, so skip them for optimization levels
that do not enable sched2.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-6.c: Skip for -O0, -O1, -Og.
* gcc.target/riscv/mcpu-7.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/riscv/mcpu-6.c | 1 +
gcc/testsuite/gcc.target/riscv/mcpu-7.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-6.c
b/gcc/testsuite/gcc.target/riscv/mcpu-6.c
index 96faa01653e..0126011939f 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-6.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-6.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
/* Verify -mtune has higher priority than -mcpu for pipeline model . */
/* { dg-options "-mcpu=sifive-u74 -mtune=rocket -fdump-rtl-sched2-details
-march=rv32i -mabi=ilp32" } */
/* { dg-final { scan-rtl-dump "simple_return\[ \]+:alu" "sched2" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-7.c
b/gcc/testsuite/gcc.target/riscv/mcpu-7.c
index 6832323e529..656436343bd 100644
--- a/gcc/testsuite/gcc.target/riscv/mcpu-7.c
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-7.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
/* Verify -mtune has higher priority than -mcpu for pipeline model . */
/* { dg-options "-mcpu=sifive-s21 -mtune=sifive-u74 -fdump-rtl-sched2-details
-march=rv32i -mabi=ilp32" } */
/* { dg-final { scan-rtl-dump "simple_return\[ \]+:sifive_7_B" "sched2" } } */
[gcc r15-1561] [PATCH v2] RISC-V: Remove integer vector eqne pattern
https://gcc.gnu.org/g:dba21b6a4085506fe730f2ff5d9b56f5944223bf
commit r15-1561-gdba21b6a4085506fe730f2ff5d9b56f5944223bf
Author: demin.han
Date: Sat Jun 22 22:02:02 2024 -0600
[PATCH v2] RISC-V: Remove integer vector eqne pattern
We can unify eqne and other comparison operations.
Tested on RV32 and RV64.
gcc/ChangeLog:
* config/riscv/predicates.md (comparison_except_eqge_operator): Only
exclude ge.
(comparison_except_ge_operator): Ditto.
* config/riscv/riscv-string.cc (expand_rawmemchr): Use cmp pattern.
(expand_strcmp): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond.
* config/riscv/vector.md (@pred_eqne_scalar): Remove eqne
patterns.
(*pred_eqne_scalar_merge_tie_mask): Ditto.
(*pred_eqne_scalar): Ditto.
(*pred_eqne_scalar_narrow): Ditto.
(*pred_eqne_extended_scalar_merge_tie_mask): Ditto.
(*pred_eqne_extended_scalar): Ditto.
(*pred_eqne_extended_scalar_narrow): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/integer-cmp-eqne.c: New test.
Diff:
---
gcc/config/riscv/predicates.md | 4 +-
gcc/config/riscv/riscv-string.cc | 4 +-
gcc/config/riscv/riscv-vector-builtins-bases.cc| 3 -
gcc/config/riscv/vector.md | 279 +
.../gcc.target/riscv/rvv/base/integer-cmp-eqne.c | 66 +
5 files changed, 81 insertions(+), 275 deletions(-)
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 0fb5729fdcf..9971fabc587 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -568,8 +568,8 @@
(define_predicate "comparison_except_ltge_operator"
(match_code "eq,ne,le,leu,gt,gtu"))
-(define_predicate "comparison_except_eqge_operator"
- (match_code "le,leu,gt,gtu,lt,ltu"))
+(define_predicate "comparison_except_ge_operator"
+ (match_code "eq,ne,le,leu,gt,gtu,lt,ltu"))
(define_predicate "ge_operator"
(match_code "ge,geu"))
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index 83e7afbd693..4702001bd9b 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -1342,7 +1342,7 @@ expand_rawmemchr (machine_mode mode, rtx dst, rtx
haystack, rtx needle,
/* Compare needle with haystack and store in a mask. */
rtx eq = gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, needle),
vec);
rtx vmsops[] = {mask, eq, vec, needle};
- emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode),
+ emit_nonvlmax_insn (code_for_pred_cmp_scalar (vmode),
riscv_vector::COMPARE_OP, vmsops, cnt);
/* Find the first bit in the mask. */
@@ -1468,7 +1468,7 @@ expand_strcmp (rtx result, rtx src1, rtx src2, rtx nbytes,
= gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, CONST0_RTX
(mode)),
vec1);
rtx vmsops1[] = {mask0, eq0, vec1, CONST0_RTX (mode)};
- emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode),
+ emit_nonvlmax_insn (code_for_pred_cmp_scalar (vmode),
riscv_vector::COMPARE_OP, vmsops1, cnt);
/* Look for vec1 != vec2 (includes vec2[i] == 0). */
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 596b88cc8a3..6483faba39c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -718,9 +718,6 @@ public:
if (CODE == GE || CODE == GEU)
return e.use_compare_insn (CODE, code_for_pred_ge_scalar (
e.vector_mode ()));
- else if (CODE == EQ || CODE == NE)
- return e.use_compare_insn (CODE, code_for_pred_eqne_scalar (
- e.vector_mode ()));
else
return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
e.vector_mode ()));
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index f8fae6557d9..fe18ee5b5f7 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -4704,7 +4704,7 @@
(match_operand 8 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator: 3 "comparison_except_eqge_operator"
+ (match_operator: 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_QHS 4 "register_operand")
(vec_duplicate:V_VLSI_QHS
(match_operand: 5 "register_operand"))])
@@ -4722,7 +4722,7 @@
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator: 2
[gcc(refs/vendors/ibm/heads/gcc-12-branch)] ibm: Merge up to top of releases/gcc-12
https://gcc.gnu.org/g:3409c8aae4b0e2a73fa34aec8c58c261384283dc commit 3409c8aae4b0e2a73fa34aec8c58c261384283dc Merge: 92786addfe0 218adac0fce Author: Peter Bergner Date: Sat Jun 22 08:54:14 2024 -0500 ibm: Merge up to top of releases/gcc-12 2024-06-22 Peter Bergner Merge up to releases/gcc-12 218adac0fce6135fcb5c0c56911272687f05872b Diff: ChangeLog | 4 + c++tools/ChangeLog | 4 + config/ChangeLog | 4 + contrib/ChangeLog | 4 + contrib/header-tools/ChangeLog | 4 + contrib/reghunt/ChangeLog | 4 + contrib/regression/ChangeLog | 4 + fixincludes/ChangeLog | 4 + gcc/BASE-VER | 2 +- gcc/ChangeLog | 411 + gcc/ChangeLog.ibm | 4 + gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 9 + gcc/ada/exp_util.adb | 6 + gcc/analyzer/ChangeLog | 4 + gcc/asan.cc| 26 +- gcc/attribs.cc | 17 +- gcc/bb-reorder.cc | 3 +- gcc/bitmap.cc | 2 +- gcc/builtins.cc| 16 +- gcc/c-family/ChangeLog | 34 ++ gcc/c-family/c-attribs.cc | 32 +- gcc/c-family/c-lex.cc | 32 +- gcc/c-family/c-warn.cc | 13 +- gcc/c/ChangeLog| 14 + gcc/c/c-decl.cc| 15 + gcc/cfgexpand.cc | 30 +- gcc/cfgrtl.cc | 3 +- gcc/combine.cc | 6 +- gcc/config/aarch64/aarch64.cc | 2 + gcc/config/alpha/alpha.md | 21 +- gcc/config/alpha/constraints.md| 2 +- gcc/config/arm/arm.cc | 76 +++- gcc/config/i386/i386-expand.cc | 17 + gcc/config/i386/i386.cc| 62 +++- gcc/config/i386/x86-tune.def | 2 +- gcc/config/mips/mips.cc| 11 +- gcc/config/rs6000/rs6000-builtin.cc| 2 +- gcc/config/rs6000/rs6000-c.cc | 62 ++-- gcc/config/rs6000/rs6000-gen-builtins.cc | 72 ++-- gcc/cp/ChangeLog | 35 ++ gcc/cp/cp-gimplify.cc | 4 + gcc/cp/semantics.cc| 10 +- gcc/d/ChangeLog| 4 + gcc/doc/generic.texi | 2 +- gcc/doc/rtl.texi | 2 +- gcc/fold-const.cc | 20 +- gcc/fortran/ChangeLog | 4 + gcc/ggc-common.cc | 2 +- gcc/gimple-ssa-sprintf.cc | 20 +- gcc/go/ChangeLog | 4 + gcc/internal-fn.cc | 19 + gcc/ipa-icf.cc | 32 +- gcc/jit/ChangeLog | 4 + gcc/lra-constraints.cc | 5 + gcc/lra.cc | 5 +- gcc/lto/ChangeLog | 4 + gcc/objc/ChangeLog | 4 + gcc/objcp/ChangeLog| 4 + gcc/opts-common.cc | 6 +- gcc/po/ChangeLog | 4 + gcc/rtl-ssa/blocks.cc | 7 +- gcc/rtlanal.cc | 11 +- gcc/system.h | 39 +- gcc/testsuite/ChangeLog| 317 gcc/testsuite/c-c++-common/Warray-compare-3.c | 13 + gcc/testsuite/c-c++-common/Wattributes-3.c | 13 + gcc/testsuite/g++.dg/cpp1z/pr115440.C | 8 + gcc/testsuite/g++.dg/cpp2a/bit-cast16.C| 16 + .../g++.dg/cpp2a/is-constant-evaluated15.C | 28 ++ gcc/testsuite/g++.dg/ext/attrib68.C| 8 + gcc/testsuite/g++.dg/ext/pr114691.C| 22 ++ gcc/testsuite/g++.dg/torture/vector-struct-1.C | 18 + gcc/testsuite/g++.target/i386/pr111497.C | 22 ++ gcc/testsuite/gcc.c-torture/compile/pr113603.c | 40 ++
[gcc/ibm/heads/gcc-12-branch] (99 commits) ibm: Merge up to top of releases/gcc-12
The branch 'ibm/heads/gcc-12-branch' was updated to point to:
3409c8aae4b... ibm: Merge up to top of releases/gcc-12
It previously pointed to:
92786addfe0... ibm: Merge up to top of releases/gcc-12
Diff:
Summary of changes (added commits):
---
3409c8a... ibm: Merge up to top of releases/gcc-12
218adac... Daily bump. (*)
169d4d1... libstdc++: Fix test on x86_64 and non-simd targets (*)
8b5bdeb... libstdc++: Fix find_last_set(simd_mask) to ignore padding b (*)
cdbff5f... Daily bump. (*)
b9569e7... libstdc++: Fix simd conversion for -fno-signed-char f (*)
f79b273... libstdc++: Avoid MMX return types from __builtin_shufflevec (*)
fb06754... libstdc++: Use __builtin_shufflevector for simd split and c (*)
c60dd0e... diagnostics: Fix add_misspelling_candidates [PR115440] (*)
8f612e6... c-family: Fix -Warray-compare warning ICE [PR115290] (*)
98794d9... Bump BASE-VER. (*)
2bada4b... Update ChangeLog and version files for release (*)
fac4fbd... Daily bump. (*)
9c0c31d... Daily bump. (*)
b87418f... Daily bump. (*)
ea0aa97... libstdc++: Fix declaration of posix_memalign for freestandi (*)
caa4702... Daily bump. (*)
26640a5... Daily bump. (*)
573a5f3... Daily bump. (*)
5319283... Daily bump. (*)
6693b1f... Daily bump. (*)
448dd00... arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR11 (*)
33663c0... cfgrtl: Fix MEM_EXPR update in duplicate_insn_chain [PR1149 (*)
959cef9... [PR111497][LRA]: Copy substituted equivalence (*)
844ff32... middle-end/40635 - SSA update losing PHI arg loations (*)
1edc6a7... rtl-optimization/54052 - RTL SSA PHI insertion compile-time (*)
3d9e4ee... testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115 (*)
55c1687... arm: Zero/Sign extends for CMSE security on Armv8-M.baselin (*)
f38ffe3... Daily bump. (*)
a995fde... Include safe-ctype.h after C++ standard headers, to avoid o (*)
8f11ed1... libcc1: fix include (*)
d30afaa... PHIOPT: Don't transform minmax if middle bb contains a phi (*)
870e389... libstdc++: Fix fwrite error parameter (*)
3837f95... libstdc++: Define __cpp_lib_constexpr_algorithms in [ (*)
80d0f82... libstdc++: Reverse arguments in constraint for std::optiona (*)
c394e29... libstdc++: Destroy allocators in re-inserted container node (*)
d4126b3... c: Fix up pointer types to may_alias structures [PR114493] (*)
b065824... fold-const: Fix up CLZ handling in tree_call_nonnegative_wa (*)
91a3712... builtins: Force SAVE_EXPR for __builtin_{add,sub,mul}_overf (*)
bda8c28... rs6000: Fix up PCH in --enable-host-pie builds [PR115324] (*)
840bc67... combine: Fix up simplify_compare_const [PR115092] (*)
25bd98d... tree-inline: Remove .ASAN_MARK calls when inlining function (*)
bf13440... gimple-ssa-sprintf: Use [0, 1] range for %lc with (wint_t) (*)
cc96dc5... openmp: Copy DECL_LANG_SPECIFIC and DECL_LANG_FLAG_? to tre (*)
7d06735... rtlanal: Fix set_noop_p for volatile loads or stores [PR114 (*)
b3ef00f... internal-fn: Temporarily disable flag_trapv during .{ADD,SU (*)
bb21a7d... attribs: Don't crash on NULL TREE_TYPE in diag_attr_exclusi (*)
e9b960e... c++: Fix bogus warnings about ignored annotations [PR114691 (*)
082fe43... asan, v3: Fix up handling of > 32 byte aligned variables wi (*)
b3b7176... c++: Fix up maybe_warn_for_constant_evaluated calls [PR1145 (*)
f8a3279... vect: Don't clear base_misaligned in update_epilogue_loop_v (*)
f33e8ee... c++: Fix ICE with weird copy assignment operator [PR114572] (*)
42afabb... fold-const: Handle NON_LVALUE_EXPR in native_encode_initial (*)
9987fe6... libquadmath: Don't assume the storage for __float128 argume (*)
81c300b... icf: Reset SSA_NAME_{PTR,RANGE}_INFO in successfully merged (*)
9f48459... aarch64: Fix TImode __sync_*_compare_and_exchange expansion (*)
b294d46... bb-reorder: Fix -freorder-blocks-and-partition ICEs on aarc (*)
9299722... i386: Fix ICEs with SUBREGs from vector etc. constants to X (*)
c2cd5ee... c: Handle scoped attributes in __has*attribute and scoped a (*)
fda7a89... attribs: Don't canonicalize lookup_scoped_attribute_spec ar (*)
e697601... ggc-common: Fix save PCH assertion (*)
f5758e8... tree-ssa-strlen: Fix up handle_store [PR113603] (*)
ba38543... docs: Fix 2 typos (*)
bc51282... i386: Add -masm=intel profiling support [PR113122] (*)
170c2bb... cfgexpand: Workaround CSE of ADDR_EXPRs in VAR_DECL partiti (*)
3f0d1e5... libgomp: Fix up FLOCK fallback handling [PR113192] (*)
ca8ad80... c-family: copy attribute diagnostic fixes [PR113262] (*)
d73137a... tree-optimization/111070 - fix ICE with recent ifcombine fi (*)
cc835f4... Daily bump. (*)
12a3ba2... Fix crash on access-to-incomplete type (*)
481a766... Daily bump. (*)
6e35fb3... Daily bump. (*)
4745c29... Daily bump. (*)
5d52558... Disable FMADD in chains for Zen4 and generic (*)
208c8dc... Daily bump. (*)
a741bb3... Daily bump. (*)
a7edd18... Daily bump.
[gcc r15-1559] [committed] [RISC-V] Skip zbs-ext-2.c for -Oz as well
https://gcc.gnu.org/g:6ceb5f7859e3fe39feb62de402bed656b8dfe6b9
commit r15-1559-g6ceb5f7859e3fe39feb62de402bed656b8dfe6b9
Author: Jeff Law
Date: Sat Jun 22 10:39:51 2024 -0600
[committed] [RISC-V] Skip zbs-ext-2.c for -Oz as well
> the test should probably also be skipped on -Oz:
>
> === gcc: Unexpected fails for rv64imafdc lp64d medlow
===
> FAIL: gcc.target/riscv/zbs-ext-2.c -Oz scan-assembler-times andi\t 1
> FAIL: gcc.target/riscv/zbs-ext-2.c -Oz scan-assembler-times andn\t 1
> FAIL: gcc.target/riscv/zbs-ext-2.c -Oz scan-assembler-times li\t 1
Yea. Just re-ran thing and sure enough we need to skip -Oz as well. So
committing the obvious change
gcc/testsuite/
* gcc.target/riscv/zbs-ext-2.c: Also skip for -Oz.
Diff:
---
gcc/testsuite/gcc.target/riscv/zbs-ext-2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-ext-2.c
b/gcc/testsuite/gcc.target/riscv/zbs-ext-2.c
index 690dd722bce..6d11543d920 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-ext-2.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-ext-2.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gc_zbb_zbs -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
typedef unsigned int uint32_t;
[gcc(refs/users/meissner/heads/work169-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:8c824f092b4c95c086a4e4eba52fa6a0024e832b commit 8c824f092b4c95c086a4e4eba52fa6a0024e832b Author: Michael Meissner Date: Sat Jun 22 12:08:19 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 17 + 1 file changed, 17 insertions(+) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index 0ec50215226..622876fd9d8 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,3 +1,20 @@ + Branch work169-tar, patch #207 + +Change TAR debug options. + +2024-06-22 Michael Meissner + + * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Delete + -mqispr, -mhispr, -msispr, -mfpspr, -mdfspr. Add -mintspr and -mfpspr. + (rs6000_debug_reg_global): Likewise. + * config/rs6000/rs6000.opt (-mqispr): Delete. + (-mhispr): Likewise. + (-msispr): Likewise. + (-msfspr): Likewise. + (-mdfspr): Likewise. + (-mintspr): New option. + (-mfpspr): Likewise. + Branch work169-tar, patch #206 Delete -mlrspr, -mintspr, -mfpspr
[gcc(refs/users/meissner/heads/work169-tar)] Change TAR debug options.
https://gcc.gnu.org/g:c0d135dce0787d4516b19615b9743260ea0a1924
commit c0d135dce0787d4516b19615b9743260ea0a1924
Author: Michael Meissner
Date: Sat Jun 22 12:07:03 2024 -0400
Change TAR debug options.
2024-06-22 Michael Meissner
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Delete
-mqispr, -mhispr, -msispr, -mfpspr, -mdfspr. Add -mintspr and
-mfpspr.
(rs6000_debug_reg_global): Likewise.
* config/rs6000/rs6000.opt (-mqispr): Delete.
(-mhispr): Likewise.
(-msispr): Likewise.
(-msfspr): Likewise.
(-mdfspr): Likewise.
(-mintspr): New option.
(-mfpspr): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 54 ++--
gcc/config/rs6000/rs6000.opt | 26 ++---
2 files changed, 19 insertions(+), 61 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index d96adf12c5d..7bd7e2f2181 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1954,34 +1954,16 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if (orig_complex_p)
return 0;
- if (GET_MODE_CLASS (mode) == MODE_CC)
- return TARGET_CCSPR != 0;
-
- switch (mode)
- {
- case E_QImode:
- return TARGET_QISPR != 0;
-
- case E_HImode:
- return TARGET_HISPR != 0;
-
- case E_SImode:
- return TARGET_SISPR || !TARGET_POWERPC64;
-
- case E_DImode:
- return TARGET_POWERPC64 != 0;
-
- case E_SFmode:
- return TARGET_SFSPR != 0;
+ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+ return 0;
- case E_DFmode:
- return TARGET_DFSPR && TARGET_POWERPC64;
+ if (SCALAR_INT_MODE_P (mode))
+ return (mode == Pmode || TARGET_INTSPR);
- default:
- break;
- }
+ if (SCALAR_FLOAT_MODE_P (mode))
+ return TARGET_FPSPR != 0;
- return false;
+ return (TARGET_CCSPR && GET_MODE_CLASS (mode) == MODE_CC);
default:
break;
@@ -2646,26 +2628,14 @@ rs6000_debug_reg_global (void)
fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
(int)VECTOR_ELEMENT_MFVSRLD_64BIT);
- fprintf (stderr, DEBUG_FMT_S, "Condition modes in SPR",
+ fprintf (stderr, DEBUG_FMT_S, "Condition code modes in SPRs",
TARGET_CCSPR ? "yes" : "no");
- fprintf (stderr, DEBUG_FMT_S, "QImode in SPR",
- TARGET_QISPR ? "yes" : "no");
-
- fprintf (stderr, DEBUG_FMT_S, "HImode in SPR",
- TARGET_HISPR ? "yes" : "no");
-
- fprintf (stderr, DEBUG_FMT_S, "SImode in SPR",
- TARGET_SISPR || !TARGET_POWERPC64 ? "yes" : "no");
-
- fprintf (stderr, DEBUG_FMT_S, "DImode in SPR",
- TARGET_POWERPC64 ? "yes" : "no");
-
- fprintf (stderr, DEBUG_FMT_S, "SFmode in SPR",
- TARGET_SFSPR ? "yes" : "no");
+ fprintf (stderr, DEBUG_FMT_S, "Small integer modes in SPRs",
+ TARGET_INTSPR ? "yes" : "no");
- fprintf (stderr, DEBUG_FMT_S, "DFmode in SPR",
- TARGET_DFSPR ? "yes" : "no");
+ fprintf (stderr, DEBUG_FMT_S, "Floating point modes in SPRs",
+ TARGET_FPSPR ? "yes" : "no");
}
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 27f873972b5..e5657003e27 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -636,27 +636,15 @@ Allow (do not allow) use the TAR register.
mccspr
Target Undocumented Var(TARGET_CCSPR) Init(0)
-Allow (do not allow) condition modes to be in the CTR or TAR registers.
+Allow (do not allow) condition modes to be in the LR, CTR or TAR registers.
-mqispr
-Target Undocumented Var(TARGET_QISPR) Init(1)
-Allow (do not allow) 8-bit integers to be in the CTR or TAR registers.
+mintspr
+Target Undocumented Var(TARGET_INTSPR) Init(0)
+Allow (do not allow) small integers to be in the LR, CTR or TAR registers.
-mhispr
-Target Undocumented Var(TARGET_HISPR) Init(1)
-Allow (do not allow) 16-bit integers to be in the CTR or TAR registers.
-
-msispr
-Target Undocumented Var(TARGET_SISPR) Init(1)
-Allow (do not allow) 32-bit integers to be in the CTR or TAR registers.
-
-msfspr
-Target Undocumented Var(TARGET_SFSPR) Init(0)
-Allow (do not allow) 32-bit floating point to be in the CTR or TAR registers.
-
-mdfspr
-Target Undocumented Var(TARGET_DFSPR) Init(0)
-Allow (do not allow) 64-bit floating point to be in the CTR or TAR registers.
+mfpspr
+Target Undocumented Var(TARGET_FPSPR) Init(0)
+Allow (do not allow) floating point to be in the LR, CTR or TAR registers.
; Documented parameters
gcc-wwwdocs branch master updated. 186d8eefd7ff819fb15990c367c5cd43150e601d
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via 186d8eefd7ff819fb15990c367c5cd43150e601d (commit) from 3da227050417c1032e5057626d6ccd2bef7282b3 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log - commit 186d8eefd7ff819fb15990c367c5cd43150e601d Author: Gerald Pfeifer Date: Sat Jun 22 14:52:06 2024 +0200 news: Tweak MPFR link diff --git a/htdocs/news.html b/htdocs/news.html index 471b31b7..e78abfc3 100644 --- a/htdocs/news.html +++ b/htdocs/news.html @@ -798,7 +798,7 @@ annual report for 2008 January 6, 2007 Kaveh Ghazi has integrated the GCC middle-end with the http://www.mpfr.org/;>MPFR library, allowing more +href="https://www.mpfr.org;>MPFR library, allowing more effective compile-time optimizations. As a result, this library and the https://gmplib.org/;>GMP library are now
[gcc r15-1558] libstdc++: Move gcc.gnu.org and sourceware.org links to https
https://gcc.gnu.org/g:d4adba21a7a1428a0ad1a2647fe98fca77f5bf3c commit r15-1558-gd4adba21a7a1428a0ad1a2647fe98fca77f5bf3c Author: Gerald Pfeifer Date: Sat Jun 22 14:44:11 2024 +0200 libstdc++: Move gcc.gnu.org and sourceware.org links to https libstdc++-v3: * doc/xml/manual/debug.xml: Move gcc.gnu.org link to https. Ditto for sourceware.org links. * doc/html/manual/debug.html: Regenerate. Diff: --- libstdc++-v3/doc/html/manual/debug.html | 10 +- libstdc++-v3/doc/xml/manual/debug.xml | 8 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/libstdc++-v3/doc/html/manual/debug.html b/libstdc++-v3/doc/html/manual/debug.html index eb83d4e15ac..a5f51569e00 100644 --- a/libstdc++-v3/doc/html/manual/debug.html +++ b/libstdc++-v3/doc/html/manual/debug.html @@ -27,7 +27,7 @@ platform can be identified via the value set by the PREFERRED_DEBUGGING_TYPE macro in the GCC sources. - Many other options are available: please see http://gcc.gnu.org/onlinedocs/gcc/Debugging-Options.html#Debugging%20Options; target="_top">"Options + Many other options are available: please see https://gcc.gnu.org/onlinedocs/gcc/Debugging-Options.html#Debugging%20Options; target="_top">"Options for Debugging Your Program" in Using the GNU Compiler Collection (GCC) for a complete list. Debug Mode @@ -180,7 +180,7 @@ Refer to the documentation of each particular tool for details. Using gdb - Many options are available for GDB itself: please see http://sourceware.org/gdb/current/onlinedocs/gdb; target="_top"> + Many options are available for GDB itself: please see https://sourceware.org/gdb/current/onlinedocs/gdb; target="_top"> "GDB features for C++" in the GDB documentation. Also recommended: the other parts of this manual. @@ -214,12 +214,12 @@ print the classes as if the Python pretty-printers were not loaded. For additional information on STL support and GDB please visit: - http://sourceware.org/gdb/wiki/STLSupport; target="_top"> "GDB Support + https://sourceware.org/gdb/wiki/STLSupport; target="_top"> "GDB Support for STL" in the GDB wiki. Additionally, in-depth documentation and discussion of the pretty printing feature can be found in "Pretty Printing" node in the GDB manual. You can find on-line versions of the GDB user manual in GDB's homepage, at - http://sourceware.org/gdb/; target="_top"> "GDB: The GNU Project + https://sourceware.org/gdb/; target="_top"> "GDB: The GNU Project Debugger" . Debug Versions of Library Binary Files As described above, libstdc++ is built with debug symbols enabled by default, @@ -250,4 +250,4 @@ with C++11 and later standards. They might be removed at a future date. Prev Up NextExceptions Home Part II. Standard Contents - \ No newline at end of file + diff --git a/libstdc++-v3/doc/xml/manual/debug.xml b/libstdc++-v3/doc/xml/manual/debug.xml index 23dbae5e521..44784071538 100644 --- a/libstdc++-v3/doc/xml/manual/debug.xml +++ b/libstdc++-v3/doc/xml/manual/debug.xml @@ -49,7 +49,7 @@ - Many other options are available: please see http://www.w3.org/1999/xlink; xlink:href="http://gcc.gnu.org/onlinedocs/gcc/Debugging-Options.html#Debugging%20Options;>"Options + Many other options are available: please see http://www.w3.org/1999/xlink; xlink:href="https://gcc.gnu.org/onlinedocs/gcc/Debugging-Options.html#Debugging%20Options;>"Options for Debugging Your Program" in Using the GNU Compiler Collection (GCC) for a complete list. @@ -270,7 +270,7 @@ - Many options are available for GDB itself: please see http://www.w3.org/1999/xlink; xlink:href="http://sourceware.org/gdb/current/onlinedocs/gdb;> + Many options are available for GDB itself: please see http://www.w3.org/1999/xlink; xlink:href="https://sourceware.org/gdb/current/onlinedocs/gdb;> "GDB features for C++" in the GDB documentation. Also recommended: the other parts of this manual. @@ -316,12 +316,12 @@ For additional information on STL support and GDB please visit: - http://www.w3.org/1999/xlink; xlink:href="http://sourceware.org/gdb/wiki/STLSupport;> "GDB Support + http://www.w3.org/1999/xlink; xlink:href="https://sourceware.org/gdb/wiki/STLSupport;> "GDB Support for STL" in the GDB wiki. Additionally, in-depth documentation and discussion of the pretty printing feature can be found in "Pretty Printing" node in the GDB manual. You can find on-line versions of the GDB user manual in GDB's homepage, at - http://www.w3.org/1999/xlink; xlink:href="http://sourceware.org/gdb/;> "GDB: The GNU Project + http://www.w3.org/1999/xlink; xlink:href="https://sourceware.org/gdb/;> "GDB: The GNU Project Debugger" .
gcc-wwwdocs branch master updated. 3da227050417c1032e5057626d6ccd2bef7282b3
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via 3da227050417c1032e5057626d6ccd2bef7282b3 (commit) from f28f3a28bd84e2ff5cd4b1017c0fa15787c9fa08 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log - commit 3da227050417c1032e5057626d6ccd2bef7282b3 Author: Gerald Pfeifer Date: Sat Jun 22 14:29:36 2024 +0200 contribute: Add a missing parenthesis diff --git a/htdocs/contribute.html b/htdocs/contribute.html index 7d85d885..24f8d30b 100644 --- a/htdocs/contribute.html +++ b/htdocs/contribute.html @@ -270,7 +270,7 @@ characters. The classifier identifies the type of contribution, for example a patch, an RFC (request for comments) or a committed patch (where -approval is not necessary. The classifier should be written in upper +approval is not necessary). The classifier should be written in upper case and surrounded with square brackets. This is the only component of the e-mail subject line that will not appear in the commit itself. The classifier may optionally contain a version number (vN) and --- Summary of changes: htdocs/contribute.html | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) hooks/post-receive -- gcc-wwwdocs
gcc-wwwdocs branch master updated. f28f3a28bd84e2ff5cd4b1017c0fa15787c9fa08
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via f28f3a28bd84e2ff5cd4b1017c0fa15787c9fa08 (commit) from 13f6a3d1282ffce8fcde986a85266556d75b7768 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log - commit f28f3a28bd84e2ff5cd4b1017c0fa15787c9fa08 Author: Gerald Pfeifer Date: Sat Jun 22 10:50:18 2024 +0200 backends: Fix markup with overly long block diff --git a/htdocs/backends.html b/htdocs/backends.html index 9272558c..2a63f91b 100644 --- a/htdocs/backends.html +++ b/htdocs/backends.html @@ -120,7 +120,7 @@ visium | B g t s xtensa | C -For AVR simulators, see +For AVR simulators, see https://github.com/sprintersb/atest; >AVRtest and @@ -131,7 +131,6 @@ xtensa | C >SimulAVR - For ARC simulator, see https://github.com/foss-for-synopsys-dwc-arc-processors/binutils-gdb;> --- Summary of changes: htdocs/backends.html | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) hooks/post-receive -- gcc-wwwdocs
[gcc(refs/users/meissner/heads/work169-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:e15e80b7fb451aef4b36d0c032e381cf9e5a0d52 commit e15e80b7fb451aef4b36d0c032e381cf9e5a0d52 Author: Michael Meissner Date: Sat Jun 22 04:49:12 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 13 + 1 file changed, 13 insertions(+) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index 597388b43a9..0ec50215226 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,3 +1,16 @@ + Branch work169-tar, patch #206 + +Delete -mlrspr, -mintspr, -mfpspr + +2024-06-21 Michael Meissner + + * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Delete + -mlrspr, -mintspr, and -mfpspr. + (rs6000_debug_reg_global): Likewise. + * config/rs6000/rs6000.opt (-mlrspr): Delete. + (-mintspr): Likewise. + (-mfpspr): Likewise. + Branch work169-tar, patch #205 Allow CCmodes in TAR register.
[gcc(refs/users/meissner/heads/work169-tar)] Delete -mlrspr, -mintspr, -mfpspr
https://gcc.gnu.org/g:ebef2cea73f63e836c2a818e5fc0bb3dd03161e2
commit ebef2cea73f63e836c2a818e5fc0bb3dd03161e2
Author: Michael Meissner
Date: Sat Jun 22 04:47:51 2024 -0400
Delete -mlrspr, -mintspr, -mfpspr
2024-06-21 Michael Meissner
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Delete
-mlrspr, -mintspr, and -mfpspr.
(rs6000_debug_reg_global): Likewise.
* config/rs6000/rs6000.opt (-mlrspr): Delete.
(-mintspr): Likewise.
(-mfpspr): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 26 +++---
gcc/config/rs6000/rs6000.opt | 12
2 files changed, 11 insertions(+), 27 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index ca551451060..d96adf12c5d 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1949,10 +1949,6 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
return (!orig_complex_p && mode == SImode);
case LR_REGNO:
- if (!TARGET_LRSPR)
- return (!orig_complex_p && mode == Pmode);
- /* fall through. */
-
case CTR_REGNO:
case TAR_REGNO:
if (orig_complex_p)
@@ -1964,22 +1960,22 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
switch (mode)
{
case E_QImode:
- return (TARGET_QISPR || TARGET_INTSPR);
+ return TARGET_QISPR != 0;
case E_HImode:
- return (TARGET_HISPR || TARGET_INTSPR);
+ return TARGET_HISPR != 0;
case E_SImode:
- return (TARGET_SISPR || TARGET_INTSPR || !TARGET_POWERPC64);
+ return TARGET_SISPR || !TARGET_POWERPC64;
case E_DImode:
- return TARGET_POWERPC64;
+ return TARGET_POWERPC64 != 0;
case E_SFmode:
- return (TARGET_SFSPR || TARGET_FPSPR);
+ return TARGET_SFSPR != 0;
case E_DFmode:
- return ((TARGET_DFSPR || TARGET_FPSPR) && TARGET_POWERPC64);
+ return TARGET_DFSPR && TARGET_POWERPC64;
default:
break;
@@ -2654,22 +2650,22 @@ rs6000_debug_reg_global (void)
TARGET_CCSPR ? "yes" : "no");
fprintf (stderr, DEBUG_FMT_S, "QImode in SPR",
- (TARGET_QISPR || TARGET_INTSPR) ? "yes" : "no");
+ TARGET_QISPR ? "yes" : "no");
fprintf (stderr, DEBUG_FMT_S, "HImode in SPR",
- TARGET_HISPR || TARGET_INTSPR ? "yes" : "no");
+ TARGET_HISPR ? "yes" : "no");
fprintf (stderr, DEBUG_FMT_S, "SImode in SPR",
- TARGET_SISPR || TARGET_INTSPR || !TARGET_POWERPC64 ? "yes" : "no");
+ TARGET_SISPR || !TARGET_POWERPC64 ? "yes" : "no");
fprintf (stderr, DEBUG_FMT_S, "DImode in SPR",
TARGET_POWERPC64 ? "yes" : "no");
fprintf (stderr, DEBUG_FMT_S, "SFmode in SPR",
- TARGET_SFSPR || TARGET_FPSPR ? "yes" : "no");
+ TARGET_SFSPR ? "yes" : "no");
fprintf (stderr, DEBUG_FMT_S, "DFmode in SPR",
- TARGET_DFSPR || TARGET_FPSPR ? "yes" : "no");
+ TARGET_DFSPR ? "yes" : "no");
}
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index b4b6dc8fa9c..27f873972b5 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -650,10 +650,6 @@ msispr
Target Undocumented Var(TARGET_SISPR) Init(1)
Allow (do not allow) 32-bit integers to be in the CTR or TAR registers.
-mintspr
-Target Undocumented Var(TARGET_INTSPR) Init(0)
-Allow (do not allow) small integers to be in the CTR or TAR registers.
-
msfspr
Target Undocumented Var(TARGET_SFSPR) Init(0)
Allow (do not allow) 32-bit floating point to be in the CTR or TAR registers.
@@ -662,14 +658,6 @@ mdfspr
Target Undocumented Var(TARGET_DFSPR) Init(0)
Allow (do not allow) 64-bit floating point to be in the CTR or TAR registers.
-mfpspr
-Target Undocumented Var(TARGET_FPSPR) Init(0)
-Allow (do not allow) floating point values to be in the CTR or TAR registers.
-
-mlrspr
-Target Undocumented Var(TARGET_LRSPR) Init(1)
-Treat (do not treat) the LR register like CTR/TAR in terms of what modes it
can hold.
-
; Documented parameters
-param=rs6000-vect-unroll-limit=
