[gcc r15-918] [testsuite] conditionalize dg-additional-sources on target and type
https://gcc.gnu.org/g:bdc264a16e327c63d133131a695a202fbbc0a6a0
commit r15-918-gbdc264a16e327c63d133131a695a202fbbc0a6a0
Author: Alexandre Oliva
Date: Thu May 30 02:06:48 2024 -0300
[testsuite] conditionalize dg-additional-sources on target and type
g++.dg/vect/pr95401.cc has dg-additional-sources, and that fails when
check_vect_support_and_set_flags finds vector support lacking for
execution tests: tests decay to compile tests, and additional sources
are rejected by the compiler when compiling to a named output file.
At first I considered using some effective target to conditionalize
the additional sources. There was no support for target-specific
additional sources, so I added that.
But then, I found that adding an effective target to check whether the
test involves linking would just make for busy work in this case, and
so I went ahead and adjusted the handling of additional sources to
refrain from adding them on compile tests, reporting them as
unsupported.
That solves the problem without using the newly-added machinery for
per-target additional sources, but I figured since I'd implemented it
I might as well contribute it, since there might be other uses for it.
for gcc/ChangeLog
* doc/sourcebuild.texi (dg-additional-sources): Document
newly-added support for target selectors, and implicit discard
on non-linking tests that name the compiler output explicitly.
for gcc/testsuite/ChangeLog
* lib/gcc-defs.exp (dg-additional-sources): Support target
selectors. Make it cumulative.
(dg-additional-files-options): Take dest and type. Note
unsupported additional sources when not linking and naming the
compiler output. Adjust source dirname prepending to cope
with leading blanks.
* lib/g++.exp (g++_target_compile): Pass dest and type on to
dg-additional-files-options.
* lib/gcc.exp (gcc_target_compile): Likewise.
* lib/gdc.exp (gdb_target_compile): Likewise.
* lib/gfortran.exp (gfortran_target_compile): Likewise.
* lib/go.exp (go_target_compile): Likewise.
* lib/obj-c++.exp (obj-c++_target_compile): Likewise.
* lib/objc.exp (objc_target_compile): Likewise.
* lib/rust.exp (rust_target_compile): Likewise.
* lib/profopt.exp (profopt-execute): Likewise-ish.
Diff:
---
gcc/doc/sourcebuild.texi | 8 +++-
gcc/testsuite/lib/g++.exp | 2 +-
gcc/testsuite/lib/gcc-defs.exp | 35 ++-
gcc/testsuite/lib/gcc.exp | 2 +-
gcc/testsuite/lib/gdc.exp | 2 +-
gcc/testsuite/lib/gfortran.exp | 2 +-
gcc/testsuite/lib/go.exp | 2 +-
gcc/testsuite/lib/obj-c++.exp | 2 +-
gcc/testsuite/lib/objc.exp | 2 +-
gcc/testsuite/lib/profopt.exp | 2 +-
gcc/testsuite/lib/rust.exp | 2 +-
11 files changed, 46 insertions(+), 15 deletions(-)
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 8e4e59ac44c..e997dbec333 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1320,9 +1320,15 @@ to @var{var_value} before execution of the program
created by the test.
Specify additional files, other than source files, that must be copied
to the system where the compiler runs.
-@item @{ dg-additional-sources "@var{filelist}" @}
+@item @{ dg-additional-sources "@var{filelist}" [@{ target @var{selector} @}]
@}
Specify additional source files to appear in the compile line
following the main test file.
+If the directive includes the optional @samp{@{ @var{selector} @}}
+then the additional sources are only added if the target system
+matches the @var{selector}.
+Additional sources are generally used only in @samp{link} and @samp{run}
+tests; they are reported as unsupported and discarded in other kinds of
+tests that direct the compiler to output to a single file.
@end table
@subsubsection Add checks at the end of a test
diff --git a/gcc/testsuite/lib/g++.exp b/gcc/testsuite/lib/g++.exp
index 0e47769c25b..a6b34d5d3a2 100644
--- a/gcc/testsuite/lib/g++.exp
+++ b/gcc/testsuite/lib/g++.exp
@@ -326,7 +326,7 @@ proc g++_target_compile { source dest type options } {
append board_info($tboard,multilib_flags) " $flags_to_postpone"
}
-set options [dg-additional-files-options $options $source]
+set options [dg-additional-files-options $options $source $dest $type]
if { [target_info needs_status_wrapper] != "" && [info exists gluefile] } {
lappend options "libs=${gluefile}"
diff --git a/gcc/testsuite/lib/gcc-defs.exp b/gcc/testsuite/lib/gcc-defs.exp
index 70215ed4905..cdca4c254d6 100644
--- a/gcc/testsuite/lib/gcc-defs.exp
+++ b/gcc/testsuite/lib/gcc-defs.exp
@@ -307,7 +307,22 @@ set additional_sources_used ""
proc dg-additional-sources { args } {
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:d34a3eb9286d547533a7226a504c229b2ab6d4b3
commit d34a3eb9286d547533a7226a504c229b2ab6d4b3
Author: Alexandre Oliva
Date: Wed May 29 02:52:14 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..46a3ebfa287 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fpcc-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc/aoliva/heads/testme] (78 commits) [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra
The branch 'aoliva/heads/testme' was updated to point to: ca809ee3fbe... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra It previously pointed to: 3bcf4294d89... [rs6000] adjust return_pc debug attrs Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 3bcf429... [rs6000] adjust return_pc debug attrs a56062c... enable adjustment of return_pc debug attrs Summary of changes (added commits): --- ca809ee... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 0276651... [libstdc++-v3] [rtems] enable filesystem support 1c34040... [tree-prof] skip if errors were seen [PR113681] 1b22d42... [testsuite] [arm] add effective target and options for pacb d34a3eb... add explicit ABI and align options to pr88233.c 0bb10f1... [rs6000] adjust return_pc debug attrs 99047b7... enable adjustment of return_pc debug attrs b644126... Align tight loop without considering max skipping bytes (*) 00ed542... Adjust generic loop alignment from 16:11:8 to 16 for Intel (*) d9933e8... testsuite, rs6000: Replace powerpc_vsx_ok with powerpc_vsx (*) a19f588... Gori_on_edge tweaks. (*) e5fc5d4... rs6000: Don't clobber return value when eh_return called [P (*) 2b84169... Daily bump. (*) 1d6199e... Reduce cost of MEM (A + imm). (*) 6f36cc2... More tweaks from gimple_outgoing_range changes. (*) 802a98d... resource.cc: Remove redundant conditionals (*) e1abce5... resource.cc (mark_target_live_regs): Remove check for bb no (*) 933ab59... resource.cc: Replace calls to find_basic_block with cfgrtl (*) 84b4ed4... resource.cc (mark_target_live_regs): Don't look past target (*) 91d7905... i386: Improve access to _Atomic DImode location via XMM reg (*) 21fc89b... diagnostics: consolidate global state in diagnostic-color.c (*) 9bda2c4... libcpp: move label_text to its own header (*) fb7a943... selftests: split out make_fndecl from selftest.h to its own (*) 7cc529f... regenerate-opt-urls.py: fix transposed values for "vax" and (*) efaaae4... c++: extend -Wself-move for mem-init-list [PR109396] (*) 5ada486... Do not invoke SCEV if it will use a different range query. (*) d52b44a... Strlen pass should set current range query. (*) 5bc731b... c++: mark TARGET_EXPRs for function arguments eliding [PR11 (*) c0d7828... testsuite/*/gomp: Remove 'dg-prune-output "not supported ye (*) 2dbb1c1... diagnostics: disable localization of events in selftest pat (*) b544ff8... Fix bootstrap on AIX by adding c-family/c-type-mismatch.cc (*) 2361160... [to-be-committed] [RISC-V] Some basic patterns for zbkb cod (*) a3aeff4... vect: Use vect representative statement instead of original (*) d8d70b7... target/115254 - fix gcc.dg/vect/vect-gather-4.c dump scanni (*) c08b0d3... tree-optimization/115236 - more points-to *ANYTHING = x fix (*) 19cc611... Avoid pessimistic constraints for asm memory constraints (*) eaaa4b8... tree-optimization/115254 - don't account single-lane SLP ag (*) 65aa46f... Fix SLP reduction neutral op value for pointer reductions (*) c650023... Fix predicate mismatch between vfcmaddcph's define_insn and (*) ded91d8... LoongArch: Guard REGNO with REG_P in loongarch_expand_condi (*) 4fcdc37... Fix bitops-9.c for -m32 and other targets that don't have v (*) 958a682... Daily bump. (*) c5a7628... match: Use uniform_integer_cst_p in bitwise_inverted_equal_ (*) a209f21... modula2: simplify xref usage in documentation, remove exter (*) 07cdba6... Fix points-to SCC collapsing bug (*) f9fbb47... tree-optimization/115220 - fix store sinking virtual operan (*) f6c5f83... Define which threading model is in use on Windows (*) 311d7f5... tree-optimization/115232 - demangle failure during -Waccess (*) 88c9b96... Add testcase for PR c++/105229: ICE in lookup_template_clas (*) 6e97482... doc: Use https for our own site (and GCC for the project) (*) 06bb125... RISC-V: Fix missing boolean_expression in zmmul extension (*) 314448f... VAX/doc: Fix issues with FP format option documentation (*) a7f6543... vax: Fix descriptions of the FP format options [PR79646] (*) 1609294... [to-be-committed][RISC-V] Reassociate constants in logical (*) 0022064... x86: Fix Logical Shift Issue in expand_vec_perm_psrlw_psllw (*) 5d99cf7... Gen-Match: Fix gen_kids_1 right hand braces mis-alignment (*) 56d0d0d... Daily bump. (*) 3a915d6... [to-be-committed] [RISC-V] Try inverting for constant synth (*) a06df66... go: Move web references from golang.org to go.dev. (*) 53d9198... doc: Quote singular '=' signs (*) 9566022... [to-be-committed][RISC-V] Generate nearby constant, then ad (*) 8746373... [PATCH] libcpp: Correct typo 'r' -> '\r' (*) f981072... Delete gori_map during destruction of GORI. (*) 3c7ae57... Daily bump. (*) 05daf61... [committed] [v2] More logical op simplifications in simplif (*) 28b5082...
[gcc/aoliva/heads/testbase] (71 commits) Align tight loop without considering max skipping bytes
The branch 'aoliva/heads/testbase' was updated to point to: b644126237a... Align tight loop without considering max skipping bytes It previously pointed to: 7acd5d71547... testsuite: adjust iteration count for ppc costmodel 76b Diff: Summary of changes (added commits): --- b644126... Align tight loop without considering max skipping bytes (*) 00ed542... Adjust generic loop alignment from 16:11:8 to 16 for Intel (*) d9933e8... testsuite, rs6000: Replace powerpc_vsx_ok with powerpc_vsx (*) a19f588... Gori_on_edge tweaks. (*) e5fc5d4... rs6000: Don't clobber return value when eh_return called [P (*) 2b84169... Daily bump. (*) 1d6199e... Reduce cost of MEM (A + imm). (*) 6f36cc2... More tweaks from gimple_outgoing_range changes. (*) 802a98d... resource.cc: Remove redundant conditionals (*) e1abce5... resource.cc (mark_target_live_regs): Remove check for bb no (*) 933ab59... resource.cc: Replace calls to find_basic_block with cfgrtl (*) 84b4ed4... resource.cc (mark_target_live_regs): Don't look past target (*) 91d7905... i386: Improve access to _Atomic DImode location via XMM reg (*) 21fc89b... diagnostics: consolidate global state in diagnostic-color.c (*) 9bda2c4... libcpp: move label_text to its own header (*) fb7a943... selftests: split out make_fndecl from selftest.h to its own (*) 7cc529f... regenerate-opt-urls.py: fix transposed values for "vax" and (*) efaaae4... c++: extend -Wself-move for mem-init-list [PR109396] (*) 5ada486... Do not invoke SCEV if it will use a different range query. (*) d52b44a... Strlen pass should set current range query. (*) 5bc731b... c++: mark TARGET_EXPRs for function arguments eliding [PR11 (*) c0d7828... testsuite/*/gomp: Remove 'dg-prune-output "not supported ye (*) 2dbb1c1... diagnostics: disable localization of events in selftest pat (*) b544ff8... Fix bootstrap on AIX by adding c-family/c-type-mismatch.cc (*) 2361160... [to-be-committed] [RISC-V] Some basic patterns for zbkb cod (*) a3aeff4... vect: Use vect representative statement instead of original (*) d8d70b7... target/115254 - fix gcc.dg/vect/vect-gather-4.c dump scanni (*) c08b0d3... tree-optimization/115236 - more points-to *ANYTHING = x fix (*) 19cc611... Avoid pessimistic constraints for asm memory constraints (*) eaaa4b8... tree-optimization/115254 - don't account single-lane SLP ag (*) 65aa46f... Fix SLP reduction neutral op value for pointer reductions (*) c650023... Fix predicate mismatch between vfcmaddcph's define_insn and (*) ded91d8... LoongArch: Guard REGNO with REG_P in loongarch_expand_condi (*) 4fcdc37... Fix bitops-9.c for -m32 and other targets that don't have v (*) 958a682... Daily bump. (*) c5a7628... match: Use uniform_integer_cst_p in bitwise_inverted_equal_ (*) a209f21... modula2: simplify xref usage in documentation, remove exter (*) 07cdba6... Fix points-to SCC collapsing bug (*) f9fbb47... tree-optimization/115220 - fix store sinking virtual operan (*) f6c5f83... Define which threading model is in use on Windows (*) 311d7f5... tree-optimization/115232 - demangle failure during -Waccess (*) 88c9b96... Add testcase for PR c++/105229: ICE in lookup_template_clas (*) 6e97482... doc: Use https for our own site (and GCC for the project) (*) 06bb125... RISC-V: Fix missing boolean_expression in zmmul extension (*) 314448f... VAX/doc: Fix issues with FP format option documentation (*) a7f6543... vax: Fix descriptions of the FP format options [PR79646] (*) 1609294... [to-be-committed][RISC-V] Reassociate constants in logical (*) 0022064... x86: Fix Logical Shift Issue in expand_vec_perm_psrlw_psllw (*) 5d99cf7... Gen-Match: Fix gen_kids_1 right hand braces mis-alignment (*) 56d0d0d... Daily bump. (*) 3a915d6... [to-be-committed] [RISC-V] Try inverting for constant synth (*) a06df66... go: Move web references from golang.org to go.dev. (*) 53d9198... doc: Quote singular '=' signs (*) 9566022... [to-be-committed][RISC-V] Generate nearby constant, then ad (*) 8746373... [PATCH] libcpp: Correct typo 'r' -> '\r' (*) f981072... Delete gori_map during destruction of GORI. (*) 3c7ae57... Daily bump. (*) 05daf61... [committed] [v2] More logical op simplifications in simplif (*) 28b5082... c++/modules: Improve diagnostic when redeclaring builtin in (*) 6c0b7e1... Daily bump. (*) 9561cf5... Fortran: improve attribute conflict checking [PR93635] (*) 9376573... Fortran: fix bounds check for assignment, class component [ (*) 73eef7a... Small enhancement to implementation of -fdump-ada-spec (*) 9f1798c... c: Fix for some variably modified types not being recognize (*) dae606a... c++/modules: Improve errors for bad module-directives [PR11 (*) 03531ec... c++/modules: Remember that header units have CMIs (*) 0173dcc... c++/modules: Fix treatment of unnamed types (*) 401994d... [to-be-committed,v2,RISC-V] Use bclri in constant synthesis
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:ca809ee3fbe8a5d383c2438c123d72dbbba7f48a
commit ca809ee3fbe8a5d383c2438c123d72dbbba7f48a
Author: Alexandre Oliva
Date: Wed May 29 02:52:18 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 3 +--
7 files changed, 9 insertions(+), 16 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..e69d9253e2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,12 +13,11 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlfdx\M|\mlfd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfdx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index f7c06e96109..ab03cd8adb0 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,13 +12,12 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* -m32 has lfs in place of lfsx */
-/* { dg-final { scan-assembler-times {\mlfsx\M|\mlfs\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfsx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index 6819d271c53..ce435d82c16 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -24,9 +24,8 @@
/* { dg-final { scan-assembler-times {\mli\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mrlwinm\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 51636926953..20e3d253489 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++
[gcc(refs/users/aoliva/heads/testme)] [tree-prof] skip if errors were seen [PR113681]
https://gcc.gnu.org/g:1c340408045fdf647edca445e40a75b09bce7493
commit 1c340408045fdf647edca445e40a75b09bce7493
Author: Alexandre Oliva
Date: Wed May 29 02:52:23 2024 -0300
[tree-prof] skip if errors were seen [PR113681]
ipa_tree_profile asserts that the symtab is in IPA_SSA state, but we
don't reach that state and ICE if e.g. ipa-strub passes report errors.
Skip this pass if errors were seen.
for gcc/ChangeLog
PR tree-optimization/113681
* tree-profiling.cc (pass_ipa_tree_profile::gate): Skip if
seen_errors.
for gcc/testsuite/ChangeLog
PR tree-optimization/113681
* c-c++-common/strub-pr113681.c: New.
Diff:
---
gcc/testsuite/c-c++-common/strub-pr113681.c | 22 ++
gcc/tree-profile.cc | 3 ++-
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/c-c++-common/strub-pr113681.c
b/gcc/testsuite/c-c++-common/strub-pr113681.c
new file mode 100644
index 000..3ef9017b2eb
--- /dev/null
+++ b/gcc/testsuite/c-c++-common/strub-pr113681.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-fstrub=relaxed -fbranch-probabilities" } */
+/* { dg-require-effective-target strub } */
+
+/* Same as torture/strub-inlineable1.c, but with -fbranch-probabilities, to
+ check that IPA tree-profiling won't ICE. It would when we refrained from
+ running passes that would take it to IPA_SSA, but ran the pass that asserted
+ for IPA_SSA. */
+
+inline void __attribute__ ((strub ("internal"), always_inline))
+inl_int_ali (void)
+{
+ /* No internal wrapper, so this body ALWAYS gets inlined,
+ but it cannot be called from non-strub contexts. */
+}
+
+void
+bat (void)
+{
+ /* Not allowed, not a strub context. */
+ inl_int_ali (); /* { dg-error "context" } */
+}
diff --git a/gcc/tree-profile.cc b/gcc/tree-profile.cc
index b87c121790c..e4bb689cef5 100644
--- a/gcc/tree-profile.cc
+++ b/gcc/tree-profile.cc
@@ -2070,7 +2070,8 @@ pass_ipa_tree_profile::gate (function *)
disabled. */
return (!in_lto_p && !flag_auto_profile
&& (flag_branch_probabilities || flag_test_coverage
- || profile_arc_flag || condition_coverage_flag));
+ || profile_arc_flag || condition_coverage_flag)
+ && !seen_error ());
}
} // anon namespace
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [arm] add effective target and options for pacbti tests
https://gcc.gnu.org/g:1b22d42a6624285073f3ef6309af74046fa875e4
commit 1b22d42a6624285073f3ef6309af74046fa875e4
Author: Alexandre Oliva
Date: Wed May 29 02:52:20 2024 -0300
[testsuite] [arm] add effective target and options for pacbti tests
arm pac and bti tests that use -march=armv8.1-m.main get an implicit
-mthumb, that is incompatible with vxworks kernel mode. Declaring the
requirement for a 8.1-m.main-compatible toolchain is enough to avoid
those fails, because the toolchain feature test fails in kernel mode,
but taking the -march options from the standardized arch tests, after
testing for support for the corresponding effective target, makes it
generally safer, and enables us to drop skip directives and extraneous
option variants.
for gcc/testsuite/ChangeLog
* gcc.target/arm/bti-1.c: Require arch, use its opts, drop skip.
* gcc.target/arm/bti-2.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-11.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-12.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.
* g++.target/arm/pac-1.C: Likewise. Drop +mve.
Diff:
---
gcc/testsuite/g++.target/arm/pac-1.C | 5 +++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c | 4 ++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c | 5 +++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c | 5 +++--
gcc/testsuite/gcc.target/arm/bti-1.c | 5 +++--
gcc/testsuite/gcc.target/arm/bti-2.c | 5 +++--
6 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/gcc/testsuite/g++.target/arm/pac-1.C
b/gcc/testsuite/g++.target/arm/pac-1.C
index f671a27b048..ac15ae18197 100644
--- a/gcc/testsuite/g++.target/arm/pac-1.C
+++ b/gcc/testsuite/g++.target/arm/pac-1.C
@@ -1,7 +1,8 @@
/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE
pseudo hard-register. */
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret
-mthumb -mfloat-abi=hard -g -O0" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
+/* { dg-additional-options "-mbranch-protection=pac-ret -mfloat-abi=hard -g
-O0" } */
__attribute__((noinline)) void
fn1 (int a, int b, int c)
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
index 6a5ae92c567..c9c40f44027 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" "-mfloat-abi=*" } } */
-/* { dg-options "-march=armv8.1-m.main+fp+pacbti" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
#if (__ARM_FEATURE_BTI != 1)
#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined to 1."
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
index db40b17c3b0..c26051347a2 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8-m.main+fp -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */
+/* { dg-add-options arm_arch_v8_1m_main } */
+/* { dg-additional-options "-mfloat-abi=softfp" } */
#if defined (__ARM_FEATURE_BTI)
#error "Feature test macro __ARM_FEATURE_BTI should not be defined."
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
index 1b25907635e..92f500c1449 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-additional-options "-march=armv8.1-m.main+pacbti+fp --save-temps
-mfloat-abi=hard" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
+/* { dg-additional-options "--save-temps -mfloat-abi=hard" } */
#if defined (__ARM_FEATURE_BTI_DEFAULT)
#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be undefined."
diff --git a/gcc/testsuite/gcc.target/arm/bti-1.c
b/gcc/testsuite/gcc.target/arm/bti-1.c
index 79dd8010d2d..a34bb0842b6 100644
--- a/gcc/testsuite/gcc.target/arm/bti-1.c
+++
[gcc(refs/users/aoliva/heads/testme)] [rs6000] adjust return_pc debug attrs
https://gcc.gnu.org/g:0bb10f149bfcbe874d348814c623b36e9232cb3f
commit 0bb10f149bfcbe874d348814c623b36e9232cb3f
Author: Alexandre Oliva
Date: Wed May 29 02:52:10 2024 -0300
[rs6000] adjust return_pc debug attrs
Some of the rs6000 call patterns, on some ABIs, issue multiple opcodes
out of a single call insn, but the call (bl) or jump (b) is not always
the last opcode in the sequence.
This does not seem to be a problem for exception handling tables, but
the return_pc attribute in the call graph output in dwarf2+ debug
information, that takes the address of a label output right after the
call, does not match the value of the link register even for non-tail
calls. E.g., with ABI_AIX or ABI_ELFv2, such code as:
foo ();
outputs:
bl foo
nop
LVL#:
[...]
.8byte .LVL# # DW_AT_call_return_pc
but debug info consumers may rely on the return_pc address, and draw
incorrect conclusions from its off-by-4 value.
This patch uses the infrastructure for targets to add an offset to the
label issued after the call_insn to set the call_return_pc attribute,
on rs6000, to account for opcodes issued after actual call opcode as
part of call insns output patterns.
for gcc/ChangeLog
* config/rs6000/rs6000.cc (TARGET_CALL_OFFSET_RETURN_LABEL):
Override.
(rs6000_call_offset_return_label): New.
Diff:
---
gcc/config/rs6000/rs6000.cc | 18 ++
1 file changed, 18 insertions(+)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index e4dc629ddcc..77e6b94a539 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1779,6 +1779,8 @@ static const scoped_attribute_specs *const
rs6000_attribute_table[] =
#undef TARGET_OVERLAP_OP_BY_PIECES_P
#define TARGET_OVERLAP_OP_BY_PIECES_P hook_bool_void_true
+#undef TARGET_CALL_OFFSET_RETURN_LABEL
+#define TARGET_CALL_OFFSET_RETURN_LABEL rs6000_call_offset_return_label
/* Processor table. */
@@ -14822,6 +14824,22 @@ rs6000_assemble_integer (rtx x, unsigned int size, int
aligned_p)
return default_assemble_integer (x, size, aligned_p);
}
+/* Return the offset to be added to the label output after CALL_INSN
+ to compute the address to be placed in DW_AT_call_return_pc. */
+
+static int
+rs6000_call_offset_return_label (rtx_insn *call_insn)
+{
+ /* All rs6000 CALL_INSN output patterns start with a b or bl, always
+ a 4-byte instruction, but some output patterns issue other
+ opcodes afterwards. The return label is issued after the entire
+ call insn, including any such post-call opcodes. Instead of
+ figuring out which cases need adjustments, we compute the offset
+ back to the address of the call opcode proper, then add the
+ constant 4 bytes, to get the address after that opcode. */
+ return 4 - get_attr_length (call_insn);
+}
+
/* Return a template string for assembly to emit when making an
external call. FUNOP is the call mem argument operand number. */
[gcc(refs/users/aoliva/heads/testme)] enable adjustment of return_pc debug attrs
https://gcc.gnu.org/g:99047b701feb580e047a1b13bdf85a7fd21224e2
commit 99047b701feb580e047a1b13bdf85a7fd21224e2
Author: Alexandre Oliva
Date: Wed May 29 02:52:07 2024 -0300
enable adjustment of return_pc debug attrs
This patch introduces infrastructure for targets to add an offset to
the label issued after the call_insn to set the call_return_pc
attribute. This will be used on rs6000, that sometimes issues another
instruction after the call proper as part of a call insn.
for gcc/ChangeLog
* target.def (call_offset_return_label): New hook.
* gcc/doc/tm.texi.in (TARGET_CALL_OFFSET_RETURN_LABEL): Add
placeholder.
* gcc/doc/tm.texi: Rebuild.
* dwarf2out.cc (struct call_arg_loc_node): Record call_insn
instad of call_arg_loc_note.
(add_AT_lbl_id): Add optional offset argument.
(gen_call_site_die): Compute and pass on a return pc offset.
(gen_subprogram_die): Move call_arg_loc_note computation...
(dwarf2out_var_location): ... from here. Set call_insn.
Diff:
---
gcc/doc/tm.texi| 7 +++
gcc/doc/tm.texi.in | 2 ++
gcc/dwarf2out.cc | 26 +-
gcc/target.def | 9 +
4 files changed, 35 insertions(+), 9 deletions(-)
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index cd50078227d..8a7aa70d605 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -5557,6 +5557,13 @@ except the last are treated as named.
You need not define this hook if it always returns @code{false}.
@end deftypefn
+@deftypefn {Target Hook} int TARGET_CALL_OFFSET_RETURN_LABEL (rtx_insn
*@var{call_insn})
+While generating call-site debug info for a CALL insn, or a SEQUENCE
+insn starting with a CALL, this target hook is invoked to compute the
+offset to be added to the debug label emitted after the call to obtain
+the return address that should be recorded as the return PC.
+@end deftypefn
+
@deftypefn {Target Hook} void TARGET_START_CALL_ARGS (cumulative_args_t
@var{complete_args})
This target hook is invoked while generating RTL for a function call,
after the argument values have been computed, and after stack arguments
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 058bd56487a..9e0830758ae 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -3887,6 +3887,8 @@ These machine description macros help implement varargs:
@hook TARGET_STRICT_ARGUMENT_NAMING
+@hook TARGET_CALL_OFFSET_RETURN_LABEL
+
@hook TARGET_START_CALL_ARGS
@hook TARGET_CALL_ARGS
diff --git a/gcc/dwarf2out.cc b/gcc/dwarf2out.cc
index 5b064ffd78a..1092880738d 100644
--- a/gcc/dwarf2out.cc
+++ b/gcc/dwarf2out.cc
@@ -3593,7 +3593,7 @@ typedef struct var_loc_list_def var_loc_list;
/* Call argument location list. */
struct GTY ((chain_next ("%h.next"))) call_arg_loc_node {
- rtx GTY (()) call_arg_loc_note;
+ rtx_insn * GTY (()) call_insn;
const char * GTY (()) label;
tree GTY (()) block;
bool tail_call_p;
@@ -3777,7 +3777,8 @@ static void remove_addr_table_entry (addr_table_entry *);
static void add_AT_addr (dw_die_ref, enum dwarf_attribute, rtx, bool);
static inline rtx AT_addr (dw_attr_node *);
static void add_AT_symview (dw_die_ref, enum dwarf_attribute, const char *);
-static void add_AT_lbl_id (dw_die_ref, enum dwarf_attribute, const char *);
+static void add_AT_lbl_id (dw_die_ref, enum dwarf_attribute, const char *,
+ int = 0);
static void add_AT_lineptr (dw_die_ref, enum dwarf_attribute, const char *);
static void add_AT_macptr (dw_die_ref, enum dwarf_attribute, const char *);
static void add_AT_range_list (dw_die_ref, enum dwarf_attribute,
@@ -5353,14 +5354,17 @@ add_AT_symview (dw_die_ref die, enum dwarf_attribute
attr_kind,
static inline void
add_AT_lbl_id (dw_die_ref die, enum dwarf_attribute attr_kind,
- const char *lbl_id)
+ const char *lbl_id, int offset)
{
dw_attr_node attr;
attr.dw_attr = attr_kind;
attr.dw_attr_val.val_class = dw_val_class_lbl_id;
attr.dw_attr_val.val_entry = NULL;
- attr.dw_attr_val.v.val_lbl_id = xstrdup (lbl_id);
+ if (!offset)
+attr.dw_attr_val.v.val_lbl_id = xstrdup (lbl_id);
+ else
+attr.dw_attr_val.v.val_lbl_id = xasprintf ("%s%+i", lbl_id, offset);
if (dwarf_split_debug_info)
attr.dw_attr_val.val_entry
= add_addr_table_entry (attr.dw_attr_val.v.val_lbl_id,
@@ -23515,7 +23519,9 @@ gen_call_site_die (tree decl, dw_die_ref subr_die,
if (stmt_die == NULL)
stmt_die = subr_die;
die = new_die (dwarf_TAG (DW_TAG_call_site), stmt_die, NULL_TREE);
- add_AT_lbl_id (die, dwarf_AT (DW_AT_call_return_pc), ca_loc->label);
+ add_AT_lbl_id (die, dwarf_AT (DW_AT_call_return_pc),
+ca_loc->label,
+targetm.calls.call_offset_return_label (ca_loc->call_insn));
if (ca_loc->tail_call_p)
add_AT_flag (die, dwarf_AT (DW_AT_call_tail_call), 1);
if
[gcc(refs/users/aoliva/heads/testme)] [rs6000] adjust return_pc debug attrs
https://gcc.gnu.org/g:3bcf4294d8937a47886d2694a5888006f5d82741
commit 3bcf4294d8937a47886d2694a5888006f5d82741
Author: Alexandre Oliva
Date: Fri Apr 14 23:53:35 2023 -0300
[rs6000] adjust return_pc debug attrs
Some of the rs6000 call patterns, on some ABIs, issue multiple opcodes
out of a single call insn, but the call (bl) or jump (b) is not always
the last opcode in the sequence.
This does not seem to be a problem for exception handling tables, but
the return_pc attribute in the call graph output in dwarf2+ debug
information, that takes the address of a label output right after the
call, does not match the value of the link register even for non-tail
calls. E.g., with ABI_AIX or ABI_ELFv2, such code as:
foo ();
outputs:
bl foo
nop
LVL#:
[...]
.8byte .LVL# # DW_AT_call_return_pc
but debug info consumers may rely on the return_pc address, and draw
incorrect conclusions from its off-by-4 value.
This patch uses the infrastructure for targets to add an offset to the
label issued after the call_insn to set the call_return_pc attribute,
on rs6000, to account for opcodes issued after actual call opcode as
part of call insns output patterns.
for gcc/ChangeLog
* config/rs6000/rs6000.cc (TARGET_CALL_OFFSET_RETURN_LABEL):
Override.
(rs6000_call_offset_return_label): New.
Diff:
---
gcc/config/rs6000/rs6000.cc | 18 ++
1 file changed, 18 insertions(+)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index e4dc629ddcc..77e6b94a539 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1779,6 +1779,8 @@ static const scoped_attribute_specs *const
rs6000_attribute_table[] =
#undef TARGET_OVERLAP_OP_BY_PIECES_P
#define TARGET_OVERLAP_OP_BY_PIECES_P hook_bool_void_true
+#undef TARGET_CALL_OFFSET_RETURN_LABEL
+#define TARGET_CALL_OFFSET_RETURN_LABEL rs6000_call_offset_return_label
/* Processor table. */
@@ -14822,6 +14824,22 @@ rs6000_assemble_integer (rtx x, unsigned int size, int
aligned_p)
return default_assemble_integer (x, size, aligned_p);
}
+/* Return the offset to be added to the label output after CALL_INSN
+ to compute the address to be placed in DW_AT_call_return_pc. */
+
+static int
+rs6000_call_offset_return_label (rtx_insn *call_insn)
+{
+ /* All rs6000 CALL_INSN output patterns start with a b or bl, always
+ a 4-byte instruction, but some output patterns issue other
+ opcodes afterwards. The return label is issued after the entire
+ call insn, including any such post-call opcodes. Instead of
+ figuring out which cases need adjustments, we compute the offset
+ back to the address of the call opcode proper, then add the
+ constant 4 bytes, to get the address after that opcode. */
+ return 4 - get_attr_length (call_insn);
+}
+
/* Return a template string for assembly to emit when making an
external call. FUNOP is the call mem argument operand number. */
[gcc(refs/users/aoliva/heads/testme)] enable adjustment of return_pc debug attrs
https://gcc.gnu.org/g:a56062c190d0324f8b84be3705fee494be390894
commit a56062c190d0324f8b84be3705fee494be390894
Author: Alexandre Oliva
Date: Fri Apr 14 23:53:34 2023 -0300
enable adjustment of return_pc debug attrs
This patch introduces infrastructure for targets to add an offset to
the label issued after the call_insn to set the call_return_pc
attribute. This will be used on rs6000, that sometimes issues another
instruction after the call proper as part of a call insn.
for gcc/ChangeLog
* target.def (call_offset_return_label): New hook.
* gcc/doc/tm.texi.in (TARGET_CALL_OFFSET_RETURN_LABEL): Add
placeholder.
* gcc/doc/tm.texi: Rebuild.
* dwarf2out.cc (struct call_arg_loc_node): Record call_insn
instad of call_arg_loc_note.
(add_AT_lbl_id): Add optional offset argument.
(gen_call_site_die): Compute and pass on a return pc offset.
(gen_subprogram_die): Move call_arg_loc_note computation...
(dwarf2out_var_location): ... from here. Set call_insn.
Diff:
---
gcc/doc/tm.texi| 7 +++
gcc/doc/tm.texi.in | 2 ++
gcc/dwarf2out.cc | 26 +-
gcc/target.def | 9 +
4 files changed, 35 insertions(+), 9 deletions(-)
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index cd50078227d..8a7aa70d605 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -5557,6 +5557,13 @@ except the last are treated as named.
You need not define this hook if it always returns @code{false}.
@end deftypefn
+@deftypefn {Target Hook} int TARGET_CALL_OFFSET_RETURN_LABEL (rtx_insn
*@var{call_insn})
+While generating call-site debug info for a CALL insn, or a SEQUENCE
+insn starting with a CALL, this target hook is invoked to compute the
+offset to be added to the debug label emitted after the call to obtain
+the return address that should be recorded as the return PC.
+@end deftypefn
+
@deftypefn {Target Hook} void TARGET_START_CALL_ARGS (cumulative_args_t
@var{complete_args})
This target hook is invoked while generating RTL for a function call,
after the argument values have been computed, and after stack arguments
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 058bd56487a..9e0830758ae 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -3887,6 +3887,8 @@ These machine description macros help implement varargs:
@hook TARGET_STRICT_ARGUMENT_NAMING
+@hook TARGET_CALL_OFFSET_RETURN_LABEL
+
@hook TARGET_START_CALL_ARGS
@hook TARGET_CALL_ARGS
diff --git a/gcc/dwarf2out.cc b/gcc/dwarf2out.cc
index 5b064ffd78a..1092880738d 100644
--- a/gcc/dwarf2out.cc
+++ b/gcc/dwarf2out.cc
@@ -3593,7 +3593,7 @@ typedef struct var_loc_list_def var_loc_list;
/* Call argument location list. */
struct GTY ((chain_next ("%h.next"))) call_arg_loc_node {
- rtx GTY (()) call_arg_loc_note;
+ rtx_insn * GTY (()) call_insn;
const char * GTY (()) label;
tree GTY (()) block;
bool tail_call_p;
@@ -3777,7 +3777,8 @@ static void remove_addr_table_entry (addr_table_entry *);
static void add_AT_addr (dw_die_ref, enum dwarf_attribute, rtx, bool);
static inline rtx AT_addr (dw_attr_node *);
static void add_AT_symview (dw_die_ref, enum dwarf_attribute, const char *);
-static void add_AT_lbl_id (dw_die_ref, enum dwarf_attribute, const char *);
+static void add_AT_lbl_id (dw_die_ref, enum dwarf_attribute, const char *,
+ int = 0);
static void add_AT_lineptr (dw_die_ref, enum dwarf_attribute, const char *);
static void add_AT_macptr (dw_die_ref, enum dwarf_attribute, const char *);
static void add_AT_range_list (dw_die_ref, enum dwarf_attribute,
@@ -5353,14 +5354,17 @@ add_AT_symview (dw_die_ref die, enum dwarf_attribute
attr_kind,
static inline void
add_AT_lbl_id (dw_die_ref die, enum dwarf_attribute attr_kind,
- const char *lbl_id)
+ const char *lbl_id, int offset)
{
dw_attr_node attr;
attr.dw_attr = attr_kind;
attr.dw_attr_val.val_class = dw_val_class_lbl_id;
attr.dw_attr_val.val_entry = NULL;
- attr.dw_attr_val.v.val_lbl_id = xstrdup (lbl_id);
+ if (!offset)
+attr.dw_attr_val.v.val_lbl_id = xstrdup (lbl_id);
+ else
+attr.dw_attr_val.v.val_lbl_id = xasprintf ("%s%+i", lbl_id, offset);
if (dwarf_split_debug_info)
attr.dw_attr_val.val_entry
= add_addr_table_entry (attr.dw_attr_val.v.val_lbl_id,
@@ -23515,7 +23519,9 @@ gen_call_site_die (tree decl, dw_die_ref subr_die,
if (stmt_die == NULL)
stmt_die = subr_die;
die = new_die (dwarf_TAG (DW_TAG_call_site), stmt_die, NULL_TREE);
- add_AT_lbl_id (die, dwarf_AT (DW_AT_call_return_pc), ca_loc->label);
+ add_AT_lbl_id (die, dwarf_AT (DW_AT_call_return_pc),
+ca_loc->label,
+targetm.calls.call_offset_return_label (ca_loc->call_insn));
if (ca_loc->tail_call_p)
add_AT_flag (die, dwarf_AT (DW_AT_call_tail_call), 1);
if
[gcc/aoliva/heads/testme] (2 commits) [rs6000] adjust return_pc debug attrs
The branch 'aoliva/heads/testme' was updated to point to: 3bcf4294d89... [rs6000] adjust return_pc debug attrs It previously pointed to: 3612317409b... Introduce attribute sym_alias Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 3612317... Introduce attribute sym_alias Summary of changes (added commits): --- 3bcf429... [rs6000] adjust return_pc debug attrs a56062c... enable adjustment of return_pc debug attrs
[gcc(refs/users/aoliva/heads/testme)] Introduce attribute sym_alias
https://gcc.gnu.org/g:3612317409b4c0ec201d7f536638015872ffbc8d commit 3612317409b4c0ec201d7f536638015872ffbc8d Author: Alexandre Oliva Date: Thu Dec 14 03:21:21 2023 -0300 Introduce attribute sym_alias This patch introduces an attribute to add extra asm names (aliases) for a decl when its definition is output. The main goal is to ease interfacing C++ with Ada, as C++ mangled names have to be named, and in some cases (e.g. when using stdint.h typedefs in function arguments) the symbol names may vary across platforms. The attribute is usable in C and C++, presumably in all C-family languages. It can be attached to global variables and functions, and also to local static variables. In C++, it can also be attached to class types, namespace-scoped variables and functions, static data members, member functions, explicit instantiations and specializations of template functions, members and classes. When applied to constructors or destructor, additional sym aliases with _Base and _Del suffixes are defined for variants other than complete-object ones. This changes the assumption that clones always carry the same attributes as their abstract declarations, so there is now a function to adjust them. C++ also had a bug in which attributes from local extern declarations failed to be propagated to a preexisting corresponding namespace-scoped decl. I've fixed that, and adjusted acc tests that distinguished between C and C++ in this regard. Applying the attribute to class types is only valid in C++, and the effect is to attach the alias to the RTTI object associated with the class type. for gcc/ChangeLog * attribs.cc: Include cgraph.h. (decl_attributes): Allow late introduction of sym_alias in types. (create_sym_alias_decl, create_sym_alias_decls): New. * attribs.h: Declare them. (FOR_EACH_SYM_ALIAS): New macro. * cgraph.cc (cgraph_node::create): Create sym_alias decls. * varpool.cc (varpool_node::get_create): Create sym_alias decls. * cgraph.h (symtab_node::remap_sym_alias_target): New. * symtab.cc (symtab_node::remap_sym_alias_target): Define. (symbol_table::insert_to_assembler_name_hash): Check for symbol name clashes. (symtab_node::noninterposable_alias): Drop sym_alias attributes. * cgraphunit.cc (cgraph_node::analyze): Create alias_target node if needed. (analyze_functions): Fixup visibility of implicit alias only after its node is analyzed. * doc/extend.texi (sym_alias): Document for variables, functions and types. for gcc/ada/ChangeLog * doc/gnat_rm/interfacing_to_other_languages.rst: Mention attribute sym_alias to give RTTI symbols mnemonic names. * doc/gnat_ugn/the_gnat_compilation_model.rst: Mention aliases. Fix incorrect ref to C1 ctor variant. for gcc/c-family/ChangeLog * c-ada-spec.cc (pp_asm_name): Use first sym_alias if available. * c-attribs.cc (handle_sym_alias_attribute): New. (c_common_attribute_table): Add sym_alias. (handle_copy_attribute): Do not copy sym_alias attribute. for gcc/c/ChangeLog * c-decl.cc (duplicate_decls): Remap sym_alias target. (finish_decl): Create varpool_node for local static variables. for gcc/cp/ChangeLog * class.cc (adjust_clone_attributes): New. (copy_fndecl_with_name, build_clone): Call it. * cp-tree.h (adjust_clone_attributes): Declare. (update_sym_alias_interface): Declare. (update_tinfo_sym_alias): Declare. * decl.cc (duplicate_decls): Remap sym_alias target. Adjust clone attributes. (grokfndecl): Tentatively create sym_alias decls after adding attributes in e.g. a template member function explicit instantiation. * decl2.cc (cplus_decl_attributes): Update tinfo sym_alias. (copy_interface, update_sym_alias_interface): New. (determine_visibility): Update sym_alias interface. (tentative_decl_linkage, import_export_decl): Likewise. * name-lookup.cc: Include target.h and cgraph.h. (push_local_extern_decl_alias): Merge attributes with namespace-scoped decl, and drop duplicate sym_alias. * optimize.cc (maybe_clone_body): Re-adjust attributes after cloning them. Update sym_alias interface. * rtti.cc: Include attribs.h and cgraph.h. (get_tinfo_decl): Copy sym_alias attributes from type to tinfo decl. Create sym_alias
[gcc/aoliva/heads/testme] (32 commits) Introduce attribute sym_alias
The branch 'aoliva/heads/testme' was updated to point to: 3612317409b... Introduce attribute sym_alias It previously pointed to: 8cc56a8291a... testsuite: adjust iteration count for ppc costmodel 76b Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 8cc56a8... testsuite: adjust iteration count for ppc costmodel 76b 0c3019c... [testsuite] conditionalize dg-additional-sources on target Summary of changes (added commits): --- 3612317... Introduce attribute sym_alias 7acd5d7... testsuite: adjust iteration count for ppc costmodel 76b (*) 85e2ce1... Fix gcc.dg/vect/vect-gather-4.c for cascadelake (*) 5b9b3ba... tree-optimization/115144 - improve sinking destination choi (*) 51f4b47... Fix typo in the testcase. (*) 3e06763... Use simple_dce_from_worklist in phiprop (*) c71886f... Avoid splitting store dataref groups during SLP discovery (*) ee49210... Daily bump. (*) 7fa0ffa... c++/modules: Ensure all partial specialisations are tracked (*) 66d2a76... libstdc++: Implement ranges::concat_view from P2542R7 (*) 83bb9ad... Move condexpr_adjust into gimple-range-fold (*) fae5e6a... Make gori_map a shared component. (*) ac0bc89... Make GORI a range_query component. (*) 44db939... Gori_compute inherits from gimple_outgoing_range. (*) a049f08... Gori_compute no longer inherits from gori_map. (*) 7615363... Default gimple_outgoing_range to not process switches. (*) efc4255... Add inferred ranges for range-ops based statements. (*) 07441e4... Move infer_manager to a range_query oracle. (*) 6c64a85... Allow components to be shared among range-queries. (*) fca649d... Rename relation oracle and API. (*) 3be530f... Move to an always available relation oracle. (*) 67afcf2... Move all relation queries into relation_oracle. (*) ed63cd2... c++: deleting array temporary [PR115187] (*) 0b3b6a8... Another small fix to implementation of -fdump-ada-spec (*) dca3e6b... Match: Add overloaded types_match to avoid code dup [NFC] (*) 2b2476d... tree-optimization/115197 - fix ICE w/ constant in LC PHI an (*) f0a0246... tree-optimization/115199 - fix PTA constraint processing fo (*) 61f5b3c... tree-optimization/115138 - ptr-vs-ptr and FUNCTION_DECLs (*) 4efa7ec... missing require target has_arch_ppc64 for pr106550.c (*) fc5e109... testsuite: vect: Fix gcc.dg/vect/vect-pr111779.c on SPARC [ (*) 2ce9051... Fortran: Fix ICEs due to comp calls in initialization exprs (*) 57e0487... s390: Implement TARGET_NOCE_CONVERSION_PROFITABLE_P [PR1095 (*) (*) This commit already exists in another branch. Because the reference `refs/users/aoliva/heads/testme' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc/aoliva/heads/testbase] (31 commits) testsuite: adjust iteration count for ppc costmodel 76b
The branch 'aoliva/heads/testbase' was updated to point to: 7acd5d71547... testsuite: adjust iteration count for ppc costmodel 76b It previously pointed to: dbdddc92a3b... [testsuite] xfail pr79004 on longdouble64; drop long_double Diff: Summary of changes (added commits): --- 7acd5d7... testsuite: adjust iteration count for ppc costmodel 76b (*) 85e2ce1... Fix gcc.dg/vect/vect-gather-4.c for cascadelake (*) 5b9b3ba... tree-optimization/115144 - improve sinking destination choi (*) 51f4b47... Fix typo in the testcase. (*) 3e06763... Use simple_dce_from_worklist in phiprop (*) c71886f... Avoid splitting store dataref groups during SLP discovery (*) ee49210... Daily bump. (*) 7fa0ffa... c++/modules: Ensure all partial specialisations are tracked (*) 66d2a76... libstdc++: Implement ranges::concat_view from P2542R7 (*) 83bb9ad... Move condexpr_adjust into gimple-range-fold (*) fae5e6a... Make gori_map a shared component. (*) ac0bc89... Make GORI a range_query component. (*) 44db939... Gori_compute inherits from gimple_outgoing_range. (*) a049f08... Gori_compute no longer inherits from gori_map. (*) 7615363... Default gimple_outgoing_range to not process switches. (*) efc4255... Add inferred ranges for range-ops based statements. (*) 07441e4... Move infer_manager to a range_query oracle. (*) 6c64a85... Allow components to be shared among range-queries. (*) fca649d... Rename relation oracle and API. (*) 3be530f... Move to an always available relation oracle. (*) 67afcf2... Move all relation queries into relation_oracle. (*) ed63cd2... c++: deleting array temporary [PR115187] (*) 0b3b6a8... Another small fix to implementation of -fdump-ada-spec (*) dca3e6b... Match: Add overloaded types_match to avoid code dup [NFC] (*) 2b2476d... tree-optimization/115197 - fix ICE w/ constant in LC PHI an (*) f0a0246... tree-optimization/115199 - fix PTA constraint processing fo (*) 61f5b3c... tree-optimization/115138 - ptr-vs-ptr and FUNCTION_DECLs (*) 4efa7ec... missing require target has_arch_ppc64 for pr106550.c (*) fc5e109... testsuite: vect: Fix gcc.dg/vect/vect-pr111779.c on SPARC [ (*) 2ce9051... Fortran: Fix ICEs due to comp calls in initialization exprs (*) 57e0487... s390: Implement TARGET_NOCE_CONVERSION_PROFITABLE_P [PR1095 (*) (*) This commit already exists in another branch. Because the reference `refs/users/aoliva/heads/testbase' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc r15-817] testsuite: adjust iteration count for ppc costmodel 76b
https://gcc.gnu.org/g:7acd5d71547f74a2af35bab1b17a518197d25d23 commit r15-817-g7acd5d71547f74a2af35bab1b17a518197d25d23 Author: Alexandre Oliva Date: Fri May 24 08:32:04 2024 -0300 testsuite: adjust iteration count for ppc costmodel 76b For some hardware which doesn't support unaligned vector memory access, test case costmodel-vect-76b.c expects to see cost modeling would make the decision that it's not profitable for peeling, according to the commit history, test case comments and the way to check. For now, the existing loop bound 14 works well for Power7, but it does not for some targets on which the cost of operation vec_perm can be different from Power7, such as: Power6, it's 3 vs. 1. This difference further causes the difference (10 vs. 12) on the minimum iteration for profitability and cause the failure. To keep the original test point, this patch is to tweak the loop bound to ensure it's not profitable to be vectorized for !vect_no_align with peeling. Co-Authored-By: Kewen Lin for gcc/testsuite/ChangeLog * gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c (N): Tweak. Diff: --- gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c index cbbfbb24658..e48b0ab759e 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c @@ -6,7 +6,7 @@ /* On Power7 without misalign vector support, this case is to check it's not profitable to perform vectorization by peeling to align the store. */ -#define N 14 +#define N 13 #define OFF 4 /* Check handling of accesses for which the "initial condition" -
[gcc(refs/users/aoliva/heads/testme)] testsuite: adjust iteration count for ppc costmodel 76b
https://gcc.gnu.org/g:8cc56a8291a75fd96f50cb00ff1505c072c70808 commit 8cc56a8291a75fd96f50cb00ff1505c072c70808 Author: Alexandre Oliva Date: Sun Apr 28 01:43:51 2024 -0300 testsuite: adjust iteration count for ppc costmodel 76b For some hardware which doesn't support unaligned vector memory access, test case costmodel-vect-76b.c expects to see cost modeling would make the decision that it's not profitable for peeling, according to the commit history, test case comments and the way to check. For now, the existing loop bound 14 works well for Power7, but it does not for some targets on which the cost of operation vec_perm can be different from Power7, such as: Power6, it's 3 vs. 1. This difference further causes the difference (10 vs. 12) on the minimum iteration for profitability and cause the failure. To keep the original test point, this patch is to tweak the loop bound to ensure it's not profitable to be vectorized for !vect_no_align with peeling. Co-Authored-By: Kewen Lin for gcc/testsuite/ChangeLog * gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c (N): Tweak. Diff: --- gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c index cbbfbb24658..e48b0ab759e 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c @@ -6,7 +6,7 @@ /* On Power7 without misalign vector support, this case is to check it's not profitable to perform vectorization by peeling to align the store. */ -#define N 14 +#define N 13 #define OFF 4 /* Check handling of accesses for which the "initial condition" -
[gcc(refs/users/aoliva/heads/testme)] [testsuite] conditionalize dg-additional-sources on target and type
https://gcc.gnu.org/g:0c3019c64cb96425320ce9c15f6c3c4187fe4c75
commit 0c3019c64cb96425320ce9c15f6c3c4187fe4c75
Author: Alexandre Oliva
Date: Thu May 23 07:20:35 2024 -0300
[testsuite] conditionalize dg-additional-sources on target and type
g++.dg/vect/pr95401.cc has dg-additional-sources, and that fails when
check_vect_support_and_set_flags finds vector support lacking for
execution tests: tests decay to compile tests, and additional sources
are rejected by the compiler when compiling to a named output file.
At first I considered using some effective target to conditionalize
the additional sources. There was no support for target-specific
additional sources, so I added that.
But then, I found that adding an effective target to check whether the
test involves linking would just make for busy work in this case, and
so I went ahead and adjusted the handling of additional sources to
refrain from adding them on compile tests, reporting them as
unsupported.
That solves the problem without using the newly-added machinery for
per-target additional sources, but I figured since I'd implemented it
I might as well contribute it, since there might be other uses for it.
for gcc/ChangeLog
* doc/sourcebuild.texi (dg-additional-sources): Document
newly-added support for target selectors, and implicit discard
on non-linking tests that name the compiler output explicitly.
for gcc/testsuite/ChangeLog
* lib/gcc-defs.exp (dg-additional-sources): Support target
selectors. Make it cumulative.
(dg-additional-files-options): Take dest and type. Note
unsupported additional sources when not linking and naming the
compiler output. Adjust source dirname prepending to cope
with leading blanks.
* lib/g++.exp (g++_target_compile): Pass dest and type on to
dg-additional-files-options.
* lib/gcc.exp (gcc_target_compile): Likewise.
* lib/gdc.exp (gdb_target_compile): Likewise.
* lib/gfortran.exp (gfortran_target_compile): Likewise.
* lib/go.exp (go_target_compile): Likewise.
* lib/obj-c++.exp (obj-c++_target_compile): Likewise.
* lib/objc.exp (objc_target_compile): Likewise.
* lib/rust.exp (rust_target_compile): Likewise.
* lib/profopt.exp (profopt-execute): Likewise-ish.
Diff:
---
gcc/doc/sourcebuild.texi | 8 +++-
gcc/testsuite/lib/g++.exp | 2 +-
gcc/testsuite/lib/gcc-defs.exp | 35 ++-
gcc/testsuite/lib/gcc.exp | 2 +-
gcc/testsuite/lib/gdc.exp | 2 +-
gcc/testsuite/lib/gfortran.exp | 2 +-
gcc/testsuite/lib/go.exp | 2 +-
gcc/testsuite/lib/obj-c++.exp | 2 +-
gcc/testsuite/lib/objc.exp | 2 +-
gcc/testsuite/lib/profopt.exp | 2 +-
gcc/testsuite/lib/rust.exp | 2 +-
11 files changed, 46 insertions(+), 15 deletions(-)
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 8e4e59ac44c..e997dbec333 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1320,9 +1320,15 @@ to @var{var_value} before execution of the program
created by the test.
Specify additional files, other than source files, that must be copied
to the system where the compiler runs.
-@item @{ dg-additional-sources "@var{filelist}" @}
+@item @{ dg-additional-sources "@var{filelist}" [@{ target @var{selector} @}]
@}
Specify additional source files to appear in the compile line
following the main test file.
+If the directive includes the optional @samp{@{ @var{selector} @}}
+then the additional sources are only added if the target system
+matches the @var{selector}.
+Additional sources are generally used only in @samp{link} and @samp{run}
+tests; they are reported as unsupported and discarded in other kinds of
+tests that direct the compiler to output to a single file.
@end table
@subsubsection Add checks at the end of a test
diff --git a/gcc/testsuite/lib/g++.exp b/gcc/testsuite/lib/g++.exp
index 0e47769c25b..a6b34d5d3a2 100644
--- a/gcc/testsuite/lib/g++.exp
+++ b/gcc/testsuite/lib/g++.exp
@@ -326,7 +326,7 @@ proc g++_target_compile { source dest type options } {
append board_info($tboard,multilib_flags) " $flags_to_postpone"
}
-set options [dg-additional-files-options $options $source]
+set options [dg-additional-files-options $options $source $dest $type]
if { [target_info needs_status_wrapper] != "" && [info exists gluefile] } {
lappend options "libs=${gluefile}"
diff --git a/gcc/testsuite/lib/gcc-defs.exp b/gcc/testsuite/lib/gcc-defs.exp
index 70215ed4905..cdca4c254d6 100644
--- a/gcc/testsuite/lib/gcc-defs.exp
+++ b/gcc/testsuite/lib/gcc-defs.exp
@@ -307,7 +307,22 @@ set additional_sources_used ""
proc dg-additional-sources { args } {
global
[gcc/aoliva/heads/testme] (202 commits) testsuite: adjust iteration count for ppc costmodel 76b
The branch 'aoliva/heads/testme' was updated to point to: 8cc56a8291a... testsuite: adjust iteration count for ppc costmodel 76b It previously pointed to: 7c088551905... [testsuite] xfail pr79004 on longdouble64; drop long_double Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 7c08855... [testsuite] xfail pr79004 on longdouble64; drop long_double db37e04... [testsuite] cope with rtems implicit -ftls-model=local-exec Summary of changes (added commits): --- 8cc56a8... testsuite: adjust iteration count for ppc costmodel 76b 0c3019c... [testsuite] conditionalize dg-additional-sources on target dbdddc9... [testsuite] xfail pr79004 on longdouble64; drop long_double (*) 35a293a... [prange] Use type agnostic range in phiopt [PR115191] (*) 01cfd60... AARCH64: Add Qualcomnm oryon-1 core (*) 0c23f15... Daily bump. (*) fd1a674... libstdc++: Add [[nodiscard]] to some std::locale functions (*) 947a9c8... libstdc++: Fix effects of combining locales [PR108323] (*) b2fdd50... libstdc++: Guard use of sized deallocation [PR114940] (*) 3c98d06... c++: canonicity of fn types w/ complex eh specs [PR115159] (*) 1d1ef1c... aarch64: Fold vget_high_* intrinsics to BIT_FIELD_REF [PR10 (*) 9ddad76... testsuite: Verify r0-r3 are extended with CMSE (*) f14ef5c... Fix internal error in seh_cfa_offset with -O2 -fno-omit-fra (*) a3b16e7... i386: Correct insn_cost of movabsq. (*) 26df7b4... Avoid ICE in except.cc on targets that don't support except (*) 3507ab1... Fix mixed input kind permute optimization (*) 31e9bae... Avoid SLP_REPRESENTATIVE access for VEC_PERM in SLP schedul (*) 0c7792f... Avoid requiring VEC_PERM represenatives (*) 1a5e4dd... libstdc++: Implement std::formatter withou (*) b33f44c... libstdc++: Ensure std::variant relops convert to bool [PR11 (*) 424f8a0... web/115183 - fix typo in C++ docs (*) 6c97934... testsuite: Allow for non-SECTION_MERGE systems in gcc.dg/pr (*) dbc9b45... strlen: Fix up !si->full_string_p handling in count_nonzero (*) d3c506e... ubsan: Use right address space for MEM_REF created for bool (*) 73a167c... i386: Disable ix86_expand_vecop_qihi2 when !TARGET_AVX512BW (*) ffab721... RISC-V: Enable vectorization for vect-early-break_124-pr114 (*) 292fc21... c++: Strengthen checks on 'main' (*) bad96a0... Daily bump. (*) 826a7d3... c++: Fix std dialect hint for std::to_address [PR107800] (*) f0c0bce... c++: folding non-dep enumerator from current inst [PR115139 (*) 9926c40... RISC-V: avoid LUI based const mat in alloca epilogue expans (*) f9cfc19... RISC-V: avoid LUI based const mat in prologue/epilogue expa (*) 20e6f36... modula2: use groups in the type resolver of the bootstrap t (*) 49c87d2... match: Disable `(type)zero_one_valuep*CST` for 1bit signed (*) 232a86f... modula2: Pass --destdir for dir index during install of m2. (*) 85f7828... tree-optimization/115137 - more ptr-vs-ptr compare fixes (*) 7f35863... Cache the set of EH_RETURN_DATA_REGNOs (*) 7b215c8... Fix Ada runtime library breakage on Solaris (bis) (*) ec9b8ba... tree-optimization/115149 - VOP live and missing PHIs (*) 9596f65... contrib/gcc-changelog/git_update_version.py: Improve diagno (*) ea793db... ada: Streamline implementation of simple nonbinary modular (*) 9fbf129... ada: Simplify test for propagation of attributes to subtype (*) bf69349... ada: Fix internal error on discriminated record with Atomic (*) ccdef2a... ada: Fix strict aliasing violation in parameter passing (co (*) d851e08... ada: Make detection of useless copy for return more robust (*) f20a57e... ada: Fix strict aliasing violation in parameter passing (*) a687d5d... ada: Fix crash with aliased array and if expression (*) 3f44856... ada: Minor typo fix in comment (*) bc54f5b... ada: Follow-up adjustment to earlier fix in Build_Allocate_ (*) e49eac8... ada: Avoid temporary for conditional expression of discrimi (*) 448157f... ada: Remove unused dependencies from gnatbind object list (*) 15ac30d... ada: Fix assembler error for gigantic library-level object (*) 0967e06... ada: Fix crash on aliased constant with packed array type a (*) dc775b1... ada: Fix small inaccuracy for Size attribute applied to obj (*) 0715ed4... ada: Fix oversight in previous change (*) 2ccf77d... ada: Missing constraint check for initial value of object w (*) 8cadfeb... ada: Fix layout in a list of aspects (*) 417b6bd... ada: Remove duplicate statement (*) 933d27a... ada: Remove useless trampolines caused by Unchecked_Convers (*) 2148450... ada: Add elaboration switch tags to info messages (*) 8af95ac... ada: Simplify management of scopes while inlining (*) 0cb4e7f... ada: Remove some explicit yields in tasking run-time (*) 238fba2... ada: Fix formatting in list of implemented Ada 2012 feature (*) ef10ed2... ada: Sort list of
[gcc/aoliva/heads/testbase] (200 commits) [testsuite] xfail pr79004 on longdouble64; drop long_double
The branch 'aoliva/heads/testbase' was updated to point to: dbdddc92a3b... [testsuite] xfail pr79004 on longdouble64; drop long_double It previously pointed to: b7483de9953... make -freg-struct-return visibly a negative alias of -fpcc- Diff: Summary of changes (added commits): --- dbdddc9... [testsuite] xfail pr79004 on longdouble64; drop long_double (*) 35a293a... [prange] Use type agnostic range in phiopt [PR115191] (*) 01cfd60... AARCH64: Add Qualcomnm oryon-1 core (*) 0c23f15... Daily bump. (*) fd1a674... libstdc++: Add [[nodiscard]] to some std::locale functions (*) 947a9c8... libstdc++: Fix effects of combining locales [PR108323] (*) b2fdd50... libstdc++: Guard use of sized deallocation [PR114940] (*) 3c98d06... c++: canonicity of fn types w/ complex eh specs [PR115159] (*) 1d1ef1c... aarch64: Fold vget_high_* intrinsics to BIT_FIELD_REF [PR10 (*) 9ddad76... testsuite: Verify r0-r3 are extended with CMSE (*) f14ef5c... Fix internal error in seh_cfa_offset with -O2 -fno-omit-fra (*) a3b16e7... i386: Correct insn_cost of movabsq. (*) 26df7b4... Avoid ICE in except.cc on targets that don't support except (*) 3507ab1... Fix mixed input kind permute optimization (*) 31e9bae... Avoid SLP_REPRESENTATIVE access for VEC_PERM in SLP schedul (*) 0c7792f... Avoid requiring VEC_PERM represenatives (*) 1a5e4dd... libstdc++: Implement std::formatter withou (*) b33f44c... libstdc++: Ensure std::variant relops convert to bool [PR11 (*) 424f8a0... web/115183 - fix typo in C++ docs (*) 6c97934... testsuite: Allow for non-SECTION_MERGE systems in gcc.dg/pr (*) dbc9b45... strlen: Fix up !si->full_string_p handling in count_nonzero (*) d3c506e... ubsan: Use right address space for MEM_REF created for bool (*) 73a167c... i386: Disable ix86_expand_vecop_qihi2 when !TARGET_AVX512BW (*) ffab721... RISC-V: Enable vectorization for vect-early-break_124-pr114 (*) 292fc21... c++: Strengthen checks on 'main' (*) bad96a0... Daily bump. (*) 826a7d3... c++: Fix std dialect hint for std::to_address [PR107800] (*) f0c0bce... c++: folding non-dep enumerator from current inst [PR115139 (*) 9926c40... RISC-V: avoid LUI based const mat in alloca epilogue expans (*) f9cfc19... RISC-V: avoid LUI based const mat in prologue/epilogue expa (*) 20e6f36... modula2: use groups in the type resolver of the bootstrap t (*) 49c87d2... match: Disable `(type)zero_one_valuep*CST` for 1bit signed (*) 232a86f... modula2: Pass --destdir for dir index during install of m2. (*) 85f7828... tree-optimization/115137 - more ptr-vs-ptr compare fixes (*) 7f35863... Cache the set of EH_RETURN_DATA_REGNOs (*) 7b215c8... Fix Ada runtime library breakage on Solaris (bis) (*) ec9b8ba... tree-optimization/115149 - VOP live and missing PHIs (*) 9596f65... contrib/gcc-changelog/git_update_version.py: Improve diagno (*) ea793db... ada: Streamline implementation of simple nonbinary modular (*) 9fbf129... ada: Simplify test for propagation of attributes to subtype (*) bf69349... ada: Fix internal error on discriminated record with Atomic (*) ccdef2a... ada: Fix strict aliasing violation in parameter passing (co (*) d851e08... ada: Make detection of useless copy for return more robust (*) f20a57e... ada: Fix strict aliasing violation in parameter passing (*) a687d5d... ada: Fix crash with aliased array and if expression (*) 3f44856... ada: Minor typo fix in comment (*) bc54f5b... ada: Follow-up adjustment to earlier fix in Build_Allocate_ (*) e49eac8... ada: Avoid temporary for conditional expression of discrimi (*) 448157f... ada: Remove unused dependencies from gnatbind object list (*) 15ac30d... ada: Fix assembler error for gigantic library-level object (*) 0967e06... ada: Fix crash on aliased constant with packed array type a (*) dc775b1... ada: Fix small inaccuracy for Size attribute applied to obj (*) 0715ed4... ada: Fix oversight in previous change (*) 2ccf77d... ada: Missing constraint check for initial value of object w (*) 8cadfeb... ada: Fix layout in a list of aspects (*) 417b6bd... ada: Remove duplicate statement (*) 933d27a... ada: Remove useless trampolines caused by Unchecked_Convers (*) 2148450... ada: Add elaboration switch tags to info messages (*) 8af95ac... ada: Simplify management of scopes while inlining (*) 0cb4e7f... ada: Remove some explicit yields in tasking run-time (*) 238fba2... ada: Fix formatting in list of implemented Ada 2012 feature (*) ef10ed2... ada: Sort list of implemented Ada 2012 features (*) b0a97d4... ada: Fix index entry for an implemented AI feature (*) 01cb6e1... ada: Update documentation of warning messages (*) a311db8... ada: Do not leak tagged type names when Discard_Names is en (*) 5035d5e... ada: Remove conversion from String_Id to String and back to (*) 1bc1fa1... ada: Remove trailing NUL in minimal expansion of Put_Image (*) b22c01d... ada:
[gcc r15-786] [testsuite] xfail pr79004 on longdouble64; drop long_double_64bit
https://gcc.gnu.org/g:dbdddc92a3b955fce71af47755c226132559eda2
commit r15-786-gdbdddc92a3b955fce71af47755c226132559eda2
Author: Alexandre Oliva
Date: Thu May 23 03:20:19 2024 -0300
[testsuite] xfail pr79004 on longdouble64; drop long_double_64bit
Some of the asm opcodes expected by pr79004 depend on
-mlong-double-128 to be output. E.g., without this flag, the
conditions of patterns @extenddf2 and extendsf2 do not
hold, and so GCC resorts to libcalls instead of even trying
rs6000_expand_float128_convert.
Perhaps the conditions are too strict, and they could enable the use
of conversion insns involving __ieee128/_Float128 even with 64-bit
long doubles.
For now, xfail the opcodes that are not available on longdouble64.
While at that, drop long_double_64bit, since it's broken and sort of
redundant.
for gcc/testsuite/ChangeLog
PR target/105359
* gcc.target/powerpc/pr79004.c: Xfail opcodes not available on
longdouble64.
* lib/target-supports.exp
(check_effective_target_long_double_64bit): Drop.
(add_options_for_long_double_64bit): Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr79004.c | 14 +-
gcc/testsuite/lib/target-supports.exp | 43 --
2 files changed, 8 insertions(+), 49 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79004.c
b/gcc/testsuite/gcc.target/powerpc/pr79004.c
index caf1f6c1eef..2cb8bf4bc14 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79004.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79004.c
@@ -100,10 +100,12 @@ void to_uns_short_store_n (TYPE a, unsigned short *p,
long n) { p[n] = (unsigned
void to_uns_int_store_n (TYPE a, unsigned int *p, long n) { p[n] = (unsigned
int)a; }
void to_uns_long_store_n (TYPE a, unsigned long *p, long n) { p[n] = (unsigned
long)a; }
-/* { dg-final { scan-assembler-not {\mbl __} } } */
-/* { dg-final { scan-assembler {\mxscvdpqp\M} } } */
-/* { dg-final { scan-assembler {\mxscvqpdp\M} } } */
-/* { dg-final { scan-assembler {\mxscvqpdpo\M} } } */
+/* On targets with 64-bit long double, some opcodes to deal with __float128 are
+ disabled, see PR target/105359. */
+/* { dg-final { scan-assembler-not {\mbl __} { xfail longdouble64 } } }
*/
+/* { dg-final { scan-assembler {\mxscvdpqp\M} { xfail longdouble64 } } }
*/
+/* { dg-final { scan-assembler {\mxscvqpdp\M} { xfail longdouble64 } } }
*/
+/* { dg-final { scan-assembler {\mxscvqpdpo\M} { xfail longdouble64 } } }
*/
/* { dg-final { scan-assembler {\mxscvqpsdz\M} } } */
/* { dg-final { scan-assembler {\mxscvqpswz\M} } } */
/* { dg-final { scan-assembler {\mxscvsdqp\M} } } */
@@ -111,7 +113,7 @@ void to_uns_long_store_n (TYPE a, unsigned long *p, long n)
{ p[n] = (unsigned l
/* { dg-final { scan-assembler {\mlxsd\M} } } */
/* { dg-final { scan-assembler {\mlxsiwax\M} } } */
/* { dg-final { scan-assembler {\mlxsiwzx\M} } } */
-/* { dg-final { scan-assembler {\mlxssp\M} } } */
+/* { dg-final { scan-assembler {\mlxssp\M} { xfail longdouble64 } } }
*/
/* { dg-final { scan-assembler {\mstxsd\M} } } */
/* { dg-final { scan-assembler {\mstxsiwx\M} } } */
-/* { dg-final { scan-assembler {\mstxssp\M}} } */
+/* { dg-final { scan-assembler {\mstxssp\M}{ xfail longdouble64 } } }
*/
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3f0f8532dc3..f0f6da52275 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2924,49 +2924,6 @@ proc add_options_for_long_double_ieee128 { flags } {
return "$flags"
}
-# Check if GCC and GLIBC supports explicitly specifying that the long double
-# format uses the IEEE 64-bit. Under little endian PowerPC Linux, you need
-# GLIBC 2.32 or later to be able to use a different long double format for
-# running a program than the system default.
-
-proc check_effective_target_long_double_64bit { } {
-return [check_runtime_nocache long_double_64bit {
- #include
- #include
- /* use volatile to prevent optimization. */
- volatile double a = 3.0;
- volatile long double one = 1.0L;
- volatile long double two = 2.0L;
- volatile long double b;
- char buffer[20];
- int main()
- {
- double a2;
- long double b2;
- if (sizeof (long double) != 8)
- return 1;
- b = one + two;
- /* eliminate removing volatile cast warning. */
- a2 = a;
- b2 = b;
- if (memcmp (, , 16) != 0)
- return 1;
- sprintf (buffer, "%lg", b);
- return strcmp (buffer, "3") != 0;
- }
-} [add_options_for_ppc_long_double_override_64bit ""]]
-}
-
-# Return the appropriate options to specify that long double
[gcc/aoliva/heads/testbase] (666 commits) make -freg-struct-return visibly a negative alias of -fpcc-
The branch 'aoliva/heads/testbase' was updated to point to: b7483de99536... make -freg-struct-return visibly a negative alias of -fpcc- It previously pointed to: f17d31e709af... Fortran: Detect 'no implicit type' error in right place [PR Diff: Summary of changes (added commits): --- b7483de... make -freg-struct-return visibly a negative alias of -fpcc- (*) d477d68... RISC-V: Cleanup some temporally files [NFC] (*) 0b2c333... Update gcc sv.po (*) 556e777... RISC-V: Enable vectorizable early exit testsuite (*) 6c1de78... RISC-V: Implement vectorizable early exit with vcond_mask_l (*) 96d5325... Fix points_to_local_or_readonly_memory_p wrt TARGET_MEM_REF (*) f3e5f4c... tree-optimization/13962 - handle ptr-ptr compares in ptrs_c (*) a9251ab... wrong code with points-to and volatile (*) 57f8a2f... Vect: Support loop len in vectorizable early exit (*) d4dee34... Vect: Support new IFN SAT_ADD for unsigned vector int (*) 52b0536... Internal-fn: Support new IFN SAT_ADD for unsigned scalar in (*) da73261... Revert "Revert: "Enable prange support."" (*) b8e3574... Cleanup prange sanity checks. (*) f6bed6d... Use a boolean type when folding conditionals in simplify_us (*) b8b82bb... RISC-V: testsuite: Drop march-string in cmpmemsi/cpymemsi t (*) 1e0ae1f... tree-optimization/79958 - make DSE track multiple paths (*) bff5328... ada: Remove obsolete reference in comment (*) f72988a... ada: Reset scope of top level object declaration during unn (*) 584ade0... ada: Redundant validity checks (*) 9ec20f1... ada: Exception on Indefinite_Vector aggregate with loop_par (*) 568c795... ada: Implement new experimental attribute 'Super (*) 33ae453... ada: Fix reference to RM clause in comment (*) 5c9205a... ada: Fix missing length checks with case expressions (*) ea64884... ada: Fix standalone Windows builds of adaint.c (*) c3b570b... ada: Avoid checking parameters of protected procedures (*) c485a15... ada: Ignore ghost nodes in call graph information for dispa (*) a802cb3... ada: Fix reason code for length check (*) 8e22376... ada: Propagate Program_Error from failed finalization of co (*) 55d11e8... ada: Improve recovery from illegal occurrence of 'Old in if (*) f5c7870... ada: No need to follow New_Occurrence_Of with Set_Etype (*) 7d2a5db... ada: Fix detection of if_expressions that are known on entr (*) fa832b4... ada: Fix comments about Get_Ranged_Checks (*) 8560a06... ada: Minor performance improvement for dynamically-allocate (*) 513f6b8... ada: Fixup one more pattern of broken scope information (*) bc35098... ada: Fix typo in CUDA error message (*) 4806875... ada: Fix latent alignment issue for dynamically-allocated c (*) b98e256... ada: Fix resolving tagged operations in array aggregates (*) 81a5815... ada: Fix bogus error on function returning noncontrolling r (*) 7c487eb... ada: Fix casing of CUDA in error messages (*) f039057... ada: Fix crash with -gnatdJ and -gnatw_q (*) a58b6be... ada: Follow up fixes for Put_Image/streaming regressions (*) 50a... ada: Implement per-finalization-collection spinlocks (*) 91c6302... ada: Formal_Derived_Type'Size is not static (*) e730d52... ada: Fix bug in maintaining dimension info (*) 8b73cb9... ada: Remove Aspect_Specifications field from N_Procedure_Sp (*) 0607818... ada: Reuse existing expression when rewriting aspects to pr (*) 492f896... ada: Cleanup reporting locations for Ada 2022 and GNAT exte (*) 1d992c4... ada: Fix alphabetic ordering of aspect identifiers (*) 61751ee... ada: Fix ordering of code for pragma Preelaborable_Initiali (*) 3549a58... ada: Fix casing in error messages (*) fd3a9ee... ada: Fix docs and comments about pragmas for Boolean-valued (*) e656656... diagnostics: use unicode art for interprocedural depth (*) 0b7ebe5... diagnostics: add warning emoji to events with VERB_danger (*) 3cd2674... diagnostics: simplify output of purely intraprocedural exec (*) a7be993... diagnostics: handle SGR codes in line_label::m_display_widt (*) 38dd4e2... RISC-V: Add Zvfbfwma extension to the -march= option (*) 090714e... Set d.one_operand_p to true when TARGET_SSSE3 in ix86_expan (*) 0cc0956... Optimize ashift >> 7 to vpcmpgtb for vector int8. (*) 25456c0... Daily bump. (*) d7e6fe0... Add missing hunk in recent change. (*) 1779e22... analyzer: fix ICE seen with -fsanitize=undefined [PR114899] (*) 1fbbae1... [v2,2/2] RISC-V: strcmp expansion: Use adjust_address() for (*) 4bf1aa1... [v2,1/2] RISC-V: Add cmpmemsi expansion (*) 1a05332... c++: ICE with reference NSDMI [PR114854] (*) 0b3eac4... c++: DR 569, DR 1693: fun with semicolons [PR113760] (*) 6ad7ca1... c++: Optimize in maybe_clone_body aliases even when not at_ (*) 0b93a0a... combine: Fix up simplify_compare_const [PR115092] (*) 7fdbefc... openmp: Diagnose using grainsize+num_tasks clauses together (*) 99b1daa... tree-optimization/114589 -
[gcc(refs/users/aoliva/heads/testme)] [testsuite] xfail pr79004 on longdouble64; drop long_double_64bit
https://gcc.gnu.org/g:7c08855190502bca6a1e59577ffe304677f126ed
commit 7c08855190502bca6a1e59577ffe304677f126ed
Author: Alexandre Oliva
Date: Fri May 17 06:40:10 2024 -0300
[testsuite] xfail pr79004 on longdouble64; drop long_double_64bit
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr79004.c | 14 +-
gcc/testsuite/lib/target-supports.exp | 43 --
2 files changed, 8 insertions(+), 49 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79004.c
b/gcc/testsuite/gcc.target/powerpc/pr79004.c
index caf1f6c1eefe..2cb8bf4bc14b 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79004.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79004.c
@@ -100,10 +100,12 @@ void to_uns_short_store_n (TYPE a, unsigned short *p,
long n) { p[n] = (unsigned
void to_uns_int_store_n (TYPE a, unsigned int *p, long n) { p[n] = (unsigned
int)a; }
void to_uns_long_store_n (TYPE a, unsigned long *p, long n) { p[n] = (unsigned
long)a; }
-/* { dg-final { scan-assembler-not {\mbl __} } } */
-/* { dg-final { scan-assembler {\mxscvdpqp\M} } } */
-/* { dg-final { scan-assembler {\mxscvqpdp\M} } } */
-/* { dg-final { scan-assembler {\mxscvqpdpo\M} } } */
+/* On targets with 64-bit long double, some opcodes to deal with __float128 are
+ disabled, see PR target/105359. */
+/* { dg-final { scan-assembler-not {\mbl __} { xfail longdouble64 } } }
*/
+/* { dg-final { scan-assembler {\mxscvdpqp\M} { xfail longdouble64 } } }
*/
+/* { dg-final { scan-assembler {\mxscvqpdp\M} { xfail longdouble64 } } }
*/
+/* { dg-final { scan-assembler {\mxscvqpdpo\M} { xfail longdouble64 } } }
*/
/* { dg-final { scan-assembler {\mxscvqpsdz\M} } } */
/* { dg-final { scan-assembler {\mxscvqpswz\M} } } */
/* { dg-final { scan-assembler {\mxscvsdqp\M} } } */
@@ -111,7 +113,7 @@ void to_uns_long_store_n (TYPE a, unsigned long *p, long n)
{ p[n] = (unsigned l
/* { dg-final { scan-assembler {\mlxsd\M} } } */
/* { dg-final { scan-assembler {\mlxsiwax\M} } } */
/* { dg-final { scan-assembler {\mlxsiwzx\M} } } */
-/* { dg-final { scan-assembler {\mlxssp\M} } } */
+/* { dg-final { scan-assembler {\mlxssp\M} { xfail longdouble64 } } }
*/
/* { dg-final { scan-assembler {\mstxsd\M} } } */
/* { dg-final { scan-assembler {\mstxsiwx\M} } } */
-/* { dg-final { scan-assembler {\mstxssp\M}} } */
+/* { dg-final { scan-assembler {\mstxssp\M}{ xfail longdouble64 } } }
*/
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index ec9baa4f32a3..dc7d4f2b5f39 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2930,49 +2930,6 @@ proc add_options_for_long_double_ieee128 { flags } {
return "$flags"
}
-# Check if GCC and GLIBC supports explicitly specifying that the long double
-# format uses the IEEE 64-bit. Under little endian PowerPC Linux, you need
-# GLIBC 2.32 or later to be able to use a different long double format for
-# running a program than the system default.
-
-proc check_effective_target_long_double_64bit { } {
-return [check_runtime_nocache long_double_64bit {
- #include
- #include
- /* use volatile to prevent optimization. */
- volatile double a = 3.0;
- volatile long double one = 1.0L;
- volatile long double two = 2.0L;
- volatile long double b;
- char buffer[20];
- int main()
- {
- double a2;
- long double b2;
- if (sizeof (long double) != 8)
- return 1;
- b = one + two;
- /* eliminate removing volatile cast warning. */
- a2 = a;
- b2 = b;
- if (memcmp (, , 16) != 0)
- return 1;
- sprintf (buffer, "%lg", b);
- return strcmp (buffer, "3") != 0;
- }
-} [add_options_for_ppc_long_double_override_64bit ""]]
-}
-
-# Return the appropriate options to specify that long double uses the IEEE
-# 64-bit format on PowerPC.
-
-proc add_options_for_long_double_64bit { flags } {
-if { [istarget powerpc*-*-*] } {
- return "$flags -mlong-double-64"
-}
-return "$flags"
-}
-
# Return 1 if the target supports executing VSX instructions, 0
# otherwise. Cache the result.
[gcc(refs/users/aoliva/heads/testme)] [testsuite] cope with rtems implicit -ftls-model=local-exec
https://gcc.gnu.org/g:db37e042c4b3ab0fc594c207a4ebe34ed84350d7
commit db37e042c4b3ab0fc594c207a4ebe34ed84350d7
Author: Alexandre Oliva
Date: Fri May 17 02:02:08 2024 -0300
[testsuite] cope with rtems implicit -ftls-model=local-exec
gcc/config/rtems.h's OS_CC1_SPEC changes the -ftls-model default to
local-exec, which breaks some tests that compile with PIC and thus
expect dynamic TLS access models.
I assume the default overriding even with PIC is intended, so I'm
adjusting the testcases.
For those in gcc.dg/tls, I adjusted the ipa dump expectations, so that
they check for tls-local- only, which covers both -dynamic and -exec.
For those in g{cc,++}.target/aarch64/sve, I've added a -ftls-local
overrider, so that the expected opcodes for dynamic TLS are generated.
for gcc/testsuite/ChangeLog
* gcc.dg/tls/vis-attr-hidden.c: Match tls-local- for both
-dynamic and -exec. Note rtems's default.
* gcc.dg/tls/vis-flag-hidden.c: Likewise.
* gcc.dg/tls/vis-pragma-hidden.c: Likewise.
* gcc.target/aarch64/sve/tls_1.c: Override -ftls-model default
on rtems.
* gcc.target/aarch64/sve/tls_preserve_2.c: Likewise.
* gcc.target/aarch64/sve/tls_preserve_3.c: Likewise.
* g++.target/aarch64/sve/tls_2.C: Likewise.
Diff:
---
gcc/testsuite/g++.target/aarch64/sve/tls_2.C | 1 +
gcc/testsuite/gcc.dg/tls/vis-attr-hidden.c| 3 ++-
gcc/testsuite/gcc.dg/tls/vis-flag-hidden.c| 3 ++-
gcc/testsuite/gcc.dg/tls/vis-pragma-hidden.c | 3 ++-
gcc/testsuite/gcc.target/aarch64/sve/tls_1.c | 1 +
gcc/testsuite/gcc.target/aarch64/sve/tls_preserve_2.c | 1 +
gcc/testsuite/gcc.target/aarch64/sve/tls_preserve_3.c | 1 +
7 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/g++.target/aarch64/sve/tls_2.C
b/gcc/testsuite/g++.target/aarch64/sve/tls_2.C
index a1a2c85e5910..23004d9984d5 100644
--- a/gcc/testsuite/g++.target/aarch64/sve/tls_2.C
+++ b/gcc/testsuite/g++.target/aarch64/sve/tls_2.C
@@ -2,6 +2,7 @@
/* { dg-require-effective-target tls } */
/* { dg-options "-O2 -fPIC -msve-vector-bits=256" } */
/* { dg-require-effective-target fpic } */
+/* { dg-additional-options "-ftls-model=global-dynamic" { target *-*-rtems* }
} */
#include
diff --git a/gcc/testsuite/gcc.dg/tls/vis-attr-hidden.c
b/gcc/testsuite/gcc.dg/tls/vis-attr-hidden.c
index 0d43fc565b09..007d382fa9a0 100644
--- a/gcc/testsuite/gcc.dg/tls/vis-attr-hidden.c
+++ b/gcc/testsuite/gcc.dg/tls/vis-attr-hidden.c
@@ -9,4 +9,5 @@ __thread int x;
void reference() { x++; }
-/* { dg-final { scan-ipa-dump "Varpool flags: tls-local-dynamic"
"whole-program" } } */
+/* rtems defaults to local-exec, others should get local-dynamic. */
+/* { dg-final { scan-ipa-dump "Varpool flags: tls-local-" "whole-program" } }
*/
diff --git a/gcc/testsuite/gcc.dg/tls/vis-flag-hidden.c
b/gcc/testsuite/gcc.dg/tls/vis-flag-hidden.c
index a15df092d4d0..baf248dc3bab 100644
--- a/gcc/testsuite/gcc.dg/tls/vis-flag-hidden.c
+++ b/gcc/testsuite/gcc.dg/tls/vis-flag-hidden.c
@@ -9,4 +9,5 @@ __thread int x;
void reference() { x++; }
-/* { dg-final { scan-ipa-dump "Varpool flags: tls-local-dynamic"
"whole-program" } } */
+/* rtems defaults to local-exec, others should get local-dynamic. */
+/* { dg-final { scan-ipa-dump "Varpool flags: tls-local-" "whole-program" } }
*/
diff --git a/gcc/testsuite/gcc.dg/tls/vis-pragma-hidden.c
b/gcc/testsuite/gcc.dg/tls/vis-pragma-hidden.c
index 1be97644243a..50cd010924cf 100644
--- a/gcc/testsuite/gcc.dg/tls/vis-pragma-hidden.c
+++ b/gcc/testsuite/gcc.dg/tls/vis-pragma-hidden.c
@@ -13,4 +13,5 @@ __thread int x;
void reference() { x++; }
-/* { dg-final { scan-ipa-dump "Varpool flags: tls-local-dynamic"
"whole-program" } } */
+/* rtems defaults to local-exec, others should get local-dynamic. */
+/* { dg-final { scan-ipa-dump "Varpool flags: tls-local-" "whole-program" } }
*/
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/tls_1.c
b/gcc/testsuite/gcc.target/aarch64/sve/tls_1.c
index 43c52bc2b906..71f354dfe1b4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/tls_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/tls_1.c
@@ -1,5 +1,6 @@
/* { dg-options "-O2 -fPIC -msve-vector-bits=256" } */
/* { dg-require-effective-target fpic } */
+/* { dg-additional-options "-ftls-model=global-dynamic" { target *-*-rtems* }
} */
typedef unsigned int v8si __attribute__((vector_size(32)));
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/tls_preserve_2.c
b/gcc/testsuite/gcc.target/aarch64/sve/tls_preserve_2.c
index 20e939fbb85b..1f477ba8c259 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/tls_preserve_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/tls_preserve_2.c
@@ -2,6 +2,7 @@
/* { dg-options "-O3 -fpic -msve-vector-bits=256 -fno-schedule-insns" } */
/* { dg-require-effective-target fpic } */
/* {
[gcc/aoliva/heads/testme] (668 commits) [testsuite] xfail pr79004 on longdouble64; drop long_double
The branch 'aoliva/heads/testme' was updated to point to: 7c0885519050... [testsuite] xfail pr79004 on longdouble64; drop long_double It previously pointed to: ec1d688d102c... adjust iteration count for ppc costmodel 76b Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- ec1d688... adjust iteration count for ppc costmodel 76b df13301... [testsuite] require sqrt_insn effective target where needed 22b9a80... xfail fetestexcept test - ppc always uses fcmpu b40c8c9... ppc: testsuite: pr79004 needs -mlong-double-128 1275905... ppc: testsuite: vec-mul requires vsx runtime 4c42bea... make -freg-struct-return visibly a negative alias of -fpcc- 7ef6054... add explicit ABI and align options to pr88233.c 760577d... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 7d97712... decay vect tests from run to link for pr95401 9cb06df... Request check for hw support in ppc run tests with -maltive 5b0e0d4... disable ldist for test, to restore vectorizing-candidate lo 6996207... [testsuite] [ppc64] expect error on vxworks too 0cbe329... [testsuite] [arm] add effective target and options for pacb Summary of changes (added commits): --- 7c08855... [testsuite] xfail pr79004 on longdouble64; drop long_double db37e04... [testsuite] cope with rtems implicit -ftls-model=local-exec b7483de... make -freg-struct-return visibly a negative alias of -fpcc- (*) d477d68... RISC-V: Cleanup some temporally files [NFC] (*) 0b2c333... Update gcc sv.po (*) 556e777... RISC-V: Enable vectorizable early exit testsuite (*) 6c1de78... RISC-V: Implement vectorizable early exit with vcond_mask_l (*) 96d5325... Fix points_to_local_or_readonly_memory_p wrt TARGET_MEM_REF (*) f3e5f4c... tree-optimization/13962 - handle ptr-ptr compares in ptrs_c (*) a9251ab... wrong code with points-to and volatile (*) 57f8a2f... Vect: Support loop len in vectorizable early exit (*) d4dee34... Vect: Support new IFN SAT_ADD for unsigned vector int (*) 52b0536... Internal-fn: Support new IFN SAT_ADD for unsigned scalar in (*) da73261... Revert "Revert: "Enable prange support."" (*) b8e3574... Cleanup prange sanity checks. (*) f6bed6d... Use a boolean type when folding conditionals in simplify_us (*) b8b82bb... RISC-V: testsuite: Drop march-string in cmpmemsi/cpymemsi t (*) 1e0ae1f... tree-optimization/79958 - make DSE track multiple paths (*) bff5328... ada: Remove obsolete reference in comment (*) f72988a... ada: Reset scope of top level object declaration during unn (*) 584ade0... ada: Redundant validity checks (*) 9ec20f1... ada: Exception on Indefinite_Vector aggregate with loop_par (*) 568c795... ada: Implement new experimental attribute 'Super (*) 33ae453... ada: Fix reference to RM clause in comment (*) 5c9205a... ada: Fix missing length checks with case expressions (*) ea64884... ada: Fix standalone Windows builds of adaint.c (*) c3b570b... ada: Avoid checking parameters of protected procedures (*) c485a15... ada: Ignore ghost nodes in call graph information for dispa (*) a802cb3... ada: Fix reason code for length check (*) 8e22376... ada: Propagate Program_Error from failed finalization of co (*) 55d11e8... ada: Improve recovery from illegal occurrence of 'Old in if (*) f5c7870... ada: No need to follow New_Occurrence_Of with Set_Etype (*) 7d2a5db... ada: Fix detection of if_expressions that are known on entr (*) fa832b4... ada: Fix comments about Get_Ranged_Checks (*) 8560a06... ada: Minor performance improvement for dynamically-allocate (*) 513f6b8... ada: Fixup one more pattern of broken scope information (*) bc35098... ada: Fix typo in CUDA error message (*) 4806875... ada: Fix latent alignment issue for dynamically-allocated c (*) b98e256... ada: Fix resolving tagged operations in array aggregates (*) 81a5815... ada: Fix bogus error on function returning noncontrolling r (*) 7c487eb... ada: Fix casing of CUDA in error messages (*) f039057... ada: Fix crash with -gnatdJ and -gnatw_q (*) a58b6be... ada: Follow up fixes for Put_Image/streaming regressions (*) 50a... ada: Implement per-finalization-collection spinlocks (*) 91c6302... ada: Formal_Derived_Type'Size is not static (*) e730d52... ada: Fix bug in maintaining dimension info (*) 8b73cb9... ada: Remove Aspect_Specifications field from N_Procedure_Sp (*) 0607818... ada: Reuse existing expression when rewriting aspects to pr (*) 492f896... ada: Cleanup reporting locations for Ada 2022 and GNAT exte (*) 1d992c4... ada: Fix alphabetic ordering of aspect identifiers (*) 61751ee... ada: Fix ordering of code for pragma Preelaborable_Initiali (*) 3549a58... ada: Fix casing in error messages (*) fd3a9ee... ada: Fix docs and comments about pragmas for Boolean-valued (*) e656656... diagnostics: use unicode art for interprocedural depth (*)
[gcc r15-586] make -freg-struct-return visibly a negative alias of -fpcc-struct-return
https://gcc.gnu.org/g:b7483de99536c05983129d9ca28b53b575861078 commit r15-586-gb7483de99536c05983129d9ca28b53b575861078 Author: Alexandre Oliva Date: Fri May 17 00:45:45 2024 -0300 make -freg-struct-return visibly a negative alias of -fpcc-struct-return The fact that both options accept negative forms suggests that maybe they aren't negative forms of each other. They are, but that isn't clear even by examining common.opt. Use NegativeAlias to make it abundantly clear. The 'Optimization' keyword next to freg-struct-return was the only thing that caused flag_pcc_struct_return to be a per-function flag, and ipa-inline relied on that. After making it an alias, the Optimization keyword was no longer operational. I'm not sure it was sensible or desirable for flag_pcc_struct_return to be a per-function setting, but this patch does not intend to change behavior. for gcc/ChangeLog * common.opt (freg-struct-return): Make it explicitly fpcc-struct-return's NegativeAlias. Copy Optimization... (freg-struct-return): ... here. Diff: --- gcc/common.opt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/common.opt b/gcc/common.opt index 40cab3cb36a3..40d90817b868 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -2412,7 +2412,7 @@ Common RejectNegative Joined UInteger Optimization -fpack-struct= Set initial maximum structure member alignment. fpcc-struct-return -Common Var(flag_pcc_struct_return,1) Init(DEFAULT_PCC_STRUCT_RETURN) +Common Var(flag_pcc_struct_return,1) Init(DEFAULT_PCC_STRUCT_RETURN) Optimization Return small aggregates in memory, not registers. fpeel-loops @@ -2602,7 +2602,7 @@ Common Var(flag_record_gcc_switches) Record gcc command line switches in the object file. freg-struct-return -Common Var(flag_pcc_struct_return,0) Optimization +Common NegativeAlias Alias(fpcc_struct_return) Optimization Return small aggregates in registers. fregmove
[gcc r15-54] Revert "decay vect tests from run to link for pr95401"
https://gcc.gnu.org/g:93a9c40ea9764773f0288e5b7ba2d8399e670f2c
commit r15-54-g93a9c40ea9764773f0288e5b7ba2d8399e670f2c
Author: Alexandre Oliva
Date: Mon Apr 29 20:33:37 2024 -0300
Revert "decay vect tests from run to link for pr95401"
This reverts commit 05d83334d5bbeae01d71080f1da524810d6740d9.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 182d80129de..3a55b2a4159 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11625,7 +11625,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default link
+set dg-do-what-default compile
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11655,14 +11655,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default link
+set dg-do-what-default compile
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default link
+set dg-do-what-default compile
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11681,7 +11681,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default link
+set dg-do-what-default compile
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11694,7 +11694,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default link
+set dg-do-what-default compile
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11707,7 +11707,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default link
+set dg-do-what-default compile
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11731,7 +11731,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default link
+set dg-do-what-default compile
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
@@ -11742,7 +11742,7 @@ proc check_vect_support_and_set_flags { } {
foreach item [add_options_for_riscv_v ""] {
lappend DEFAULT_VECTCFLAGS $item
}
- set dg-do-what-default link
+ set dg-do-what-default compile
}
} elseif [istarget loongarch*-*-*] {
# Set the default vectorization option to "-mlsx" due to the problem
@@ -11751,7 +11751,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_loongarch_sx_hw] {
set dg-do-what-default run
} else {
- set dg-do-what-default link
+ set dg-do-what-default compile
}
} else {
return 0
[gcc r15-21] [testsuite] require sqrt_insn effective target where needed
https://gcc.gnu.org/g:bc07fa6af54cc67f7fc85cc144f9686fad07f205
commit r15-21-gbc07fa6af54cc67f7fc85cc144f9686fad07f205
Author: Alexandre Oliva
Date: Sun Apr 28 04:30:30 2024 -0300
[testsuite] require sqrt_insn effective target where needed
Some tests fail on ppc and ppc64 when testing a compiler [with options
for] for a CPU [emulator] that doesn't support the sqrt insn.
The gcc.dg/cdce3.c is one in which the expected shrink-wrap
optimization only takes place when the target CPU supports a sqrt
insn.
The gcc.target/powerpc/pr46728-1[0-4].c tests use -mpowerpc-gpopt and
call sqrt(), which involves the sqrt insn that the target CPU under
test may not support.
Require a sqrt_insn effective target for all the affected tests.
for gcc/testsuite/ChangeLog
* gcc.dg/cdce3.c: Require sqrt_insn effective target.
* gcc.target/powerpc/pr46728-10.c: Likewise. Drop darwin
explicit skipping.
* gcc.target/powerpc/pr46728-11.c: Likewise. Likewise.
* gcc.target/powerpc/pr46728-13.c: Likewise. Likewise.
* gcc.target/powerpc/pr46728-14.c: Likewise. Likewise.
Diff:
---
gcc/testsuite/gcc.dg/cdce3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-10.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr46728-11.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr46728-13.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr46728-14.c | 2 +-
5 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/cdce3.c b/gcc/testsuite/gcc.dg/cdce3.c
index 601ddf055fd..f759a95972e 100644
--- a/gcc/testsuite/gcc.dg/cdce3.c
+++ b/gcc/testsuite/gcc.dg/cdce3.c
@@ -1,7 +1,8 @@
/* { dg-do compile } */
/* { dg-require-effective-target hard_float } */
+/* { dg-require-effective-target sqrt_insn } */
/* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details
-fdump-tree-optimized" } */
-/* { dg-final { scan-tree-dump "cdce3.c:11: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
+/* { dg-final { scan-tree-dump "cdce3.c:12: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
/* { dg-final { scan-tree-dump "sqrtf \\(\[^\n\r]*\\); \\\[tail call\\\]"
"optimized" } } */
/* { dg-skip-if "doesn't have a sqrtf insn" { mmix-*-* } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
index 3be4728d333..c04a3101c11 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
-/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
index 43b6728a4b8..d0e3d602121 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
-/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
index b9fd63973b7..2b9df737a9b 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
-/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
index 5a13bdb..e6836f515e4 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
-/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
[gcc r15-19] ppc: testsuite: vec-mul requires vsx runtime
https://gcc.gnu.org/g:d48aba3c8b61e4a33d0f1fdd126e5cd15dc99a7f
commit r15-19-gd48aba3c8b61e4a33d0f1fdd126e5cd15dc99a7f
Author: Alexandre Oliva
Date: Sun Apr 28 04:30:19 2024 -0300
ppc: testsuite: vec-mul requires vsx runtime
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d..aa0ef7aa45a 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,5 +1,5 @@
-/* { dg-do run } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-do compile { target { { ! vsx_hw } && powerpc_vsx_ok } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-options "-mvsx -O3" } */
/* Test that the vec_mul builtin works as expected. */
[gcc r15-20] xfail fetestexcept test - ppc always uses fcmpu
https://gcc.gnu.org/g:6e95dca31c6b4688e0f0a25c9c3aa8a0bedc9056
commit r15-20-g6e95dca31c6b4688e0f0a25c9c3aa8a0bedc9056
Author: Alexandre Oliva
Date: Sun Apr 28 04:30:24 2024 -0300
xfail fetestexcept test - ppc always uses fcmpu
gcc.dg/torture/pr91323.c tests that a compare with NaNf doesn't set an
exception using builtin compare intrinsics, and that it does when
using regular compare operators.
That doesn't seem to be expected to work on powerpc targets. It fails
on GNU/Linux, it's marked to be skipped on AIX, and a similar test,
gcc.dg/torture/pr93133.c, has the execution test xfailed for all of
powerpc*-*-*.
In this test, the functions that use intrinsics for the compare end up
with the same code as the one that uses compare operators, using
fcmpu, a floating compare that, unlike fcmpo, does not set the invalid
operand exception for quiet NaN. I couldn't find any evidence that
the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
execution xfail marker to this test.
for gcc/testsuite/ChangeLog
PR target/58684
* gcc.dg/torture/pr91323.c: Expect execution fail on
powerpc*-*-*.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr91323.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr91323.c
b/gcc/testsuite/gcc.dg/torture/pr91323.c
index 1411fcaa396..4574342e728 100644
--- a/gcc/testsuite/gcc.dg/torture/pr91323.c
+++ b/gcc/testsuite/gcc.dg/torture/pr91323.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do run { xfail powerpc*-*-* } } */
+/* remove the xfail for powerpc when pr58684 is fixed */
/* { dg-add-options ieee } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-skip-if "fenv" { powerpc-ibm-aix* } } */
[gcc r15-18] disable ldist for test, to restore vectorizing-candidate loop
https://gcc.gnu.org/g:cc6a439fdab933963b00c488e221ae33d7199aeb
commit r15-18-gcc6a439fdab933963b00c488e221ae33d7199aeb
Author: Alexandre Oliva
Date: Sun Apr 28 04:30:15 2024 -0300
disable ldist for test, to restore vectorizing-candidate loop
The loop we're supposed to try to vectorize in
gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c is turned into a memset
before the vectorizer runs.
Various other tests in this set have already run into this, and the
solution has been to disable this loop distribution transformation,
enabled at -O2, so that the vectorizer gets a chance to transform the
loop and, in this testcase, fail to do so.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c: Disable
ldist.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
index 454a714a309..90b5d5a7f40 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
@@ -1,4 +1,5 @@
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-fno-tree-loop-distribute-patterns" } */
#include
#include "../../tree-vect.h"
[gcc r15-17] Request check for hw support in ppc run tests with -maltivec/-mvsx
https://gcc.gnu.org/g:9929a683dae6d8d584acef38a8652f186492560f
commit r15-17-g9929a683dae6d8d584acef38a8652f186492560f
Author: Olivier Hainque
Date: Sun Apr 28 04:30:06 2024 -0300
Request check for hw support in ppc run tests with -maltivec/-mvsx
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/swaps-p8-20.c: Change powerpc_altivec_ok
require-effective-target test into vmx_hw.
* gcc.target/powerpc/vsx-vector-5.c: Change powerpc_vsx_ok
require-effective-target test into vsx_hw.
Diff:
---
gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c | 5 +
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
index 564e8acb1f4..755519bfe84 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target vmx_hw } */
/* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec" } */
/* The expansion for vector character multiply introduces a vperm operation.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
index dcc88b1f3a4..37a324b6f89 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
@@ -1,11 +1,8 @@
/* { dg-do run { target lp64 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target vsx_hw } */
/* { dg-options "-mvsx -O2" } */
-/* This will run, and someday we should add the support to test whether we are
- running on VSX hardware. */
-
#include
#include
[gcc r15-16] [testsuite] [ppc64] expect error on vxworks too
https://gcc.gnu.org/g:818ec41d50bc906523f8fd86d7c463dd90e16d24
commit r15-16-g818ec41d50bc906523f8fd86d7c463dd90e16d24
Author: Alexandre Oliva
Date: Sun Apr 28 04:30:00 2024 -0300
[testsuite] [ppc64] expect error on vxworks too
These ppc lp64 tests check for errors or warnings on -mno-powerpc64.
On powerpc64-*-vxworks* we get the same errors as on most other
covered platforms, but the tests did not mark them as expected for
this target. On powerpc-*-vxworks*, the tests are skipped because
lp64 is not satisfied, so I'm naming powerpc*-*-vxworks* rather than
something more specific.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr106680-1.c: Error on vxworks too.
* gcc.target/powerpc/pr106680-2.c: Likewise.
* gcc.target/powerpc/pr106680-3.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr106680-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr106680-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr106680-3.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
index d624d43230a..aadaa614cfe 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
@@ -8,6 +8,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
index a9ed73726ef..f0758e30335 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
@@ -9,6 +9,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
index b642d5c7a00..bca012e2cf6 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
@@ -8,6 +8,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
[gcc r15-15] decay vect tests from run to link for pr95401
https://gcc.gnu.org/g:05d83334d5bbeae01d71080f1da524810d6740d9
commit r15-15-g05d83334d5bbeae01d71080f1da524810d6740d9
Author: Alexandre Oliva
Date: Sun Apr 28 04:29:54 2024 -0300
decay vect tests from run to link for pr95401
When vect.exp finds our configuration disables altivec by default, it
disables the execution of vectorization tests, assuming the test
hardware doesn't support it.
Tests become just compile tests, but compile tests won't work
correctly when additional sources are named, e.g. pr95401.cc, because
GCC refuses to compile multiple files into the same asm output.
With this patch, the default for when execution is not possible
becomes link.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_vect_support_and_set_flags):
Decay to link rather than compile.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3a55b2a4159..182d80129de 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11625,7 +11625,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11655,14 +11655,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11681,7 +11681,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11694,7 +11694,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11707,7 +11707,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11731,7 +11731,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
@@ -11742,7 +11742,7 @@ proc check_vect_support_and_set_flags { } {
foreach item [add_options_for_riscv_v ""] {
lappend DEFAULT_VECTCFLAGS $item
}
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} elseif [istarget loongarch*-*-*] {
# Set the default vectorization option to "-mlsx" due to the problem
@@ -11751,7 +11751,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_loongarch_sx_hw] {
set dg-do-what-default run
} else {
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} else {
return 0
[gcc(refs/users/aoliva/heads/testme)] adjust iteration count for ppc costmodel 76b
https://gcc.gnu.org/g:ec1d688d102cd30572320e7224b55127182e2432 commit ec1d688d102cd30572320e7224b55127182e2432 Author: Kewen Lin Date: Sun Apr 28 01:43:51 2024 -0300 adjust iteration count for ppc costmodel 76b The original intention of this case is to expect not profitable for peeling. Tweak the loop bound to make this loop not profitable to be vectorized for !vect_no_align with peeling (both pwr7 and pwr6) and keep consistent. for gcc/testsuite/ChangeLog * gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c (N): Tweak. Diff: --- gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c index cbbfbb24658..e48b0ab759e 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c @@ -6,7 +6,7 @@ /* On Power7 without misalign vector support, this case is to check it's not profitable to perform vectorization by peeling to align the store. */ -#define N 14 +#define N 13 #define OFF 4 /* Check handling of accesses for which the "initial condition" -
[gcc(refs/users/aoliva/heads/testme)] [testsuite] require sqrt_insn effective target where needed
https://gcc.gnu.org/g:df1330158bb0926d6af9a3d115dd63a931a3006d
commit df1330158bb0926d6af9a3d115dd63a931a3006d
Author: Alexandre Oliva
Date: Mon Apr 22 01:12:55 2024 -0300
[testsuite] require sqrt_insn effective target where needed
Some tests fail on ppc and ppc64 when testing a compiler [with options
for] for a CPU [emulator] that doesn't support the sqrt insn.
The gcc.dg/cdce3.c is one in which the expected shrink-wrap
optimization only takes place when the target CPU supports a sqrt
insn.
The gcc.target/powerpc/pr46728-1[0-4].c tests use -mpowerpc-gpopt and
call sqrt(), which involves the sqrt insn that the target CPU under
test may not support.
Require a sqrt_insn effective target for all the affected tests.
for gcc/testsuite/ChangeLog
* gcc.dg/cdce3.c: Require sqrt_insn effective target.
* gcc.target/powerpc/pr46728-10.c: Likewise. Drop darwin
explicit skipping.
* gcc.target/powerpc/pr46728-11.c: Likewise. Likewise.
* gcc.target/powerpc/pr46728-13.c: Likewise. Likewise.
* gcc.target/powerpc/pr46728-14.c: Likewise. Likewise.
Diff:
---
gcc/testsuite/gcc.dg/cdce3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-10.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr46728-11.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr46728-13.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr46728-14.c | 2 +-
5 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/cdce3.c b/gcc/testsuite/gcc.dg/cdce3.c
index 601ddf055fd..f759a95972e 100644
--- a/gcc/testsuite/gcc.dg/cdce3.c
+++ b/gcc/testsuite/gcc.dg/cdce3.c
@@ -1,7 +1,8 @@
/* { dg-do compile } */
/* { dg-require-effective-target hard_float } */
+/* { dg-require-effective-target sqrt_insn } */
/* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details
-fdump-tree-optimized" } */
-/* { dg-final { scan-tree-dump "cdce3.c:11: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
+/* { dg-final { scan-tree-dump "cdce3.c:12: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
/* { dg-final { scan-tree-dump "sqrtf \\(\[^\n\r]*\\); \\\[tail call\\\]"
"optimized" } } */
/* { dg-skip-if "doesn't have a sqrtf insn" { mmix-*-* } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
index 3be4728d333..c04a3101c11 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
-/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
index 43b6728a4b8..d0e3d602121 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
-/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
index b9fd63973b7..2b9df737a9b 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
-/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
index 5a13bdb..e6836f515e4 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
@@ -1,6 +1,6 @@
/* { dg-do run } */
-/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
[gcc(refs/users/aoliva/heads/testme)] xfail fetestexcept test - ppc always uses fcmpu
https://gcc.gnu.org/g:22b9a800e1cbf491f98a2813ef4c09463d76aaf1
commit 22b9a800e1cbf491f98a2813ef4c09463d76aaf1
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:11 2024 -0300
xfail fetestexcept test - ppc always uses fcmpu
gcc.dg/torture/pr91323.c tests that a compare with NaNf doesn't set an
exception using builtin compare intrinsics, and that it does when
using regular compare operators.
That doesn't seem to be expected to work on powerpc targets. It fails
on GNU/Linux, it's marked to be skipped on AIX, and a similar test,
gcc.dg/torture/pr93133.c, has the execution test xfailed for all of
powerpc*-*-*.
In this test, the functions that use intrinsics for the compare end up
with the same code as the one that uses compare operators, using
fcmpu, a floating compare that, unlike fcmpo, does not set the invalid
operand exception for quiet NaN. I couldn't find any evidence that
the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
execution xfail marker to this test.
for gcc/testsuite/ChangeLog
PR target/58684
* gcc.dg/torture/pr91323.c: Expect execution fail on
powerpc*-*-*.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr91323.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr91323.c
b/gcc/testsuite/gcc.dg/torture/pr91323.c
index 1411fcaa396..4574342e728 100644
--- a/gcc/testsuite/gcc.dg/torture/pr91323.c
+++ b/gcc/testsuite/gcc.dg/torture/pr91323.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do run { xfail powerpc*-*-* } } */
+/* remove the xfail for powerpc when pr58684 is fixed */
/* { dg-add-options ieee } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-skip-if "fenv" { powerpc-ibm-aix* } } */
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: pr79004 needs -mlong-double-128
https://gcc.gnu.org/g:b40c8c90da105a4628907dccecf571db059d86f3
commit b40c8c90da105a4628907dccecf571db059d86f3
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:28 2024 -0300
ppc: testsuite: pr79004 needs -mlong-double-128
Some of the asm opcodes expected by pr79004 depend on
-mlong-double-128 to be output. E.g., without this flag, the
conditions of patterns @extenddf2 and extendsf2 do not
hold, and so GCC resorts to libcalls instead of even trying
rs6000_expand_float128_convert.
Perhaps the conditions are too strict, and they could enable the use
of conversion insns involving __ieee128/_Float128 even with 64-bit
long doubles. Alas, for now, we need this flag for the test to pass
on target variants that use 64-bit long doubles.
for gcc/testsuite/ChangeLog
PR target/105359
* gcc.target/powerpr/pr79004.c: Add -mlong-double-128 as a
temporary workaround.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr79004.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79004.c
b/gcc/testsuite/gcc.target/powerpc/pr79004.c
index caf1f6c1eef..83f20ca2243 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79004.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79004.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mfloat128" } */
+/* { dg-additional-options "-mlong-double-128" } */
#include
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: vec-mul requires vsx runtime
https://gcc.gnu.org/g:12759057f7d42045403e7c41216e51c50d26afc9
commit 12759057f7d42045403e7c41216e51c50d26afc9
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:37 2024 -0300
ppc: testsuite: vec-mul requires vsx runtime
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
To check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d..aa0ef7aa45a 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,5 +1,5 @@
-/* { dg-do run } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-do compile { target { { ! vsx_hw } && powerpc_vsx_ok } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-options "-mvsx -O3" } */
/* Test that the vec_mul builtin works as expected. */
[gcc(refs/users/aoliva/heads/testme)] make -freg-struct-return visibly a negative alias of -fpcc-struct-return
https://gcc.gnu.org/g:4c42beadc660572409d3e6f452bf4c0209f320c3 commit 4c42beadc660572409d3e6f452bf4c0209f320c3 Author: Alexandre Oliva Date: Tue Apr 23 00:33:04 2024 -0300 make -freg-struct-return visibly a negative alias of -fpcc-struct-return The fact that both options accept negative forms suggests that maybe they aren't negative forms of each other. They are, but that isn't clear even by examining common.opt. Use NegativeAlias to make it abundantly clear. The 'Optimization' keyword next to freg-struct-return was the only thing that caused flag_pcc_struct_return to be a per-function flag, and ipa-inline relied on that. After making it an alias, the Optimization keyword was no longer operational. I'm not sure it was sensible or desirable for flag_pcc_struct_return to be a per-function setting, but this patch does not intend to change behavior. for gcc/ChangeLog * common.opt (freg-struct-return): Make it explicitly fpcc-struct-return's NegativeAlias. Copy Optimization... (freg-struct-return): ... here. Diff: --- gcc/common.opt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/common.opt b/gcc/common.opt index ad348844775..12d93c76a1e 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -2406,7 +2406,7 @@ Common RejectNegative Joined UInteger Optimization -fpack-struct= Set initial maximum structure member alignment. fpcc-struct-return -Common Var(flag_pcc_struct_return,1) Init(DEFAULT_PCC_STRUCT_RETURN) +Common Var(flag_pcc_struct_return,1) Init(DEFAULT_PCC_STRUCT_RETURN) Optimization Return small aggregates in memory, not registers. fpeel-loops @@ -2596,7 +2596,7 @@ Common Var(flag_record_gcc_switches) Record gcc command line switches in the object file. freg-struct-return -Common Var(flag_pcc_struct_return,0) Optimization +Common NegativeAlias Alias(fpcc_struct_return) Optimization Return small aggregates in registers. fregmove
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:7ef60541a89b2e7b3585df434d14010396769ca2
commit 7ef60541a89b2e7b3585df434d14010396769ca2
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..46a3ebfa287 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fpcc-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:760577dcf78b33b9e8a2256bb122e824187bd2ab
commit 760577dcf78b33b9e8a2256bb122e824187bd2ab
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..e69d9253e2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,12 +13,11 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlfdx\M|\mlfd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfdx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..9ff197a7049 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,13 +12,12 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* -m32 has lfs in place of lfsx */
-/* { dg-final { scan-assembler-times {\mlfsx\M|\mlfs\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfsx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..cc3c803b49c 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final {
[gcc(refs/users/aoliva/heads/testme)] decay vect tests from run to link for pr95401
https://gcc.gnu.org/g:7d9771291b4943de287cadd09d94a80512158376
commit 7d9771291b4943de287cadd09d94a80512158376
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:21 2024 -0300
decay vect tests from run to link for pr95401
When vect.exp finds our configuration disables altivec by default, it
disables the execution of vectorization tests, assuming the test
hardware doesn't support it.
Tests become just compile tests, but compile tests won't work
correctly when additional sources are named, e.g. pr95401.cc, because
GCC refuses to compile multiple files into the same asm output.
With this patch, the default for when execution is not possible
becomes link.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_vect_support_and_set_flags):
Decay to link rather than compile.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3a5713d9869..54a55585371 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11625,7 +11625,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11655,14 +11655,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11681,7 +11681,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11694,7 +11694,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11707,7 +11707,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11731,7 +11731,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
@@ -11742,7 +11742,7 @@ proc check_vect_support_and_set_flags { } {
foreach item [add_options_for_riscv_v ""] {
lappend DEFAULT_VECTCFLAGS $item
}
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} elseif [istarget loongarch*-*-*] {
# Set the default vectorization option to "-mlsx" due to the problem
@@ -11751,7 +11751,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_loongarch_sx_hw] {
set dg-do-what-default run
} else {
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} else {
return 0
[gcc(refs/users/aoliva/heads/testme)] Request check for hw support in ppc run tests with -maltivec/-mvsx
https://gcc.gnu.org/g:9cb06df620798c762a344e61e574384c8e80b083
commit 9cb06df620798c762a344e61e574384c8e80b083
Author: Olivier Hainque
Date: Sun Apr 21 17:24:24 2024 -0300
Request check for hw support in ppc run tests with -maltivec/-mvsx
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/swaps-p8-20.c: Change powerpc_altivec_ok
require-effective-target test into vmx_hw.
* gcc.target/powerpc/vsx-vector-5.c: Change powerpc_vsx_ok
require-effective-target test into vsx_hw.
Diff:
---
gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c | 5 +
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
index 564e8acb1f4..755519bfe84 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target vmx_hw } */
/* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec" } */
/* The expansion for vector character multiply introduces a vperm operation.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
index dcc88b1f3a4..37a324b6f89 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
@@ -1,11 +1,8 @@
/* { dg-do run { target lp64 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target vsx_hw } */
/* { dg-options "-mvsx -O2" } */
-/* This will run, and someday we should add the support to test whether we are
- running on VSX hardware. */
-
#include
#include
[gcc/aoliva/heads/testme] (10 commits) adjust iteration count for ppc costmodel 76b
The branch 'aoliva/heads/testme' was updated to point to: ec1d688d102... adjust iteration count for ppc costmodel 76b It previously pointed to: ffb3aca361d... make -freg-struct-return visibly a negative alias of -fpcc- Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- ffb3aca... make -freg-struct-return visibly a negative alias of -fpcc- 30e8256... add explicit ABI and align options to pr88233.c 9aad468... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra f7a0734... decay vect tests from run to link for pr95401 2062c8d... xfail fetestexcept test - ppc always uses fcmpu 4923693... [testsuite] require sqrt_insn effective target where needed 25b2dc8... ppc: testsuite: vec-mul requires vsx runtime 9c266e6... ppc: testsuite: pr79004 needs -mlong-double-128 b610d91... Request check for hw support in ppc run tests with -maltive 06cec5e... adjust vectorization expectations for ppc costmodel 76b Summary of changes (added commits): --- ec1d688... adjust iteration count for ppc costmodel 76b df13301... [testsuite] require sqrt_insn effective target where needed 22b9a80... xfail fetestexcept test - ppc always uses fcmpu b40c8c9... ppc: testsuite: pr79004 needs -mlong-double-128 1275905... ppc: testsuite: vec-mul requires vsx runtime 4c42bea... make -freg-struct-return visibly a negative alias of -fpcc- 7ef6054... add explicit ABI and align options to pr88233.c 760577d... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 7d97712... decay vect tests from run to link for pr95401 9cb06df... Request check for hw support in ppc run tests with -maltive
[gcc(refs/users/aoliva/heads/testme)] make -freg-struct-return visibly a negative alias of -fpcc-struct-return
https://gcc.gnu.org/g:ffb3aca361d2b0e9ba415930a0fc61e8219c635c commit ffb3aca361d2b0e9ba415930a0fc61e8219c635c Author: Alexandre Oliva Date: Tue Apr 23 00:33:04 2024 -0300 make -freg-struct-return visibly a negative alias of -fpcc-struct-return The fact that both options accept negative forms suggests that maybe they aren't negative forms of each other. They are, but that isn't clear even by examining common.opt. Use NegativeAlias to make it abundantly clear. The 'Optimization' keyword next to freg-struct-return was the only thing that caused flag_pcc_struct_return to be a per-function flag, and ipa-inline relied on that. After making it an alias, the Optimization keyword was no longer operational. I'm not sure it was sensible or desirable for flag_pcc_struct_return to be a per-function setting, but this patch does not intend to change behavior. for gcc/ChangeLog * common.opt (freg-struct-return): Make it explicitly fpcc-struct-return's NegativeAlias. Copy Optimization... (freg-struct-return): ... here. Diff: --- gcc/common.opt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/common.opt b/gcc/common.opt index ad348844775..12d93c76a1e 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -2406,7 +2406,7 @@ Common RejectNegative Joined UInteger Optimization -fpack-struct= Set initial maximum structure member alignment. fpcc-struct-return -Common Var(flag_pcc_struct_return,1) Init(DEFAULT_PCC_STRUCT_RETURN) +Common Var(flag_pcc_struct_return,1) Init(DEFAULT_PCC_STRUCT_RETURN) Optimization Return small aggregates in memory, not registers. fpeel-loops @@ -2596,7 +2596,7 @@ Common Var(flag_record_gcc_switches) Record gcc command line switches in the object file. freg-struct-return -Common Var(flag_pcc_struct_return,0) Optimization +Common NegativeAlias Alias(fpcc_struct_return) Optimization Return small aggregates in registers. fregmove
[gcc/aoliva/heads/testme] make -freg-struct-return visibly a negative alias of -fpcc-
The branch 'aoliva/heads/testme' was updated to point to: ffb3aca361d... make -freg-struct-return visibly a negative alias of -fpcc- It previously pointed to: 60e63cf86f9... make -freg-struct-return visibly a negative alias of -fpcc- Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 60e63cf... make -freg-struct-return visibly a negative alias of -fpcc- Summary of changes (added commits): --- ffb3aca... make -freg-struct-return visibly a negative alias of -fpcc-
[gcc(refs/users/aoliva/heads/testme)] make -freg-struct-return visibly a negative alias of -fpcc-struct-return
https://gcc.gnu.org/g:60e63cf86f91608df32377f9ffc7c3f3e9f316fd commit 60e63cf86f91608df32377f9ffc7c3f3e9f316fd Author: Alexandre Oliva Date: Tue Apr 23 00:33:04 2024 -0300 make -freg-struct-return visibly a negative alias of -fpcc-struct-return The fact that both options accept negative forms suggests that maybe they aren't negative forms of each other. They are, but that isn't clear even by examining common.opt. Use NegativeAlias to make it abundantly clear. for gcc/ChangeLog * common.opt (freg-struct-return): Make it explicitly fpcc-struct-return's NegativeAlias. Diff: --- gcc/common.opt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/common.opt b/gcc/common.opt index ad348844775..12d93c76a1e 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -2406,7 +2406,7 @@ Common RejectNegative Joined UInteger Optimization -fpack-struct= Set initial maximum structure member alignment. fpcc-struct-return -Common Var(flag_pcc_struct_return,1) Init(DEFAULT_PCC_STRUCT_RETURN) +Common Var(flag_pcc_struct_return,1) Init(DEFAULT_PCC_STRUCT_RETURN) Optimization Return small aggregates in memory, not registers. fpeel-loops @@ -2596,7 +2596,7 @@ Common Var(flag_record_gcc_switches) Record gcc command line switches in the object file. freg-struct-return -Common Var(flag_pcc_struct_return,0) Optimization +Common NegativeAlias Alias(fpcc_struct_return) Optimization Return small aggregates in registers. fregmove
[gcc/aoliva/heads/testme] make -freg-struct-return visibly a negative alias of -fpcc-
The branch 'aoliva/heads/testme' was updated to point to: 60e63cf86f9... make -freg-struct-return visibly a negative alias of -fpcc- It previously pointed to: 9d8a2a67a84... make -freg-struct-return visibly a negative alias of -fpcc- Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 9d8a2a6... make -freg-struct-return visibly a negative alias of -fpcc- Summary of changes (added commits): --- 60e63cf... make -freg-struct-return visibly a negative alias of -fpcc-
[gcc(refs/users/aoliva/heads/testme)] make -freg-struct-return visibly a negative alias of -fpcc-struct-return
https://gcc.gnu.org/g:9d8a2a67a84deaaf0645a73d17564d68059b2433 commit 9d8a2a67a84deaaf0645a73d17564d68059b2433 Author: Alexandre Oliva Date: Tue Apr 23 00:33:04 2024 -0300 make -freg-struct-return visibly a negative alias of -fpcc-struct-return The fact that both options accept negative forms suggests that maybe they aren't negative forms of each other. They are, but that isn't clear even by examining common.opt. Use NegativeAlias to make it abundantly clear. for gcc/ChangeLog * common.opt (freg-struct-return): Make it explicitly fpcc-struct-return's NegativeAlias. Diff: --- gcc/common.opt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/common.opt b/gcc/common.opt index ad348844775..f973d767584 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -2596,7 +2596,7 @@ Common Var(flag_record_gcc_switches) Record gcc command line switches in the object file. freg-struct-return -Common Var(flag_pcc_struct_return,0) Optimization +Common NegativeAlias Alias(fpcc_struct_return) Optimization Return small aggregates in registers. fregmove
[gcc/aoliva/heads/testme] make -freg-struct-return visibly a negative alias of -fpcc-
The branch 'aoliva/heads/testme' was updated to point to: 9d8a2a67a84... make -freg-struct-return visibly a negative alias of -fpcc- It previously pointed to: e50550cae7e... make -freg-struct-return visibly a negative alias of -fpcc- Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- e50550c... make -freg-struct-return visibly a negative alias of -fpcc- Summary of changes (added commits): --- 9d8a2a6... make -freg-struct-return visibly a negative alias of -fpcc-
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:30e8256702cc4dfb56d329ee279e957a10fc962b
commit 30e8256702cc4dfb56d329ee279e957a10fc962b
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..46a3ebfa287 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fpcc-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc(refs/users/aoliva/heads/testme)] make -freg-struct-return visibly a negative alias of -fpcc-struct-return
https://gcc.gnu.org/g:e50550cae7e3108d7f7a0ba2f9b8f14c16e29e35 commit e50550cae7e3108d7f7a0ba2f9b8f14c16e29e35 Author: Alexandre Oliva Date: Tue Apr 23 00:33:04 2024 -0300 make -freg-struct-return visibly a negative alias of -fpcc-struct-return The fact that both options accept negative forms suggests that maybe they aren't negative forms of each other. They are, but that isn't clear even by examining common.opt. Use NegativeAlias to make it abundantly clear. for gcc/ChangeLog * common.opt (freg-struct-return): Make it explicitly fpcc-struct-return's NegativeAlias. Diff: --- gcc/common.opt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/common.opt b/gcc/common.opt index ad348844775..ebef5977451 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -2596,7 +2596,7 @@ Common Var(flag_record_gcc_switches) Record gcc command line switches in the object file. freg-struct-return -Common Var(flag_pcc_struct_return,0) Optimization +Common NegativeAlias Alias(pcc_struct_return) Optimization Return small aggregates in registers. fregmove
[gcc/aoliva/heads/testme] (2 commits) make -freg-struct-return visibly a negative alias of -fpcc-
The branch 'aoliva/heads/testme' was updated to point to: e50550cae7e... make -freg-struct-return visibly a negative alias of -fpcc- It previously pointed to: 68e3d62f56e... add explicit ABI and align options to pr88233.c Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 68e3d62... add explicit ABI and align options to pr88233.c Summary of changes (added commits): --- e50550c... make -freg-struct-return visibly a negative alias of -fpcc- 30e8256... add explicit ABI and align options to pr88233.c
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:68e3d62f56eea3a5fa798ec514bd89ddc6668c4a
commit 68e3d62f56eea3a5fa798ec514bd89ddc6668c4a
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..7ea459cb802 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fno-reg-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc(refs/users/aoliva/heads/testme)] decay vect tests from run to link for pr95401
https://gcc.gnu.org/g:f7a0734ee96341645e18e183210deb0d9a0c97d7
commit f7a0734ee96341645e18e183210deb0d9a0c97d7
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:21 2024 -0300
decay vect tests from run to link for pr95401
When vect.exp finds our configuration disables altivec by default, it
disables the execution of vectorization tests, assuming the test
hardware doesn't support it.
Tests become just compile tests, but compile tests won't work
correctly when additional sources are named, e.g. pr95401.cc, because
GCC refuses to compile multiple files into the same asm output.
With this patch, the default for when execution is not possible
becomes link.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_vect_support_and_set_flags):
Decay to link rather than compile.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3a5713d9869..54a55585371 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11625,7 +11625,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11655,14 +11655,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11681,7 +11681,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11694,7 +11694,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11707,7 +11707,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11731,7 +11731,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
@@ -11742,7 +11742,7 @@ proc check_vect_support_and_set_flags { } {
foreach item [add_options_for_riscv_v ""] {
lappend DEFAULT_VECTCFLAGS $item
}
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} elseif [istarget loongarch*-*-*] {
# Set the default vectorization option to "-mlsx" due to the problem
@@ -11751,7 +11751,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_loongarch_sx_hw] {
set dg-do-what-default run
} else {
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} else {
return 0
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:9aad4681cb81920420e3cef32d02acf4bec891d6
commit 9aad4681cb81920420e3cef32d02acf4bec891d6
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..e69d9253e2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,12 +13,11 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlfdx\M|\mlfd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfdx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..9ff197a7049 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,13 +12,12 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* -m32 has lfs in place of lfsx */
-/* { dg-final { scan-assembler-times {\mlfsx\M|\mlfs\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfsx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..cc3c803b49c 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final {
[gcc(refs/users/aoliva/heads/testme)] xfail fetestexcept test - ppc always uses fcmpu
https://gcc.gnu.org/g:2062c8d2122c4b7dc82af9a7114136ca371da5ff
commit 2062c8d2122c4b7dc82af9a7114136ca371da5ff
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:11 2024 -0300
xfail fetestexcept test - ppc always uses fcmpu
gcc.dg/torture/pr91323.c tests that a compare with NaNf doesn't set an
exception using builtin compare intrinsics, and that it does when
using regular compare operators.
That doesn't seem to be expected to work on powerpc targets. It fails
on GNU/Linux, it's marked to be skipped on AIX, and a similar test,
gcc.dg/torture/pr93133.c, has the execution test xfailed for all of
powerpc*-*-*.
In this test, the functions that use intrinsics for the compare end up
with the same code as the one that uses compare operators, using
fcmpu, a floating compare that, unlike fcmpo, does not set the invalid
operand exception for quiet NaN. I couldn't find any evidence that
the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
execution xfail marker to this test.
for gcc/testsuite/ChangeLog
PR target/58684
* gcc.dg/torture/pr91323.c: Expect execution fail on
powerpc*-*-*.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr91323.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr91323.c
b/gcc/testsuite/gcc.dg/torture/pr91323.c
index 1411fcaa396..f188faa3ccf 100644
--- a/gcc/testsuite/gcc.dg/torture/pr91323.c
+++ b/gcc/testsuite/gcc.dg/torture/pr91323.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do run { xfail powerpc*-*-* } } */
+/* The ppc xfail is because of PR target/58684. */
/* { dg-add-options ieee } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-skip-if "fenv" { powerpc-ibm-aix* } } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] require sqrt_insn effective target where needed
https://gcc.gnu.org/g:4923693ac47e4bb3d6a6d72dd538fbeec68c478d
commit 4923693ac47e4bb3d6a6d72dd538fbeec68c478d
Author: Alexandre Oliva
Date: Mon Apr 22 01:12:55 2024 -0300
[testsuite] require sqrt_insn effective target where needed
Some tests fail on ppc and ppc64 when testing a compiler [with options
for] for a CPU [emulator] that doesn't support the sqrt insn.
The gcc.dg/cdce3.c is one in which the expected shrink-wrap
optimization only takes place when the target CPU supports a sqrt
insn.
The gcc.target/powerpc/pr46728-1[0-4].c tests use -mpowerpc-gpopt and
call sqrt(), which involves the sqrt insn that the target CPU under
test may not support.
Require a sqrt_insn effective target for all the affected tests.
for gcc/testsuite/ChangeLog
* gcc.dg/cdce3.c: Require sqrt_insn effective target.
* gcc.target/powerpc/pr46728-10.c: Likewise.
* gcc.target/powerpc/pr46728-11.c: Likewise.
* gcc.target/powerpc/pr46728-13.c: Likewise.
* gcc.target/powerpc/pr46728-14.c: Likewise.
Diff:
---
gcc/testsuite/gcc.dg/cdce3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-10.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-11.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-13.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-14.c | 1 +
5 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/cdce3.c b/gcc/testsuite/gcc.dg/cdce3.c
index 601ddf055fd..f759a95972e 100644
--- a/gcc/testsuite/gcc.dg/cdce3.c
+++ b/gcc/testsuite/gcc.dg/cdce3.c
@@ -1,7 +1,8 @@
/* { dg-do compile } */
/* { dg-require-effective-target hard_float } */
+/* { dg-require-effective-target sqrt_insn } */
/* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details
-fdump-tree-optimized" } */
-/* { dg-final { scan-tree-dump "cdce3.c:11: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
+/* { dg-final { scan-tree-dump "cdce3.c:12: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
/* { dg-final { scan-tree-dump "sqrtf \\(\[^\n\r]*\\); \\\[tail call\\\]"
"optimized" } } */
/* { dg-skip-if "doesn't have a sqrtf insn" { mmix-*-* } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
index 3be4728d333..7e9bb638106 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
index 43b6728a4b8..5bfa2592567 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
index b9fd63973b7..b66d0209a5e 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
index 5a13bdb..71a1a70c4e7 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
[gcc/aoliva/heads/testme] (5 commits) add explicit ABI and align options to pr88233.c
The branch 'aoliva/heads/testme' was updated to point to: 68e3d62f56e... add explicit ABI and align options to pr88233.c It previously pointed to: edf330eeb9d... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- edf330e... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 960142e... decay vect tests from run to link for pr95401 1dd110c... xfail fetestexcept test - ppc always uses fcmpu cef8842... [testsuite] require sqrt_insn effective target where needed c5fbace... add explicit ABI and align options to pr88233.c Summary of changes (added commits): --- 68e3d62... add explicit ABI and align options to pr88233.c 9aad468... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra f7a0734... decay vect tests from run to link for pr95401 2062c8d... xfail fetestexcept test - ppc always uses fcmpu 4923693... [testsuite] require sqrt_insn effective target where needed
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:edf330eeb9d4832b1972516bcf6b54cd897e5fa9
commit edf330eeb9d4832b1972516bcf6b54cd897e5fa9
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 5 ++---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..e69d9253e2d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,12 +13,11 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlfdx\M|\mlfd\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfdx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..9ff197a7049 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,13 +12,12 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi?\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* -m32 has lfs in place of lfsx */
-/* { dg-final { scan-assembler-times {\mlfsx\M|\mlfs\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfsx?\M} 1 } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..cc3c803b49c 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final {
[gcc(refs/users/aoliva/heads/testme)] decay vect tests from run to link for pr95401
https://gcc.gnu.org/g:960142effc3218ccb3463464d3dbe3c0ce3d5280
commit 960142effc3218ccb3463464d3dbe3c0ce3d5280
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:21 2024 -0300
decay vect tests from run to link for pr95401
When vect.exp finds our configuration disables altivec by default, it
disables the execution of vectorization tests, assuming the test
hardware doesn't support it.
Tests become just compile tests, but compile tests won't work
correctly when additional sources are named, e.g. pr95401.cc, because
GCC refuses to compile multiple files into the same asm output.
With this patch, the default for when execution is not possible
becomes link.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_vect_support_and_set_flags):
Decay to link rather than compile.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3a5713d9869..54a55585371 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11625,7 +11625,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11655,14 +11655,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11681,7 +11681,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11694,7 +11694,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11707,7 +11707,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11731,7 +11731,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
@@ -11742,7 +11742,7 @@ proc check_vect_support_and_set_flags { } {
foreach item [add_options_for_riscv_v ""] {
lappend DEFAULT_VECTCFLAGS $item
}
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} elseif [istarget loongarch*-*-*] {
# Set the default vectorization option to "-mlsx" due to the problem
@@ -11751,7 +11751,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_loongarch_sx_hw] {
set dg-do-what-default run
} else {
- set dg-do-what-default compile
+ set dg-do-what-default link
}
} else {
return 0
[gcc(refs/users/aoliva/heads/testme)] xfail fetestexcept test - ppc always uses fcmpu
https://gcc.gnu.org/g:1dd110cf0d45a2716102a53cc42f809e29d909ae
commit 1dd110cf0d45a2716102a53cc42f809e29d909ae
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:11 2024 -0300
xfail fetestexcept test - ppc always uses fcmpu
gcc.dg/torture/pr91323.c tests that a compare with NaNf doesn't set an
exception using builtin compare intrinsics, and that it does when
using regular compare operators.
That doesn't seem to be expected to work on powerpc targets. It fails
on GNU/Linux, it's marked to be skipped on AIX, and a similar test,
gcc.dg/torture/pr93133.c, has the execution test xfailed for all of
powerpc*-*-*.
In this test, the functions that use intrinsics for the compare end up
with the same code as the one that uses compare operators, using
fcmpu, a floating compare that, unlike fcmpo, does not set the invalid
operand exception for quiet NaN. I couldn't find any evidence that
the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
execution xfail marker to this test.
for gcc/testsuite/ChangeLog
PR target/58684
* gcc.dg/torture/pr91323.c: Expect execution fail on
powerpc*-*-*.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr91323.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr91323.c
b/gcc/testsuite/gcc.dg/torture/pr91323.c
index 1411fcaa396..f188faa3ccf 100644
--- a/gcc/testsuite/gcc.dg/torture/pr91323.c
+++ b/gcc/testsuite/gcc.dg/torture/pr91323.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do run { xfail powerpc*-*-* } } */
+/* The ppc xfail is because of PR target/58684. */
/* { dg-add-options ieee } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-skip-if "fenv" { powerpc-ibm-aix* } } */
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:c5fbacee0313fb1b760a870964877f343bf4b90e
commit c5fbacee0313fb1b760a870964877f343bf4b90e
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..46a3ebfa287 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fpcc-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] require sqrt_insn effective target where needed
https://gcc.gnu.org/g:cef88428efe311383bc65c47e4f6c96a8b16452a
commit cef88428efe311383bc65c47e4f6c96a8b16452a
Author: Alexandre Oliva
Date: Mon Apr 22 01:12:55 2024 -0300
[testsuite] require sqrt_insn effective target where needed
Some tests fail on ppc and ppc64 when testing a compiler [with options
for] for a CPU [emulator] that doesn't support the sqrt insn.
The gcc.dg/cdce3.c is one in which the expected shrink-wrap
optimization only takes place when the target CPU supports a sqrt
insn.
The gcc.target/powerpc/pr46728-1[0-4].c tests use -mpowerpc-gpopt and
call sqrt(), which involves the sqrt insn that the target CPU under
test may not support.
Require a sqrt_insn effective target for all the affected tests.
for gcc/testsuite/ChangeLog
* gcc.dg/cdce3.c: Require sqrt_insn effective target.
* gcc.target/powerpc/pr46728-10.c: Likewise.
* gcc.target/powerpc/pr46728-11.c: Likewise.
* gcc.target/powerpc/pr46728-13.c: Likewise.
* gcc.target/powerpc/pr46728-14.c: Likewise.
Diff:
---
gcc/testsuite/gcc.dg/cdce3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-10.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-11.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-13.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-14.c | 1 +
5 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/cdce3.c b/gcc/testsuite/gcc.dg/cdce3.c
index 601ddf055fd..f759a95972e 100644
--- a/gcc/testsuite/gcc.dg/cdce3.c
+++ b/gcc/testsuite/gcc.dg/cdce3.c
@@ -1,7 +1,8 @@
/* { dg-do compile } */
/* { dg-require-effective-target hard_float } */
+/* { dg-require-effective-target sqrt_insn } */
/* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details
-fdump-tree-optimized" } */
-/* { dg-final { scan-tree-dump "cdce3.c:11: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
+/* { dg-final { scan-tree-dump "cdce3.c:12: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
/* { dg-final { scan-tree-dump "sqrtf \\(\[^\n\r]*\\); \\\[tail call\\\]"
"optimized" } } */
/* { dg-skip-if "doesn't have a sqrtf insn" { mmix-*-* } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
index 3be4728d333..7e9bb638106 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
index 43b6728a4b8..5bfa2592567 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
index b9fd63973b7..b66d0209a5e 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
index 5a13bdb..71a1a70c4e7 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: pr79004 needs -mlong-double-128
https://gcc.gnu.org/g:9c266e6f78ee2bd8fad3b1310996ba5012a16735
commit 9c266e6f78ee2bd8fad3b1310996ba5012a16735
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:28 2024 -0300
ppc: testsuite: pr79004 needs -mlong-double-128
Some of the asm opcodes expected by pr79004 depend on
-mlong-double-128 to be output. E.g., without this flag, the
conditions of patterns @extenddf2 and extendsf2 do not
hold, and so GCC resorts to libcalls instead of even trying
rs6000_expand_float128_convert.
Perhaps the conditions are too strict, and they could enable the use
of conversion insns involving __ieee128/_Float128 even with 64-bit
long doubles. Alas, for now, we need this flag for the test to pass
on target variants that use 64-bit long doubles.
for gcc/testsuite/ChangeLog
* gcc.target/powerpr/pr79004.c: Add -mlong-double-128.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr79004.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79004.c
b/gcc/testsuite/gcc.target/powerpc/pr79004.c
index caf1f6c1eef..83f20ca2243 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79004.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79004.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mfloat128" } */
+/* { dg-additional-options "-mlong-double-128" } */
#include
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: vec-mul requires vsx runtime
https://gcc.gnu.org/g:25b2dc8c3befb8a19584f5052db75753fcd78351
commit 25b2dc8c3befb8a19584f5052db75753fcd78351
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:37 2024 -0300
ppc: testsuite: vec-mul requires vsx runtime
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
To check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d..11da8615972 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do compile { target { ! vsx_hw } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O3" } */
[gcc(refs/users/aoliva/heads/testme)] Request check for hw support in ppc run tests with -maltivec/-mvsx
https://gcc.gnu.org/g:b610d91071d1c8887481b7f5b3ca57342911cdea
commit b610d91071d1c8887481b7f5b3ca57342911cdea
Author: Olivier Hainque
Date: Sun Apr 21 17:24:24 2024 -0300
Request check for hw support in ppc run tests with -maltivec/-mvsx
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/swaps-p8-20.c: Change powerpc_altivec_ok
require-effective-target test into vmx_hw.
* gcc.target/powerpc/vsx-vector-5.c: Change powerpc_vsx_ok
require-effective-target test into vsx_hw.
Diff:
---
gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c | 5 +
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
index 564e8acb1f4..755519bfe84 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target vmx_hw } */
/* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec" } */
/* The expansion for vector character multiply introduces a vperm operation.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
index dcc88b1f3a4..37a324b6f89 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
@@ -1,11 +1,8 @@
/* { dg-do run { target lp64 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target vsx_hw } */
/* { dg-options "-mvsx -O2" } */
-/* This will run, and someday we should add the support to test whether we are
- running on VSX hardware. */
-
#include
#include
[gcc(refs/users/aoliva/heads/testme)] adjust vectorization expectations for ppc costmodel 76b
https://gcc.gnu.org/g:06cec5e7261a78413d7ccfeea4c8e85b224d370f
commit 06cec5e7261a78413d7ccfeea4c8e85b224d370f
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:18 2024 -0300
adjust vectorization expectations for ppc costmodel 76b
This test expects vectorization at power8+ because strict alignment is
not required for vectors. For power7, vectorization is not to take
place because it's not deemed profitable: 12 iterations would be
required to make it so.
But for power6 and below, the test's 10 iterations are enough to make
vectorization profitable, but the test doesn't expect this. Assuming
the decision is indeed appropriate, I'm adjusting the expectations.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c: Adjust
expectations for cpus below power7.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
index cbbfbb24658..0dab2c08acd 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
@@ -46,9 +46,10 @@ int main (void)
return 0;
}
-/* Peeling to align the store is used. Overhead of peeling is too high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
vector_alignment_reachable && {! vect_no_align} } } } } */
-/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { vector_alignment_reachable && {! vect_hw_misalign} } } } } */
+/* Peeling to align the store is used. Overhead of peeling is too high
+ for power7, but acceptable for earlier architectures. */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
has_arch_pwr7 && { vector_alignment_reachable && {! vect_no_align} } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { has_arch_pwr7 && { vector_alignment_reachable && {! vect_hw_misalign}
} } } } } */
/* Versioning to align the store is used. Overhead of versioning is not too
high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || {! vector_alignment_reachable} } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || { {! vector_alignment_reachable} || {! has_arch_pwr7 } } } } }
} */
[gcc(refs/users/aoliva/heads/testme)] disable ldist for test, to restore vectorizing-candidate loop
https://gcc.gnu.org/g:5b0e0d473bcd6a06a4dc4876890477a9d30582d8
commit 5b0e0d473bcd6a06a4dc4876890477a9d30582d8
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:14 2024 -0300
disable ldist for test, to restore vectorizing-candidate loop
The loop we're supposed to try to vectorize in
gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c is turned into a memset
before the vectorizer runs.
Various other tests in this set have already run into this, and the
solution has been to disable this loop distribution transformation,
enabled at -O2, so that the vectorizer gets a chance to transform the
loop and, in this testcase, fail to do so.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c: Disable
ldist.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
index 454a714a309..90b5d5a7f40 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
@@ -1,4 +1,5 @@
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-fno-tree-loop-distribute-patterns" } */
#include
#include "../../tree-vect.h"
[gcc/aoliva/heads/testme] (10 commits) [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra
The branch 'aoliva/heads/testme' was updated to point to: edf330eeb9d... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra It previously pointed to: 650181136ad... [testsuite] require sqrt_insn effective target where needed Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- 6501811... [testsuite] require sqrt_insn effective target where needed 387ce53... add explicit ABI and align options to pr88233.c 40cc97a... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra bd7a059... ppc: testsuite: vec-mul requires vsx runtime 762f75a... ppc: testsuite: pr79004 needs -mlong-double-128 de156d0... Request check for hw support in ppc run tests with -maltive 4aed989... decay vect tests from run to link for pr95401 9b0c52b... adjust vectorization expectations for ppc costmodel 76b 7ef3c86... disable ldist for test, to restore vectorizing-candidate lo f605eec... xfail fetestexcept test - ppc always uses fcmpu Summary of changes (added commits): --- edf330e... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 960142e... decay vect tests from run to link for pr95401 1dd110c... xfail fetestexcept test - ppc always uses fcmpu cef8842... [testsuite] require sqrt_insn effective target where needed c5fbace... add explicit ABI and align options to pr88233.c 25b2dc8... ppc: testsuite: vec-mul requires vsx runtime 9c266e6... ppc: testsuite: pr79004 needs -mlong-double-128 b610d91... Request check for hw support in ppc run tests with -maltive 06cec5e... adjust vectorization expectations for ppc costmodel 76b 5b0e0d4... disable ldist for test, to restore vectorizing-candidate lo
[gcc(refs/users/aoliva/heads/testme)] [testsuite] require sqrt_insn effective target where needed
https://gcc.gnu.org/g:650181136ad3e9ec7be716f69b4bde29c883cd71
commit 650181136ad3e9ec7be716f69b4bde29c883cd71
Author: Alexandre Oliva
Date: Mon Apr 22 01:12:55 2024 -0300
[testsuite] require sqrt_insn effective target where needed
Some tests fail on ppc and ppc64 when testing a compiler [with options
for] for a CPU [emulator] that doesn't support the sqrt insn.
The gcc.dg/cdce3.c is one in which the expected shrink-wrap
optimization only takes place when the target CPU supports a sqrt
insn.
The gcc.target/powerpc/pr46728-1[0-4].c tests use -mpowerpc-gpopt and
call sqrt(), which involves the sqrt insn that the target CPU under
test may not support.
Require a sqrt_insn effective target for all the affected tests.
for gcc/testsuite/ChangeLog
* gcc.dg/cdce3.c: Require sqrt_insn effective target.
* gcc.target/powerpc/pr46728-10.c: Likewise.
* gcc.target/powerpc/pr46728-11.c: Likewise.
* gcc.target/powerpc/pr46728-13.c: Likewise.
* gcc.target/powerpc/pr46728-14.c: Likewise.
Diff:
---
gcc/testsuite/gcc.dg/cdce3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-10.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-11.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-13.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr46728-14.c | 1 +
5 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/cdce3.c b/gcc/testsuite/gcc.dg/cdce3.c
index 601ddf055fd..f759a95972e 100644
--- a/gcc/testsuite/gcc.dg/cdce3.c
+++ b/gcc/testsuite/gcc.dg/cdce3.c
@@ -1,7 +1,8 @@
/* { dg-do compile } */
/* { dg-require-effective-target hard_float } */
+/* { dg-require-effective-target sqrt_insn } */
/* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details
-fdump-tree-optimized" } */
-/* { dg-final { scan-tree-dump "cdce3.c:11: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
+/* { dg-final { scan-tree-dump "cdce3.c:12: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
/* { dg-final { scan-tree-dump "sqrtf \\(\[^\n\r]*\\); \\\[tail call\\\]"
"optimized" } } */
/* { dg-skip-if "doesn't have a sqrtf insn" { mmix-*-* } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
index 3be4728d333..7e9bb638106 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
index 43b6728a4b8..5bfa2592567 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
index b9fd63973b7..b66d0209a5e 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
index 5a13bdb..71a1a70c4e7 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:387ce53fd3fdaeefc7dc9d603df0d66495580fbf
commit 387ce53fd3fdaeefc7dc9d603df0d66495580fbf
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..46a3ebfa287 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fpcc-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:40cc97a1048c76e6f94e7b1b4a39089686ec6a84
commit 40cc97a1048c76e6f94e7b1b4a39089686ec6a84
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..cbf6cffbeba 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,8 +13,7 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..c9abb6c1f35 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,8 +12,7 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..418762e3948 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } }
} */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
/* { dg-final {
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: vec-mul requires vsx runtime
https://gcc.gnu.org/g:bd7a059057714d60f0b7a3db37152ae898e4a293
commit bd7a059057714d60f0b7a3db37152ae898e4a293
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:37 2024 -0300
ppc: testsuite: vec-mul requires vsx runtime
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
To check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d..11da8615972 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do compile { target { ! vsx_hw } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O3" } */
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: pr79004 needs -mlong-double-128
https://gcc.gnu.org/g:762f75a75a192bdc4f7b056a978f9ae37b12bcf7
commit 762f75a75a192bdc4f7b056a978f9ae37b12bcf7
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:28 2024 -0300
ppc: testsuite: pr79004 needs -mlong-double-128
Some of the asm opcodes expected by pr79004 depend on
-mlong-double-128 to be output. E.g., without this flag, the
conditions of patterns @extenddf2 and extendsf2 do not
hold, and so GCC resorts to libcalls instead of even trying
rs6000_expand_float128_convert.
Perhaps the conditions are too strict, and they could enable the use
of conversion insns involving __ieee128/_Float128 even with 64-bit
long doubles. Alas, for now, we need this flag for the test to pass
on target variants that use 64-bit long doubles.
for gcc/testsuite/ChangeLog
* gcc.target/powerpr/pr79004.c: Add -mlong-double-128.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr79004.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79004.c
b/gcc/testsuite/gcc.target/powerpc/pr79004.c
index caf1f6c1eef..83f20ca2243 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79004.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79004.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mfloat128" } */
+/* { dg-additional-options "-mlong-double-128" } */
#include
[gcc(refs/users/aoliva/heads/testme)] Request check for hw support in ppc run tests with -maltivec/-mvsx
https://gcc.gnu.org/g:de156d08943e343720819a9920ba7e4f67bbd8e4
commit de156d08943e343720819a9920ba7e4f67bbd8e4
Author: Olivier Hainque
Date: Sun Apr 21 17:24:24 2024 -0300
Request check for hw support in ppc run tests with -maltivec/-mvsx
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/swaps-p8-20.c: Change powerpc_altivec_ok
require-effective-target test into vmx_hw.
* gcc.target/powerpc/vsx-vector-5.c: Change powerpc_vsx_ok
require-effective-target test into vsx_hw.
Diff:
---
gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c | 5 +
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
index 564e8acb1f4..755519bfe84 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target vmx_hw } */
/* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec" } */
/* The expansion for vector character multiply introduces a vperm operation.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
index dcc88b1f3a4..37a324b6f89 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
@@ -1,11 +1,8 @@
/* { dg-do run { target lp64 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target vsx_hw } */
/* { dg-options "-mvsx -O2" } */
-/* This will run, and someday we should add the support to test whether we are
- running on VSX hardware. */
-
#include
#include
[gcc(refs/users/aoliva/heads/testme)] decay vect tests from run to link for pr95401
https://gcc.gnu.org/g:4aed9893ba8413ee38770d909995f3925659b670
commit 4aed9893ba8413ee38770d909995f3925659b670
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:21 2024 -0300
decay vect tests from run to link for pr95401
When vect.exp finds our configuration disables altivec by default, it
disables the execution of vectorization tests, assuming the test
hardware doesn't support it.
Tests become just compile tests, but compile tests won't work
correctly when additional sources are named, e.g. pr95401.cc, because
GCC refuses to compile multiple files into the same asm output.
With this patch, the default for when execution is not possible
becomes link.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_vect_support_and_set_flags):
Decay to link rather than compile.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3a5713d9869..df5a1457cd1 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11625,7 +11625,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11655,14 +11655,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11681,7 +11681,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11694,7 +11694,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11707,7 +11707,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11731,7 +11731,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
[gcc(refs/users/aoliva/heads/testme)] adjust vectorization expectations for ppc costmodel 76b
https://gcc.gnu.org/g:9b0c52b69c85acbceccc5676509cfc0fbb41dd52
commit 9b0c52b69c85acbceccc5676509cfc0fbb41dd52
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:18 2024 -0300
adjust vectorization expectations for ppc costmodel 76b
This test expects vectorization at power8+ because strict alignment is
not required for vectors. For power7, vectorization is not to take
place because it's not deemed profitable: 12 iterations would be
required to make it so.
But for power6 and below, the test's 10 iterations are enough to make
vectorization profitable, but the test doesn't expect this. Assuming
the decision is indeed appropriate, I'm adjusting the expectations.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c: Adjust
expectations for cpus below power7.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
index cbbfbb24658..0dab2c08acd 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
@@ -46,9 +46,10 @@ int main (void)
return 0;
}
-/* Peeling to align the store is used. Overhead of peeling is too high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
vector_alignment_reachable && {! vect_no_align} } } } } */
-/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { vector_alignment_reachable && {! vect_hw_misalign} } } } } */
+/* Peeling to align the store is used. Overhead of peeling is too high
+ for power7, but acceptable for earlier architectures. */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
has_arch_pwr7 && { vector_alignment_reachable && {! vect_no_align} } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { has_arch_pwr7 && { vector_alignment_reachable && {! vect_hw_misalign}
} } } } } */
/* Versioning to align the store is used. Overhead of versioning is not too
high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || {! vector_alignment_reachable} } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || { {! vector_alignment_reachable} || {! has_arch_pwr7 } } } } }
} */
[gcc(refs/users/aoliva/heads/testme)] disable ldist for test, to restore vectorizing-candidate loop
https://gcc.gnu.org/g:7ef3c86bc8ac48a834a787aad1809e623def6b64
commit 7ef3c86bc8ac48a834a787aad1809e623def6b64
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:14 2024 -0300
disable ldist for test, to restore vectorizing-candidate loop
The loop we're supposed to try to vectorize in
gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c is turned into a memset
before the vectorizer runs.
Various other tests in this set have already run into this, and the
solution has been to disable this loop distribution transformation,
enabled at -O2, so that the vectorizer gets a chance to transform the
loop and, in this testcase, fail to do so.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c: Disable
ldist.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
index 454a714a309..90b5d5a7f40 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
@@ -1,4 +1,5 @@
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-fno-tree-loop-distribute-patterns" } */
#include
#include "../../tree-vect.h"
[gcc(refs/users/aoliva/heads/testme)] xfail fetestexcept test - ppc always uses fcmpu
https://gcc.gnu.org/g:f605eecb06d40c99be2d48169c5fafda2df6babb
commit f605eecb06d40c99be2d48169c5fafda2df6babb
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:11 2024 -0300
xfail fetestexcept test - ppc always uses fcmpu
gcc.dg/torture/pr91323.c tests that a compare with NaNf doesn't set an
exception using builtin compare intrinsics, and that it does when
using regular compare operators.
That doesn't seem to be expected to work on powerpc targets. It fails
on GNU/Linux, it's marked to be skipped on AIX, and a similar test,
gcc.dg/torture/pr93133.c, has the execution test xfailed for all of
powerpc*-*-*.
In this test, the functions that use intrinsics for the compare end up
with the same code as the one that uses compare operators, using
fcmpu, a floating compare that, unlike fcmpo, does not set the invalid
operand exception for quiet NaN. I couldn't find any evidence that
the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
execution xfail marker to this test.
for gcc/testsuite/ChangeLog
PR target/58684
* gcc.dg/torture/pr91323.c: Expect execution fail on
powerpc*-*-*.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr91323.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr91323.c
b/gcc/testsuite/gcc.dg/torture/pr91323.c
index 1411fcaa396..f97dcc12cac 100644
--- a/gcc/testsuite/gcc.dg/torture/pr91323.c
+++ b/gcc/testsuite/gcc.dg/torture/pr91323.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { xfail powerpc*-*-* } } */
/* { dg-add-options ieee } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-skip-if "fenv" { powerpc-ibm-aix* } } */
[gcc/aoliva/heads/testme] (10 commits) [testsuite] require sqrt_insn effective target where needed
The branch 'aoliva/heads/testme' was updated to point to: 650181136ad... [testsuite] require sqrt_insn effective target where needed It previously pointed to: c3999e0292d... add explicit ABI and align options to pr88233.c Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- c3999e0... add explicit ABI and align options to pr88233.c d20a933... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 347b4d5... ppc: testsuite: vec-mul requires vsx runtime fe3c0a3... ppc: testsuite: pr79004 needs -mlong-double-128 2d28d2a... Request check for hw support in ppc run tests with -maltive ad51db7... decay vect tests from run to link for pr95401 106f3cf... adjust vectorization expectations for ppc costmodel 76b 8e6d181... disable ldist for test, to restore vectorizing-candidate lo 0e8ef1e... xfail fetestexcept test - ppc always uses fcmpu 4488f8d... add sqrt options and test for sqrt support in ppc tests 048689c... enable sqrt insns for cdce3.c 032f38d... add -mpowerpc-gpopt to options for sqrt insn on PowerPC Summary of changes (added commits): --- 6501811... [testsuite] require sqrt_insn effective target where needed 387ce53... add explicit ABI and align options to pr88233.c 40cc97a... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra bd7a059... ppc: testsuite: vec-mul requires vsx runtime 762f75a... ppc: testsuite: pr79004 needs -mlong-double-128 de156d0... Request check for hw support in ppc run tests with -maltive 4aed989... decay vect tests from run to link for pr95401 9b0c52b... adjust vectorization expectations for ppc costmodel 76b 7ef3c86... disable ldist for test, to restore vectorizing-candidate lo f605eec... xfail fetestexcept test - ppc always uses fcmpu
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:c3999e0292deb3c5f3c8ccc8ddccc21da4ef3644
commit c3999e0292deb3c5f3c8ccc8ddccc21da4ef3644
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the original expectations to be met.
The test was later modified to have different expectations for big and
little endian code generation. This patch restores the original
codegen expectations, that, with the explicit options, don't vary any
more.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit. Restore uniform
codegen expectations
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..46a3ebfa287 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fpcc-struct-return" } */
typedef struct { double a[2]; } A;
A
@@ -9,6 +9,5 @@ foo (const A *a)
}
/* { dg-final { scan-assembler-not {\mmtvsr} } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target { be } } } } */
-/* { dg-final { scan-assembler-times {\mlfd\M} 2 { target { le } } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:d20a933141e6b8dd34fb578635ccbd49abcab15e
commit d20a933141e6b8dd34fb578635ccbd49abcab15e
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..cbf6cffbeba 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,8 +13,7 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..c9abb6c1f35 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,8 +12,7 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..418762e3948 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } }
} */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
/* { dg-final {
[gcc/aoliva/heads/testme] (3 commits) add explicit ABI and align options to pr88233.c
The branch 'aoliva/heads/testme' was updated to point to: c3999e0292d... add explicit ABI and align options to pr88233.c It previously pointed to: b6144ccafe3... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): --- b6144cc... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 0197e8f... ppc: testsuite: vec-mul requires vsx runtime 89e5150... add explicit ABI and align options to pr88233.c Summary of changes (added commits): --- c3999e0... add explicit ABI and align options to pr88233.c d20a933... [testsuite] [powerpc] adjust -m32 counts for fold-vec-extra 347b4d5... ppc: testsuite: vec-mul requires vsx runtime
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: vec-mul requires vsx runtime
https://gcc.gnu.org/g:347b4d5eb8a1418393f6e406d4d052d3c6b0790e
commit 347b4d5eb8a1418393f6e406d4d052d3c6b0790e
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:37 2024 -0300
ppc: testsuite: vec-mul requires vsx runtime
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
To check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d..11da8615972 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do compile { target { ! vsx_hw } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O3" } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
https://gcc.gnu.org/g:b6144ccafe3acc445ee5b2a23000a37824923d3b
commit b6144ccafe3acc445ee5b2a23000a37824923d3b
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:41 2024 -0300
[testsuite] [powerpc] adjust -m32 counts for fold-vec-extract*
Codegen changes caused add instruction count mismatches on
ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
expected counts were adjusted for lp64, but ilp32 differences
remained, and published test results confirm it.
for gcc/testsuite/ChangeLog
PR testsuite/101169
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Adjust addi
counts for ilp32.
* gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c| 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c| 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +--
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
7 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
index 3cae644b90b..cbf6cffbeba 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
@@ -13,8 +13,7 @@
/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 target has an 'add' in place of one of the 'addi'. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* -m32 target has a rlwinm in place of a rldic . */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
index 59a4979457d..c9abb6c1f35 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
@@ -12,8 +12,7 @@
/* { dg-final { scan-assembler-times {\mxscvspdp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mli\M} 1 } } */
/* -m32 as an add in place of an addi. */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } } }
*/
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
/* -m32 uses rlwinm in place of rldic */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index ce4e43c1fb4..cd80c5e1b19 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 3729a1646e9..418762e3948 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,8 +10,7 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } }
*/
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } }
} */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
/* { dg-final {
[gcc(refs/users/aoliva/heads/testme)] add explicit ABI and align options to pr88233.c
https://gcc.gnu.org/g:89e5150772d91d129fd4a8ca6ebda361e546
commit 89e5150772d91d129fd4a8ca6ebda361e546
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:30 2024 -0300
add explicit ABI and align options to pr88233.c
We've observed failures of this test on powerpc configurations that
default to different calling conventions and alignment requirements.
Both settings are needed for the expectations to be met.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr88233.c: Make some alignment strictness
and calling conventions assumptions explicit.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr88233.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr88233.c
b/gcc/testsuite/gcc.target/powerpc/pr88233.c
index 27c73717a3f..c667a28ebfe 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr88233.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr88233.c
@@ -1,5 +1,5 @@
/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-strict-align
-fno-reg-struct-return" } */
typedef struct { double a[2]; } A;
A
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: vec-mul requires vsx runtime
https://gcc.gnu.org/g:0197e8f80932063526f0bd7437c80c9ca420cf38
commit 0197e8f80932063526f0bd7437c80c9ca420cf38
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:37 2024 -0300
ppc: testsuite: vec-mul requires vsx runtime
vec-mul is an execution test, but it only requires a powerpc_vsx_ok
effective target, which is enough only for compile tests. In order to
To check for runtime and execution environment support, we need to
require vsx_hw. Make that a condition for execution, but still
perform a compile test if the condition is not satisfied.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/vec-mul.c: Run on target vsx_hw, just
compile otherwise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-mul.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
index bfcaf80719d..11da8615972 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-mul.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-mul.c
@@ -1,4 +1,5 @@
-/* { dg-do run } */
+/* { dg-do compile { target { ! vsx_hw } } } */
+/* { dg-do run { target vsx_hw } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mvsx -O3" } */
[gcc(refs/users/aoliva/heads/testme)] ppc: testsuite: pr79004 needs -mlong-double-128
https://gcc.gnu.org/g:fe3c0a30e72c978dcd9a70d131b2e9cb9f90e8e0
commit fe3c0a30e72c978dcd9a70d131b2e9cb9f90e8e0
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:28 2024 -0300
ppc: testsuite: pr79004 needs -mlong-double-128
Some of the asm opcodes expected by pr79004 depend on
-mlong-double-128 to be output. E.g., without this flag, the
conditions of patterns @extenddf2 and extendsf2 do not
hold, and so GCC resorts to libcalls instead of even trying
rs6000_expand_float128_convert.
Perhaps the conditions are too strict, and they could enable the use
of conversion insns involving __ieee128/_Float128 even with 64-bit
long doubles. Alas, for now, we need this flag for the test to pass
on target variants that use 64-bit long doubles.
for gcc/testsuite/ChangeLog
* gcc.target/powerpr/pr79004.c: Add -mlong-double-128.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr79004.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr79004.c
b/gcc/testsuite/gcc.target/powerpc/pr79004.c
index caf1f6c1eef..83f20ca2243 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr79004.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr79004.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-require-effective-target powerpc_vsx_ok } */
/* { dg-options "-mdejagnu-cpu=power9 -mvsx -O2 -mfloat128" } */
+/* { dg-additional-options "-mlong-double-128" } */
#include
[gcc(refs/users/aoliva/heads/testme)] Request check for hw support in ppc run tests with -maltivec/-mvsx
https://gcc.gnu.org/g:2d28d2a79906d56cb121c5e08af68c81d7a5dea7
commit 2d28d2a79906d56cb121c5e08af68c81d7a5dea7
Author: Olivier Hainque
Date: Sun Apr 21 17:24:24 2024 -0300
Request check for hw support in ppc run tests with -maltivec/-mvsx
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/swaps-p8-20.c: Change powerpc_altivec_ok
require-effective-target test into vmx_hw.
* gcc.target/powerpc/vsx-vector-5.c: Change powerpc_vsx_ok
require-effective-target test into vsx_hw.
Diff:
---
gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c | 2 +-
gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c | 5 +
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
index 564e8acb1f4..755519bfe84 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target vmx_hw } */
/* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec" } */
/* The expansion for vector character multiply introduces a vperm operation.
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
index dcc88b1f3a4..37a324b6f89 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
@@ -1,11 +1,8 @@
/* { dg-do run { target lp64 } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target vsx_hw } */
/* { dg-options "-mvsx -O2" } */
-/* This will run, and someday we should add the support to test whether we are
- running on VSX hardware. */
-
#include
#include
[gcc(refs/users/aoliva/heads/testme)] decay vect tests from run to link for pr95401
https://gcc.gnu.org/g:ad51db74dc7e057ee1d81ed09d380f65c18d1f0f
commit ad51db74dc7e057ee1d81ed09d380f65c18d1f0f
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:21 2024 -0300
decay vect tests from run to link for pr95401
When vect.exp finds our configuration disables altivec by default, it
disables the execution of vectorization tests, assuming the test
hardware doesn't support it.
Tests become just compile tests, but compile tests won't work
correctly when additional sources are named, e.g. pr95401.cc, because
GCC refuses to compile multiple files into the same asm output.
With this patch, the default for when execution is not possible
becomes link.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_vect_support_and_set_flags):
Decay to link rather than compile.
Diff:
---
gcc/testsuite/lib/target-supports.exp | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index ec753b19e2f..b55bd65bdbb 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -11628,7 +11628,7 @@ proc check_vect_support_and_set_flags { } {
if [check_750cl_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget powerpc*-*-*] {
# Skip targets not supporting -maltivec.
@@ -11658,14 +11658,14 @@ proc check_vect_support_and_set_flags { } {
# some other cpu type specified above.
set DEFAULT_VECTCFLAGS [linsert $DEFAULT_VECTCFLAGS 0
"-mcpu=970"]
}
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget i?86-*-*] || [istarget x86_64-*-*] } {
lappend DEFAULT_VECTCFLAGS "-msse2"
if { [check_effective_target_sse2_runtime] } {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif { [istarget mips*-*-*]
&& [check_effective_target_nomips16] } {
@@ -11684,7 +11684,7 @@ proc check_vect_support_and_set_flags { } {
if [check_effective_target_ultrasparc_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget alpha*-*-*] {
# Alpha's vectorization capabilities are extremely limited.
@@ -11697,7 +11697,7 @@ proc check_vect_support_and_set_flags { } {
if [check_alpha_max_hw_available] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget ia64-*-*] {
set dg-do-what-default run
@@ -11710,7 +11710,7 @@ proc check_vect_support_and_set_flags { } {
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget aarch64*-*-*] {
set dg-do-what-default run
@@ -11734,7 +11734,7 @@ proc check_vect_support_and_set_flags { } {
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=z14" "-mzarch"
-set dg-do-what-default compile
+set dg-do-what-default link
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
[gcc(refs/users/aoliva/heads/testme)] adjust vectorization expectations for ppc costmodel 76b
https://gcc.gnu.org/g:106f3cf414881d14a285a18919bfec14d2d1ca23
commit 106f3cf414881d14a285a18919bfec14d2d1ca23
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:18 2024 -0300
adjust vectorization expectations for ppc costmodel 76b
This test expects vectorization at power8+ because strict alignment is
not required for vectors. For power7, vectorization is not to take
place because it's not deemed profitable: 12 iterations would be
required to make it so.
But for power6 and below, the test's 10 iterations are enough to make
vectorization profitable, but the test doesn't expect this. Assuming
the decision is indeed appropriate, I'm adjusting the expectations.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c: Adjust
expectations for cpus below power7.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
index cbbfbb24658..0dab2c08acd 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c
@@ -46,9 +46,10 @@ int main (void)
return 0;
}
-/* Peeling to align the store is used. Overhead of peeling is too high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
vector_alignment_reachable && {! vect_no_align} } } } } */
-/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { vector_alignment_reachable && {! vect_hw_misalign} } } } } */
+/* Peeling to align the store is used. Overhead of peeling is too high
+ for power7, but acceptable for earlier architectures. */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 0 "vect" { target {
has_arch_pwr7 && { vector_alignment_reachable && {! vect_no_align} } } } } } */
+/* { dg-final { scan-tree-dump-times "vectorization not profitable" 1 "vect" {
target { has_arch_pwr7 && { vector_alignment_reachable && {! vect_hw_misalign}
} } } } } */
/* Versioning to align the store is used. Overhead of versioning is not too
high. */
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || {! vector_alignment_reachable} } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target {
vect_no_align || { {! vector_alignment_reachable} || {! has_arch_pwr7 } } } } }
} */
[gcc(refs/users/aoliva/heads/testme)] disable ldist for test, to restore vectorizing-candidate loop
https://gcc.gnu.org/g:8e6d1811a6aae7902225fb37a97214c3a2fed32b
commit 8e6d1811a6aae7902225fb37a97214c3a2fed32b
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:14 2024 -0300
disable ldist for test, to restore vectorizing-candidate loop
The loop we're supposed to try to vectorize in
gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c is turned into a memset
before the vectorizer runs.
Various other tests in this set have already run into this, and the
solution has been to disable this loop distribution transformation,
enabled at -O2, so that the vectorizer gets a chance to transform the
loop and, in this testcase, fail to do so.
for gcc/testsuite/ChangeLog
* gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c: Disable
ldist.
Diff:
---
gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
index 454a714a309..90b5d5a7f40 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c
@@ -1,4 +1,5 @@
/* { dg-require-effective-target vect_int } */
+/* { dg-additional-options "-fno-tree-loop-distribute-patterns" } */
#include
#include "../../tree-vect.h"
[gcc(refs/users/aoliva/heads/testme)] xfail fetestexcept test - ppc always uses fcmpu
https://gcc.gnu.org/g:0e8ef1e608028e5812900b717406d1901d98d4cf
commit 0e8ef1e608028e5812900b717406d1901d98d4cf
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:11 2024 -0300
xfail fetestexcept test - ppc always uses fcmpu
gcc.dg/torture/pr91323.c tests that a compare with NaNf doesn't set an
exception using builtin compare intrinsics, and that it does when
using regular compare operators.
That doesn't seem to be expected to work on powerpc targets. It fails
on GNU/Linux, it's marked to be skipped on AIX, and a similar test,
gcc.dg/torture/pr93133.c, has the execution test xfailed for all of
powerpc*-*-*.
In this test, the functions that use intrinsics for the compare end up
with the same code as the one that uses compare operators, using
fcmpu, a floating compare that, unlike fcmpo, does not set the invalid
operand exception for quiet NaN. I couldn't find any evidence that
the rs6000 backend ever outputs fcmpo. Therefore, I'm adding the same
execution xfail marker to this test.
for gcc/testsuite/ChangeLog
PR target/58684
* gcc.dg/torture/pr91323.c: Expect execution fail on
powerpc*-*-*.
Diff:
---
gcc/testsuite/gcc.dg/torture/pr91323.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/torture/pr91323.c
b/gcc/testsuite/gcc.dg/torture/pr91323.c
index 1411fcaa396..f97dcc12cac 100644
--- a/gcc/testsuite/gcc.dg/torture/pr91323.c
+++ b/gcc/testsuite/gcc.dg/torture/pr91323.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */
+/* { dg-do run { xfail powerpc*-*-* } } */
/* { dg-add-options ieee } */
/* { dg-require-effective-target fenv_exceptions } */
/* { dg-skip-if "fenv" { powerpc-ibm-aix* } } */
[gcc(refs/users/aoliva/heads/testme)] add sqrt options and test for sqrt support in ppc tests
https://gcc.gnu.org/g:4488f8d930768029f3ca3b18709a2652462bd7c5
commit 4488f8d930768029f3ca3b18709a2652462bd7c5
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:06 2024 -0300
add sqrt options and test for sqrt support in ppc tests
Some powerpc tests that require the fsqrt insn to be enabled
explicitly use the -mpowerpc-gpopt option. This fails if the fsqrt
opcode is not available on the target machine.
Switch to dg-add-options sqrt_insn for compile tests, that adds the
option for the feature (pending approval of another patch for the same
PR), and to dg-require-effective-target sqrt_insn for execution tests.
for gcc/testsuite/ChangeLog
PR testsuite/99371
* gcc.target/powerpc/pr46728-10.c: Drop explicit
-mpowerpc-gpopt in favor of dg-require-effective-target sqrt_insn.
* gcc.target/powerpc/pr46728-11.c: Likewise.
* gcc.target/powerpc/pr46728-13.c: Likewise.
* gcc.target/powerpc/pr46728-14.c: Likewise.
* gcc.target/powerpc/pr46728-15.c: Likewise.
* gcc.target/powerpc/recip-7.c: Likewise.
* gcc.target/powerpc/pr46728-1.c: Drop explicit
-mpowerpc-gpopt in favor of dg-add-options sqrt_insn.
* gcc.target/powerpc/pr46728-2.c: Likewise.
* gcc.target/powerpc/pr46728-3.c: Likewise.
* gcc.target/powerpc/pr46728-4.c: Likewise.
* gcc.target/powerpc/pr46728-5.c: Likewise.
* gcc.target/powerpc/pr46728-7.c: Likewise.
* gcc.target/powerpc/pr46728-8.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr46728-1.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-10.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-11.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-13.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-14.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-15.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-2.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-3.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-4.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-5.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-7.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/pr46728-8.c | 3 ++-
gcc/testsuite/gcc.target/powerpc/recip-7.c| 3 ++-
13 files changed, 26 insertions(+), 13 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-1.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-1.c
index fc2cd7d7c9c..b561d8b6e42 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-1.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt -fno-ident" } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -fno-ident"
} */
+/* { dg-add-options sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
index 3be4728d333..cdde53b8de0 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
-/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
index 43b6728a4b8..62b49b14793 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
-/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
index b9fd63973b7..3e55fa86e0b 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
-/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm
-mpowerpc-gpopt" } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm" } */
+/* { dg-require-effective-target sqrt_insn } */
#include
diff --git a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
index 5a13bdb..472b9d5b601 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* {
[gcc(refs/users/aoliva/heads/testme)] add -mpowerpc-gpopt to options for sqrt insn on PowerPC
https://gcc.gnu.org/g:032f38d814d0ba4f8713e616f21b0475d4e61937
commit 032f38d814d0ba4f8713e616f21b0475d4e61937
Author: Eric Botcazou
Date: Sun Apr 21 17:23:56 2024 -0300
add -mpowerpc-gpopt to options for sqrt insn on PowerPC
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (add_options_for_sqrt_insn): For
PowerPC targets, add -mpowerpc-gpopt option.
Diff:
---
gcc/testsuite/gcc.dg/gimplefe-28.c| 1 +
gcc/testsuite/lib/target-supports.exp | 3 +++
2 files changed, 4 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/gimplefe-28.c
b/gcc/testsuite/gcc.dg/gimplefe-28.c
index d2f6b4c5c3d..5f478b32d52 100644
--- a/gcc/testsuite/gcc.dg/gimplefe-28.c
+++ b/gcc/testsuite/gcc.dg/gimplefe-28.c
@@ -1,6 +1,7 @@
/* { dg-do compile { target sqrt_insn } } */
/* { dg-options "-fgimple -O2" } */
/* { dg-add-options sqrt_insn } */
+/* { dg-require-effective-target sqrt_insn } */
double __GIMPLE
f1 (double x)
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3a5713d9869..ec753b19e2f 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -9260,6 +9260,9 @@ proc add_options_for_sqrt_insn { flags } {
if { [istarget arm*-*-*] } {
return [add_options_for_arm_vfp "$flags"]
}
+if { [istarget powerpc*-*-*] } {
+ return "$flags -mpowerpc-gpopt"
+}
return $flags
}
[gcc(refs/users/aoliva/heads/testme)] enable sqrt insns for cdce3.c
https://gcc.gnu.org/g:048689c644c10a99d8618bd0479f727e87e74b90
commit 048689c644c10a99d8618bd0479f727e87e74b90
Author: Alexandre Oliva
Date: Sun Apr 21 17:24:00 2024 -0300
enable sqrt insns for cdce3.c
The test expects shrink-wrapping of the fsqrt call, but that will only
occur when there is a usable sqrt insn.
Arrange for dejagnu to add the options that enable the sqrt insn, if
one is available, and to skip the test otherwise.
for gcc/testsuite/ChangeLog
* gcc.dg/cdce3.c: Add sqrt insn options.
Diff:
---
gcc/testsuite/gcc.dg/cdce3.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/cdce3.c b/gcc/testsuite/gcc.dg/cdce3.c
index 601ddf055fd..218c24d38f1 100644
--- a/gcc/testsuite/gcc.dg/cdce3.c
+++ b/gcc/testsuite/gcc.dg/cdce3.c
@@ -1,9 +1,10 @@
/* { dg-do compile } */
/* { dg-require-effective-target hard_float } */
/* { dg-options "-O2 -fmath-errno -fdump-tree-cdce-details
-fdump-tree-optimized" } */
-/* { dg-final { scan-tree-dump "cdce3.c:11: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
+/* { dg-add-options sqrt_insn } */
+/* { dg-require-effective-target sqrt_insn } */
+/* { dg-final { scan-tree-dump "cdce3.c:12: \[^\n\r]* function call is
shrink-wrapped into error conditions\." "cdce" } } */
/* { dg-final { scan-tree-dump "sqrtf \\(\[^\n\r]*\\); \\\[tail call\\\]"
"optimized" } } */
-/* { dg-skip-if "doesn't have a sqrtf insn" { mmix-*-* } } */
float sqrtf (float);
float foo (float x)
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [ppc64] expect error on vxworks too
https://gcc.gnu.org/g:6996207325751e10e468d03c9fe492f2ad5161f2
commit 6996207325751e10e468d03c9fe492f2ad5161f2
Author: Alexandre Oliva
Date: Sun Apr 21 17:23:52 2024 -0300
[testsuite] [ppc64] expect error on vxworks too
These ppc lp64 tests check for errors or warnings on -mno-powerpc64.
On powerpc64-*-vxworks* we get the same errors as on most other
covered platforms, but the tests did not mark them as expected for
this target. On powerpc-*-vxworks*, the tests are skipped because
lp64 is not satisfied, so I'm naming powerpc*-*-vxworks* rather than
something more specific.
for gcc/testsuite/ChangeLog
* gcc.target/powerpc/pr106680-1.c: Error on vxworks too.
* gcc.target/powerpc/pr106680-2.c: Likewise.
* gcc.target/powerpc/pr106680-3.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/pr106680-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr106680-2.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr106680-3.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
index d624d43230a..aadaa614cfe 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-1.c
@@ -8,6 +8,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
index a9ed73726ef..f0758e30335 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-2.c
@@ -9,6 +9,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
b/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
index b642d5c7a00..bca012e2cf6 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr106680-3.c
@@ -8,6 +8,6 @@ int foo ()
return 1;
}
-/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* } 0 } */
+/* { dg-error "'-m64' requires a PowerPC64 cpu" "PR106680" { target
powerpc*-*-linux* powerpc*-*-freebsd* powerpc-*-rtems* powerpc*-*-vxworks* } 0
} */
/* { dg-warning "'-m64' requires PowerPC64 architecture, enabling" "PR106680"
{ target powerpc*-*-darwin* } 0 } */
/* { dg-warning "'-maix64' requires PowerPC64 architecture remain enabled"
"PR106680" { target powerpc*-*-aix* } 0 } */
[gcc(refs/users/aoliva/heads/testme)] [testsuite] [arm] add effective target and options for pacbti tests
https://gcc.gnu.org/g:0cbe32956b7bd3c91c90531cff119b6bd97efcc4
commit 0cbe32956b7bd3c91c90531cff119b6bd97efcc4
Author: Alexandre Oliva
Date: Sun Apr 21 17:23:46 2024 -0300
[testsuite] [arm] add effective target and options for pacbti tests
arm pac and bti tests that use -march=armv8.1-m.main get an implicit
-mthumb, that is incompatible with vxworks kernel mode. Declaring the
requirement for a 8.1-m.main-compatible toolchain is enough to avoid
those fails, because the toolchain feature test fails in kernel mode,
but taking the -march options from the standardized arch tests, after
testing for support for the corresponding effective target, makes it
generally safer, and enables us to drop skip directives and extraneous
option variants.
for gcc/testsuite/ChangeLog
* gcc.target/arm/bti-1.c: Require arch, use its opts, drop skip.
* gcc.target/arm/bti-2.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-11.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-12.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise.
* g++.target/arm/pac-1.C: Likewise. Drop +mve.
Diff:
---
gcc/testsuite/g++.target/arm/pac-1.C | 5 +++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c | 4 ++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c | 5 +++--
gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c | 5 +++--
gcc/testsuite/gcc.target/arm/bti-1.c | 5 +++--
gcc/testsuite/gcc.target/arm/bti-2.c | 5 +++--
6 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/gcc/testsuite/g++.target/arm/pac-1.C
b/gcc/testsuite/g++.target/arm/pac-1.C
index f671a27b048..ac15ae18197 100644
--- a/gcc/testsuite/g++.target/arm/pac-1.C
+++ b/gcc/testsuite/g++.target/arm/pac-1.C
@@ -1,7 +1,8 @@
/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE
pseudo hard-register. */
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8.1-m.main+mve+pacbti -mbranch-protection=pac-ret
-mthumb -mfloat-abi=hard -g -O0" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
+/* { dg-additional-options "-mbranch-protection=pac-ret -mfloat-abi=hard -g
-O0" } */
__attribute__((noinline)) void
fn1 (int a, int b, int c)
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
index 6a5ae92c567..c9c40f44027 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-11.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" "-mfloat-abi=*" } } */
-/* { dg-options "-march=armv8.1-m.main+fp+pacbti" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
#if (__ARM_FEATURE_BTI != 1)
#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined to 1."
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
index db40b17c3b0..c26051347a2 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-12.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-options "-march=armv8-m.main+fp -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_ok } */
+/* { dg-add-options arm_arch_v8_1m_main } */
+/* { dg-additional-options "-mfloat-abi=softfp" } */
#if defined (__ARM_FEATURE_BTI)
#error "Feature test macro __ARM_FEATURE_BTI should not be defined."
diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
index 1b25907635e..92f500c1449 100644
--- a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
+++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm"
"-mcpu=*" } } */
-/* { dg-additional-options "-march=armv8.1-m.main+pacbti+fp --save-temps
-mfloat-abi=hard" } */
+/* { dg-require-effective-target arm_arch_v8_1m_main_pacbti_ok } */
+/* { dg-add-options arm_arch_v8_1m_main_pacbti } */
+/* { dg-additional-options "--save-temps -mfloat-abi=hard" } */
#if defined (__ARM_FEATURE_BTI_DEFAULT)
#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be undefined."
diff --git a/gcc/testsuite/gcc.target/arm/bti-1.c
b/gcc/testsuite/gcc.target/arm/bti-1.c
index 79dd8010d2d..a34bb0842b6 100644
--- a/gcc/testsuite/gcc.target/arm/bti-1.c
+++
