[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:13eae3ea598541647de32a3a81b6188403990565

commit 13eae3ea598541647de32a3a81b6188403990565
Author: Pan Li 
Date:   Tue Jun 18 16:22:59 2024 +0800

RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

After the middle-end support the form 12 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 12.

Form 12:
  #define DEF_SAT_U_SUB_FMT_12(T)\
  T __attribute__((noinline))\
  sat_u_sub_##T##_fmt_12 (T x, T y)  \
  {  \
T ret;   \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return !overflow ? ret : 0;  \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for
testing.
* gcc.target/riscv/sat_u_sub-45.c: New test.
* gcc.target/riscv/sat_u_sub-46.c: New test.
* gcc.target/riscv/sat_u_sub-47.c: New test.
* gcc.target/riscv/sat_u_sub-48.c: New test.
* gcc.target/riscv/sat_u_sub-run-45.c: New test.
* gcc.target/riscv/sat_u_sub-run-46.c: New test.
* gcc.target/riscv/sat_u_sub-run-47.c: New test.
* gcc.target/riscv/sat_u_sub-run-48.c: New test.

Signed-off-by: Pan Li 
(cherry picked from commit 61655f5c95186960f637c26130f08098e5407516)

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h| 10 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c | 19 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-47.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-48.c | 17 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-45.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-46.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-47.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-48.c | 25 +++
 9 files changed, 182 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index ab7289a6947..0c2e44af718 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -150,6 +150,15 @@ sat_u_sub_##T##_fmt_11 (T x, T y)  \
   return overflow ? 0 : ret;   \
 }
 
+#define DEF_SAT_U_SUB_FMT_12(T)\
+T __attribute__((noinline))\
+sat_u_sub_##T##_fmt_12 (T x, T y)  \
+{  \
+  T ret;   \
+  bool overflow = __builtin_sub_overflow (x, y, &ret); \
+  return !overflow ? ret : 0;  \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
 #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -161,5 +170,6 @@ sat_u_sub_##T##_fmt_11 (T x, T y)  \
 #define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
 #define RUN_SAT_U_SUB_FMT_10(T, x, y) sat_u_sub_##T##_fmt_10(x, y)
 #define RUN_SAT_U_SUB_FMT_11(T, x, y) sat_u_sub_##T##_fmt_11(x, y)
+#define RUN_SAT_U_SUB_FMT_12(T, x, y) sat_u_sub_##T##_fmt_12(x, y)
 
 #endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c
new file mode 100644
index 000..1aad8961e29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_12:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_12(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c
new file mode 100644
index 000..d184043f6f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:d7b67c6459575d6844e22ff01b135e8682d7b0cd

commit d7b67c6459575d6844e22ff01b135e8682d7b0cd
Author: Pan Li 
Date:   Tue Jun 18 16:22:59 2024 +0800

RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

After the middle-end support the form 12 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 12.

Form 12:
  #define DEF_SAT_U_SUB_FMT_12(T)\
  T __attribute__((noinline))\
  sat_u_sub_##T##_fmt_12 (T x, T y)  \
  {  \
T ret;   \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return !overflow ? ret : 0;  \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for
testing.
* gcc.target/riscv/sat_u_sub-45.c: New test.
* gcc.target/riscv/sat_u_sub-46.c: New test.
* gcc.target/riscv/sat_u_sub-47.c: New test.
* gcc.target/riscv/sat_u_sub-48.c: New test.
* gcc.target/riscv/sat_u_sub-run-45.c: New test.
* gcc.target/riscv/sat_u_sub-run-46.c: New test.
* gcc.target/riscv/sat_u_sub-run-47.c: New test.
* gcc.target/riscv/sat_u_sub-run-48.c: New test.

Signed-off-by: Pan Li 
(cherry picked from commit 61655f5c95186960f637c26130f08098e5407516)

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h| 10 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c | 19 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-47.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-48.c | 17 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-45.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-46.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-47.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-48.c | 25 +++
 9 files changed, 182 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index ab7289a6947..0c2e44af718 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -150,6 +150,15 @@ sat_u_sub_##T##_fmt_11 (T x, T y)  \
   return overflow ? 0 : ret;   \
 }
 
+#define DEF_SAT_U_SUB_FMT_12(T)\
+T __attribute__((noinline))\
+sat_u_sub_##T##_fmt_12 (T x, T y)  \
+{  \
+  T ret;   \
+  bool overflow = __builtin_sub_overflow (x, y, &ret); \
+  return !overflow ? ret : 0;  \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
 #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -161,5 +170,6 @@ sat_u_sub_##T##_fmt_11 (T x, T y)  \
 #define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
 #define RUN_SAT_U_SUB_FMT_10(T, x, y) sat_u_sub_##T##_fmt_10(x, y)
 #define RUN_SAT_U_SUB_FMT_11(T, x, y) sat_u_sub_##T##_fmt_11(x, y)
+#define RUN_SAT_U_SUB_FMT_12(T, x, y) sat_u_sub_##T##_fmt_12(x, y)
 
 #endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c
new file mode 100644
index 000..1aad8961e29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-45.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_12:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_12(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c
new file mode 100644
index 000..d184043f6f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-46.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_