[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Test cbo.zero expansion for rv32
https://gcc.gnu.org/g:d8f7ba2edaecdaa515d0dfca65934d2a90c63db6 commit d8f7ba2edaecdaa515d0dfca65934d2a90c63db6 Author: Christoph Müllner Date: Wed May 15 01:34:54 2024 +0200 RISC-V: Test cbo.zero expansion for rv32 We had an issue when expanding via cmo-zero for RV32. This was fixed upstream, but we don't have a RV32 test. Therefore, this patch introduces such a test. gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-zicboz-zic64-1.c: Fix for rv32. Signed-off-by: Christoph Müllner (cherry picked from commit 5609d77e683944439fae38323ecabc44a1eb4671) Diff: --- .../gcc.target/riscv/cmo-zicboz-zic64-1.c | 37 +++--- 1 file changed, 11 insertions(+), 26 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c index 6d4535287d0..9192b391b11 100644 --- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c @@ -1,24 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc_zic64b_zicboz -mabi=lp64d" } */ +/* { dg-options "-march=rv32gc_zic64b_zicboz" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_zic64b_zicboz" { target { rv64 } } } */ /* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-allow-blank-lines-in-output 1 } */ -/* -**clear_buf_123: -**... -**cbo\.zero\t0\(a[0-9]+\) -**sd\tzero,64\(a[0-9]+\) -**sd\tzero,72\(a[0-9]+\) -**sd\tzero,80\(a[0-9]+\) -**sd\tzero,88\(a[0-9]+\) -**sd\tzero,96\(a[0-9]+\) -**sd\tzero,104\(a[0-9]+\) -**sd\tzero,112\(a[0-9]+\) -**sh\tzero,120\(a[0-9]+\) -**sb\tzero,122\(a[0-9]+\) -**... -*/ +// 1x cbo.zero, 7x sd (rv64) or 14x sw (rv32), 1x sh, 1x sb int clear_buf_123 (void *p) { @@ -26,17 +11,17 @@ clear_buf_123 (void *p) __builtin_memset (p, 0, 123); } -/* -**clear_buf_128: -**... -**cbo\.zero\t0\(a[0-9]+\) -**addi\ta[0-9]+,a[0-9]+,64 -**cbo\.zero\t0\(a[0-9]+\) -**... -*/ +// 2x cbo.zero, 1x addi 64 int clear_buf_128 (void *p) { p = __builtin_assume_aligned(p, 64); __builtin_memset (p, 0, 128); } + +/* { dg-final { scan-assembler-times "cbo\.zero\t" 3 } } */ +/* { dg-final { scan-assembler-times "addi\ta\[0-9\]+,a\[0-9\]+,64" 1 } } */ +/* { dg-final { scan-assembler-times "sd\t" 7 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "sw\t" 14 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "sh\t" 1 } } */ +/* { dg-final { scan-assembler-times "sb\t" 1 } } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Test cbo.zero expansion for rv32
https://gcc.gnu.org/g:c34c8a587139cd1103d2d742c003574c88bc5e85 commit c34c8a587139cd1103d2d742c003574c88bc5e85 Author: Christoph Müllner Date: Wed May 15 01:34:54 2024 +0200 RISC-V: Test cbo.zero expansion for rv32 We had an issue when expanding via cmo-zero for RV32. This was fixed upstream, but we don't have a RV32 test. Therefore, this patch introduces such a test. gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-zicboz-zic64-1.c: Fix for rv32. Signed-off-by: Christoph Müllner (cherry picked from commit 5609d77e683944439fae38323ecabc44a1eb4671) Diff: --- .../gcc.target/riscv/cmo-zicboz-zic64-1.c | 37 +++--- 1 file changed, 11 insertions(+), 26 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c index 6d4535287d0..9192b391b11 100644 --- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c @@ -1,24 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc_zic64b_zicboz -mabi=lp64d" } */ +/* { dg-options "-march=rv32gc_zic64b_zicboz" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_zic64b_zicboz" { target { rv64 } } } */ /* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-allow-blank-lines-in-output 1 } */ -/* -**clear_buf_123: -**... -**cbo\.zero\t0\(a[0-9]+\) -**sd\tzero,64\(a[0-9]+\) -**sd\tzero,72\(a[0-9]+\) -**sd\tzero,80\(a[0-9]+\) -**sd\tzero,88\(a[0-9]+\) -**sd\tzero,96\(a[0-9]+\) -**sd\tzero,104\(a[0-9]+\) -**sd\tzero,112\(a[0-9]+\) -**sh\tzero,120\(a[0-9]+\) -**sb\tzero,122\(a[0-9]+\) -**... -*/ +// 1x cbo.zero, 7x sd (rv64) or 14x sw (rv32), 1x sh, 1x sb int clear_buf_123 (void *p) { @@ -26,17 +11,17 @@ clear_buf_123 (void *p) __builtin_memset (p, 0, 123); } -/* -**clear_buf_128: -**... -**cbo\.zero\t0\(a[0-9]+\) -**addi\ta[0-9]+,a[0-9]+,64 -**cbo\.zero\t0\(a[0-9]+\) -**... -*/ +// 2x cbo.zero, 1x addi 64 int clear_buf_128 (void *p) { p = __builtin_assume_aligned(p, 64); __builtin_memset (p, 0, 128); } + +/* { dg-final { scan-assembler-times "cbo\.zero\t" 3 } } */ +/* { dg-final { scan-assembler-times "addi\ta\[0-9\]+,a\[0-9\]+,64" 1 } } */ +/* { dg-final { scan-assembler-times "sd\t" 7 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "sw\t" 14 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "sh\t" 1 } } */ +/* { dg-final { scan-assembler-times "sb\t" 1 } } */
[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Test cbo.zero expansion for rv32
https://gcc.gnu.org/g:f3d5808070acf09d4ca1da5f5e692be52e3a73a6 commit f3d5808070acf09d4ca1da5f5e692be52e3a73a6 Author: Christoph Müllner Date: Wed May 15 01:34:54 2024 +0200 RISC-V: Test cbo.zero expansion for rv32 We had an issue when expanding via cmo-zero for RV32. This was fixed upstream, but we don't have a RV32 test. Therefore, this patch introduces such a test. gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-zicboz-zic64-1.c: Fix for rv32. Signed-off-by: Christoph Müllner (cherry picked from commit 5609d77e683944439fae38323ecabc44a1eb4671) Diff: --- .../gcc.target/riscv/cmo-zicboz-zic64-1.c | 37 +++--- 1 file changed, 11 insertions(+), 26 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c index 6d4535287d08..9192b391b11d 100644 --- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c @@ -1,24 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc_zic64b_zicboz -mabi=lp64d" } */ +/* { dg-options "-march=rv32gc_zic64b_zicboz" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_zic64b_zicboz" { target { rv64 } } } */ /* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ -/* { dg-allow-blank-lines-in-output 1 } */ -/* -**clear_buf_123: -**... -**cbo\.zero\t0\(a[0-9]+\) -**sd\tzero,64\(a[0-9]+\) -**sd\tzero,72\(a[0-9]+\) -**sd\tzero,80\(a[0-9]+\) -**sd\tzero,88\(a[0-9]+\) -**sd\tzero,96\(a[0-9]+\) -**sd\tzero,104\(a[0-9]+\) -**sd\tzero,112\(a[0-9]+\) -**sh\tzero,120\(a[0-9]+\) -**sb\tzero,122\(a[0-9]+\) -**... -*/ +// 1x cbo.zero, 7x sd (rv64) or 14x sw (rv32), 1x sh, 1x sb int clear_buf_123 (void *p) { @@ -26,17 +11,17 @@ clear_buf_123 (void *p) __builtin_memset (p, 0, 123); } -/* -**clear_buf_128: -**... -**cbo\.zero\t0\(a[0-9]+\) -**addi\ta[0-9]+,a[0-9]+,64 -**cbo\.zero\t0\(a[0-9]+\) -**... -*/ +// 2x cbo.zero, 1x addi 64 int clear_buf_128 (void *p) { p = __builtin_assume_aligned(p, 64); __builtin_memset (p, 0, 128); } + +/* { dg-final { scan-assembler-times "cbo\.zero\t" 3 } } */ +/* { dg-final { scan-assembler-times "addi\ta\[0-9\]+,a\[0-9\]+,64" 1 } } */ +/* { dg-final { scan-assembler-times "sd\t" 7 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "sw\t" 14 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "sh\t" 1 } } */ +/* { dg-final { scan-assembler-times "sb\t" 1 } } */