[gcc r15-1199] doc: Update Cygwin web link

[Gerald Pfeifer via Gcc-cvs]

https://gcc.gnu.org/g:2d6874ac667e215604ad1521e25eed9d12c98956

commit r15-1199-g2d6874ac667e215604ad1521e25eed9d12c98956
Author: Gerald Pfeifer 
Date:   Wed Jun 12 09:00:40 2024 +0200

doc: Update Cygwin web link

gcc:
PR target/69374
* doc/install.texi (Specific) <*-*-cygwin>: Update web link.

Diff:
---
 gcc/doc/install.texi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 621c874d268d..165d48c02f8a 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -5193,7 +5193,7 @@ UWIN support has been removed due to a lack of 
maintenance.
 @anchor{x-x-cygwin}
 @heading *-*-cygwin
 Ports of GCC are included with the
-@uref{http://www.cygwin.com/,,Cygwin environment}.
+@uref{https://cygwin.com,,Cygwin environment}.
 
 GCC will build under Cygwin without modification; it does not build
 with Microsoft's C++ compiler and there are no plans to make it do so.

[gcc r15-1200] arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

[Torbjorn Svensson via Gcc-cvs]

https://gcc.gnu.org/g:65bd0655ece268895e5018e393bafb769e201c78

commit r15-1200-g65bd0655ece268895e5018e393bafb769e201c78
Author: Torbjörn SVENSSON 
Date:   Thu Jun 6 17:12:11 2024 +0200

arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

Properly handle zero and sign extension for Armv8-M.baseline as
Cortex-M23 can have the security extension active.
Currently, there is an internal compiler error on Cortex-M23 for the
epilog processing of sign extension.

This patch addresses the following CVE-2024-0151 for Armv8-M.baseline.

gcc/ChangeLog:

PR target/115253
* config/arm/arm.cc (cmse_nonsecure_call_inline_register_clear):
Sign extend for Thumb1.
(thumb1_expand_prologue): Add zero/sign extend.

Signed-off-by: Torbjörn SVENSSON 
Co-authored-by: Yvan ROUX 

Diff:
---
 gcc/config/arm/arm.cc | 76 +--
 1 file changed, 68 insertions(+), 8 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index ea0c963a4d67..b8c32db0a1d7 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -19220,17 +19220,25 @@ cmse_nonsecure_call_inline_register_clear (void)
  || TREE_CODE (ret_type) == BOOLEAN_TYPE)
  && known_lt (GET_MODE_SIZE (TYPE_MODE (ret_type)), 4))
{
- machine_mode ret_mode = TYPE_MODE (ret_type);
+ rtx ret_reg = gen_rtx_REG (TYPE_MODE (ret_type), R0_REGNUM);
+ rtx si_reg = gen_rtx_REG (SImode, R0_REGNUM);
  rtx extend;
  if (TYPE_UNSIGNED (ret_type))
-   extend = gen_rtx_ZERO_EXTEND (SImode,
- gen_rtx_REG (ret_mode, 
R0_REGNUM));
+   extend = gen_rtx_SET (si_reg, gen_rtx_ZERO_EXTEND (SImode,
+  ret_reg));
  else
-   extend = gen_rtx_SIGN_EXTEND (SImode,
- gen_rtx_REG (ret_mode, 
R0_REGNUM));
- emit_insn_after (gen_rtx_SET (gen_rtx_REG (SImode, R0_REGNUM),
-extend), insn);
-
+   {
+ /* Signed-extension is a special case because of
+thumb1_extendhisi2.  */
+ if (TARGET_THUMB1
+ && known_eq (GET_MODE_SIZE (TYPE_MODE (ret_type)), 2))
+   extend = gen_thumb1_extendhisi2 (si_reg, ret_reg);
+ else
+   extend = gen_rtx_SET (si_reg,
+ gen_rtx_SIGN_EXTEND (SImode,
+  ret_reg));
+   }
+ emit_insn_after (extend, insn);
}
 
 
@@ -27250,6 +27258,58 @@ thumb1_expand_prologue (void)
   live_regs_mask = offsets->saved_regs_mask;
   lr_needs_saving = live_regs_mask & (1 << LR_REGNUM);
 
+  /* The AAPCS requires the callee to widen integral types narrower
+ than 32 bits to the full width of the register; but when handling
+ calls to non-secure space, we cannot trust the callee to have
+ correctly done so.  So forcibly re-widen the result here.  */
+  if (IS_CMSE_ENTRY (func_type))
+{
+  function_args_iterator args_iter;
+  CUMULATIVE_ARGS args_so_far_v;
+  cumulative_args_t args_so_far;
+  bool first_param = true;
+  tree arg_type;
+  tree fndecl = current_function_decl;
+  tree fntype = TREE_TYPE (fndecl);
+  arm_init_cumulative_args (&args_so_far_v, fntype, NULL_RTX, fndecl);
+  args_so_far = pack_cumulative_args (&args_so_far_v);
+  FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
+   {
+ rtx arg_rtx;
+
+ if (VOID_TYPE_P (arg_type))
+   break;
+
+ function_arg_info arg (arg_type, /*named=*/true);
+ if (!first_param)
+   /* We should advance after processing the argument and pass
+  the argument we're advancing past.  */
+   arm_function_arg_advance (args_so_far, arg);
+ first_param = false;
+ arg_rtx = arm_function_arg (args_so_far, arg);
+ gcc_assert (REG_P (arg_rtx));
+ if ((TREE_CODE (arg_type) == INTEGER_TYPE
+ || TREE_CODE (arg_type) == ENUMERAL_TYPE
+ || TREE_CODE (arg_type) == BOOLEAN_TYPE)
+ && known_lt (GET_MODE_SIZE (GET_MODE (arg_rtx)), 4))
+   {
+ rtx res_reg = gen_rtx_REG (SImode, REGNO (arg_rtx));
+ if (TYPE_UNSIGNED (arg_type))
+   emit_set_insn (res_reg, gen_rtx_ZERO_EXTEND (SImode, arg_rtx));
+ else
+   {
+ /* Signed-extension is a special case because of
+thumb1_extendhisi2.  */
+ if (known_eq (GET_MODE_SIZE (GET_MODE (arg_rtx)), 2))
+   emit_insn (gen_thumb1_extendhisi2 (re

[gcc r15-1201] testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115253]

[Torbjorn Svensson via Gcc-cvs]

https://gcc.gnu.org/g:cf5f9171bae1f5f3034dc9a055b77446962f1a8c

commit r15-1201-gcf5f9171bae1f5f3034dc9a055b77446962f1a8c
Author: Torbjörn SVENSSON 
Date:   Fri Jun 7 10:42:22 2024 +0200

testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115253]

For Armv8.1-M, the clearing of the registers is handled differently than
for Armv8-M, so update the test case accordingly.

gcc/testsuite/ChangeLog:

PR target/115253
* gcc.target/arm/cmse/extend-return.c: Update test case
condition for Armv8.1-M.

Signed-off-by: Torbjörn SVENSSON 
Co-authored-by: Yvan ROUX 

Diff:
---
 gcc/testsuite/gcc.target/arm/cmse/extend-return.c | 62 ---
 1 file changed, 56 insertions(+), 6 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/cmse/extend-return.c 
b/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
index 081de0d699f8..2288d166bd3b 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -fshort-enums" } */
+/* ARMv8-M expectation with target { ! arm_cmse_clear_ok }.  */
+/* ARMv8.1-M expectation with target arm_cmse_clear_ok.  */
 /* { dg-final { check-function-bodies "**" "" "" } } */
 
 #include 
@@ -20,7 +22,15 @@ typedef enum offset __attribute__ ((cmse_nonsecure_call)) 
ns_enum_foo_t (void);
 typedef bool __attribute__ ((cmse_nonsecure_call)) ns_bool_foo_t (void);
 
 /*
-**unsignNonsecure0:
+**unsignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**unsignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0
@@ -32,7 +42,15 @@ unsigned char unsignNonsecure0 (ns_unsign_foo_t * ns_foo_p)
 }
 
 /*
-**signNonsecure0:
+**signNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** sxtbr0, r0
+** ...
+*/
+/*
+**signNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** sxtbr0, r0
@@ -44,7 +62,15 @@ signed char signNonsecure0 (ns_sign_foo_t * ns_foo_p)
 }
 
 /*
-**shortUnsignNonsecure0:
+**shortUnsignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxthr0, r0
+** ...
+*/
+/*
+**shortUnsignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxthr0, r0
@@ -56,7 +82,15 @@ unsigned short shortUnsignNonsecure0 (ns_short_unsign_foo_t 
* ns_foo_p)
 }
 
 /*
-**shortSignNonsecure0:
+**shortSignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** sxthr0, r0
+** ...
+*/
+/*
+**shortSignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** sxthr0, r0
@@ -68,7 +102,15 @@ signed short shortSignNonsecure0 (ns_short_sign_foo_t * 
ns_foo_p)
 }
 
 /*
-**enumNonsecure0:
+**enumNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**enumNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0
@@ -80,7 +122,15 @@ unsigned char __attribute__((noipa)) enumNonsecure0 
(ns_enum_foo_t * ns_foo_p)
 }
 
 /*
-**boolNonsecure0:
+**boolNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**boolNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0

[gcc r14-10306] arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

[Torbjorn Svensson via Gcc-cvs]

https://gcc.gnu.org/g:a657148995e1c46178637c8de82d1fab5474a37d

commit r14-10306-ga657148995e1c46178637c8de82d1fab5474a37d
Author: Torbjörn SVENSSON 
Date:   Thu Jun 6 17:12:11 2024 +0200

arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

Properly handle zero and sign extension for Armv8-M.baseline as
Cortex-M23 can have the security extension active.
Currently, there is an internal compiler error on Cortex-M23 for the
epilog processing of sign extension.

This patch addresses the following CVE-2024-0151 for Armv8-M.baseline.

gcc/ChangeLog:

PR target/115253
* config/arm/arm.cc (cmse_nonsecure_call_inline_register_clear):
Sign extend for Thumb1.
(thumb1_expand_prologue): Add zero/sign extend.

Signed-off-by: Torbjörn SVENSSON 
Co-authored-by: Yvan ROUX 
(cherry picked from commit 65bd0655ece268895e5018e393bafb769e201c78)

Diff:
---
 gcc/config/arm/arm.cc | 76 +--
 1 file changed, 68 insertions(+), 8 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index ea0c963a4d67..b8c32db0a1d7 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -19220,17 +19220,25 @@ cmse_nonsecure_call_inline_register_clear (void)
  || TREE_CODE (ret_type) == BOOLEAN_TYPE)
  && known_lt (GET_MODE_SIZE (TYPE_MODE (ret_type)), 4))
{
- machine_mode ret_mode = TYPE_MODE (ret_type);
+ rtx ret_reg = gen_rtx_REG (TYPE_MODE (ret_type), R0_REGNUM);
+ rtx si_reg = gen_rtx_REG (SImode, R0_REGNUM);
  rtx extend;
  if (TYPE_UNSIGNED (ret_type))
-   extend = gen_rtx_ZERO_EXTEND (SImode,
- gen_rtx_REG (ret_mode, 
R0_REGNUM));
+   extend = gen_rtx_SET (si_reg, gen_rtx_ZERO_EXTEND (SImode,
+  ret_reg));
  else
-   extend = gen_rtx_SIGN_EXTEND (SImode,
- gen_rtx_REG (ret_mode, 
R0_REGNUM));
- emit_insn_after (gen_rtx_SET (gen_rtx_REG (SImode, R0_REGNUM),
-extend), insn);
-
+   {
+ /* Signed-extension is a special case because of
+thumb1_extendhisi2.  */
+ if (TARGET_THUMB1
+ && known_eq (GET_MODE_SIZE (TYPE_MODE (ret_type)), 2))
+   extend = gen_thumb1_extendhisi2 (si_reg, ret_reg);
+ else
+   extend = gen_rtx_SET (si_reg,
+ gen_rtx_SIGN_EXTEND (SImode,
+  ret_reg));
+   }
+ emit_insn_after (extend, insn);
}
 
 
@@ -27250,6 +27258,58 @@ thumb1_expand_prologue (void)
   live_regs_mask = offsets->saved_regs_mask;
   lr_needs_saving = live_regs_mask & (1 << LR_REGNUM);
 
+  /* The AAPCS requires the callee to widen integral types narrower
+ than 32 bits to the full width of the register; but when handling
+ calls to non-secure space, we cannot trust the callee to have
+ correctly done so.  So forcibly re-widen the result here.  */
+  if (IS_CMSE_ENTRY (func_type))
+{
+  function_args_iterator args_iter;
+  CUMULATIVE_ARGS args_so_far_v;
+  cumulative_args_t args_so_far;
+  bool first_param = true;
+  tree arg_type;
+  tree fndecl = current_function_decl;
+  tree fntype = TREE_TYPE (fndecl);
+  arm_init_cumulative_args (&args_so_far_v, fntype, NULL_RTX, fndecl);
+  args_so_far = pack_cumulative_args (&args_so_far_v);
+  FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
+   {
+ rtx arg_rtx;
+
+ if (VOID_TYPE_P (arg_type))
+   break;
+
+ function_arg_info arg (arg_type, /*named=*/true);
+ if (!first_param)
+   /* We should advance after processing the argument and pass
+  the argument we're advancing past.  */
+   arm_function_arg_advance (args_so_far, arg);
+ first_param = false;
+ arg_rtx = arm_function_arg (args_so_far, arg);
+ gcc_assert (REG_P (arg_rtx));
+ if ((TREE_CODE (arg_type) == INTEGER_TYPE
+ || TREE_CODE (arg_type) == ENUMERAL_TYPE
+ || TREE_CODE (arg_type) == BOOLEAN_TYPE)
+ && known_lt (GET_MODE_SIZE (GET_MODE (arg_rtx)), 4))
+   {
+ rtx res_reg = gen_rtx_REG (SImode, REGNO (arg_rtx));
+ if (TYPE_UNSIGNED (arg_type))
+   emit_set_insn (res_reg, gen_rtx_ZERO_EXTEND (SImode, arg_rtx));
+ else
+   {
+ /* Signed-extension is a special case because of
+thumb1_extendhisi2.  */
+ if (known_eq (GET_MODE_SIZE (GET_MODE

[gcc r14-10307] testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115253]

[Torbjorn Svensson via Gcc-cvs]

https://gcc.gnu.org/g:9100e78ba28b1b69d1362d18088e897ca0f99594

commit r14-10307-g9100e78ba28b1b69d1362d18088e897ca0f99594
Author: Torbjörn SVENSSON 
Date:   Fri Jun 7 10:42:22 2024 +0200

testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115253]

For Armv8.1-M, the clearing of the registers is handled differently than
for Armv8-M, so update the test case accordingly.

gcc/testsuite/ChangeLog:

PR target/115253
* gcc.target/arm/cmse/extend-return.c: Update test case
condition for Armv8.1-M.

Signed-off-by: Torbjörn SVENSSON 
Co-authored-by: Yvan ROUX 
(cherry picked from commit cf5f9171bae1f5f3034dc9a055b77446962f1a8c)

Diff:
---
 gcc/testsuite/gcc.target/arm/cmse/extend-return.c | 62 ---
 1 file changed, 56 insertions(+), 6 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/cmse/extend-return.c 
b/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
index 081de0d699f8..2288d166bd3b 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -fshort-enums" } */
+/* ARMv8-M expectation with target { ! arm_cmse_clear_ok }.  */
+/* ARMv8.1-M expectation with target arm_cmse_clear_ok.  */
 /* { dg-final { check-function-bodies "**" "" "" } } */
 
 #include 
@@ -20,7 +22,15 @@ typedef enum offset __attribute__ ((cmse_nonsecure_call)) 
ns_enum_foo_t (void);
 typedef bool __attribute__ ((cmse_nonsecure_call)) ns_bool_foo_t (void);
 
 /*
-**unsignNonsecure0:
+**unsignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**unsignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0
@@ -32,7 +42,15 @@ unsigned char unsignNonsecure0 (ns_unsign_foo_t * ns_foo_p)
 }
 
 /*
-**signNonsecure0:
+**signNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** sxtbr0, r0
+** ...
+*/
+/*
+**signNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** sxtbr0, r0
@@ -44,7 +62,15 @@ signed char signNonsecure0 (ns_sign_foo_t * ns_foo_p)
 }
 
 /*
-**shortUnsignNonsecure0:
+**shortUnsignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxthr0, r0
+** ...
+*/
+/*
+**shortUnsignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxthr0, r0
@@ -56,7 +82,15 @@ unsigned short shortUnsignNonsecure0 (ns_short_unsign_foo_t 
* ns_foo_p)
 }
 
 /*
-**shortSignNonsecure0:
+**shortSignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** sxthr0, r0
+** ...
+*/
+/*
+**shortSignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** sxthr0, r0
@@ -68,7 +102,15 @@ signed short shortSignNonsecure0 (ns_short_sign_foo_t * 
ns_foo_p)
 }
 
 /*
-**enumNonsecure0:
+**enumNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**enumNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0
@@ -80,7 +122,15 @@ unsigned char __attribute__((noipa)) enumNonsecure0 
(ns_enum_foo_t * ns_foo_p)
 }
 
 /*
-**boolNonsecure0:
+**boolNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**boolNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0

[gcc r13-8844] arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

[Torbjorn Svensson via Gcc-cvs]

https://gcc.gnu.org/g:bf3ffb44355ca8aeea18c95a2b027023b3dab569

commit r13-8844-gbf3ffb44355ca8aeea18c95a2b027023b3dab569
Author: Torbjörn SVENSSON 
Date:   Thu Jun 6 17:12:11 2024 +0200

arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

Properly handle zero and sign extension for Armv8-M.baseline as
Cortex-M23 can have the security extension active.
Currently, there is an internal compiler error on Cortex-M23 for the
epilog processing of sign extension.

This patch addresses the following CVE-2024-0151 for Armv8-M.baseline.

gcc/ChangeLog:

PR target/115253
* config/arm/arm.cc (cmse_nonsecure_call_inline_register_clear):
Sign extend for Thumb1.
(thumb1_expand_prologue): Add zero/sign extend.

Signed-off-by: Torbjörn SVENSSON 
Co-authored-by: Yvan ROUX 
(cherry picked from commit 65bd0655ece268895e5018e393bafb769e201c78)

Diff:
---
 gcc/config/arm/arm.cc | 76 +--
 1 file changed, 68 insertions(+), 8 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index cd82728ae603..c00c6d7c1e66 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -19143,17 +19143,25 @@ cmse_nonsecure_call_inline_register_clear (void)
  || TREE_CODE (ret_type) == BOOLEAN_TYPE)
  && known_lt (GET_MODE_SIZE (TYPE_MODE (ret_type)), 4))
{
- machine_mode ret_mode = TYPE_MODE (ret_type);
+ rtx ret_reg = gen_rtx_REG (TYPE_MODE (ret_type), R0_REGNUM);
+ rtx si_reg = gen_rtx_REG (SImode, R0_REGNUM);
  rtx extend;
  if (TYPE_UNSIGNED (ret_type))
-   extend = gen_rtx_ZERO_EXTEND (SImode,
- gen_rtx_REG (ret_mode, 
R0_REGNUM));
+   extend = gen_rtx_SET (si_reg, gen_rtx_ZERO_EXTEND (SImode,
+  ret_reg));
  else
-   extend = gen_rtx_SIGN_EXTEND (SImode,
- gen_rtx_REG (ret_mode, 
R0_REGNUM));
- emit_insn_after (gen_rtx_SET (gen_rtx_REG (SImode, R0_REGNUM),
-extend), insn);
-
+   {
+ /* Signed-extension is a special case because of
+thumb1_extendhisi2.  */
+ if (TARGET_THUMB1
+ && known_eq (GET_MODE_SIZE (TYPE_MODE (ret_type)), 2))
+   extend = gen_thumb1_extendhisi2 (si_reg, ret_reg);
+ else
+   extend = gen_rtx_SET (si_reg,
+ gen_rtx_SIGN_EXTEND (SImode,
+  ret_reg));
+   }
+ emit_insn_after (extend, insn);
}
 
 
@@ -27172,6 +27180,58 @@ thumb1_expand_prologue (void)
   live_regs_mask = offsets->saved_regs_mask;
   lr_needs_saving = live_regs_mask & (1 << LR_REGNUM);
 
+  /* The AAPCS requires the callee to widen integral types narrower
+ than 32 bits to the full width of the register; but when handling
+ calls to non-secure space, we cannot trust the callee to have
+ correctly done so.  So forcibly re-widen the result here.  */
+  if (IS_CMSE_ENTRY (func_type))
+{
+  function_args_iterator args_iter;
+  CUMULATIVE_ARGS args_so_far_v;
+  cumulative_args_t args_so_far;
+  bool first_param = true;
+  tree arg_type;
+  tree fndecl = current_function_decl;
+  tree fntype = TREE_TYPE (fndecl);
+  arm_init_cumulative_args (&args_so_far_v, fntype, NULL_RTX, fndecl);
+  args_so_far = pack_cumulative_args (&args_so_far_v);
+  FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
+   {
+ rtx arg_rtx;
+
+ if (VOID_TYPE_P (arg_type))
+   break;
+
+ function_arg_info arg (arg_type, /*named=*/true);
+ if (!first_param)
+   /* We should advance after processing the argument and pass
+  the argument we're advancing past.  */
+   arm_function_arg_advance (args_so_far, arg);
+ first_param = false;
+ arg_rtx = arm_function_arg (args_so_far, arg);
+ gcc_assert (REG_P (arg_rtx));
+ if ((TREE_CODE (arg_type) == INTEGER_TYPE
+ || TREE_CODE (arg_type) == ENUMERAL_TYPE
+ || TREE_CODE (arg_type) == BOOLEAN_TYPE)
+ && known_lt (GET_MODE_SIZE (GET_MODE (arg_rtx)), 4))
+   {
+ rtx res_reg = gen_rtx_REG (SImode, REGNO (arg_rtx));
+ if (TYPE_UNSIGNED (arg_type))
+   emit_set_insn (res_reg, gen_rtx_ZERO_EXTEND (SImode, arg_rtx));
+ else
+   {
+ /* Signed-extension is a special case because of
+thumb1_extendhisi2.  */
+ if (known_eq (GET_MODE_SIZE (GET_MODE 

[gcc r13-8845] testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115253]

[Torbjorn Svensson via Gcc-cvs]

https://gcc.gnu.org/g:dfab6851eb557a47a5e61d00ad4c519072a69f61

commit r13-8845-gdfab6851eb557a47a5e61d00ad4c519072a69f61
Author: Torbjörn SVENSSON 
Date:   Fri Jun 7 10:42:22 2024 +0200

testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115253]

For Armv8.1-M, the clearing of the registers is handled differently than
for Armv8-M, so update the test case accordingly.

gcc/testsuite/ChangeLog:

PR target/115253
* gcc.target/arm/cmse/extend-return.c: Update test case
condition for Armv8.1-M.

Signed-off-by: Torbjörn SVENSSON 
Co-authored-by: Yvan ROUX 
(cherry picked from commit cf5f9171bae1f5f3034dc9a055b77446962f1a8c)

Diff:
---
 gcc/testsuite/gcc.target/arm/cmse/extend-return.c | 62 ---
 1 file changed, 56 insertions(+), 6 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/cmse/extend-return.c 
b/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
index 081de0d699f8..2288d166bd3b 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -fshort-enums" } */
+/* ARMv8-M expectation with target { ! arm_cmse_clear_ok }.  */
+/* ARMv8.1-M expectation with target arm_cmse_clear_ok.  */
 /* { dg-final { check-function-bodies "**" "" "" } } */
 
 #include 
@@ -20,7 +22,15 @@ typedef enum offset __attribute__ ((cmse_nonsecure_call)) 
ns_enum_foo_t (void);
 typedef bool __attribute__ ((cmse_nonsecure_call)) ns_bool_foo_t (void);
 
 /*
-**unsignNonsecure0:
+**unsignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**unsignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0
@@ -32,7 +42,15 @@ unsigned char unsignNonsecure0 (ns_unsign_foo_t * ns_foo_p)
 }
 
 /*
-**signNonsecure0:
+**signNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** sxtbr0, r0
+** ...
+*/
+/*
+**signNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** sxtbr0, r0
@@ -44,7 +62,15 @@ signed char signNonsecure0 (ns_sign_foo_t * ns_foo_p)
 }
 
 /*
-**shortUnsignNonsecure0:
+**shortUnsignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxthr0, r0
+** ...
+*/
+/*
+**shortUnsignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxthr0, r0
@@ -56,7 +82,15 @@ unsigned short shortUnsignNonsecure0 (ns_short_unsign_foo_t 
* ns_foo_p)
 }
 
 /*
-**shortSignNonsecure0:
+**shortSignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** sxthr0, r0
+** ...
+*/
+/*
+**shortSignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** sxthr0, r0
@@ -68,7 +102,15 @@ signed short shortSignNonsecure0 (ns_short_sign_foo_t * 
ns_foo_p)
 }
 
 /*
-**enumNonsecure0:
+**enumNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**enumNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0
@@ -80,7 +122,15 @@ unsigned char __attribute__((noipa)) enumNonsecure0 
(ns_enum_foo_t * ns_foo_p)
 }
 
 /*
-**boolNonsecure0:
+**boolNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**boolNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0

[gcc r12-10550] arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

[Torbjorn Svensson via Gcc-cvs]

https://gcc.gnu.org/g:55c1687d542e40f0d4ad1d3dc624695a1854d967

commit r12-10550-g55c1687d542e40f0d4ad1d3dc624695a1854d967
Author: Torbjörn SVENSSON 
Date:   Thu Jun 6 17:12:11 2024 +0200

arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

Properly handle zero and sign extension for Armv8-M.baseline as
Cortex-M23 can have the security extension active.
Currently, there is an internal compiler error on Cortex-M23 for the
epilog processing of sign extension.

This patch addresses the following CVE-2024-0151 for Armv8-M.baseline.

gcc/ChangeLog:

PR target/115253
* config/arm/arm.cc (cmse_nonsecure_call_inline_register_clear):
Sign extend for Thumb1.
(thumb1_expand_prologue): Add zero/sign extend.

Signed-off-by: Torbjörn SVENSSON 
Co-authored-by: Yvan ROUX 
(cherry picked from commit 65bd0655ece268895e5018e393bafb769e201c78)

Diff:
---
 gcc/config/arm/arm.cc | 76 +--
 1 file changed, 68 insertions(+), 8 deletions(-)

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index f3064b4e2709..afaa599b6f0f 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -18999,17 +18999,25 @@ cmse_nonsecure_call_inline_register_clear (void)
  || TREE_CODE (ret_type) == BOOLEAN_TYPE)
  && known_lt (GET_MODE_SIZE (TYPE_MODE (ret_type)), 4))
{
- machine_mode ret_mode = TYPE_MODE (ret_type);
+ rtx ret_reg = gen_rtx_REG (TYPE_MODE (ret_type), R0_REGNUM);
+ rtx si_reg = gen_rtx_REG (SImode, R0_REGNUM);
  rtx extend;
  if (TYPE_UNSIGNED (ret_type))
-   extend = gen_rtx_ZERO_EXTEND (SImode,
- gen_rtx_REG (ret_mode, 
R0_REGNUM));
+   extend = gen_rtx_SET (si_reg, gen_rtx_ZERO_EXTEND (SImode,
+  ret_reg));
  else
-   extend = gen_rtx_SIGN_EXTEND (SImode,
- gen_rtx_REG (ret_mode, 
R0_REGNUM));
- emit_insn_after (gen_rtx_SET (gen_rtx_REG (SImode, R0_REGNUM),
-extend), insn);
-
+   {
+ /* Signed-extension is a special case because of
+thumb1_extendhisi2.  */
+ if (TARGET_THUMB1
+ && known_eq (GET_MODE_SIZE (TYPE_MODE (ret_type)), 2))
+   extend = gen_thumb1_extendhisi2 (si_reg, ret_reg);
+ else
+   extend = gen_rtx_SET (si_reg,
+ gen_rtx_SIGN_EXTEND (SImode,
+  ret_reg));
+   }
+ emit_insn_after (extend, insn);
}
 
 
@@ -26947,6 +26955,58 @@ thumb1_expand_prologue (void)
   live_regs_mask = offsets->saved_regs_mask;
   lr_needs_saving = live_regs_mask & (1 << LR_REGNUM);
 
+  /* The AAPCS requires the callee to widen integral types narrower
+ than 32 bits to the full width of the register; but when handling
+ calls to non-secure space, we cannot trust the callee to have
+ correctly done so.  So forcibly re-widen the result here.  */
+  if (IS_CMSE_ENTRY (func_type))
+{
+  function_args_iterator args_iter;
+  CUMULATIVE_ARGS args_so_far_v;
+  cumulative_args_t args_so_far;
+  bool first_param = true;
+  tree arg_type;
+  tree fndecl = current_function_decl;
+  tree fntype = TREE_TYPE (fndecl);
+  arm_init_cumulative_args (&args_so_far_v, fntype, NULL_RTX, fndecl);
+  args_so_far = pack_cumulative_args (&args_so_far_v);
+  FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
+   {
+ rtx arg_rtx;
+
+ if (VOID_TYPE_P (arg_type))
+   break;
+
+ function_arg_info arg (arg_type, /*named=*/true);
+ if (!first_param)
+   /* We should advance after processing the argument and pass
+  the argument we're advancing past.  */
+   arm_function_arg_advance (args_so_far, arg);
+ first_param = false;
+ arg_rtx = arm_function_arg (args_so_far, arg);
+ gcc_assert (REG_P (arg_rtx));
+ if ((TREE_CODE (arg_type) == INTEGER_TYPE
+ || TREE_CODE (arg_type) == ENUMERAL_TYPE
+ || TREE_CODE (arg_type) == BOOLEAN_TYPE)
+ && known_lt (GET_MODE_SIZE (GET_MODE (arg_rtx)), 4))
+   {
+ rtx res_reg = gen_rtx_REG (SImode, REGNO (arg_rtx));
+ if (TYPE_UNSIGNED (arg_type))
+   emit_set_insn (res_reg, gen_rtx_ZERO_EXTEND (SImode, arg_rtx));
+ else
+   {
+ /* Signed-extension is a special case because of
+thumb1_extendhisi2.  */
+ if (known_eq (GET_MODE_SIZE (GET_MODE

[gcc r12-10551] testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115253]

[Torbjorn Svensson via Gcc-cvs]

https://gcc.gnu.org/g:3d9e4eedb6b1f43e5d0cd46c9aa06caf7c2d3500

commit r12-10551-g3d9e4eedb6b1f43e5d0cd46c9aa06caf7c2d3500
Author: Torbjörn SVENSSON 
Date:   Fri Jun 7 10:42:22 2024 +0200

testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115253]

For Armv8.1-M, the clearing of the registers is handled differently than
for Armv8-M, so update the test case accordingly.

gcc/testsuite/ChangeLog:

PR target/115253
* gcc.target/arm/cmse/extend-return.c: Update test case
condition for Armv8.1-M.

Signed-off-by: Torbjörn SVENSSON 
Co-authored-by: Yvan ROUX 
(cherry picked from commit cf5f9171bae1f5f3034dc9a055b77446962f1a8c)

Diff:
---
 gcc/testsuite/gcc.target/arm/cmse/extend-return.c | 62 ---
 1 file changed, 56 insertions(+), 6 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/cmse/extend-return.c 
b/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
index 081de0d699f8..2288d166bd3b 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -fshort-enums" } */
+/* ARMv8-M expectation with target { ! arm_cmse_clear_ok }.  */
+/* ARMv8.1-M expectation with target arm_cmse_clear_ok.  */
 /* { dg-final { check-function-bodies "**" "" "" } } */
 
 #include 
@@ -20,7 +22,15 @@ typedef enum offset __attribute__ ((cmse_nonsecure_call)) 
ns_enum_foo_t (void);
 typedef bool __attribute__ ((cmse_nonsecure_call)) ns_bool_foo_t (void);
 
 /*
-**unsignNonsecure0:
+**unsignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**unsignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0
@@ -32,7 +42,15 @@ unsigned char unsignNonsecure0 (ns_unsign_foo_t * ns_foo_p)
 }
 
 /*
-**signNonsecure0:
+**signNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** sxtbr0, r0
+** ...
+*/
+/*
+**signNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** sxtbr0, r0
@@ -44,7 +62,15 @@ signed char signNonsecure0 (ns_sign_foo_t * ns_foo_p)
 }
 
 /*
-**shortUnsignNonsecure0:
+**shortUnsignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxthr0, r0
+** ...
+*/
+/*
+**shortUnsignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxthr0, r0
@@ -56,7 +82,15 @@ unsigned short shortUnsignNonsecure0 (ns_short_unsign_foo_t 
* ns_foo_p)
 }
 
 /*
-**shortSignNonsecure0:
+**shortSignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** sxthr0, r0
+** ...
+*/
+/*
+**shortSignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** sxthr0, r0
@@ -68,7 +102,15 @@ signed short shortSignNonsecure0 (ns_short_sign_foo_t * 
ns_foo_p)
 }
 
 /*
-**enumNonsecure0:
+**enumNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**enumNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0
@@ -80,7 +122,15 @@ unsigned char __attribute__((noipa)) enumNonsecure0 
(ns_enum_foo_t * ns_foo_p)
 }
 
 /*
-**boolNonsecure0:
+**boolNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**boolNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0

[gcc r11-11477] arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

[Torbjorn Svensson via Gcc-cvs]

https://gcc.gnu.org/g:319081d614dec354ae415472121e0e8ebc4b1402

commit r11-11477-g319081d614dec354ae415472121e0e8ebc4b1402
Author: Torbjörn SVENSSON 
Date:   Thu Jun 6 17:12:11 2024 +0200

arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]

Properly handle zero and sign extension for Armv8-M.baseline as
Cortex-M23 can have the security extension active.
Currently, there is an internal compiler error on Cortex-M23 for the
epilog processing of sign extension.

This patch addresses the following CVE-2024-0151 for Armv8-M.baseline.

gcc/ChangeLog:

PR target/115253
* config/arm/arm.c (cmse_nonsecure_call_inline_register_clear):
Sign extend for Thumb1.
(thumb1_expand_prologue): Add zero/sign extend.

Signed-off-by: Torbjörn SVENSSON 
Co-authored-by: Yvan ROUX 
(cherry picked from commit 65bd0655ece268895e5018e393bafb769e201c78)

Diff:
---
 gcc/config/arm/arm.c | 76 ++--
 1 file changed, 68 insertions(+), 8 deletions(-)

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index e386186db6f9..b152aeed77f1 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -18874,17 +18874,25 @@ cmse_nonsecure_call_inline_register_clear (void)
  || TREE_CODE (ret_type) == BOOLEAN_TYPE)
  && known_lt (GET_MODE_SIZE (TYPE_MODE (ret_type)), 4))
{
- machine_mode ret_mode = TYPE_MODE (ret_type);
+ rtx ret_reg = gen_rtx_REG (TYPE_MODE (ret_type), R0_REGNUM);
+ rtx si_reg = gen_rtx_REG (SImode, R0_REGNUM);
  rtx extend;
  if (TYPE_UNSIGNED (ret_type))
-   extend = gen_rtx_ZERO_EXTEND (SImode,
- gen_rtx_REG (ret_mode, 
R0_REGNUM));
+   extend = gen_rtx_SET (si_reg, gen_rtx_ZERO_EXTEND (SImode,
+  ret_reg));
  else
-   extend = gen_rtx_SIGN_EXTEND (SImode,
- gen_rtx_REG (ret_mode, 
R0_REGNUM));
- emit_insn_after (gen_rtx_SET (gen_rtx_REG (SImode, R0_REGNUM),
-extend), insn);
-
+   {
+ /* Signed-extension is a special case because of
+thumb1_extendhisi2.  */
+ if (TARGET_THUMB1
+ && known_eq (GET_MODE_SIZE (TYPE_MODE (ret_type)), 2))
+   extend = gen_thumb1_extendhisi2 (si_reg, ret_reg);
+ else
+   extend = gen_rtx_SET (si_reg,
+ gen_rtx_SIGN_EXTEND (SImode,
+  ret_reg));
+   }
+ emit_insn_after (extend, insn);
}
 
 
@@ -26815,6 +26823,58 @@ thumb1_expand_prologue (void)
   live_regs_mask = offsets->saved_regs_mask;
   lr_needs_saving = live_regs_mask & (1 << LR_REGNUM);
 
+  /* The AAPCS requires the callee to widen integral types narrower
+ than 32 bits to the full width of the register; but when handling
+ calls to non-secure space, we cannot trust the callee to have
+ correctly done so.  So forcibly re-widen the result here.  */
+  if (IS_CMSE_ENTRY (func_type))
+{
+  function_args_iterator args_iter;
+  CUMULATIVE_ARGS args_so_far_v;
+  cumulative_args_t args_so_far;
+  bool first_param = true;
+  tree arg_type;
+  tree fndecl = current_function_decl;
+  tree fntype = TREE_TYPE (fndecl);
+  arm_init_cumulative_args (&args_so_far_v, fntype, NULL_RTX, fndecl);
+  args_so_far = pack_cumulative_args (&args_so_far_v);
+  FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
+   {
+ rtx arg_rtx;
+
+ if (VOID_TYPE_P (arg_type))
+   break;
+
+ function_arg_info arg (arg_type, /*named=*/true);
+ if (!first_param)
+   /* We should advance after processing the argument and pass
+  the argument we're advancing past.  */
+   arm_function_arg_advance (args_so_far, arg);
+ first_param = false;
+ arg_rtx = arm_function_arg (args_so_far, arg);
+ gcc_assert (REG_P (arg_rtx));
+ if ((TREE_CODE (arg_type) == INTEGER_TYPE
+ || TREE_CODE (arg_type) == ENUMERAL_TYPE
+ || TREE_CODE (arg_type) == BOOLEAN_TYPE)
+ && known_lt (GET_MODE_SIZE (GET_MODE (arg_rtx)), 4))
+   {
+ rtx res_reg = gen_rtx_REG (SImode, REGNO (arg_rtx));
+ if (TYPE_UNSIGNED (arg_type))
+   emit_set_insn (res_reg, gen_rtx_ZERO_EXTEND (SImode, arg_rtx));
+ else
+   {
+ /* Signed-extension is a special case because of
+thumb1_extendhisi2.  */
+ if (known_eq (GET_MODE_SIZE (GET_MODE (arg

[gcc r11-11478] testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115253]

[Torbjorn Svensson via Gcc-cvs]

https://gcc.gnu.org/g:bf9c877c4c9939274520a3f694037a9921ba9878

commit r11-11478-gbf9c877c4c9939274520a3f694037a9921ba9878
Author: Torbjörn SVENSSON 
Date:   Fri Jun 7 10:42:22 2024 +0200

testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115253]

For Armv8.1-M, the clearing of the registers is handled differently than
for Armv8-M, so update the test case accordingly.

gcc/testsuite/ChangeLog:

PR target/115253
* gcc.target/arm/cmse/extend-return.c: Update test case
condition for Armv8.1-M.

Signed-off-by: Torbjörn SVENSSON 
Co-authored-by: Yvan ROUX 
(cherry picked from commit cf5f9171bae1f5f3034dc9a055b77446962f1a8c)

Diff:
---
 gcc/testsuite/gcc.target/arm/cmse/extend-return.c | 62 ---
 1 file changed, 56 insertions(+), 6 deletions(-)

diff --git a/gcc/testsuite/gcc.target/arm/cmse/extend-return.c 
b/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
index 081de0d699f8..2288d166bd3b 100644
--- a/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
+++ b/gcc/testsuite/gcc.target/arm/cmse/extend-return.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mcmse -fshort-enums" } */
+/* ARMv8-M expectation with target { ! arm_cmse_clear_ok }.  */
+/* ARMv8.1-M expectation with target arm_cmse_clear_ok.  */
 /* { dg-final { check-function-bodies "**" "" "" } } */
 
 #include 
@@ -20,7 +22,15 @@ typedef enum offset __attribute__ ((cmse_nonsecure_call)) 
ns_enum_foo_t (void);
 typedef bool __attribute__ ((cmse_nonsecure_call)) ns_bool_foo_t (void);
 
 /*
-**unsignNonsecure0:
+**unsignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**unsignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0
@@ -32,7 +42,15 @@ unsigned char unsignNonsecure0 (ns_unsign_foo_t * ns_foo_p)
 }
 
 /*
-**signNonsecure0:
+**signNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** sxtbr0, r0
+** ...
+*/
+/*
+**signNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** sxtbr0, r0
@@ -44,7 +62,15 @@ signed char signNonsecure0 (ns_sign_foo_t * ns_foo_p)
 }
 
 /*
-**shortUnsignNonsecure0:
+**shortUnsignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxthr0, r0
+** ...
+*/
+/*
+**shortUnsignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxthr0, r0
@@ -56,7 +82,15 @@ unsigned short shortUnsignNonsecure0 (ns_short_unsign_foo_t 
* ns_foo_p)
 }
 
 /*
-**shortSignNonsecure0:
+**shortSignNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** sxthr0, r0
+** ...
+*/
+/*
+**shortSignNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** sxthr0, r0
@@ -68,7 +102,15 @@ signed short shortSignNonsecure0 (ns_short_sign_foo_t * 
ns_foo_p)
 }
 
 /*
-**enumNonsecure0:
+**enumNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**enumNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0
@@ -80,7 +122,15 @@ unsigned char __attribute__((noipa)) enumNonsecure0 
(ns_enum_foo_t * ns_foo_p)
 }
 
 /*
-**boolNonsecure0:
+**boolNonsecure0:  { target arm_cmse_clear_ok }
+** ...
+** blxns   r[0-3]
+** ...
+** uxtbr0, r0
+** ...
+*/
+/*
+**boolNonsecure0: { target { ! arm_cmse_clear_ok } }
 ** ...
 ** bl  __gnu_cmse_nonsecure_call
 ** uxtbr0, r0

[gcc r15-1203] Libatomic: Define per-file identifier macros

[Victor Do Nascimento via Gcc-cvs]

https://gcc.gnu.org/g:6edf6fe75bd5ab84ae85d008e531002b9d80600c

commit r15-1203-g6edf6fe75bd5ab84ae85d008e531002b9d80600c
Author: Victor Do Nascimento 
Date:   Wed Jan 31 20:24:45 2024 +

Libatomic: Define per-file identifier macros

In order to facilitate the fine-tuning of how `libatomic_i.h' and
`host-config.h' headers are used by different atomic functions, we
define distinct identifier macros for each file which, in implementing
atomic operations, imports these headers.

The idea is that different parts of these headers could then be
conditionally defined depending on the macros set by the file that
`#include'd them.

Given how it is possible that some file names are generic enough that
using them as-is for macro names (e.g. flag.c -> FLAG) may potentially
lead to name clashes with other macros, all file names first have LAT_
prepended to them such that, for example, flag.c is assigned the
LAT_FLAG macro.

Libatomic/ChangeLog:

* cas_n.c (LAT_CAS_N): New.
* exch_n.c (LAT_EXCH_N): Likewise.
* fadd_n.c (LAT_FADD_N): Likewise.
* fand_n.c (LAT_FAND_N): Likewise.
* fence.c (LAT_FENCE): Likewise.
* fenv.c (LAT_FENV): Likewise.
* fior_n.c (LAT_FIOR_N): Likewise.
* flag.c (LAT_FLAG): Likewise.
* fnand_n.c (LAT_FNAND_N): Likewise.
* fop_n.c (LAT_FOP_N): Likewise
* fsub_n.c (LAT_FSUB_N): Likewise.
* fxor_n.c (LAT_FXOR_N): Likewise.
* gcas.c (LAT_GCAS): Likewise.
* gexch.c (LAT_GEXCH): Likewise.
* glfree.c (LAT_GLFREE): Likewise.
* gload.c (LAT_GLOAD): Likewise.
* gstore.c (LAT_GSTORE): Likewise.
* load_n.c (LAT_LOAD_N): Likewise.
* store_n.c (LAT_STORE_N): Likewise.
* tas_n.c (LAT_TAS_N): Likewise.

Diff:
---
 libatomic/cas_n.c   | 2 ++
 libatomic/exch_n.c  | 2 ++
 libatomic/fadd_n.c  | 2 ++
 libatomic/fand_n.c  | 2 ++
 libatomic/fence.c   | 2 ++
 libatomic/fenv.c| 2 ++
 libatomic/fior_n.c  | 2 ++
 libatomic/flag.c| 2 ++
 libatomic/fnand_n.c | 2 ++
 libatomic/fop_n.c   | 2 ++
 libatomic/fsub_n.c  | 2 ++
 libatomic/fxor_n.c  | 2 ++
 libatomic/gcas.c| 2 ++
 libatomic/gexch.c   | 2 ++
 libatomic/glfree.c  | 2 ++
 libatomic/gload.c   | 2 ++
 libatomic/gstore.c  | 2 ++
 libatomic/load_n.c  | 2 ++
 libatomic/store_n.c | 2 ++
 libatomic/tas_n.c   | 2 ++
 20 files changed, 40 insertions(+)

diff --git a/libatomic/cas_n.c b/libatomic/cas_n.c
index a080b990371b..2a6357e48db3 100644
--- a/libatomic/cas_n.c
+++ b/libatomic/cas_n.c
@@ -22,6 +22,7 @@
see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
.  */
 
+#define LAT_CAS_N
 #include "libatomic_i.h"
 
 
@@ -122,3 +123,4 @@ SIZE(libat_compare_exchange) (UTYPE *mptr, UTYPE *eptr, 
UTYPE newval,
 #endif
 
 EXPORT_ALIAS (SIZE(compare_exchange));
+#undef LAT_CAS_N
diff --git a/libatomic/exch_n.c b/libatomic/exch_n.c
index e5ff80769b90..184d3de1009e 100644
--- a/libatomic/exch_n.c
+++ b/libatomic/exch_n.c
@@ -22,6 +22,7 @@
see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
.  */
 
+#define LAT_EXCH_N
 #include "libatomic_i.h"
 
 
@@ -126,3 +127,4 @@ SIZE(libat_exchange) (UTYPE *mptr, UTYPE newval, int smodel 
UNUSED)
 #endif
 
 EXPORT_ALIAS (SIZE(exchange));
+#undef LAT_EXCH_N
diff --git a/libatomic/fadd_n.c b/libatomic/fadd_n.c
index bc15b8bc0e64..32b75cec654f 100644
--- a/libatomic/fadd_n.c
+++ b/libatomic/fadd_n.c
@@ -22,6 +22,7 @@
see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
.  */
 
+#define LAT_FADD_N
 #include 
 
 #define NAME   add
@@ -43,3 +44,4 @@
 #endif
 
 #include "fop_n.c"
+#undef LAT_FADD_N
diff --git a/libatomic/fand_n.c b/libatomic/fand_n.c
index ffe9ed8700fd..9eab55bcd72b 100644
--- a/libatomic/fand_n.c
+++ b/libatomic/fand_n.c
@@ -1,3 +1,5 @@
+#define LAT_FAND_N
 #define NAME   and
 #define OP(X,Y)((X) & (Y))
 #include "fop_n.c"
+#undef LAT_FAND_N
diff --git a/libatomic/fence.c b/libatomic/fence.c
index a9b1e280c5a0..4022194a57ad 100644
--- a/libatomic/fence.c
+++ b/libatomic/fence.c
@@ -21,6 +21,7 @@
see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
.  */
 
+#define LAT_FENCE
 #include "libatomic_i.h"
 
 #include 
@@ -43,3 +44,4 @@ void
 {
   atomic_signal_fence (order);
 }
+#undef LAT_FENCE
diff --git a/libatomic/fenv.c b/libatomic/fenv.c
index 41f187c1f850..dccad356a31f 100644
--- a/libatomic/fenv.c
+++ b/libatomic/fenv.c
@@ -21,6 +21,7 @@
see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
.  */
 
+#define LAT_FENV
 #include "libatomic_i.h"
 
 #ifdef HAVE_FENV_H
@@ -70,3 +71,4 @@ __atomic_feraiseexcept (int excepts __attribute__ ((unused

[gcc r15-1204] Libatomic: Make ifunc selector behavior contingent on importing file

[Victor Do Nascimento via Gcc-cvs]

https://gcc.gnu.org/g:1af4a8451d4149ecbddfe9963e7f7ea3d273cc2d

commit r15-1204-g1af4a8451d4149ecbddfe9963e7f7ea3d273cc2d
Author: Victor Do Nascimento 
Date:   Thu Feb 1 13:27:50 2024 +

Libatomic: Make ifunc selector behavior contingent on importing file

By querying previously-defined file-identifier macros, `host-config.h'
is able to get information about its environment and, based on this
information, select more appropriate function-specific ifunc
selectors.  This reduces the number of unnecessary feature tests that
need to be carried out in order to find the best atomic implementation
for a function at run-time.

An immediate benefit of this is that we can further fine-tune the
architectural requirements for each atomic function without risk of
incurring the maintenance and runtime-performance penalties of having
to maintain an ifunc selector with a huge number of alternatives, most
of which are irrelevant for any particular function.  Consequently,
for AArch64 targets, we relax the architectural requirements of
`compare_exchange_16', which now requires only LSE as opposed to the
newer LSE2.

The new flexibility provided by this approach also means that certain
functions can now be called directly, doing away with ifunc selectors
altogether when only a single implementation is available for it on a
given target.  As per the macro expansion framework laid out in
`libatomic_i.h', such functions should have their names prefixed with
`__atomic_' as opposed to `libat_'.  This is the same prefix applied
to function names when Libatomic is configured with
`--disable-gnu-indirect-function'.

To achieve this, these functions unconditionally apply the aliasing
rule that at present is conditionally applied only when libatomic is
built without ifunc support, which ensures that the default
`libat_##NAME' is accessible via the equivalent `__atomic_##NAME' too.
This is ensured by using the new `ENTRY_ALIASED' macro.

Finally, this means we are able to do away with a whole set of
function aliases that were needed until now, thus considerably
cleaning up the implementation.

libatomic/ChangeLog:

* config/linux/aarch64/atomic_16.S: Remove unnecessary
aliasing.
(LSE): New.
(ENTRY_ALIASED): Likewise.
* config/linux/aarch64/host-config.h (LSE_ATOP): New.
(LSE2_ATOP): Likewise.
(LSE128_ATOP): Likewise.
(IFUNC_COND_1): Make its definition conditional on above 3
macros.
(IFUNC_NCOND): Likewise.

Diff:
---
 libatomic/config/linux/aarch64/atomic_16.S   | 64 
 libatomic/config/linux/aarch64/host-config.h | 35 ---
 2 files changed, 45 insertions(+), 54 deletions(-)

diff --git a/libatomic/config/linux/aarch64/atomic_16.S 
b/libatomic/config/linux/aarch64/atomic_16.S
index d6e71ba6e167..11a296dacc3a 100644
--- a/libatomic/config/linux/aarch64/atomic_16.S
+++ b/libatomic/config/linux/aarch64/atomic_16.S
@@ -45,17 +45,20 @@
.arch   armv8-a+lse
 
 #define LSE128(NAME)   libat_##NAME##_i1
-#define LSE2(NAME) libat_##NAME##_i2
+#define LSE(NAME)  libat_##NAME##_i1
+#define LSE2(NAME) libat_##NAME##_i1
 #define CORE(NAME) libat_##NAME
 #define ATOMIC(NAME)   __atomic_##NAME
 
+/* Emit __atomic_* entrypoints if no ifuncs.  */
+#define ENTRY_ALIASED(NAME)ENTRY2 (CORE (NAME), ALIAS (NAME, ATOMIC, CORE))
+
 #if HAVE_IFUNC
 # define ENTRY(NAME)   ENTRY2 (CORE (NAME), )
 # define ENTRY_FEAT(NAME, FEAT) ENTRY2 (FEAT (NAME), )
 # define END_FEAT(NAME, FEAT)  END2 (FEAT (NAME))
 #else
-/* Emit __atomic_* entrypoints if no ifuncs.  */
-# define ENTRY(NAME)   ENTRY2 (CORE (NAME), ALIAS (NAME, ATOMIC, CORE))
+# define ENTRY(NAME)   ENTRY_ALIASED (NAME)
 #endif
 
 #define END(NAME)  END2 (CORE (NAME))
@@ -291,7 +294,7 @@ END (compare_exchange_16)
 
 
 #if HAVE_FEAT_LSE2
-ENTRY_FEAT (compare_exchange_16, LSE2)
+ENTRY_FEAT (compare_exchange_16, LSE)
ldp exp0, exp1, [x1]
mov tmp0, exp0
mov tmp1, exp1
@@ -324,11 +327,11 @@ ENTRY_FEAT (compare_exchange_16, LSE2)
/* ACQ_REL/SEQ_CST.  */
 4: caspal  exp0, exp1, in0, in1, [x0]
b   0b
-END_FEAT (compare_exchange_16, LSE2)
+END_FEAT (compare_exchange_16, LSE)
 #endif
 
 
-ENTRY (fetch_add_16)
+ENTRY_ALIASED (fetch_add_16)
mov x5, x0
cbnzw4, 2f
 
@@ -350,7 +353,7 @@ ENTRY (fetch_add_16)
 END (fetch_add_16)
 
 
-ENTRY (add_fetch_16)
+ENTRY_ALIASED (add_fetch_16)
mov x5, x0
cbnzw4, 2f
 
@@ -372,7 +375,7 @@ ENTRY (add_fetch_16)
 END (add_fetch_16)
 
 
-ENTRY (fetch_sub_16)
+ENTRY_ALIASED (fetch_sub_16)
mov x5, x0
cbnzw4, 2f
 
@@ -394,7 +397,7 @@ ENTRY (fetch_sub_16)
 END (fetch_sub_16)
 
 
-ENTRY (sub_fetch_16)
+ENTRY_A

[gcc r15-1205] Libatomic: Clean up AArch64 `atomic_16.S' implementation file

[Victor Do Nascimento via Gcc-cvs]

https://gcc.gnu.org/g:7663154c93a0193e88e1d8a1f24e4617dcaf9058

commit r15-1205-g7663154c93a0193e88e1d8a1f24e4617dcaf9058
Author: Victor Do Nascimento 
Date:   Mon Jun 10 11:02:43 2024 +0100

Libatomic: Clean up AArch64 `atomic_16.S' implementation file

At present, `atomic_16.S' groups different implementations of the
same functions together in the file.  Therefore, as an example,
the LSE2 implementation of `load_16' follows on immediately from its
core implementation, as does the `store_16' LSE2 implementation.

Such architectural extension-dependent implementations are dependent
on ifunc support, such that they are guarded by the relevant
preprocessor macro, i.e.  `#if HAVE_IFUNC'.

Having to apply these guards on a per-function basis adds unnecessary
clutter to the file and makes its maintenance more error-prone.

We therefore reorganize the layout of the file in such a way that all
core implementations needing no `#ifdef's are placed first, followed
by all ifunc-dependent implementations, which can all be guarded by a
single `#if HAVE_IFUNC', greatly reducing the overall number of
required `#ifdef' macros.

libatomic/ChangeLog:

* config/linux/aarch64/atomic_16.S: Reorganize functions in
file.
(HAVE_FEAT_LSE2): Delete.

Diff:
---
 libatomic/config/linux/aarch64/atomic_16.S | 445 +++--
 1 file changed, 223 insertions(+), 222 deletions(-)

diff --git a/libatomic/config/linux/aarch64/atomic_16.S 
b/libatomic/config/linux/aarch64/atomic_16.S
index 11a296dacc3a..c44c31c64184 100644
--- a/libatomic/config/linux/aarch64/atomic_16.S
+++ b/libatomic/config/linux/aarch64/atomic_16.S
@@ -40,8 +40,6 @@
 
 #include "auto-config.h"
 
-#define HAVE_FEAT_LSE2 HAVE_IFUNC
-
.arch   armv8-a+lse
 
 #define LSE128(NAME)   libat_##NAME##_i1
@@ -116,6 +114,9 @@ NAME:   \
 #define SEQ_CST 5
 
 
+/* Core implementations: Not dependent on the presence of further architectural
+   extensions.  */
+
 ENTRY (load_16)
mov x5, x0
cbnzw1, 2f
@@ -134,31 +135,6 @@ ENTRY (load_16)
 END (load_16)
 
 
-#if HAVE_FEAT_LSE2
-ENTRY_FEAT (load_16, LSE2)
-   cbnzw1, 1f
-
-   /* RELAXED.  */
-   ldp res0, res1, [x0]
-   ret
-1:
-   cmp w1, SEQ_CST
-   b.eq2f
-
-   /* ACQUIRE/CONSUME (Load-AcquirePC semantics).  */
-   ldp res0, res1, [x0]
-   dmb ishld
-   ret
-
-   /* SEQ_CST.  */
-2: ldartmp0, [x0]  /* Block reordering with Store-Release instr.  
*/
-   ldp res0, res1, [x0]
-   dmb ishld
-   ret
-END_FEAT (load_16, LSE2)
-#endif
-
-
 ENTRY (store_16)
cbnzw4, 2f
 
@@ -176,23 +152,6 @@ ENTRY (store_16)
 END (store_16)
 
 
-#if HAVE_FEAT_LSE2
-ENTRY_FEAT (store_16, LSE2)
-   cbnzw4, 1f
-
-   /* RELAXED.  */
-   stp in0, in1, [x0]
-   ret
-
-   /* RELEASE/SEQ_CST.  */
-1: ldxpxzr, tmp0, [x0]
-   stlxp   w4, in0, in1, [x0]
-   cbnzw4, 1b
-   ret
-END_FEAT (store_16, LSE2)
-#endif
-
-
 ENTRY (exchange_16)
mov x5, x0
cbnzw4, 2f
@@ -220,32 +179,6 @@ ENTRY (exchange_16)
 END (exchange_16)
 
 
-ENTRY_FEAT (exchange_16, LSE128)
-   mov tmp0, x0
-   mov res0, in0
-   mov res1, in1
-   cbnzw4, 1f
-
-   /* RELAXED.  */
-   /* swpp res0, res1, [tmp0]  */
-   .inst   0x192180c0
-   ret
-1:
-   cmp w4, ACQUIRE
-   b.hi2f
-
-   /* ACQUIRE/CONSUME.  */
-   /* swppa res0, res1, [tmp0]  */
-   .inst   0x19a180c0
-   ret
-
-   /* RELEASE/ACQ_REL/SEQ_CST.  */
-2: /* swppal res0, res1, [tmp0]  */
-   .inst   0x19e180c0
-   ret
-END_FEAT (exchange_16, LSE128)
-
-
 ENTRY (compare_exchange_16)
ldp exp0, exp1, [x1]
cbz w4, 3f
@@ -293,42 +226,6 @@ ENTRY (compare_exchange_16)
 END (compare_exchange_16)
 
 
-#if HAVE_FEAT_LSE2
-ENTRY_FEAT (compare_exchange_16, LSE)
-   ldp exp0, exp1, [x1]
-   mov tmp0, exp0
-   mov tmp1, exp1
-   cbz w4, 2f
-   cmp w4, RELEASE
-   b.hs3f
-
-   /* ACQUIRE/CONSUME.  */
-   caspa   exp0, exp1, in0, in1, [x0]
-0:
-   cmp exp0, tmp0
-   ccmpexp1, tmp1, 0, eq
-   bne 1f
-   mov x0, 1
-   ret
-1:
-   stp exp0, exp1, [x1]
-   mov x0, 0
-   ret
-
-   /* RELAXED.  */
-2: caspexp0, exp1, in0, in1, [x0]
-   b   0b
-
-   /* RELEASE.  */
-3: b.hi4f
-   caspl   exp0, exp1, in0, in1, [x0]
-   b   0b
-
-   /* ACQ_REL/SEQ_CST.  */
-4: caspal  exp0, exp1, in0, in1, [x0]
-   b   0b
-END_FEAT (compare_exchange_16, LSE)
-#endif
 
 
 ENTRY_ALIASED (fetch_add_16)
@@ -441,32 +338,6 @@ ENTRY (fetch_or_16)
 END (fetch_or_16)
 
 
-ENTRY_FEAT (fetch_or_16, LSE128)
-   mov tmp0, x0
-  

[gcc r15-1202] Libatomic: AArch64: Convert all lse128 assembly to .insn directives

[Victor Do Nascimento via Gcc-cvs]

https://gcc.gnu.org/g:f6b9a064a295f5371901e2fac380d20e77cf7131

commit r15-1202-gf6b9a064a295f5371901e2fac380d20e77cf7131
Author: Victor Do Nascimento 
Date:   Fri May 31 14:25:11 2024 +0100

Libatomic: AArch64: Convert all lse128 assembly to .insn directives

Given the lack of support for the LSE128 instructions in all but the
the most up-to-date version of Binutils (2.42), having the build-time
test for assembler support for these instructions often leads to the
building of Libatomic without support for LSE128-dependent atomic
function implementations.  This ultimately leads to different people
having different versions of Libatomic on their machines, depending on
which assembler was available at compilation time.

Furthermore, the conditional inclusion of these atomic function
implementations predicated on assembler support leads to a series of
`#if HAVE_FEAT_LSE128' guards scattered throughout the codebase and
the need for a series of aliases when the feature flag evaluates
to false.  The preprocessor macro guards, together with the
conditional aliasing leads to code that is cumbersome to understand
and maintain.

Both of the issues highlighted above will only get worse with the
coming support for LRCPC3 atomics which under the current scheme will
also require build-time checks.

Consequently, a better option for both consistency across builds and
code cleanness is to make recourse to the `.inst' directive.  By
replacing all novel assembly instructions for their hexadecimal
representation within `.inst's, we ensure that the Libatomic code is
both considerably cleaner and all machines build the same binary,
irrespective of binutils version available at compile time.

This patch therefore removes all configure checks for LSE128-support
in the assembler and all the guards and aliases that were associated
with `HAVE_FEAT_LSE128'

libatomic/ChangeLog:

* acinclude.m4 (LIBAT_TEST_FEAT_AARCH64_LSE128): Delete.
* auto-config.h.in (HAVE_FEAT_LSE128): Likewise
* config/linux/aarch64/atomic_16.S: Replace all LSE128
instructions with equivalent `.inst' directives.
(HAVE_FEAT_LSE128): Remove all references.
* configure: Regenerate.
* configure.ac: Remove call to LIBAT_TEST_FEAT_AARCH64_LSE128.

Diff:
---
 libatomic/acinclude.m4 | 18 ---
 libatomic/auto-config.h.in |  3 --
 libatomic/config/linux/aarch64/atomic_16.S | 76 +-
 libatomic/configure| 43 -
 libatomic/configure.ac |  3 --
 5 files changed, 32 insertions(+), 111 deletions(-)

diff --git a/libatomic/acinclude.m4 b/libatomic/acinclude.m4
index 6d2e0b1c355c..f35ab5b60a50 100644
--- a/libatomic/acinclude.m4
+++ b/libatomic/acinclude.m4
@@ -83,24 +83,6 @@ AC_DEFUN([LIBAT_TEST_ATOMIC_BUILTIN],[
   ])
 ])
 
-dnl
-dnl Test if the host assembler supports armv9.4-a LSE128 isns.
-dnl
-AC_DEFUN([LIBAT_TEST_FEAT_AARCH64_LSE128],[
-  AC_CACHE_CHECK([for armv9.4-a LSE128 insn support],
-[libat_cv_have_feat_lse128],[
-AC_LANG_CONFTEST([AC_LANG_PROGRAM([],[asm(".arch armv9-a+lse128")])])
-if AC_TRY_EVAL(ac_compile); then
-  eval libat_cv_have_feat_lse128=yes
-else
-  eval libat_cv_have_feat_lse128=no
-fi
-rm -f conftest*
-  ])
-  LIBAT_DEFINE_YESNO([HAVE_FEAT_LSE128], [$libat_cv_have_feat_lse128],
-   [Have LSE128 support for 16 byte integers.])
-])
-
 dnl
 dnl Test if we have __atomic_load and __atomic_store for mode $1, size $2
 dnl
diff --git a/libatomic/auto-config.h.in b/libatomic/auto-config.h.in
index 7c78933b07d1..ab3424a759ea 100644
--- a/libatomic/auto-config.h.in
+++ b/libatomic/auto-config.h.in
@@ -105,9 +105,6 @@
 /* Define to 1 if you have the  header file. */
 #undef HAVE_DLFCN_H
 
-/* Have LSE128 support for 16 byte integers. */
-#undef HAVE_FEAT_LSE128
-
 /* Define to 1 if you have the  header file. */
 #undef HAVE_FENV_H
 
diff --git a/libatomic/config/linux/aarch64/atomic_16.S 
b/libatomic/config/linux/aarch64/atomic_16.S
index b63e97ac5a22..d6e71ba6e167 100644
--- a/libatomic/config/linux/aarch64/atomic_16.S
+++ b/libatomic/config/linux/aarch64/atomic_16.S
@@ -40,18 +40,9 @@
 
 #include "auto-config.h"
 
-#if !HAVE_IFUNC
-# undef HAVE_FEAT_LSE128
-# define HAVE_FEAT_LSE128 0
-#endif
-
 #define HAVE_FEAT_LSE2 HAVE_IFUNC
 
-#if HAVE_FEAT_LSE128
-   .arch   armv9-a+lse128
-#else
.arch   armv8-a+lse
-#endif
 
 #define LSE128(NAME)   libat_##NAME##_i1
 #define LSE2(NAME) libat_##NAME##_i2
@@ -226,7 +217,6 @@ ENTRY (exchange_16)
 END (exchange_16)
 
 
-#if HAVE_FEAT_LSE128
 ENTRY_FEAT (exchange_16, LSE128)
mov tmp0, x0
mov res0, in0
@@ -234,21 +224,23 @@ ENTRY_FEAT (exchange_16, LSE128)
cbnzw4, 1f
 
/* RELAXED.  */
-

[gcc r12-10552] rtl-optimization/54052 - RTL SSA PHI insertion compile-time hog

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:1edc6a71feeb8460fbd4938b8926b5692fbab43f

commit r12-10552-g1edc6a71feeb8460fbd4938b8926b5692fbab43f
Author: Richard Biener 
Date:   Mon Feb 19 11:10:50 2024 +0100

rtl-optimization/54052 - RTL SSA PHI insertion compile-time hog

The following tries to address the PHI insertion compile-time hog in
RTL fwprop observed with the PR54052 testcase where the loop computing
the "unfiltered" set of variables possibly needing PHI nodes for each
block exhibits quadratic compile-time and memory-use.

It does so by pruning the local DEFs with LR_OUT of the block, removing
regs that can never be LR_IN (defined by this block) in the dominance
frontier.

PR rtl-optimization/54052
* rtl-ssa/blocks.cc (function_info::place_phis): Filter
local defs by LR_OUT.

(cherry picked from commit c7151283dc747769d4ac4f216d8f519bda2569b5)

Diff:
---
 gcc/rtl-ssa/blocks.cc | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/rtl-ssa/blocks.cc b/gcc/rtl-ssa/blocks.cc
index 959fad8f829d..0c5998f4b65f 100644
--- a/gcc/rtl-ssa/blocks.cc
+++ b/gcc/rtl-ssa/blocks.cc
@@ -639,7 +639,12 @@ function_info::place_phis (build_info &bi)
   if (bitmap_empty_p (&frontiers[b1]))
continue;
 
-  bitmap b1_def = &DF_LR_BB_INFO (BASIC_BLOCK_FOR_FN (m_fn, b1))->def;
+  // Defs in B1 that are possibly in LR_IN in the dominance frontier
+  // blocks.
+  auto_bitmap b1_def;
+  bitmap_and (b1_def, &DF_LR_BB_INFO (BASIC_BLOCK_FOR_FN (m_fn, b1))->def,
+ DF_LR_OUT (BASIC_BLOCK_FOR_FN (m_fn, b1)));
+
   bitmap_iterator bmi;
   unsigned int b2;
   EXECUTE_IF_SET_IN_BITMAP (&frontiers[b1], 0, b2, bmi)

[gcc r12-10554] [PR111497][LRA]: Copy substituted equivalence

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:959cef942508b818c7dcb8df0f3c7bf4968d406a

commit r12-10554-g959cef942508b818c7dcb8df0f3c7bf4968d406a
Author: Vladimir N. Makarov 
Date:   Mon Sep 25 16:19:50 2023 -0400

[PR111497][LRA]: Copy substituted equivalence

When we substitute the equivalence and it becomes shared, we can fail
to correctly update reg info used by LRA.  This can result in wrong
code generation, e.g. because of incorrect live analysis.  It can also
result in compiler crash as the pseudo survives RA.  This is what
exactly happened for the PR.  This patch solves this problem by
unsharing substituted equivalences.

gcc/ChangeLog:

PR middle-end/111497
* lra-constraints.cc (lra_constraints): Copy substituted
equivalence.
* lra.cc (lra): Change comment for calling unshare_all_rtl_again.

gcc/testsuite/ChangeLog:

PR middle-end/111497
* g++.target/i386/pr111497.C: new test.

(cherry picked from commit 3c23defed384cf17518ad6c817d94463a445d21b)

Diff:
---
 gcc/lra-constraints.cc   |  5 +
 gcc/lra.cc   |  5 ++---
 gcc/testsuite/g++.target/i386/pr111497.C | 22 ++
 3 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index d92ab76908c8..04b0b6fbfc2a 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -5139,6 +5139,11 @@ lra_constraints (bool first_p)
   loc_equivalence_callback, curr_insn);
  if (old != *curr_id->operand_loc[0])
{
+ /* If we substitute pseudo by shared equivalence, we can fail
+to update LRA reg info and this can result in many
+unexpected consequences.  So keep rtl unshared:  */
+ *curr_id->operand_loc[0]
+   = copy_rtx (*curr_id->operand_loc[0]);
  lra_update_insn_regno_info (curr_insn);
  changed_p = true;
}
diff --git a/gcc/lra.cc b/gcc/lra.cc
index 1444cb759144..5e29d3270d7d 100644
--- a/gcc/lra.cc
+++ b/gcc/lra.cc
@@ -2535,9 +2535,8 @@ lra (FILE *f)
   if (inserted_p)
 commit_edge_insertions ();
 
-  /* Replacing pseudos with their memory equivalents might have
- created shared rtx.  Subsequent passes would get confused
- by this, so unshare everything here.  */
+  /* Subsequent passes expect that rtl is unshared, so unshare everything
+ here.  */
   unshare_all_rtl_again (get_insns ());
 
   if (flag_checking)
diff --git a/gcc/testsuite/g++.target/i386/pr111497.C 
b/gcc/testsuite/g++.target/i386/pr111497.C
new file mode 100644
index ..a645bb95907e
--- /dev/null
+++ b/gcc/testsuite/g++.target/i386/pr111497.C
@@ -0,0 +1,22 @@
+// { dg-do compile { target ia32 } }
+// { dg-options "-march=i686 -mtune=generic -fPIC -O2 -g" }
+
+class A;
+struct B { const char *b1; int b2; };
+struct C : B { C (const char *x, int y) { b1 = x; b2 = y; } };
+struct D : C { D (B x) : C (x.b1, x.b2) {} };
+struct E { E (A *); };
+struct F : E { D f1, f2, f3, f4, f5, f6; F (A *, const B &, const B &, const B 
&); };
+struct G : F { G (A *, const B &, const B &, const B &); };
+struct H { int h; };
+struct I { H i; };
+struct J { I *j; };
+struct A : J {};
+inline F::F (A *x, const B &y, const B &z, const B &w)
+  : E(x), f1(y), f2(z), f3(w), f4(y), f5(z), f6(w) {}
+G::G (A *x, const B &y, const B &z, const B &w) : F(x, y, z, w)
+{
+  H *h = &x->j->i;
+  if (h)
+h->h++;
+}

[gcc r12-10553] middle-end/40635 - SSA update losing PHI arg loations

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:844ff32c04a4e36bf69f3878634d9f50aec3a332

commit r12-10553-g844ff32c04a4e36bf69f3878634d9f50aec3a332
Author: Richard Biener 
Date:   Mon Dec 5 16:03:21 2022 +0100

middle-end/40635 - SSA update losing PHI arg loations

The following fixes an issue where SSA update loses PHI argument
locations when updating PHI nodes it didn't create as part of the
SSA update.  For the case where the reaching def is the same as
the current argument opt to do nothing and for the case where the
PHI argument already has a location keep that (that's an indication
the PHI node wasn't created as part of the update SSA process).

PR middle-end/40635
* tree-into-ssa.cc (rewrite_update_phi_arguments): Only
update the argument when the reaching definition is different
from the current argument.  Keep an existing argument
location.

* gcc.dg/uninit-pr40635.c: New testcase.

(cherry picked from commit 0d14720f93a8139a7f234b2762c361e8e5da99cc)

Diff:
---
 gcc/testsuite/gcc.dg/uninit-pr40635.c | 33 +
 gcc/tree-into-ssa.cc  | 11 +++
 2 files changed, 40 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/uninit-pr40635.c 
b/gcc/testsuite/gcc.dg/uninit-pr40635.c
new file mode 100644
index ..fab7c3d49d9d
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/uninit-pr40635.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O -Wuninitialized" } */
+
+struct hostent {
+char **h_addr_list;
+};
+struct hostent *gethostbyname(const char*);
+int socket(void);
+int close(int);
+int connect(int, const char*);
+
+int get_tcp_socket(const char *machine)
+{
+  struct hostent *hp;
+  int s42, x;
+  char **addr;
+
+  hp = gethostbyname(machine);
+  x = 0;
+  for (addr = hp->h_addr_list; *addr; addr++)
+{
+  s42 = socket();
+  if (s42 < 0)
+   return -1;
+  x = connect(s42, *addr);
+  if (x == 0)
+   break;
+  close(s42);
+}
+  if (x < 0)
+return -1;
+  return s42;  /* { dg-warning "uninitialized" } */
+}
diff --git a/gcc/tree-into-ssa.cc b/gcc/tree-into-ssa.cc
index dd41b1b77b7a..fa53beec2abf 100644
--- a/gcc/tree-into-ssa.cc
+++ b/gcc/tree-into-ssa.cc
@@ -2107,7 +2107,6 @@ rewrite_update_phi_arguments (basic_block bb)
 symbol we may find NULL arguments.  That's why we
 take the symbol from the LHS of the PHI node.  */
  reaching_def = get_reaching_def (lhs_sym);
-
}
  else
{
@@ -2119,8 +2118,9 @@ rewrite_update_phi_arguments (basic_block bb)
reaching_def = get_reaching_def (arg);
}
 
-  /* Update the argument if there is a reaching def.  */
- if (reaching_def)
+ /* Update the argument if there is a reaching def different
+from arg.  */
+ if (reaching_def && reaching_def != arg)
{
  location_t locus;
  int arg_i = PHI_ARG_INDEX_FROM_USE (arg_p);
@@ -2130,6 +2130,10 @@ rewrite_update_phi_arguments (basic_block bb)
  /* Virtual operands do not need a location.  */
  if (virtual_operand_p (reaching_def))
locus = UNKNOWN_LOCATION;
+ /* If SSA update didn't insert this PHI the argument
+might have a location already, keep that.  */
+ else if (gimple_phi_arg_has_location (phi, arg_i))
+   locus = gimple_phi_arg_location (phi, arg_i);
  else
{
  gimple *stmt = SSA_NAME_DEF_STMT (reaching_def);
@@ -2147,7 +2151,6 @@ rewrite_update_phi_arguments (basic_block bb)
  gimple_phi_arg_set_location (phi, arg_i, locus);
}
 
-
  if (e->flags & EDGE_ABNORMAL)
SSA_NAME_OCCURS_IN_ABNORMAL_PHI (USE_FROM_PTR (arg_p)) = 1;
}

[gcc r12-10555] cfgrtl: Fix MEM_EXPR update in duplicate_insn_chain [PR114924]

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:33663c0701a723846527f9bf2ea01d67d7033c0b

commit r12-10555-g33663c0701a723846527f9bf2ea01d67d7033c0b
Author: Alex Coplan 
Date:   Fri May 3 09:23:59 2024 +0100

cfgrtl: Fix MEM_EXPR update in duplicate_insn_chain [PR114924]

The PR shows that when cfgrtl.cc:duplicate_insn_chain attempts to
update the MR_DEPENDENCE_CLIQUE information for a MEM_EXPR we can end up
accidentally dropping (e.g.) an ARRAY_REF from the MEM_EXPR and end up
replacing it with the underlying MEM_REF.  This leads to an
inconsistency in the MEM_EXPR information, and could lead to wrong code.

While the walk down to the MEM_REF is necessary to update
MR_DEPENDENCE_CLIQUE, we should use the outer tree expression for the
MEM_EXPR.  This patch does that.

gcc/ChangeLog:

PR rtl-optimization/114924
* cfgrtl.cc (duplicate_insn_chain): When updating MEM_EXPRs,
don't strip (e.g.) ARRAY_REFs from the final MEM_EXPR.

(cherry picked from commit fe40d525619eee9c2821126390df75068df4773a)

Diff:
---
 gcc/cfgrtl.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/cfgrtl.cc b/gcc/cfgrtl.cc
index 8decf4007e83..a8c95d82a2a7 100644
--- a/gcc/cfgrtl.cc
+++ b/gcc/cfgrtl.cc
@@ -4374,12 +4374,13 @@ duplicate_insn_chain (rtx_insn *from, rtx_insn *to,
   since MEM_EXPR is shared so make a copy and
   walk to the subtree again.  */
tree new_expr = unshare_expr (MEM_EXPR (*iter));
+   tree orig_new_expr = new_expr;
if (TREE_CODE (new_expr) == WITH_SIZE_EXPR)
  new_expr = TREE_OPERAND (new_expr, 0);
while (handled_component_p (new_expr))
  new_expr = TREE_OPERAND (new_expr, 0);
MR_DEPENDENCE_CLIQUE (new_expr) = newc;
-   set_mem_expr (const_cast  (*iter), new_expr);
+   set_mem_expr (const_cast  (*iter), orig_new_expr);
  }
  }
}

[gcc r15-1206] LoongArch: Fix mode size comparision in loongarch_expand_conditional_move

[Xi Ruoyao via Gcc-cvs]

https://gcc.gnu.org/g:53c703888eb51314f762c8998dc9215871b12722

commit r15-1206-g53c703888eb51314f762c8998dc9215871b12722
Author: Xi Ruoyao 
Date:   Wed Jun 12 11:01:53 2024 +0800

LoongArch: Fix mode size comparision in loongarch_expand_conditional_move

We were comparing a mode size with word_mode, but word_mode is an enum
value thus this does not really make any sense.  (Un)luckily E_DImode
happens to be 8 so this seemed to work, but let's make it correct so it
won't blow up when we add LA32 support or add another machine mode...

gcc/ChangeLog:

* config/loongarch/loongarch.cc
(loongarch_expand_conditional_move): Compare mode size with
UNITS_PER_WORD instead of word_mode.

Diff:
---
 gcc/config/loongarch/loongarch.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc
index 1b6df6a43650..6ec3ee625026 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -5352,7 +5352,7 @@ loongarch_expand_conditional_move (rtx *operands)
 loongarch_emit_float_compare (&code, &op0, &op1);
   else
 {
-  if (GET_MODE_SIZE (GET_MODE (op0)) < word_mode)
+  if (GET_MODE_SIZE (GET_MODE (op0)) < UNITS_PER_WORD)
{
  promote_op[0] = (REG_P (op0) && REG_P (operands[2]) &&
   REGNO (op0) == REGNO (operands[2]));

[gcc r15-1207] LoongArch: Use bstrins for "value & (-1u << const)"

[Xi Ruoyao via Gcc-cvs]

https://gcc.gnu.org/g:d0da347a1dd6e57cb0e0c55fd654d81dde545cf8

commit r15-1207-gd0da347a1dd6e57cb0e0c55fd654d81dde545cf8
Author: Xi Ruoyao 
Date:   Sun Jun 9 14:43:48 2024 +0800

LoongArch: Use bstrins for "value & (-1u << const)"

A move/bstrins pair is as fast as a (addi.w|lu12i.w|lu32i.d|lu52i.d)/and
pair, and twice fast as a srli/slli pair.  When the src reg and the dst
reg happens to be the same, the move instruction can be optimized away.

gcc/ChangeLog:

* config/loongarch/predicates.md (high_bitmask_operand): New
predicate.
* config/loongarch/constraints.md (Yy): New constriant.
* config/loongarch/loongarch.md (and3_align): New
define_insn_and_split.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/bstrins-1.c: New test.
* gcc.target/loongarch/bstrins-2.c: New test.

Diff:
---
 gcc/config/loongarch/constraints.md|  5 +
 gcc/config/loongarch/loongarch.md  | 17 +
 gcc/config/loongarch/predicates.md |  4 
 gcc/testsuite/gcc.target/loongarch/bstrins-1.c |  9 +
 gcc/testsuite/gcc.target/loongarch/bstrins-2.c | 14 ++
 5 files changed, 49 insertions(+)

diff --git a/gcc/config/loongarch/constraints.md 
b/gcc/config/loongarch/constraints.md
index f07d31650d29..12cf5e2924a3 100644
--- a/gcc/config/loongarch/constraints.md
+++ b/gcc/config/loongarch/constraints.md
@@ -94,6 +94,7 @@
 ;;   "A constant @code{move_operand} that can be safely loaded using
 ;;   @code{la}."
 ;;"Yx"
+;;"Yy"
 ;; "Z" -
 ;;"ZC"
 ;;  "A memory operand whose address is formed by a base register and offset
@@ -291,6 +292,10 @@
"@internal"
(match_operand 0 "low_bitmask_operand"))
 
+(define_constraint "Yy"
+   "@internal"
+   (match_operand 0 "high_bitmask_operand"))
+
 (define_constraint "YI"
   "@internal
A replicated vector const in which the replicated value is in the range
diff --git a/gcc/config/loongarch/loongarch.md 
b/gcc/config/loongarch/loongarch.md
index 5c80c169cbf1..25c1d323ba0f 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -1542,6 +1542,23 @@
   [(set_attr "move_type" "pick_ins")
(set_attr "mode" "")])
 
+(define_insn_and_split "and3_align"
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+   (and:GPR (match_operand:GPR 1 "register_operand" "r")
+(match_operand:GPR 2 "high_bitmask_operand" "Yy")))]
+  ""
+  "#"
+  ""
+  [(set (match_dup 0) (match_dup 1))
+   (set (zero_extract:GPR (match_dup 0) (match_dup 2) (const_int 0))
+   (const_int 0))]
+{
+  int len;
+
+  len = low_bitmask_len (mode, ~INTVAL (operands[2]));
+  operands[2] = GEN_INT (len);
+})
+
 (define_insn_and_split "*bstrins__for_mask"
   [(set (match_operand:GPR 0 "register_operand" "=r")
(and:GPR (match_operand:GPR 1 "register_operand" "r")
diff --git a/gcc/config/loongarch/predicates.md 
b/gcc/config/loongarch/predicates.md
index eba7f246c84d..58e406ea522b 100644
--- a/gcc/config/loongarch/predicates.md
+++ b/gcc/config/loongarch/predicates.md
@@ -293,6 +293,10 @@
   (and (match_code "const_int")
(match_test "low_bitmask_len (mode, INTVAL (op)) > 12")))
 
+(define_predicate "high_bitmask_operand"
+  (and (match_code "const_int")
+   (match_test "low_bitmask_len (mode, ~INTVAL (op)) > 0")))
+
 (define_predicate "d_operand"
   (and (match_code "reg")
(match_test "GP_REG_P (REGNO (op))")))
diff --git a/gcc/testsuite/gcc.target/loongarch/bstrins-1.c 
b/gcc/testsuite/gcc.target/loongarch/bstrins-1.c
new file mode 100644
index ..7cb3a9523222
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/bstrins-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */
+/* { dg-final { scan-assembler "bstrins\\.d\t\\\$r4,\\\$r0,4,0" } } */
+
+long
+x (long a)
+{
+  return a & -32;
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/bstrins-2.c 
b/gcc/testsuite/gcc.target/loongarch/bstrins-2.c
new file mode 100644
index ..9777f502e5af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/bstrins-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */
+/* { dg-final { scan-assembler "bstrins\\.d\t\\\$r\[0-9\]+,\\\$r0,4,0" } } */
+
+struct aligned_buffer {
+  _Alignas(32) char x[1024];
+};
+
+extern int f(char *);
+int g(void)
+{
+  struct aligned_buffer buf;
+  return f(buf.x);
+}

[gcc r15-1209] pretty_printer: make all fields private

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:c5e3be456888aa48f591512ec28183703e70978c

commit r15-1209-gc5e3be456888aa48f591512ec28183703e70978c
Author: David Malcolm 
Date:   Wed Jun 12 09:15:09 2024 -0400

pretty_printer: make all fields private

No functional change intended.

gcc/analyzer/ChangeLog:
* access-diagram.cc (access_range::dump): Update for fields of
pretty_printer becoming private.
* call-details.cc (call_details::dump): Likewise.
* call-summary.cc (call_summary::dump): Likewise.
(call_summary_replay::dump): Likewise.
* checker-event.cc (checker_event::debug): Likewise.
* constraint-manager.cc (range::dump): Likewise.
(bounded_range::dump): Likewise.
(constraint_manager::dump): Likewise.
* engine.cc (exploded_node::dump): Likewise.
(exploded_path::dump): Likewise.
(exploded_path::dump_to_file): Likewise.
* feasible-graph.cc (feasible_graph::dump_feasible_path): Likewise.
* program-point.cc (program_point::dump): Likewise.
* program-state.cc (extrinsic_state::dump_to_file): Likewise.
(sm_state_map::dump): Likewise.
(program_state::dump_to_file): Likewise.
* ranges.cc (symbolic_byte_offset::dump): Likewise.
(symbolic_byte_range::dump): Likewise.
* record-layout.cc (record_layout::dump): Likewise.
* region-model-reachability.cc (reachable_regions::dump): Likewise.
* region-model.cc (region_to_value_map::dump): Likewise.
(region_model::dump): Likewise.
(model_merger::dump): Likewise.
* region-model.h (one_way_id_map::dump): Likewise.
* region.cc (region_offset::dump): Likewise.
(region::dump): Likewise.
* sm-malloc.cc (deallocator_set::dump): Likewise.
* store.cc (uncertainty_t::dump): Likewise.
(binding_key::dump): Likewise.
(bit_range::dump): Likewise.
(byte_range::dump): Likewise.
(binding_map::dump): Likewise.
(binding_cluster::dump): Likewise.
(store::dump): Likewise.
* supergraph.cc (supergraph::dump_dot_to_file): Likewise.
(superedge::dump): Likewise.
* svalue.cc (svalue::dump): Likewise.

gcc/c-family/ChangeLog:
* c-ada-spec.cc (dump_ads): Update for fields of pretty_printer
becoming private.
* c-pretty-print.cc: Likewise throughout.

gcc/c/ChangeLog:
* c-objc-common.cc (print_type): Update for fields of
pretty_printer becoming private.
(c_tree_printer): Likewise.

gcc/cp/ChangeLog:
* cxx-pretty-print.cc: Update throughout for fields of
pretty_printer becoming private.
* error.cc: Likewise.

gcc/ChangeLog:
* diagnostic.cc (diagnostic_context::urls_init): Update for fields
of pretty_printer becoming private.
(diagnostic_context::print_any_cwe): Likewise.
(diagnostic_context::print_any_rules): Likewise.
(diagnostic_context::print_option_information): Likewise.
* diagnostic.h (diagnostic_format_decoder): Likewise.
(diagnostic_prefixing_rule): Likewise, fixing typo.
* digraph.cc (test_dump_to_dot): Likewise.
* digraph.h (digraph::dump_dot_to_file): Likewise.
* dumpfile.cc
(dump_pretty_printer::emit_any_pending_textual_chunks): Likewise.
* gimple-pretty-print.cc (print_gimple_stmt): Likewise.
(print_gimple_expr): Likewise.
(print_gimple_seq): Likewise.
(dump_ssaname_info_to_file): Likewise.
(gimple_dump_bb): Likewise.
* graph.cc (print_graph_cfg): Likewise.
(start_graph_dump): Likewise.
* langhooks.cc (lhd_print_error_function): Likewise.
* lto-wrapper.cc (print_lto_docs_link): Likewise.
* pretty-print.cc (pp_set_real_maximum_length): Convert to...
(pretty_printer::set_real_maximum_length): ...this.
(pp_clear_state): Convert to...
(pretty_printer::clear_state): ...this.
(pp_wrap_text): Update for pp_remaining_character_count_for_line
becoming a member function.
(urlify_quoted_string): Update for fields of pretty_printer becoming
private.
(pp_format): Convert to...
(pretty_printer::format): ...this.  Reduce the scope of local
variables "old_line_length" and "old_wrapping_mode" and make
const.  Reduce the scope of locals "args", "new_chunk_array",
"curarg", "any_unnumbered", and "any_numbered".
(pp_output_formatted_text): Update for fields of pretty_printer
becoming private.
(pp_flush): L

[gcc r15-1210] pretty_printer: convert chunk_info into a class

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:1cae1a5ce088c1fa351b5752d43de52f1f116a75

commit r15-1210-g1cae1a5ce088c1fa351b5752d43de52f1f116a75
Author: David Malcolm 
Date:   Wed Jun 12 09:15:09 2024 -0400

pretty_printer: convert chunk_info into a class

No functional change intended.

gcc/cp/ChangeLog:
* error.cc (append_formatted_chunk): Move part of body into
chunk_info::append_formatted_chunk.

gcc/ChangeLog:
* dumpfile.cc (dump_pretty_printer::emit_items): Update for
changes to chunk_info.
* pretty-print.cc (chunk_info::append_formatted_chunk): New, based
on code in cp/error.cc's append_formatted_chunk.
(chunk_info::pop_from_output_buffer): New, based on code in
pp_output_formatted_text and dump_pretty_printer::emit_items.
(on_begin_quote): Convert to...
(chunk_info::on_begin_quote): ...this.
(on_end_quote): Convert to...
(chunk_info::on_end_quote): ...this.
(pretty_printer::format): Update for chunk_info becoming a class
and its fields gaining "m_" prefixes.  Update for on_begin_quote
and on_end_quote moving to chunk_info.
(quoting_info::handle_phase_3): Update for changes to chunk_info.
(pp_output_formatted_text): Likewise.  Move cleanup code to
chunk_info::pop_from_output_buffer.
* pretty-print.h (class output_buffer): New forward decl.
(class urlifier): New forward decl.
(struct chunk_info): Convert to...
(class chunk_info): ...this.  Add friend class pretty_printer.
(chunk_info::get_args): New accessor.
(chunk_info::get_quoting_info): New accessor.
(chunk_info::append_formatted_chunk): New decl.
(chunk_info::pop_from_output_buffer): New decl.
(chunk_info::on_begin_quote): New decl.
(chunk_info::on_end_quote): New decl.
(chunk_info::prev): Rename to...
(chunk_info::m_prev): ...this.
(chunk_info::args): Rename to...
(chunk_info::m_args): ...this.
(output_buffer::cur_chunk_array): Drop "struct" from decl.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/cp/error.cc | 10 ++
 gcc/dumpfile.cc |  9 ++---
 gcc/pretty-print.cc | 96 -
 gcc/pretty-print.h  | 30 ++---
 4 files changed, 90 insertions(+), 55 deletions(-)

diff --git a/gcc/cp/error.cc b/gcc/cp/error.cc
index 01ad794df8e3..171a352c85fd 100644
--- a/gcc/cp/error.cc
+++ b/gcc/cp/error.cc
@@ -4307,14 +4307,8 @@ static void
 append_formatted_chunk (pretty_printer *pp, const char *content)
 {
   output_buffer *buffer = pp_buffer (pp);
-  struct chunk_info *chunk_array = buffer->cur_chunk_array;
-  const char **args = chunk_array->args;
-
-  unsigned int chunk_idx;
-  for (chunk_idx = 0; args[chunk_idx]; chunk_idx++)
-;
-  args[chunk_idx++] = content;
-  args[chunk_idx] = NULL;
+  chunk_info *chunk_array = buffer->cur_chunk_array;
+  chunk_array->append_formatted_chunk (content);
 }
 
 /* Create a copy of CONTENT, with quotes added, and,
diff --git a/gcc/dumpfile.cc b/gcc/dumpfile.cc
index 097f9bcfff21..82bd8b06bebf 100644
--- a/gcc/dumpfile.cc
+++ b/gcc/dumpfile.cc
@@ -819,8 +819,8 @@ void
 dump_pretty_printer::emit_items (optinfo *dest)
 {
   output_buffer *buffer = pp_buffer (this);
-  struct chunk_info *chunk_array = buffer->cur_chunk_array;
-  const char **args = chunk_array->args;
+  chunk_info *chunk_array = buffer->cur_chunk_array;
+  const char * const *args = chunk_array->get_args ();
 
   gcc_assert (buffer->obstack == &buffer->formatted_obstack);
   gcc_assert (buffer->line_length == 0);
@@ -847,10 +847,7 @@ dump_pretty_printer::emit_items (optinfo *dest)
   /* Ensure that we consumed all of stashed_items.  */
   gcc_assert (stashed_item_idx == m_stashed_items.length ());
 
-  /* Deallocate the chunk structure and everything after it (i.e. the
- associated series of formatted strings).  */
-  buffer->cur_chunk_array = chunk_array->prev;
-  obstack_free (&buffer->chunk_obstack, chunk_array);
+  chunk_array->pop_from_output_buffer (*buffer);
 }
 
 /* Subroutine of dump_pretty_printer::emit_items
diff --git a/gcc/pretty-print.cc b/gcc/pretty-print.cc
index 271cd650c4d1..639e2b881586 100644
--- a/gcc/pretty-print.cc
+++ b/gcc/pretty-print.cc
@@ -1239,29 +1239,53 @@ private:
   std::vector m_phase_3_quotes;
 };
 
-static void
-on_begin_quote (const output_buffer &buf,
-   unsigned chunk_idx,
-   const urlifier *urlifier)
+/* Adds a chunk to the end of formatted output, so that it
+   will be printed by pp_output_formatted_text.  */
+
+void
+chunk_info::append_formatted_chunk (const char *content)
+{
+  unsigned int chunk_idx;
+  for (chunk_idx = 0; m_args[chunk_idx]; chunk_idx++)
+;
+  m_args[chunk_idx++] = content;
+  m_args[chunk_i

[gcc r15-1211] middle-end: Drop __builtin_prefetch calls in autovectorization [PR114061]

[Victor Do Nascimento via Gcc-cvs]

https://gcc.gnu.org/g:adcc815a01ae009d2768b6afb546e357bd37bbd2

commit r15-1211-gadcc815a01ae009d2768b6afb546e357bd37bbd2
Author: Victor Do Nascimento 
Date:   Wed May 22 12:14:11 2024 +0100

middle-end: Drop __builtin_prefetch calls in autovectorization [PR114061]

At present the autovectorizer fails to vectorize simple loops
involving calls to `__builtin_prefetch'.  A simple example of such
loop is given below:

void foo(double * restrict a, double * restrict b, int n){
  int i;
  for(i=0; i *references)
clobbers_memory = true;
break;
  }
+  else if (gimple_call_builtin_p (stmt, BUILT_IN_PREFETCH))
+   clobbers_memory = false;
   else
clobbers_memory = true;
 }
diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index 5b1ad06eca66..bbd5d261907c 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -12185,8 +12185,10 @@ vect_transform_loop (loop_vec_info loop_vinfo, gimple 
*loop_vectorized_call)
   !gsi_end_p (si);)
{
  stmt = gsi_stmt (si);
- /* During vectorization remove existing clobber stmts.  */
- if (gimple_clobber_p (stmt))
+ /* During vectorization remove existing clobber stmts and
+prefetches.  */
+ if (gimple_clobber_p (stmt)
+ || gimple_call_builtin_p (stmt, BUILT_IN_PREFETCH))
{
  unlink_stmt_vdef (stmt);
  gsi_remove (&si, true);

[gcc r15-1212] libstdc++: Do not use memset in _Hashtable::clear()

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:3f2f9059c7f76ff888e9d0e8f10dec6f48e346c9

commit r15-1212-g3f2f9059c7f76ff888e9d0e8f10dec6f48e346c9
Author: Jonathan Wakely 
Date:   Mon Jun 10 13:51:52 2024 +0100

libstdc++: Do not use memset in _Hashtable::clear()

Using memset is incorrect if the __bucket_ptr type is non-trivial, or
does not use an all-zero bit pattern for its null value.

Replace the three uses of memset with std::fill_n to set the pointers to
nullptr.

libstdc++-v3/ChangeLog:

* include/bits/hashtable.h (_Hashtable::clear): Do not use
memset to zero out bucket pointers.
(_Hashtable::_M_assign_elements): Likewise.

Diff:
---
 libstdc++-v3/include/bits/hashtable.h | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/libstdc++-v3/include/bits/hashtable.h 
b/libstdc++-v3/include/bits/hashtable.h
index 6e78cb7d9c09..983aa909d6c7 100644
--- a/libstdc++-v3/include/bits/hashtable.h
+++ b/libstdc++-v3/include/bits/hashtable.h
@@ -34,6 +34,7 @@
 
 #include 
 #include 
+#include  // fill_n
 #include  // __has_is_transparent_t
 #if __cplusplus > 201402L
 # include 
@@ -1376,8 +1377,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
_M_bucket_count = __ht._M_bucket_count;
  }
else
- __builtin_memset(_M_buckets, 0,
-  _M_bucket_count * sizeof(__node_base_ptr));
+ std::fill_n(_M_buckets, _M_bucket_count, nullptr);
 
__try
  {
@@ -1400,8 +1400,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
_M_buckets = __former_buckets;
_M_bucket_count = __former_bucket_count;
  }
-   __builtin_memset(_M_buckets, 0,
-_M_bucket_count * sizeof(__node_base_ptr));
+   std::fill_n(_M_buckets, _M_bucket_count, nullptr);
__throw_exception_again;
  }
   }
@@ -2582,8 +2581,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 clear() noexcept
 {
   this->_M_deallocate_nodes(_M_begin());
-  __builtin_memset(_M_buckets, 0,
-  _M_bucket_count * sizeof(__node_base_ptr));
+  std::fill_n(_M_buckets, _M_bucket_count, nullptr);
   _M_element_count = 0;
   _M_before_begin._M_nxt = nullptr;
 }

[gcc r15-1213] libstdc++: Fix std::tr2::dynamic_bitset shift operations [PR115399]

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:bd3a312728fbf8c35a09239b9180269f938f872e

commit r15-1213-gbd3a312728fbf8c35a09239b9180269f938f872e
Author: Jonathan Wakely 
Date:   Mon Jun 10 14:08:16 2024 +0100

libstdc++: Fix std::tr2::dynamic_bitset shift operations [PR115399]

The shift operations for dynamic_bitset fail to zero out words where the
non-zero bits were shifted to a completely different word.

For a right shift we don't need to sanitize the unused bits in the high
word, because we know they were already clear and a right shift doesn't
change that.

libstdc++-v3/ChangeLog:

PR libstdc++/115399
* include/tr2/dynamic_bitset (operator>>=): Remove redundant
call to _M_do_sanitize.
* include/tr2/dynamic_bitset.tcc (_M_do_left_shift): Zero out
low bits in words that should no longer be populated.
(_M_do_right_shift): Likewise for high bits.
* testsuite/tr2/dynamic_bitset/pr115399.cc: New test.

Diff:
---
 libstdc++-v3/include/tr2/dynamic_bitset|  5 +--
 libstdc++-v3/include/tr2/dynamic_bitset.tcc|  6 ++--
 .../testsuite/tr2/dynamic_bitset/pr115399.cc   | 37 ++
 3 files changed, 40 insertions(+), 8 deletions(-)

diff --git a/libstdc++-v3/include/tr2/dynamic_bitset 
b/libstdc++-v3/include/tr2/dynamic_bitset
index 0e4e88942870..274c4f6a1386 100644
--- a/libstdc++-v3/include/tr2/dynamic_bitset
+++ b/libstdc++-v3/include/tr2/dynamic_bitset
@@ -815,10 +815,7 @@ namespace tr2
   operator>>=(size_type __pos)
   {
if (__builtin_expect(__pos < this->_M_Nb, 1))
- {
-   this->_M_do_right_shift(__pos);
-   this->_M_do_sanitize();
- }
+ this->_M_do_right_shift(__pos);
else
  this->_M_do_reset();
return *this;
diff --git a/libstdc++-v3/include/tr2/dynamic_bitset.tcc 
b/libstdc++-v3/include/tr2/dynamic_bitset.tcc
index 63ba6f285c7a..5aac7d88ee37 100644
--- a/libstdc++-v3/include/tr2/dynamic_bitset.tcc
+++ b/libstdc++-v3/include/tr2/dynamic_bitset.tcc
@@ -60,8 +60,7 @@ namespace tr2
  this->_M_w[__wshift] = this->_M_w[0] << __offset;
}
 
-  std::fill(this->_M_w.begin(), this->_M_w.begin() + __wshift,
-   static_cast<_WordT>(0));
+ std::fill_n(this->_M_w.begin(), __wshift, _WordT(0));
}
 }
 
@@ -88,8 +87,7 @@ namespace tr2
  this->_M_w[__limit] = this->_M_w[_M_w.size()-1] >> __offset;
}
 
- std::fill(this->_M_w.begin() + __limit + 1, this->_M_w.end(),
-   static_cast<_WordT>(0));
+ std::fill_n(this->_M_w.end() - __wshift, __wshift, _WordT(0));
}
 }
 
diff --git a/libstdc++-v3/testsuite/tr2/dynamic_bitset/pr115399.cc 
b/libstdc++-v3/testsuite/tr2/dynamic_bitset/pr115399.cc
new file mode 100644
index ..e626e4a5d156
--- /dev/null
+++ b/libstdc++-v3/testsuite/tr2/dynamic_bitset/pr115399.cc
@@ -0,0 +1,37 @@
+// { dg-do run { target c++11 } }
+
+// PR libstdc++/115399
+// std::tr2::dynamic_bitset shift behaves differently from std::bitset
+
+#include 
+#include 
+
+void
+test_left_shift()
+{
+  std::tr2::dynamic_bitset<> b(65);
+  b[0] = 1;
+  auto b2 = b << 64;
+  VERIFY(b2[64] == 1);
+  VERIFY(b2[0] == 0);
+  b <<= 64;
+  VERIFY( b2 == b );
+}
+
+void
+test_right_shift()
+{
+  std::tr2::dynamic_bitset<> b(65);
+  b[64] = 1;
+  auto b2 = b >> 64;
+  VERIFY(b2[64] == 0);
+  VERIFY(b2[0] == 1);
+  b >>= 64;
+  VERIFY( b2 == b );
+}
+
+int main()
+{
+  test_left_shift();
+  test_right_shift();
+}

[gcc r14-10308] arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR115360]

[Andre Simoes Dias Vieira via Gcc-cvs]

https://gcc.gnu.org/g:7593dae69ba06ffe63bc22d26c16b19aa9ab24e8

commit r14-10308-g7593dae69ba06ffe63bc22d26c16b19aa9ab24e8
Author: Andre Vieira 
Date:   Thu Jun 6 16:02:50 2024 +0100

arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR115360]

This patch adds missing assembly directives to the CMSE library wrapper to 
call
functions with attribute cmse_nonsecure_call.  Without the .type directive 
the
linker will fail to produce the correct veneer if a call to this wrapper
function is to far from the wrapper itself.  The .size was added for
completeness, though we don't necessarily have a usecase for it.

libgcc/ChangeLog:

PR target/115360
* config/arm/cmse_nonsecure_call.S: Add .type and .size directives.

(cherry picked from commit c559353af49fe5743d226ac3112a285b27a50f6a)

Diff:
---
 libgcc/config/arm/cmse_nonsecure_call.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/libgcc/config/arm/cmse_nonsecure_call.S 
b/libgcc/config/arm/cmse_nonsecure_call.S
index f93ce6bb4f9f..fef37b955af6 100644
--- a/libgcc/config/arm/cmse_nonsecure_call.S
+++ b/libgcc/config/arm/cmse_nonsecure_call.S
@@ -33,6 +33,7 @@
 #endif
 
 .thumb
+.type __gnu_cmse_nonsecure_call, %function
 .global __gnu_cmse_nonsecure_call
 __gnu_cmse_nonsecure_call:
 #if defined(__ARM_ARCH_8M_MAIN__)
@@ -142,3 +143,4 @@ pop {r5-r7, pc}
 #else
 #error "This should only be used for armv8-m base- and mainline."
 #endif
+.size __gnu_cmse_nonsecure_call, .-__gnu_cmse_nonsecure_call

[gcc r13-8846] arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR115360]

[Andre Simoes Dias Vieira via Gcc-cvs]

https://gcc.gnu.org/g:113a104edb5c31fbaa767ba8526f0da4dcf39ebe

commit r13-8846-g113a104edb5c31fbaa767ba8526f0da4dcf39ebe
Author: Andre Vieira 
Date:   Thu Jun 6 16:02:50 2024 +0100

arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR115360]

This patch adds missing assembly directives to the CMSE library wrapper to 
call
functions with attribute cmse_nonsecure_call.  Without the .type directive 
the
linker will fail to produce the correct veneer if a call to this wrapper
function is to far from the wrapper itself.  The .size was added for
completeness, though we don't necessarily have a usecase for it.

libgcc/ChangeLog:

PR target/115360
* config/arm/cmse_nonsecure_call.S: Add .type and .size directives.

(cherry picked from commit c559353af49fe5743d226ac3112a285b27a50f6a)

Diff:
---
 libgcc/config/arm/cmse_nonsecure_call.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/libgcc/config/arm/cmse_nonsecure_call.S 
b/libgcc/config/arm/cmse_nonsecure_call.S
index c92eb62c473d..8c3b8f466a13 100644
--- a/libgcc/config/arm/cmse_nonsecure_call.S
+++ b/libgcc/config/arm/cmse_nonsecure_call.S
@@ -33,6 +33,7 @@
 #endif
 
 .thumb
+.type __gnu_cmse_nonsecure_call, %function
 .global __gnu_cmse_nonsecure_call
 __gnu_cmse_nonsecure_call:
 #if defined(__ARM_ARCH_8M_MAIN__)
@@ -142,3 +143,4 @@ pop {r5-r7, pc}
 #else
 #error "This should only be used for armv8-m base- and mainline."
 #endif
+.size __gnu_cmse_nonsecure_call, .-__gnu_cmse_nonsecure_call

[gcc r12-10556] arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR115360]

[Andre Simoes Dias Vieira via Gcc-cvs]

https://gcc.gnu.org/g:448dd002a07aa268c00318066bfe843adebe7292

commit r12-10556-g448dd002a07aa268c00318066bfe843adebe7292
Author: Andre Vieira 
Date:   Thu Jun 6 16:02:50 2024 +0100

arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR115360]

This patch adds missing assembly directives to the CMSE library wrapper to 
call
functions with attribute cmse_nonsecure_call.  Without the .type directive 
the
linker will fail to produce the correct veneer if a call to this wrapper
function is to far from the wrapper itself.  The .size was added for
completeness, though we don't necessarily have a usecase for it.

libgcc/ChangeLog:

PR target/115360
* config/arm/cmse_nonsecure_call.S: Add .type and .size directives.

(cherry picked from commit c559353af49fe5743d226ac3112a285b27a50f6a)

Diff:
---
 libgcc/config/arm/cmse_nonsecure_call.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/libgcc/config/arm/cmse_nonsecure_call.S 
b/libgcc/config/arm/cmse_nonsecure_call.S
index 805136537e75..19bf18a59318 100644
--- a/libgcc/config/arm/cmse_nonsecure_call.S
+++ b/libgcc/config/arm/cmse_nonsecure_call.S
@@ -33,6 +33,7 @@
 #endif
 
 .thumb
+.type __gnu_cmse_nonsecure_call, %function
 .global __gnu_cmse_nonsecure_call
 __gnu_cmse_nonsecure_call:
 #if defined(__ARM_ARCH_8M_MAIN__)
@@ -142,3 +143,4 @@ pop {r5-r7, pc}
 #else
 #error "This should only be used for armv8-m base- and mainline."
 #endif
+.size __gnu_cmse_nonsecure_call, .-__gnu_cmse_nonsecure_call

[gcc r11-11479] arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR115360]

[Andre Simoes Dias Vieira via Gcc-cvs]

https://gcc.gnu.org/g:e8d2679c0163f190984c6e5c20f17fe0ceec77fd

commit r11-11479-ge8d2679c0163f190984c6e5c20f17fe0ceec77fd
Author: Andre Vieira 
Date:   Thu Jun 6 16:02:50 2024 +0100

arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR115360]

This patch adds missing assembly directives to the CMSE library wrapper to 
call
functions with attribute cmse_nonsecure_call.  Without the .type directive 
the
linker will fail to produce the correct veneer if a call to this wrapper
function is to far from the wrapper itself.  The .size was added for
completeness, though we don't necessarily have a usecase for it.

libgcc/ChangeLog:

PR target/115360
* config/arm/cmse_nonsecure_call.S: Add .type and .size directives.

(cherry picked from commit c559353af49fe5743d226ac3112a285b27a50f6a)

Diff:
---
 libgcc/config/arm/cmse_nonsecure_call.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/libgcc/config/arm/cmse_nonsecure_call.S 
b/libgcc/config/arm/cmse_nonsecure_call.S
index c8e0fbbe665d..f36ddef447ae 100644
--- a/libgcc/config/arm/cmse_nonsecure_call.S
+++ b/libgcc/config/arm/cmse_nonsecure_call.S
@@ -33,6 +33,7 @@
 #endif
 
 .thumb
+.type __gnu_cmse_nonsecure_call, %function
 .global __gnu_cmse_nonsecure_call
 __gnu_cmse_nonsecure_call:
 #if defined(__ARM_ARCH_8M_MAIN__)
@@ -142,3 +143,4 @@ pop {r5-r7, pc}
 #else
 #error "This should only be used for armv8-m base- and mainline."
 #endif
+.size __gnu_cmse_nonsecure_call, .-__gnu_cmse_nonsecure_call

[gcc r15-1214] Move cexpr_stree tree string build into utility function

[Andi Kleen via Gcc-cvs]

https://gcc.gnu.org/g:bd6bc352d96304a13da63fed6aeb1615be535fd7

commit r15-1214-gbd6bc352d96304a13da63fed6aeb1615be535fd7
Author: Andi Kleen 
Date:   Wed Jun 12 06:59:37 2024 -0700

Move cexpr_stree tree string build into utility function

No semantics changes.

gcc/cp/ChangeLog:

* cp-tree.h (extract): Add new overload to return tree.
* parser.cc (cp_parser_asm_string_expression): Use tree extract.
* semantics.cc (cexpr_str::extract): Add new overload to return
tree.

Diff:
---
 gcc/cp/cp-tree.h|  1 +
 gcc/cp/parser.cc|  5 +
 gcc/cp/semantics.cc | 14 ++
 3 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h
index 62718ff126a2..416c60b7311e 100644
--- a/gcc/cp/cp-tree.h
+++ b/gcc/cp/cp-tree.h
@@ -9026,6 +9026,7 @@ public:
 
   bool type_check (location_t location);
   bool extract (location_t location, const char * & msg, int &len);
+  bool extract (location_t location, tree &str);
   tree message;
 private:
   tree message_data = NULL_TREE;
diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc
index 6cd7274046da..de5f0483c120 100644
--- a/gcc/cp/parser.cc
+++ b/gcc/cp/parser.cc
@@ -22862,12 +22862,9 @@ cp_parser_asm_string_expression (cp_parser *parser)
   cexpr_str cstr (string);
   if (!cstr.type_check (tok->location))
return error_mark_node;
-  const char *msg;
-  int len;
-  if (!cstr.extract (tok->location, msg, len))
+  if (!cstr.extract (tok->location, string))
return error_mark_node;
   parens.require_close (parser);
-  string = build_string (len, msg);
   return string;
 }
   else if (!cp_parser_is_string_literal (tok))
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index 20f4675833e2..08f5f245e7d1 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -11728,6 +11728,20 @@ cexpr_str::type_check (location_t location)
   return true;
 }
 
+/* Extract constant string at LOCATON into output string STR.
+   Returns true if successful, otherwise false.  */
+
+bool
+cexpr_str::extract (location_t location, tree &str)
+{
+  const char *msg;
+  int len;
+  if (!extract (location, msg, len))
+return false;
+  str = build_string (len, msg);
+  return true;
+}
+
 /* Extract constant string at LOCATION into output string MSG with LEN.
Returns true if successful, otherwise false.  */

[gcc r15-1215] match: Improve gimple_bitwise_equal_p and gimple_bitwise_inverted_equal_p for truncating casts [PR11

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:0256121e2f23ac3550e87410c9b1e690c8edfc7c

commit r15-1215-g0256121e2f23ac3550e87410c9b1e690c8edfc7c
Author: Andrew Pinski 
Date:   Tue Jun 11 17:16:42 2024 -0700

match: Improve gimple_bitwise_equal_p and gimple_bitwise_inverted_equal_p 
for truncating casts [PR115449]

As mentioned by Jeff in r15-831-g05daf617ea22e1d818295ed2d037456937e23530, 
we don't handle
`(X | Y) & ~Y` -> `X & ~Y` on the gimple level when there are some 
different signed
(but same precision) types dealing with matching `~Y` with the `Y` part. 
This
improves both gimple_bitwise_equal_p and gimple_bitwise_inverted_equal_p to
be able to say `(truncate)a` and `(truncate)a` are bitwise_equal and
that `~(truncate)a` and `(truncate)a` are bitwise_invert_equal.

Bootstrapped and tested on x86_64-linux-gnu with no regressions.

PR tree-optimization/115449

gcc/ChangeLog:

* gimple-match-head.cc (gimple_maybe_truncate): New declaration.
(gimple_bitwise_equal_p): Match truncations that differ only
in types with the same precision.
(gimple_bitwise_inverted_equal_p): For matching after 
bit_not_with_nop
call gimple_bitwise_equal_p.
* match.pd (maybe_truncate): New match pattern.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/bitops-10.c: New test.

Signed-off-by: Andrew Pinski 

Diff:
---
 gcc/gimple-match-head.cc  | 17 +++-
 gcc/match.pd  |  7 +++
 gcc/testsuite/gcc.dg/tree-ssa/bitops-10.c | 34 +++
 3 files changed, 48 insertions(+), 10 deletions(-)

diff --git a/gcc/gimple-match-head.cc b/gcc/gimple-match-head.cc
index e26fa0860ee9..924d3f1e7103 100644
--- a/gcc/gimple-match-head.cc
+++ b/gcc/gimple-match-head.cc
@@ -243,6 +243,7 @@ optimize_successive_divisions_p (tree divisor, tree 
inner_div)
   gimple_bitwise_equal_p (expr1, expr2, valueize)
 
 bool gimple_nop_convert (tree, tree *, tree (*) (tree));
+bool gimple_maybe_truncate (tree, tree *, tree (*) (tree));
 
 /* Helper function for bitwise_equal_p macro.  */
 
@@ -271,6 +272,10 @@ gimple_bitwise_equal_p (tree expr1, tree expr2, tree 
(*valueize) (tree))
 }
   if (expr2 != expr4 && operand_equal_p (expr1, expr4, 0))
 return true;
+  if (gimple_maybe_truncate (expr3, &expr3, valueize)
+  && gimple_maybe_truncate (expr4, &expr4, valueize)
+  && operand_equal_p (expr3, expr4, 0))
+return true;
   return false;
 }
 
@@ -318,21 +323,13 @@ gimple_bitwise_inverted_equal_p (tree expr1, tree expr2, 
bool &wascmp, tree (*va
   /* Try if EXPR1 was defined as ~EXPR2. */
   if (gimple_bit_not_with_nop (expr1, &other, valueize))
 {
-  if (operand_equal_p (other, expr2, 0))
-   return true;
-  tree expr4;
-  if (gimple_nop_convert (expr2, &expr4, valueize)
- && operand_equal_p (other, expr4, 0))
+  if (gimple_bitwise_equal_p (other, expr2, valueize))
return true;
 }
   /* Try if EXPR2 was defined as ~EXPR1. */
   if (gimple_bit_not_with_nop (expr2, &other, valueize))
 {
-  if (operand_equal_p (other, expr1, 0))
-   return true;
-  tree expr3;
-  if (gimple_nop_convert (expr1, &expr3, valueize)
- && operand_equal_p (other, expr3, 0))
+  if (gimple_bitwise_equal_p (other, expr1, valueize))
return true;
 }
 
diff --git a/gcc/match.pd b/gcc/match.pd
index 5cfe81e80b31..3204cf415387 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -200,6 +200,13 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
 (match (maybe_bit_not @0)
  (bit_xor_cst@0 @1 @2))
 
+#if GIMPLE
+(match (maybe_truncate @0)
+ (convert @0)
+ (if (INTEGRAL_TYPE_P (type)
+  && TYPE_PRECISION (type) < TYPE_PRECISION (TREE_TYPE (@0)
+#endif
+
 /* Transform likes of (char) ABS_EXPR <(int) x> into (char) ABSU_EXPR 
ABSU_EXPR returns unsigned absolute value of the operand and the operand
of the ABSU_EXPR will have the corresponding signed type.  */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/bitops-10.c 
b/gcc/testsuite/gcc.dg/tree-ssa/bitops-10.c
new file mode 100644
index ..000c5aef2377
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/bitops-10.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -fdump-tree-optimized-raw" } */
+/* PR tree-optimization/115449 */
+
+void setBit_un(unsigned char *a, int b) {
+   unsigned char c = 0x1UL << b;
+   *a &= ~c;
+   *a |= c;
+}
+
+void setBit_sign(signed char *a, int b) {
+   signed char c = 0x1UL << b;
+   *a &= ~c;
+   *a |= c;
+}
+
+void setBit(char *a, int b) {
+   char c = 0x1UL << b;
+   *a &= ~c;
+   *a |= c;
+}
+/*
+   All three should produce:
+_1 = 1 << b_4(D);
+c_5 = (cast) _1;
+_2 = *a_7(D);
+_3 = _2 | c_5;
+*a_7(D) = _3;
+   Removing the `&~c` as we are matching `(~x & y) | x` -> `x | y`
+   match pattern even with extra casts are being involved. */
+
+/* { dg-final 

[gcc] Created branch 'ibm/heads/gcc-14-branch' in namespace 'refs/vendors'

[Peter Bergner via Gcc-cvs]

The branch 'ibm/heads/gcc-14-branch' was created in namespace 'refs/vendors' 
pointing to:

 7593dae69ba0... arm: Add .type and .size to __gnu_cmse_nonsecure_call [PR11

[gcc r15-1216] aarch64: Use bitreverse rtl code instead of unspec [PR115176]

[Andrew Pinski via Gcc-cvs]

https://gcc.gnu.org/g:c2f0aaf7539c42b024ed6b3fb6909bd2c86bb206

commit r15-1216-gc2f0aaf7539c42b024ed6b3fb6909bd2c86bb206
Author: Andrew Pinski 
Date:   Tue Jun 11 20:36:34 2024 +

aarch64: Use bitreverse rtl code instead of unspec [PR115176]

Bitreverse rtl code was added with r14-1586-g6160572f8d243c. So let's
use it instead of an unspec. This is just a small cleanup but it does
have one small fix with respect to rtx costs which didn't handle vector 
modes
correctly for the UNSPEC and now it does.
This is part of the first step in adding __builtin_bitreverse's builtins
but it is independent of it though.

Bootstrapped and tested on aarch64-linux-gnu with no regressions.

gcc/ChangeLog:

PR target/115176
* config/aarch64/aarch64-simd.md 
(aarch64_rbit): Use
bitreverse instead of unspec.
* config/aarch64/aarch64-sve-builtins-base.cc (svrbit): Convert 
over to using
rtx_code_function instead of unspec_based_function.
* config/aarch64/aarch64-sve.md: Update comment where RBIT is 
included.
* config/aarch64/aarch64.cc (aarch64_rtx_costs): Handle BITREVERSE 
like BSWAP.
Remove UNSPEC_RBIT support.
* config/aarch64/aarch64.md (unspec): Remove UNSPEC_RBIT.
(aarch64_rbit): Use bitreverse instead of unspec.
* config/aarch64/iterators.md (SVE_INT_UNARY): Add bitreverse.
(optab): Likewise.
(sve_int_op): Likewise.
(SVE_INT_UNARY): Remove UNSPEC_RBIT.
(optab): Likewise.
(sve_int_op): Likewise.
(min_elem_bits): Likewise.

Signed-off-by: Andrew Pinski 

Diff:
---
 gcc/config/aarch64/aarch64-simd.md  |  3 +--
 gcc/config/aarch64/aarch64-sve-builtins-base.cc |  2 +-
 gcc/config/aarch64/aarch64-sve.md   |  2 +-
 gcc/config/aarch64/aarch64.cc   |  9 +
 gcc/config/aarch64/aarch64.md   |  3 +--
 gcc/config/aarch64/iterators.md | 10 +-
 6 files changed, 10 insertions(+), 19 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-simd.md 
b/gcc/config/aarch64/aarch64-simd.md
index f644bd1731e5..0bb39091a385 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -377,8 +377,7 @@
 
 (define_insn "aarch64_rbit"
   [(set (match_operand:VB 0 "register_operand" "=w")
-   (unspec:VB [(match_operand:VB 1 "register_operand" "w")]
-  UNSPEC_RBIT))]
+   (bitreverse:VB (match_operand:VB 1 "register_operand" "w")))]
   "TARGET_SIMD"
   "rbit\\t%0., %1."
   [(set_attr "type" "neon_rbit")]
diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc 
b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
index 0d2edf3f19e1..dea2f6e6bfc4 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc
+++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc
@@ -3186,7 +3186,7 @@ FUNCTION (svqincp, svqdecp_svqincp_impl, (SS_PLUS, 
US_PLUS))
 FUNCTION (svqincw, svqinc_bhwd_impl, (SImode))
 FUNCTION (svqincw_pat, svqinc_bhwd_impl, (SImode))
 FUNCTION (svqsub, rtx_code_function, (SS_MINUS, US_MINUS, -1))
-FUNCTION (svrbit, unspec_based_function, (UNSPEC_RBIT, UNSPEC_RBIT, -1))
+FUNCTION (svrbit, rtx_code_function, (BITREVERSE, BITREVERSE, -1))
 FUNCTION (svrdffr, svrdffr_impl,)
 FUNCTION (svrecpe, unspec_based_function, (-1, UNSPEC_URECPE, UNSPEC_FRECPE))
 FUNCTION (svrecps, unspec_based_function, (-1, -1, UNSPEC_FRECPS))
diff --git a/gcc/config/aarch64/aarch64-sve.md 
b/gcc/config/aarch64/aarch64-sve.md
index d69db34016a5..5331e7121d55 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -3083,6 +3083,7 @@
 ;; - CLS (= clrsb)
 ;; - CLZ
 ;; - CNT (= popcount)
+;; - RBIT (= bitreverse)
 ;; - NEG
 ;; - NOT
 ;; -
@@ -3171,7 +3172,6 @@
 ;;  [INT] General unary arithmetic corresponding to unspecs
 ;; -
 ;; Includes
-;; - RBIT
 ;; - REVB
 ;; - REVH
 ;; - REVW
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 13191ec8e345..149e5b2f69ae 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -14690,6 +14690,7 @@ cost_plus:
return true;
   }
 
+case BITREVERSE:
 case BSWAP:
   *cost = COSTS_N_INSNS (1);
 
@@ -15339,14 +15340,6 @@ cost_plus:
 
   return false;
 }
-
-  if (XINT (x, 1) == UNSPEC_RBIT)
-{
-  if (speed)
-*cost += extra_cost->alu.rev;
-
-  return false;
-}
   break;
 
 case TRUNCATE:
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 389a1906e236..9de6235b1398 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -259,7 +259,6 @@
 UNSPEC_PACIBSP
 UNSPEC_

[gcc(refs/vendors/ibm/heads/gcc-14-branch)] ibm: Create the ibm/gcc-14-branch

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:96b284e64a7f1c3bfce4e5434c407799bbfbcd98

commit 96b284e64a7f1c3bfce4e5434c407799bbfbcd98
Author: Peter Bergner 
Date:   Wed Jun 12 11:19:31 2024 -0500

ibm: Create the ibm/gcc-14-branch

2024-06-12  Peter Bergner  

Create ibm/gcc-14-branch which follows the releases/gcc-14 branch.

Diff:
---
 gcc/ChangeLog.ibm | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gcc/ChangeLog.ibm b/gcc/ChangeLog.ibm
new file mode 100644
index ..3ebc8710b3b7
--- /dev/null
+++ b/gcc/ChangeLog.ibm
@@ -0,0 +1,3 @@
+2024-06-12  Peter Bergner  
+
+   Create ibm/gcc-14-branch which follows the releases/gcc-14 branch.

[gcc r15-1217] RISC-V: Move amo tests into subfolder

[Patrick O'Neill via Gcc-cvs]

https://gcc.gnu.org/g:8c944f2559ff279ed7e04c2a75881c04c0c31a9b

commit r15-1217-g8c944f2559ff279ed7e04c2a75881c04c0c31a9b
Author: Patrick O'Neill 
Date:   Mon Jun 10 16:32:11 2024 -0700

RISC-V: Move amo tests into subfolder

There's a large number of atomic related testcases in the riscv folder.
Move them into a subfolder similar to what was done for rvv testcases.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/amo-table-a-6-amo-add-1.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c: ...here.
* gcc.target/riscv/amo-table-a-6-amo-add-2.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c: ...here.
* gcc.target/riscv/amo-table-a-6-amo-add-3.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c: ...here.
* gcc.target/riscv/amo-table-a-6-amo-add-4.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c: ...here.
* gcc.target/riscv/amo-table-a-6-amo-add-5.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c: ...here.
* gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-1.c: ...here.
* gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-2.c: ...here.
* gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-3.c: ...here.
* gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-4.c: ...here.
* gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-5.c: ...here.
* gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-6.c: ...here.
* gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-compare-exchange-7.c: ...here.
* gcc.target/riscv/amo-table-a-6-fence-1.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-fence-1.c: ...here.
* gcc.target/riscv/amo-table-a-6-fence-2.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-fence-2.c: ...here.
* gcc.target/riscv/amo-table-a-6-fence-3.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-fence-3.c: ...here.
* gcc.target/riscv/amo-table-a-6-fence-4.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-fence-4.c: ...here.
* gcc.target/riscv/amo-table-a-6-fence-5.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-fence-5.c: ...here.
* gcc.target/riscv/amo-table-a-6-load-1.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-load-1.c: ...here.
* gcc.target/riscv/amo-table-a-6-load-2.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-load-2.c: ...here.
* gcc.target/riscv/amo-table-a-6-load-3.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-load-3.c: ...here.
* gcc.target/riscv/amo-table-a-6-store-1.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-store-1.c: ...here.
* gcc.target/riscv/amo-table-a-6-store-2.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-store-2.c: ...here.
* gcc.target/riscv/amo-table-a-6-store-compat-3.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: ...here.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c: ...here.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c: ...here.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c: ...here.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c: ...here.
* gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Move to...
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c: ...here.
* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Move to...
* gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c: ...here.
* gcc.target/riscv/amo-table-ztso-amo-add-2.c: Move to...
* gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c: ...here.
* gcc.target/riscv/amo-table-ztso-amo-add-3.c: Move to...
* gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c: ...here.
* gcc.target/riscv/amo-table-ztso-amo-add-4.c: 

[gcc r15-1218] RISC-V: Fix amoadd call arguments

[Patrick O'Neill via Gcc-cvs]

https://gcc.gnu.org/g:6343adcef7de1a1214c9b6dd845810aa4a0d19e5

commit r15-1218-g6343adcef7de1a1214c9b6dd845810aa4a0d19e5
Author: Patrick O'Neill 
Date:   Mon Jun 10 16:58:12 2024 -0700

RISC-V: Fix amoadd call arguments

Update __atomic_add_fetch arguments to be a pointer and value rather
than two pointers.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c: Update
__atomic_add_fetch args.
* gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c: Ditto.
* gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c: Ditto.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c: Ditto.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c: Ditto.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c: Ditto.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c: Ditto.
* gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c: Ditto.

Signed-off-by: Patrick O'Neill 

Diff:
---
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-3.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-4.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-5.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-1.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-2.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-3.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-4.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-subword-amo-add-5.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-1.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-2.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-3.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-4.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-amo-add-5.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-1.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-2.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-3.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-4.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-subword-amo-add-5.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-zaamo-preferred-over-zalrsc.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-1.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-2.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-3.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-4.c | 2 +-
 gcc/testsuite/gcc.target/riscv/amo/amo-zalrsc-amo-add-5.c | 2 +-
 26 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c 
b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c
index 9c2ba39789ae..2e53abf28aa2 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-1.c
@@ -10,7 +10,7 @@
 ** amoadd\.w\tzero,a1,0\(a0\)
 ** ret
 */
-void foo (int* bar, int* baz)
+void foo (int* bar, int baz)
 {
   __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED);
 }
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-amo-add-2.c 
b/gcc/testsu

[gcc r15-1219] RISC-V: Allow any temp register to be used in amo tests

[Patrick O'Neill via Gcc-cvs]

https://gcc.gnu.org/g:439c0cc9f7f6e83b898cabbd2e34f98484b432d3

commit r15-1219-g439c0cc9f7f6e83b898cabbd2e34f98484b432d3
Author: Patrick O'Neill 
Date:   Mon Jun 10 17:00:38 2024 -0700

RISC-V: Allow any temp register to be used in amo tests

We artifically restrict the temp registers to be a[0-9]+ when other
registers like t[0-9]+ are valid too. Update to make the regex
accept any register for the temp value.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/amo/amo-table-a-6-load-1.c: Update temp register 
regex.
* gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-load-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-load-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-load-3.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-store-1.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-store-2.c: Ditto.
* gcc.target/riscv/amo/amo-table-ztso-store-3.c: Ditto.

Signed-off-by: Patrick O'Neill 

Diff:
---
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c | 4 ++--
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c | 4 ++--
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c | 4 ++--
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c| 4 ++--
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c| 4 ++--
 gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c | 4 ++--
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c| 4 ++--
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c| 4 ++--
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c| 4 ++--
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c   | 4 ++--
 gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c   | 4 ++--
 12 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c 
b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c
index 3c79035e46d6..53dd52344527 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c
@@ -6,8 +6,8 @@
 
 /*
 ** foo:
-** lw\ta[0-9]+,0\(a0\)
-** sw\ta[0-9]+,0\(a1\)
+** lw\t[atx][0-9]+,0\(a0\)
+** sw\t[atx][0-9]+,0\(a1\)
 ** ret
 */
 void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c 
b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c
index 7d74841846fa..dda0f5415156 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c
@@ -6,9 +6,9 @@
 
 /*
 ** foo:
-** lw\ta[0-9]+,0\(a0\)
+** lw\t[atx][0-9]+,0\(a0\)
 ** fence\tr,rw
-** sw\ta[0-9]+,0\(a1\)
+** sw\t[atx][0-9]+,0\(a1\)
 ** ret
 */
 void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c 
b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c
index ab95fa660d25..3279557fa4a9 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c
@@ -7,9 +7,9 @@
 /*
 ** foo:
 ** fence\trw,rw
-** lw\ta[0-9]+,0\(a0\)
+** lw\t[atx][0-9]+,0\(a0\)
 ** fence\tr,rw
-** sw\ta[0-9]+,0\(a1\)
+** sw\t[atx][0-9]+,0\(a1\)
 ** ret
 */
 void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c 
b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c
index d852fddf03de..6b05429520bf 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c
@@ -6,8 +6,8 @@
 
 /*
 ** foo:
-** lw\ta[0-9]+,0\(a1\)
-** sw\ta[0-9]+,0\(a0\)
+** lw\t[atx][0-9]+,0\(a1\)
+** sw\t[atx][0-9]+,0\(a0\)
 ** ret
 */
 void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c 
b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c
index ccb5e2af7cc1..1ad7dede931b 100644
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c
@@ -6,9 +6,9 @@
 
 /*
 ** foo:
-** lw\ta[0-9]+,0\(a1\)
+** lw\t[atx][0-9]+,0\(a1\)
 ** fence\trw,w
-** sw\ta[0-9]+,0\(a0\)
+** sw\t[atx][0-9]+,0\(a0\)
 ** ret
 */
 void foo (int* bar, int* baz)
diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c 
b/gcc/testsuite/g

[gcc r15-1220] pretty_printer: unbreak build on aarch64 [PR115465]

[David Malcolm via Gcc-cvs]

https://gcc.gnu.org/g:e35f4eab68773b08324f9784ca69f8ace3c657cc

commit r15-1220-ge35f4eab68773b08324f9784ca69f8ace3c657cc
Author: David Malcolm 
Date:   Wed Jun 12 14:24:47 2024 -0400

pretty_printer: unbreak build on aarch64 [PR115465]

I missed this target-specific usage of pretty_printer::buffer when
making the fields private in r15-1209-gc5e3be456888aa; sorry.

gcc/ChangeLog:
PR bootstrap/115465
* config/aarch64/aarch64-early-ra.cc (early_ra::process_block):
Update for fields of pretty_printer becoming private in
r15-1209-gc5e3be456888aa.

Signed-off-by: David Malcolm 

Diff:
---
 gcc/config/aarch64/aarch64-early-ra.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64-early-ra.cc 
b/gcc/config/aarch64/aarch64-early-ra.cc
index 1e2c823cb2eb..99324423ee5a 100644
--- a/gcc/config/aarch64/aarch64-early-ra.cc
+++ b/gcc/config/aarch64/aarch64-early-ra.cc
@@ -3446,7 +3446,7 @@ early_ra::process_block (basic_block bb, bool is_isolated)
fprintf (dump_file, "\nBlock %d:\n", bb->index);
  fprintf (dump_file, "%6d:", m_current_point);
  pretty_printer rtl_slim_pp;
- rtl_slim_pp.buffer->stream = dump_file;
+ rtl_slim_pp.set_output_stream (dump_file);
  print_insn (&rtl_slim_pp, insn, 1);
  pp_flush (&rtl_slim_pp);
  fprintf (dump_file, "\n");

[gcc r15-1221] Whitespace cleanup for target-supports.exp

[Patrick O'Neill via Gcc-cvs]

https://gcc.gnu.org/g:eaff4d6714805ba2504270dfff51fca61854542d

commit r15-1221-geaff4d6714805ba2504270dfff51fca61854542d
Author: Patrick O'Neill 
Date:   Wed Jun 12 11:33:11 2024 -0700

Whitespace cleanup for target-supports.exp

This patch removes trailing whitespace and replaces leading groups of 8-16
spaces with tabs.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp: Cleanup whitespace.

Diff:
---
 gcc/testsuite/lib/target-supports.exp | 1168 -
 1 file changed, 584 insertions(+), 584 deletions(-)

diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index e862a8932449..e307f4e69efb 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -28,7 +28,7 @@
 # If ARGS is not empty, its first element is a string that
 # should be added to the command line.
 #
-# Assume by default that CONTENTS is C code.  
+# Assume by default that CONTENTS is C code.
 # Otherwise, code should contain:
 # "/* Assembly" for assembly code,
 # "// C++" for c++,
@@ -39,12 +39,12 @@
 # "// Go" for Go
 # "// Rust" for Rust
 # and "(* Modula-2" for Modula-2
-# If the tool is ObjC/ObjC++ then we overide the extension to .m/.mm to 
+# If the tool is ObjC/ObjC++ then we overide the extension to .m/.mm to
 # allow for ObjC/ObjC++ specific flags.
 
 proc check_compile {basename type contents args} {
 global tool
-verbose "check_compile tool: $tool for $basename" 
+verbose "check_compile tool: $tool for $basename"
 
 # Save additional_sources to avoid compiling testsuite's sources
 # against check_compile's source.
@@ -100,7 +100,7 @@ proc check_compile {basename type contents args} {
 global compiler_flags
 set save_compiler_flags $compiler_flags
 set lines [${tool}_target_compile $src $output $compile_type "$options"]
-set compiler_flags $save_compiler_flags 
+set compiler_flags $save_compiler_flags
 file delete $src
 
 set scan_output $output
@@ -280,8 +280,8 @@ proc check_configured_with { pattern } {
 set options [list "additional_flags=-v"]
 set gcc_output [${tool}_target_compile "" "" "none" $options]
 if { [ regexp "Configured with: \[^\n\]*$pattern" $gcc_output ] } {
-verbose "Matched: $pattern" 2
-return 1
+   verbose "Matched: $pattern" 2
+   return 1
 }
 
 verbose "Failed to match: $pattern" 2
@@ -301,19 +301,19 @@ proc check_weak_available { } {
 # All mips targets should support it
 
 if { [ string first "mips" $target_cpu ] >= 0 } {
-return 1
+   return 1
 }
 
 # All AIX targets should support it
 
 if { [istarget *-*-aix*] } {
-return 1
+   return 1
 }
 
 # All solaris2 targets should support it
 
 if { [istarget *-*-solaris2*] } {
-return 1
+   return 1
 }
 
 # Windows targets Cygwin and MingW32 support it
@@ -346,13 +346,13 @@ proc check_weak_available { } {
 set objformat [gcc_target_object_format]
 
 switch $objformat {
-elf  { return 1 }
-ecoff{ return 1 }
-a.out{ return 1 }
+   elf  { return 1 }
+   ecoff{ return 1 }
+   a.out{ return 1 }
mach-o   { return 1 }
som  { return 1 }
-unknown  { return -1 }
-default  { return 0 }
+   unknown  { return -1 }
+   default  { return 0 }
 }
 }
 
@@ -414,31 +414,31 @@ proc check_effective_target_vma_equals_lma { } {
if [string match "" $lines] then {
# No error messages
 
-set objdump_name [find_binutils_prog objdump]
-set output [remote_exec host "$objdump_name" "--section-headers 
--section=.data $exe"]
-set output [lindex $output 1]
-
-remote_file build delete $exe
-
-# Example output of objdump:
-#vma_equals_lma9059.exe: file format elf32-littlearm
-#
-#Sections:
-#Idx Name  Size  VMA   LMA   File off  Algn
-#  6 .data 0558  2000  08002658  0002  2**3
-#  CONTENTS, ALLOC, LOAD, DATA
-
-# Capture LMA and VMA columns for .data section
-if ![ regexp {\d*\d+\s+\.data\s+\d+\s+(\d+)\s+(\d+)} $output dummy 
vma lma ] {
-verbose "Could not parse objdump output" 2
-return 0
-} else {
-return [string equal $vma $lma]
-}
+   set objdump_name [find_binutils_prog objdump]
+   set output [remote_exec host "$objdump_name" "--section-headers 
--section=.data $exe"]
+   set output [lindex $output 1]
+
+   remote_file build delete $exe
+
+   # Example output of objdump:
+   #vma_equals_lma9059.exe: file format elf32-littlearm
+   #
+   #Sections:
+   #Idx Name  Size  VMA  

[gcc r15-1222] c++: fix testcase diagnostics

[Jason Merrill via Gcc-cvs]

https://gcc.gnu.org/g:7bf072e87a03c9eaff9b7a1ac182537b70f0ba8e

commit r15-1222-g7bf072e87a03c9eaff9b7a1ac182537b70f0ba8e
Author: Jason Merrill 
Date:   Wed Jun 12 14:14:16 2024 -0400

c++: fix testcase diagnostics

The r15-1180 adjustments to this testcase broke a couple of tests in C++26
mode.

gcc/testsuite/ChangeLog:

* g++.dg/cpp26/static_assert1.C: Fix diagnostic typos.

Diff:
---
 gcc/testsuite/g++.dg/cpp26/static_assert1.C | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/g++.dg/cpp26/static_assert1.C 
b/gcc/testsuite/g++.dg/cpp26/static_assert1.C
index 7840b6b04d27..f9ac8311b827 100644
--- a/gcc/testsuite/g++.dg/cpp26/static_assert1.C
+++ b/gcc/testsuite/g++.dg/cpp26/static_assert1.C
@@ -286,14 +286,14 @@ namespace NN
   };
   static_assert (true, M{});   // { dg-warning "'static_assert' with 
non-string message only available with" "" { target c++23_only } }
   static_assert (false, M{});  // { dg-warning "'static_assert' with 
non-string message only available with" "" { target c++23_only } }
-   // { dg-error "'constexpr string 
'size\\\(\\\)' must be a constant expression" "" { target c++23 } .-1 }
+   // { dg-error "constexpr string 
'size\\\(\\\)' must be a constant expression" "" { target c++23 } .-1 }
   struct N {
 static constexpr int size () { return 4; }
 static constexpr const char *data () { if consteval { throw 1; } else { 
return "test"; } } // { dg-error "expression '' is not a 
constant expression" "" { target c++23 } }
   };
   static_assert (true, N{});   // { dg-warning "'static_assert' with 
non-string message only available with" "" { target c++23_only } }
   static_assert (false, N{});  // { dg-warning "'static_assert' with 
non-string message only available with" "" { target c++23_only } }
-   // { dg-error "'constexpr string 
'data\\\(\\\)\\\[0\\\]' must be a constant expression" "" { target c++23 } .-1 }
+   // { dg-error "constexpr string 
'data\\\(\\\)\\\[0\\\]' must be a constant expression" "" { target c++23 } .-1 }
 #endif
   struct O { constexpr int operator () () const { return 12; } };
   struct P { constexpr const char *operator () () const { return "another 
test"; } };

[gcc r15-1224] c++: repeated export using

[Jason Merrill via Gcc-cvs]

https://gcc.gnu.org/g:074c1fc797435979c00b24aff2a4f895b8273bcf

commit r15-1224-g074c1fc797435979c00b24aff2a4f895b8273bcf
Author: Jason Merrill 
Date:   Wed Jun 12 08:06:47 2024 -0400

c++: repeated export using

A sample implementation of module std was breaking because the exports
included 'using std::operator&' twice.  Since Nathaniel's r15-964 for
PR114867, the first using added an extra instance of each function that was
revealed/exported by that using, resulting in duplicates for
lookup_maybe_add to dedup.  But if the duplicate is the first thing in the
list, lookup_add doesn't make an OVERLOAD, so trying to set OVL_USING_P
crashes.  Fixed by using ovl_make in the case where we want to set the flag.

gcc/cp/ChangeLog:

* tree.cc (lookup_maybe_add): Use ovl_make when setting OVL_USING_P.

gcc/testsuite/ChangeLog:

* g++.dg/modules/using-21_a.C: New test.

Diff:
---
 gcc/cp/tree.cc|  8 ++--
 gcc/testsuite/g++.dg/modules/using-21_a.C | 11 +++
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/gcc/cp/tree.cc b/gcc/cp/tree.cc
index d2a8f79ffab4..28648c14c6da 100644
--- a/gcc/cp/tree.cc
+++ b/gcc/cp/tree.cc
@@ -2526,11 +2526,15 @@ lookup_maybe_add (tree fns, tree lookup, bool deduping)
   predecessors onto the lookup.  */
for (; fns != probe; fns = OVL_CHAIN (fns))
  {
-   lookup = lookup_add (OVL_FUNCTION (fns), lookup);
/* Propagate OVL_USING, but OVL_HIDDEN &
   OVL_DEDUP_P don't matter.  */
if (OVL_USING_P (fns))
- OVL_USING_P (lookup) = true;
+ {
+   lookup = ovl_make (OVL_FUNCTION (fns), lookup);
+   OVL_USING_P (lookup) = true;
+ }
+   else
+ lookup = lookup_add (OVL_FUNCTION (fns), lookup);
  }
 
/* And now skip this function.  */
diff --git a/gcc/testsuite/g++.dg/modules/using-21_a.C 
b/gcc/testsuite/g++.dg/modules/using-21_a.C
new file mode 100644
index ..ce6e3f920f1e
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/using-21_a.C
@@ -0,0 +1,11 @@
+// { dg-additional-options "-fmodules-ts -Wno-global-module" }
+
+module;
+namespace foo {
+  void baz();
+}
+export module foo;
+namespace foo {
+  export using foo::baz;
+  export using foo::baz;
+}

[gcc r15-1223] c++: module std and exception_ptr

[Jason Merrill via Gcc-cvs]

https://gcc.gnu.org/g:f8356d66cfbda1e65536016d3049342a43f6af63

commit r15-1223-gf8356d66cfbda1e65536016d3049342a43f6af63
Author: Jason Merrill 
Date:   Wed Jun 12 00:13:45 2024 -0400

c++: module std and exception_ptr

exception_ptr.h contains

  namespace __exception_ptr
  {
class exception_ptr;
  }
  using __exception_ptr::exception_ptr;

so when module std tries to 'export using std::exception_ptr', it names
another using-directive rather than the class directly, so __exception_ptr
is never explicitly opened in module purview.

gcc/cp/ChangeLog:

* module.cc (depset::hash::add_binding_entity): Set
DECL_MODULE_PURVIEW_P instead of asserting.

gcc/testsuite/ChangeLog:

* g++.dg/modules/using-20_a.C: New test.

Diff:
---
 gcc/cp/module.cc  |  7 +--
 gcc/testsuite/g++.dg/modules/using-20_a.C | 14 ++
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc
index 21fc85150c9e..72e876cec187 100644
--- a/gcc/cp/module.cc
+++ b/gcc/cp/module.cc
@@ -13253,8 +13253,11 @@ depset::hash::add_binding_entity (tree decl, WMB_Flags 
flags, void *data_)
   data->met_namespace = true;
   if (data->hash->add_namespace_entities (decl, data->partitions))
{
- /* It contains an exported thing, so it is exported.  */
- gcc_checking_assert (DECL_MODULE_PURVIEW_P (decl));
+ /* It contains an exported thing, so it is exported.
+We used to assert DECL_MODULE_PURVIEW_P, but that fails for a
+namespace like std::__exception_ptr which is never opened in
+module purview; the exporting using finds another using.  */
+ DECL_MODULE_PURVIEW_P (decl) = true;
  DECL_MODULE_EXPORT_P (decl) = true;
}
 
diff --git a/gcc/testsuite/g++.dg/modules/using-20_a.C 
b/gcc/testsuite/g++.dg/modules/using-20_a.C
new file mode 100644
index ..bb3bb6160f8b
--- /dev/null
+++ b/gcc/testsuite/g++.dg/modules/using-20_a.C
@@ -0,0 +1,14 @@
+// { dg-additional-options "-fmodules-ts -fdump-lang-module 
-Wno-global-module" }
+// { dg-final { scan-lang-dump {Writing definition '::foo::bar::baz'} module } 
}
+
+module;
+namespace foo {
+  namespace bar {
+struct baz { };
+  }
+  using bar::baz;
+}
+export module foo;
+namespace foo {
+  export using foo::baz;
+}

[gcc r15-1225] [libstdc++] [testsuite] xfail double-prec from_chars for float128_t

[Alexandre Oliva via Libstdc++-cvs]

https://gcc.gnu.org/g:6c3b01db8274f0392a3f4dccbd9ac71d0c53c04f

commit r15-1225-g6c3b01db8274f0392a3f4dccbd9ac71d0c53c04f
Author: Alexandre Oliva 
Date:   Wed Jun 12 19:48:04 2024 -0300

[libstdc++] [testsuite] xfail double-prec from_chars for float128_t

Tests involving float128_t were xfailed or otherwise worked around for
vxworks on aarch64.  The same issue came up on rtems.  This patch
adjusts them similarly.


for  libstdc++-v3/ChangeLog

* testsuite/20_util/from_chars/8.cc: Skip float128_t testing
on aarch64-rtems*.
* testsuite/20_util/to_chars/float128_c++23.cc: Xfail run on
aarch64-rtems*.

Diff:
---
 libstdc++-v3/testsuite/20_util/from_chars/8.cc| 2 +-
 libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/libstdc++-v3/testsuite/20_util/from_chars/8.cc 
b/libstdc++-v3/testsuite/20_util/from_chars/8.cc
index a6343422c5a9..bacad89943b5 100644
--- a/libstdc++-v3/testsuite/20_util/from_chars/8.cc
+++ b/libstdc++-v3/testsuite/20_util/from_chars/8.cc
@@ -17,7 +17,7 @@
 
 // { dg-do run { target c++23 } }
 // { dg-add-options ieee }
-// { dg-additional-options "-DSKIP_LONG_DOUBLE" { target aarch64-*-vxworks* } }
+// { dg-additional-options "-DSKIP_LONG_DOUBLE" { target aarch64-*-vxworks* 
aarch64-*-rtems* } }
 
 #include 
 #include 
diff --git a/libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc 
b/libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc
index ca00761ee7c9..6cb9cadcd204 100644
--- a/libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc
+++ b/libstdc++-v3/testsuite/20_util/to_chars/float128_c++23.cc
@@ -19,7 +19,7 @@
 // { dg-require-effective-target ieee_floats }
 // { dg-require-effective-target size32plus }
 // { dg-add-options ieee }
-// { dg-xfail-run-if "from_chars limited to double-precision" { 
aarch64-*-vxworks* } }
+// { dg-xfail-run-if "from_chars limited to double-precision" { 
aarch64-*-vxworks* aarch64-*-rtems* } }
 
 #include 
 #include 

[gcc r15-1226] [libstdc++] [testsuite] require cmath for c++23 cmath tests

[Alexandre Oliva via Libstdc++-cvs]

https://gcc.gnu.org/g:5288935d30c4615cce664ca8fba65eecf05c326f

commit r15-1226-g5288935d30c4615cce664ca8fba65eecf05c326f
Author: Alexandre Oliva 
Date:   Wed Jun 12 19:48:06 2024 -0300

[libstdc++] [testsuite] require cmath for c++23 cmath tests

Some c++23 tests fail on targets that don't satisfy dg-require-cmath,
because referenced math functions don't get declared in std.  Add the
missing requirement.


for  libstdc++-v3/ChangeLog

* testsuite/26_numerics/headers/cmath/constexpr_std_c++23.cc:
Require cmath.
* testsuite/26_numerics/headers/cmath/functions_std_c++23.cc:
Likewise.
* testsuite/26_numerics/headers/cmath/nextafter_c++23.cc:
Likewise.

Diff:
---
 libstdc++-v3/testsuite/26_numerics/headers/cmath/constexpr_std_c++23.cc | 1 +
 libstdc++-v3/testsuite/26_numerics/headers/cmath/functions_std_c++23.cc | 1 +
 libstdc++-v3/testsuite/26_numerics/headers/cmath/nextafter_c++23.cc | 1 +
 3 files changed, 3 insertions(+)

diff --git 
a/libstdc++-v3/testsuite/26_numerics/headers/cmath/constexpr_std_c++23.cc 
b/libstdc++-v3/testsuite/26_numerics/headers/cmath/constexpr_std_c++23.cc
index 0e3d112fe2e8..3c2377fd6987 100644
--- a/libstdc++-v3/testsuite/26_numerics/headers/cmath/constexpr_std_c++23.cc
+++ b/libstdc++-v3/testsuite/26_numerics/headers/cmath/constexpr_std_c++23.cc
@@ -16,6 +16,7 @@
 // .
 
 // { dg-do link { target c++23 } }
+// { dg-require-cmath "" }
 
 #include 
 #include 
diff --git 
a/libstdc++-v3/testsuite/26_numerics/headers/cmath/functions_std_c++23.cc 
b/libstdc++-v3/testsuite/26_numerics/headers/cmath/functions_std_c++23.cc
index 000cebf364aa..ea68ac5da755 100644
--- a/libstdc++-v3/testsuite/26_numerics/headers/cmath/functions_std_c++23.cc
+++ b/libstdc++-v3/testsuite/26_numerics/headers/cmath/functions_std_c++23.cc
@@ -16,6 +16,7 @@
 // .
 
 // { dg-do link { target c++23 } }
+// { dg-require-cmath "" }
 
 #include 
 #include 
diff --git 
a/libstdc++-v3/testsuite/26_numerics/headers/cmath/nextafter_c++23.cc 
b/libstdc++-v3/testsuite/26_numerics/headers/cmath/nextafter_c++23.cc
index 7d7e10bd8aea..91767d22cc3f 100644
--- a/libstdc++-v3/testsuite/26_numerics/headers/cmath/nextafter_c++23.cc
+++ b/libstdc++-v3/testsuite/26_numerics/headers/cmath/nextafter_c++23.cc
@@ -16,6 +16,7 @@
 // .
 
 // { dg-do run { target c++23 } }
+// { dg-require-cmath "" }
 
 #include 
 #include 

[gcc r15-1227] c++: visibility wrt concept-id as targ [PR115283]

[Patrick Palka via Gcc-cvs]

https://gcc.gnu.org/g:b1fe718cbe0c8883af89f52e0aad3ebf913683de

commit r15-1227-gb1fe718cbe0c8883af89f52e0aad3ebf913683de
Author: Patrick Palka 
Date:   Wed Jun 12 20:05:05 2024 -0400

c++: visibility wrt concept-id as targ [PR115283]

Like with alias templates, it seems we don't maintain visibility flags
for concepts either, so min_vis_expr_r should ignore them for now.
Otherwise after r14-6789 we may incorrectly give a function template that
uses a concept-id in its signature internal linkage.

PR c++/115283

gcc/cp/ChangeLog:

* decl2.cc (min_vis_expr_r) : Ignore
concepts.

gcc/testsuite/ChangeLog:

* g++.dg/template/linkage5.C: New test.

Reviewed-by: Jason Merrill 

Diff:
---
 gcc/cp/decl2.cc  |  5 +++--
 gcc/testsuite/g++.dg/template/linkage5.C | 14 ++
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/gcc/cp/decl2.cc b/gcc/cp/decl2.cc
index 7baff46a1921..6c3ef60d51f8 100644
--- a/gcc/cp/decl2.cc
+++ b/gcc/cp/decl2.cc
@@ -2723,9 +2723,10 @@ min_vis_expr_r (tree *tp, int */*walk_subtrees*/, void 
*data)
   break;
 
 case TEMPLATE_DECL:
-  if (DECL_ALIAS_TEMPLATE_P (t))
+  if (DECL_ALIAS_TEMPLATE_P (t) || standard_concept_p (t))
/* FIXME: We don't maintain TREE_PUBLIC / DECL_VISIBILITY for
-  alias templates so we can't trust it here (PR107906).  */
+  alias templates so we can't trust it here (PR107906).  Ditto
+  for concepts.  */
break;
   t = DECL_TEMPLATE_RESULT (t);
   /* Fall through.  */
diff --git a/gcc/testsuite/g++.dg/template/linkage5.C 
b/gcc/testsuite/g++.dg/template/linkage5.C
new file mode 100644
index ..7e8f93f546f1
--- /dev/null
+++ b/gcc/testsuite/g++.dg/template/linkage5.C
@@ -0,0 +1,14 @@
+// PR c++/115283
+// { dg-final { scan-assembler "(weak|glob)\[^\n\]*_Z1fIiEv1AIX1CIT_EEE" } }
+// { dg-do compile { target c++20 } }
+
+template
+concept C = true;
+
+template
+struct A { };
+
+template
+void f(A>) { }
+
+template void f(A);

[gcc(refs/users/meissner/heads/work168-test)] Restrict modes that can got in SPRs.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:2ef7f940f369356534008c21b3472856a6060d22

commit 2ef7f940f369356534008c21b3472856a6060d22
Author: Michael Meissner 
Date:   Wed Jun 12 21:01:31 2024 -0400

Restrict modes that can got in SPRs.

2024-06-04  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): 
Restrict
the modes that can go in SPR registers.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c5c4191127e4..02be24b1a914 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1851,9 +1851,13 @@ static int
 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
 {
   int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
+  bool orig_complex_p = false;
 
   if (COMPLEX_MODE_P (mode))
-mode = GET_MODE_INNER (mode);
+{
+  mode = GET_MODE_INNER (mode);
+  orig_complex_p = true;
+}
 
   /* Vector pair modes need even/odd VSX register pairs.  Only allow vector
  registers.  */
@@ -1935,6 +1939,18 @@ rs6000_hard_regno_mode_ok_uncached (int regno, 
machine_mode mode)
   if (CA_REGNO_P (regno))
 return mode == Pmode || mode == SImode;
 
+  /* Do some consistancy checks for SPRs.  Don't allow complex modes.
+ VRSAVE/VSCR are always 32-bit SPRs.  Don't allow floating point modes in
+ the other SPRs.  Don't allow large modes that don't fit in a single
+ register. */
+  if (regno == VRSAVE_REGNO || regno == VSCR_REGNO)
+  return (!orig_complex_p && mode == SImode);
+
+  if (regno == LR_REGNO || regno == CTR_REGNO)
+return (!orig_complex_p
+   && GET_MODE_SIZE (mode) <= UNITS_PER_WORD
+   && !SCALAR_FLOAT_MODE_P (mode));
+
   /* AltiVec only in AldyVec registers.  */
   if (ALTIVEC_REGNO_P (regno))
 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)

[gcc(refs/users/meissner/heads/work168-test)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:c3aa0ae32bf157ec50661712c530f03d5ebde645

commit c3aa0ae32bf157ec50661712c530f03d5ebde645
Author: Michael Meissner 
Date:   Wed Jun 12 21:03:35 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.test | 172 -
 1 file changed, 171 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index dc8d3ec04278..4c1c466a3db6 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,6 +1,176 @@
+ Branch work168-test, patch #300 
+
+Restrict modes that can got in SPRs.
+
+2024-06-04  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Restrict
+   the modes that can go in SPR registers.
+
+ Branch work168-test, patch #11 from work168 branch 

+
+Add -mcpu=future tuning support.
+
+This patch makes -mtune=future use the same tuning decision as -mtune=power11.
+
+2024-06-03  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/power10.md (all reservations): Add future as an
+   alterntive to power10 and power11.
+
+ Branch work168-test, patch #10 from work168 branch 

+
+Add -mcpu=future support.
+
+This patch adds the future option to the -mcpu= and -mtune= switches.
+
+This patch treats the future like a power11 in terms of costs and reassociation
+width.
+
+This patch issues a ".machine future" to the assembly file if you use
+-mcpu=power11.
+
+This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.
+
+This patch allows GCC to be configured with the --with-cpu=future and
+--with-tune=future options.
+
+This patch passes -mfuture to the assembler if the user uses -mcpu=future.
+
+2024-06-03  Michael Meissner  
+
+gcc/
+
+   * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
+   * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11.
+   * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/driver-rs6000.cc (asm_names): Likewise.
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+   _ARCH_PWR_FUTURE if -mcpu=future.
+   * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define.
+   (POWERPC_MASKS): Add future isa bit.
+   (power11 cpu): Add future definition.
+   * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor.
+   * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
+   * config/rs6000/rs6000-tables.opt: Regenerate.
+   * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future
+   support.
+   (rs6000_machine_from_flags): Likewise.
+   (rs6000_reassociation_width): Likewise.
+   (rs6000_adjust_cost): Likewise.
+   (rs6000_issue_rate): Likewise.
+   (rs6000_sched_reorder): Likewise.
+   (rs6000_sched_reorder2): Likewise.
+   (rs6000_register_move_cost): Likewise.
+   (rs6000_opt_masks): Likewise.
+   * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/rs6000.md (cpu attribute): Add future.
+   * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag.
+   * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future.
+
+ Branch work168-test, patch #3 from work168 branch 

+
+Add -mcpu=power11 tests.
+
+This patch adds some simple tests for -mcpu=power11 support.  In order to run
+these tests, you need an assembler that supports the appropriate option for
+supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX).
+
+2024-06-03  Michael Meissner  
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/power11-1.c: New test.
+   * gcc.target/powerpc/power11-2.c: Likewise.
+   * gcc.target/powerpc/power11-3.c: Likewise.
+   * lib/target-supports.exp (check_effective_target_power11_ok): Add new
+   effective target.
+
+ Branch work168-test, patch #2 from work168 branch 

+
+Add -mcpu=power11 tuning support.
+
+This patch makes -mtune=power11 use the same tuning decisions as 
-mtune=power10.
+
+2024-06-03  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/power10.md (all reservations): Add power11 as an
+   alternative to power10.
+
+ Branch work168-test, patch #1 from work168 branch 

+
+Add -mcpu=power11 support.
+
+This patch adds the power11 option to the -mcpu= and -mtune= switches.
+
+This patch treats the power11 like a power10 in terms of costs and 
reassociation
+width.
+
+This patch issues a ".machine power11" to the assembly file if you use
+-mcpu=power11.
+
+This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
+
+This patch allows GCC to be configured with the --with-cpu=power11 and
+--with-tune=power11 options.
+
+This patch

[gcc r15-1229] [APX ZU] Support APX zero-upper

[Kong Lingling via Gcc-cvs]

https://gcc.gnu.org/g:8a5d0d72ea8c324bbfa2cff1284fa8e473fc466d

commit r15-1229-g8a5d0d72ea8c324bbfa2cff1284fa8e473fc466d
Author: Lingling Kong 
Date:   Thu Jun 13 09:18:18 2024 +0800

[APX ZU] Support APX zero-upper

Enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc.

gcc/ChangeLog:

* config/i386/i386-opts.h (enum apx_features): Add apx_zu.
* config/i386/i386.h (TARGET_APX_ZU): Define.
* config/i386/i386.md (*imulhizu): New define_insn.
(*setcc__zu): Ditto.
* config/i386/i386.opt: Add enum value for zu.

gcc/testsuite/ChangeLog:

* gcc.target/i386/apx-zu-1.c: New test.
* gcc.target/i386/apx-zu-2.c: New test.

Diff:
---
 gcc/config/i386/i386-opts.h  |  3 ++-
 gcc/config/i386/i386.h   |  1 +
 gcc/config/i386/i386.md  | 25 +++--
 gcc/config/i386/i386.opt |  3 +++
 gcc/testsuite/gcc.target/i386/apx-zu-1.c | 38 
 gcc/testsuite/gcc.target/i386/apx-zu-2.c | 19 
 6 files changed, 86 insertions(+), 3 deletions(-)

diff --git a/gcc/config/i386/i386-opts.h b/gcc/config/i386/i386-opts.h
index 5fcc49279789..c7ec0d9fd397 100644
--- a/gcc/config/i386/i386-opts.h
+++ b/gcc/config/i386/i386-opts.h
@@ -142,8 +142,9 @@ enum apx_features {
   apx_ppx = 1 << 3,
   apx_nf = 1 << 4,
   apx_ccmp = 1 << 5,
+  apx_zu = 1 << 6,
   apx_all = apx_egpr | apx_push2pop2 | apx_ndd
-   | apx_ppx | apx_nf | apx_ccmp,
+   | apx_ppx | apx_nf | apx_ccmp | apx_zu,
 };
 
 #endif
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 7051c6c13e4c..dc1a1f443207 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -57,6 +57,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If 
not, see
 #define TARGET_APX_PPX (ix86_apx_features & apx_ppx)
 #define TARGET_APX_NF (ix86_apx_features & apx_nf)
 #define TARGET_APX_CCMP (ix86_apx_features & apx_ccmp)
+#define TARGET_APX_ZU (ix86_apx_features & apx_zu)
 
 #include "config/vxworks-dummy.h"
 
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index a64f2ad4f5f0..5fc2bae67f6b 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -10060,6 +10060,19 @@
(const_string "direct")))
(set_attr "mode" "")])
 
+(define_insn "*imulhizu"
+  [(set (match_operand:SWI48x 0 "register_operand" "=r,r")
+   (zero_extend:SWI48x
+ (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm")
+  (match_operand:HI 2 "immediate_operand" "K,n"
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_APX_ZU"
+  "@
+   imulzu{w}\t{%2, %1, %w0|%w0, %1, %2}
+   imulzu{w}\t{%2, %1, %w0|%w0, %1, %2}"
+  [(set_attr "type" "imul")
+   (set_attr "mode" "HI")])
+
 (define_insn "*mulsi3_1_zext"
   [(set (match_operand:DI 0 "register_operand" "=r,r,r")
(zero_extend:DI
@@ -18447,11 +18460,19 @@
 ;; For all sCOND expanders, also expand the compare or test insn that
 ;; generates cc0.  Generate an equality comparison if `seq' or `sne'.
 
+(define_insn "*setcc__zu"
+  [(set (match_operand:SWI248 0 "register_operand" "=r")
+   (match_operator:SWI248 1 "ix86_comparison_operator"
+ [(reg FLAGS_REG) (const_int 0)]))]
+  "TARGET_APX_ZU"
+  "setzu%C1\t%b0"
+  [(set_attr "type" "setcc")])
+
 (define_insn_and_split "*setcc_di_1"
   [(set (match_operand:DI 0 "register_operand" "=q")
(match_operator:DI 1 "ix86_comparison_operator"
  [(reg FLAGS_REG) (const_int 0)]))]
-  "TARGET_64BIT && !TARGET_PARTIAL_REG_STALL"
+  "!TARGET_APX_ZU && TARGET_64BIT && !TARGET_PARTIAL_REG_STALL"
   "#"
   "&& reload_completed"
   [(set (match_dup 2) (match_dup 1))
@@ -18484,7 +18505,7 @@
   [(set (match_operand:SWI24 0 "register_operand" "=q")
(match_operator:SWI24 1 "ix86_comparison_operator"
  [(reg FLAGS_REG) (const_int 0)]))]
-  "!TARGET_PARTIAL_REG_STALL
+  "!TARGET_APX_ZU && !TARGET_PARTIAL_REG_STALL
&& (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))"
   "#"
   "&& reload_completed"
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 7017cc87cec3..353fffb23430 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1342,6 +1342,9 @@ Enum(apx_features) String(nf) Value(apx_nf) Set(6)
 EnumValue
 Enum(apx_features) String(ccmp) Value(apx_ccmp) Set(7)
 
+EnumValue
+Enum(apx_features) String(zu) Value(apx_zu) Set(8)
+
 EnumValue
 Enum(apx_features) String(all) Value(apx_all) Set(1)
 
diff --git a/gcc/testsuite/gcc.target/i386/apx-zu-1.c 
b/gcc/testsuite/gcc.target/i386/apx-zu-1.c
new file mode 100644
index ..927a87673a7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/apx-zu-1.c
@@ -0,0 +1,38 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mapxf -march=x86-64 -O2" } */
+/* { dg-final { scan-assembler-not "setle"} } */
+/* { dg-final { scan-assembler-not "setge"} } */

[gcc r15-1230] MIPS: Use signaling fcmp instructions for LT/LE/LTGT

[YunQiang Su via Gcc-cvs]

https://gcc.gnu.org/g:e3e5fd0c24c9b82d824da27bf8455bb3654e8eff

commit r15-1230-ge3e5fd0c24c9b82d824da27bf8455bb3654e8eff
Author: YunQiang Su 
Date:   Sat Jun 8 11:31:19 2024 +0800

MIPS: Use signaling fcmp instructions for LT/LE/LTGT

LT/LE: c.lt.fmt/c.le.fmt on pre-R6 and cmp.lt.fmt/cmp.le.fmt have
different semantic:
   c.lt.fmt will signal for all NaN, including qNaN;
   cmp.lt.fmt will only signal sNaN, while not qNaN;
   cmp.slt.fmt has the same semantic as c.lt.fmt;
   lt/le of RTL will signaling qNaN.

while in `s__using_`, RTL operation
`lt`/`le` are convert to c/cmp's lt/le, which is correct for C.cond.fmt,
while not for CMP.cond.fmt. Let's convert them to slt/sle if ISA_HAS_CCF.

For LTGT, which signals qNaN, `sne` of r6 has same semantic, while pre-R6
has only inverse one `ngl`.  Thus for RTL we have to use the `uneq` as the
operator, and introduce a new CC mode: CCEmode to mark it as signaling.

This patch can fix
   gcc.dg/torture/pr91323.c for pre-R6;
   gcc.dg/torture/builtin-iseqsig-* for R6.

gcc:
* config/mips/mips-modes.def: New CC_MODE CCE.
* config/mips/mips-protos.h(mips_output_compare): New function.
* config/mips/mips.cc(mips_allocate_fcc): Set CCEmode count=1.
(mips_emit_compare): Use CCEmode for LTGT/LT/LE for pre-R6.
(mips_output_compare): New function. Convert lt/le to slt/sle
for R6; convert ueq to ngl for CCEmode.
(mips_hard_regno_mode_ok_uncached): Mention CCEmode.
* config/mips/mips.h: Mention CCEmode for LOAD_EXTEND_OP.
* config/mips/mips.md(FPCC): Add CCE.
(define_mode_iterator MOVECC): Mention CCE.
(define_mode_attr reg): Add CCE with "z".
(define_mode_attr fpcmp): Add CCE with "c".
(define_code_attr fcond): ltgt should use sne instead of ne.
(s__using_): call 
mips_output_compare.

Diff:
---
 gcc/config/mips/mips-modes.def |  1 +
 gcc/config/mips/mips-protos.h  |  2 ++
 gcc/config/mips/mips.cc| 48 ++
 gcc/config/mips/mips.h |  2 +-
 gcc/config/mips/mips.md| 19 +++--
 5 files changed, 61 insertions(+), 11 deletions(-)

diff --git a/gcc/config/mips/mips-modes.def b/gcc/config/mips/mips-modes.def
index 323570928fcd..21f50a225469 100644
--- a/gcc/config/mips/mips-modes.def
+++ b/gcc/config/mips/mips-modes.def
@@ -54,4 +54,5 @@ ADJUST_ALIGNMENT (CCV4, 16);
 CC_MODE (CCDSP);
 
 /* For floating point conditions in FP registers.  */
+CC_MODE (CCE);
 CC_MODE (CCF);
diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index 835f42128b91..fcc0a0ae663f 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -394,4 +394,6 @@ extern bool mips_bit_clear_p (enum machine_mode, unsigned 
HOST_WIDE_INT);
 extern void mips_bit_clear_info (enum machine_mode, unsigned HOST_WIDE_INT,
  int *, int *);
 
+extern const char *mips_output_compare (const char *fpcmp, const char *fcond,
+   const char *fmt, const char *fpcc_mode, bool swap);
 #endif /* ! GCC_MIPS_PROTOS_H */
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 278d94464826..b7acf0419035 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -5659,7 +5659,7 @@ mips_allocate_fcc (machine_mode mode)
 
   gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
 
-  if (mode == CCmode)
+  if (mode == CCmode || mode == CCEmode)
 count = 1;
   else if (mode == CCV2mode)
 count = 2;
@@ -5788,17 +5788,57 @@ mips_emit_compare (enum rtx_code *code, rtx *op0, rtx 
*op1, bool need_eq_ne_p)
  /* Three FP conditions cannot be implemented by reversing the
 operands for C.cond.fmt, instead a reversed condition code is
 required and a test for false.  */
+ machine_mode ccmode = CCmode;
+ switch (*code)
+   {
+   case LTGT:
+   case LT:
+   case LE:
+ ccmode = CCEmode;
+ break;
+   default:
+ break;
+   }
  *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
  if (ISA_HAS_8CC)
-   *op0 = mips_allocate_fcc (CCmode);
+   *op0 = mips_allocate_fcc (ccmode);
  else
-   *op0 = gen_rtx_REG (CCmode, FPSW_REGNUM);
+   *op0 = gen_rtx_REG (ccmode, FPSW_REGNUM);
}
 
   *op1 = const0_rtx;
   mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
 }
 }
+
+
+const char *
+mips_output_compare (const char *fpcmp, const char *fcond,
+   const char *fmt, const char *fpcc_mode, bool swap)
+{
+  const char *fc = fcond;
+
+  if (ISA_HAS_CCF)
+{
+  /* c.lt.fmt is signaling, while cmp.lt.fmt is quiet.  */
+  if (strcmp (fcond, "lt") == 0)
+   fc = "slt";
+  else if (strcmp (fcond

[gcc r15-1231] MIPS: Use FPU-enabled tune for mips32/mips64/mips64r2/mips64r3/mips64r5

[YunQiang Su via Gcc-cvs]

https://gcc.gnu.org/g:f10896c8e5fe34e51ea61aaa4d4aaedb4677ff13

commit r15-1231-gf10896c8e5fe34e51ea61aaa4d4aaedb4677ff13
Author: YunQiang Su 
Date:   Mon Jun 10 14:31:12 2024 +0800

MIPS: Use FPU-enabled tune for mips32/mips64/mips64r2/mips64r3/mips64r5

Currently, the default tune value of mips32 is PROCESSOR_4KC, and
the default tune value of mips64/mips64r2/mips64r3/mips64r5 is
PROCESSOR_5KC.  PROCESSOR_4KC and PROCESSOR_5KC are both FPU-less.

Let's use PROCESSOR_24KF1_1 for mips32, and PROCESSOR_5KF for mips64/
mips64r2/mips64r3/mips64r5.

We find this problem when we try to fix gcc.target/mips/movcc-3.c.

gcc:
* config/mips/mips-cpus.def: Use PROCESSOR_24KF1_1 for mips32;
Use PROCESSOR_5KF for mips64/mips64r2/mips64r3/mips64r5.

Diff:
---
 gcc/config/mips/mips-cpus.def | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
index 490195406e78..17bbba42bd62 100644
--- a/gcc/config/mips/mips-cpus.def
+++ b/gcc/config/mips/mips-cpus.def
@@ -42,17 +42,17 @@ MIPS_CPU ("mips4", PROCESSOR_R1, MIPS_ISA_MIPS4, 
PTF_AVOID_BRANCHLIKELY_SIZE
in revisions 2 and earlier, but revision 3 is likely to downgrade
that to a recommendation to avoid the instructions in code that
isn't tuned to a specific processor.  */
-MIPS_CPU ("mips32", PROCESSOR_4KC, MIPS_ISA_MIPS32, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
+MIPS_CPU ("mips32", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
 MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, MIPS_ISA_MIPS32R2, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
 /* mips32r3 is micromips hense why it uses the M4K processor.  */
 MIPS_CPU ("mips32r3", PROCESSOR_M4K, MIPS_ISA_MIPS32R3, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
 MIPS_CPU ("mips32r5", PROCESSOR_P5600, MIPS_ISA_MIPS32R5, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
 MIPS_CPU ("mips32r6", PROCESSOR_I6400, MIPS_ISA_MIPS32R6, 0)
-MIPS_CPU ("mips64", PROCESSOR_5KC, MIPS_ISA_MIPS64, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
+MIPS_CPU ("mips64", PROCESSOR_5KF, MIPS_ISA_MIPS64, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
 /* ??? For now just tune the generic MIPS64r2 and above for 5KC as well.   */
-MIPS_CPU ("mips64r2", PROCESSOR_5KC, MIPS_ISA_MIPS64R2, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
-MIPS_CPU ("mips64r3", PROCESSOR_5KC, MIPS_ISA_MIPS64R3, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
-MIPS_CPU ("mips64r5", PROCESSOR_5KC, MIPS_ISA_MIPS64R5, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
+MIPS_CPU ("mips64r2", PROCESSOR_5KF, MIPS_ISA_MIPS64R2, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
+MIPS_CPU ("mips64r3", PROCESSOR_5KF, MIPS_ISA_MIPS64R3, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
+MIPS_CPU ("mips64r5", PROCESSOR_5KF, MIPS_ISA_MIPS64R5, 
PTF_AVOID_BRANCHLIKELY_ALWAYS)
 MIPS_CPU ("mips64r6", PROCESSOR_I6400, MIPS_ISA_MIPS64R6, 0)
 
 /* MIPS I processors.  */

[gcc r15-1232] rs6000: Fix pr66144-3.c test to accept multiple equivalent insns. [PR115262]

[Peter Bergner via Gcc-cvs]

https://gcc.gnu.org/g:ae8103a3a13ac412b9ca33222594cb507ceac9f7

commit r15-1232-gae8103a3a13ac412b9ca33222594cb507ceac9f7
Author: Peter Bergner 
Date:   Wed Jun 12 21:05:34 2024 -0500

rs6000: Fix pr66144-3.c test to accept multiple equivalent insns. [PR115262]

Jeff's commit r15-831-g05daf617ea22e1 changed the instruction we expected
for this test case into an equivalent instruction.  Modify the test case
so it will accept any of three instructions we could get depending on the
options used.

2024-06-12  Peter Bergner  

gcc/testsuite/
PR testsuite/115262
* gcc.target/powerpc/pr66144-3.c (dg-do): Compile for all targets.
(dg-options): Add -fno-unroll-loops and remove -mvsx.
(scan-assembler): Change from this...
(scan-assembler-times): ...to this.  Tweak regex to accept multiple
allowable instructions.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/pr66144-3.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/pr66144-3.c 
b/gcc/testsuite/gcc.target/powerpc/pr66144-3.c
index 4c93b2a7a3da..14ecb809edc2 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr66144-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr66144-3.c
@@ -1,5 +1,5 @@
-/* { dg-do compile { target { powerpc64*-*-* } } } */
-/* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize" } */
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2 -ftree-vectorize -fno-unroll-loops" 
} */
 /* { dg-require-effective-target powerpc_vsx } */
 
 /* Verify that we can optimize a vector conditional move, where one of the arms
@@ -20,7 +20,7 @@ test (void)
 a[i] = (b[i] == c[i]) ? -1 : a[i];
 }
 
-/* { dg-final { scan-assembler {\mvcmpequw\M} } } */
-/* { dg-final { scan-assembler {\mxxsel\M}} } */
+/* { dg-final { scan-assembler-times {\mvcmpequw\M} 1 } } */
+/* { dg-final { scan-assembler-times {\m(?:xxsel|xxlor|vor)\M} 1 } } */
 /* { dg-final { scan-assembler-not {\mvspltisw\M} } } */
 /* { dg-final { scan-assembler-not {\mxxlorc\M}   } } */

[gcc r15-1233] Test: Move target independent test cases to gcc.dg/torture

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:b6eda6b61c52aa005bb07465969d2ef089eb28e6

commit r15-1233-gb6eda6b61c52aa005bb07465969d2ef089eb28e6
Author: Pan Li 
Date:   Tue Jun 11 10:56:23 2024 +0800

Test: Move target independent test cases to gcc.dg/torture

The test cases of pr115387 are target independent,  at least x86
and riscv are able to reproduce.  Thus,  move these cases to
the gcc.dg/torture.

The below test suites are passed.
1. The rv64gcv fully regression test.
2. The x86 fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr115387-1.c: Move to...
* gcc.dg/torture/pr115387-1.c: ...here.
* gcc.target/riscv/pr115387-2.c: Move to...
* gcc.dg/torture/pr115387-2.c: ...here.

Signed-off-by: Pan Li 

Diff:
---
 gcc/testsuite/{gcc.target/riscv => gcc.dg/torture}/pr115387-1.c | 1 -
 gcc/testsuite/{gcc.target/riscv => gcc.dg/torture}/pr115387-2.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/pr115387-1.c 
b/gcc/testsuite/gcc.dg/torture/pr115387-1.c
similarity index 92%
rename from gcc/testsuite/gcc.target/riscv/pr115387-1.c
rename to gcc/testsuite/gcc.dg/torture/pr115387-1.c
index a1c926977c42..d94e935fadec 100644
--- a/gcc/testsuite/gcc.target/riscv/pr115387-1.c
+++ b/gcc/testsuite/gcc.dg/torture/pr115387-1.c
@@ -1,6 +1,5 @@
 /* Test there is no ICE when compile.  */
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
 
 #define PRINTF_CHK 0x34
 
diff --git a/gcc/testsuite/gcc.target/riscv/pr115387-2.c 
b/gcc/testsuite/gcc.dg/torture/pr115387-2.c
similarity index 84%
rename from gcc/testsuite/gcc.target/riscv/pr115387-2.c
rename to gcc/testsuite/gcc.dg/torture/pr115387-2.c
index 7183bf18dfd5..9e93024b45ce 100644
--- a/gcc/testsuite/gcc.target/riscv/pr115387-2.c
+++ b/gcc/testsuite/gcc.dg/torture/pr115387-2.c
@@ -1,6 +1,5 @@
 /* Test there is no ICE when compile.  */
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
 
 #include 
 #include 

[gcc/aoliva/heads/testbase] (129 commits) [libstdc++] [testsuite] require cmath for c++23 cmath tests

[Alexandre Oliva via Gcc-cvs]

The branch 'aoliva/heads/testbase' was updated to point to:

 5288935d30c4... [libstdc++] [testsuite] require cmath for c++23 cmath tests

It previously pointed to:

 dd6f942c2665... Fix fold-left reduction vectorization with multiple stmt co

Diff:

Summary of changes (added commits):
---

  5288935... [libstdc++] [testsuite] require cmath for c++23 cmath tests (*)
  6c3b01d... [libstdc++] [testsuite] xfail double-prec from_chars for fl (*)
  074c1fc... c++: repeated export using (*)
  f8356d6... c++: module std and exception_ptr (*)
  7bf072e... c++: fix testcase diagnostics (*)
  eaff4d6... Whitespace cleanup for target-supports.exp (*)
  e35f4ea... pretty_printer: unbreak build on aarch64 [PR115465] (*)
  439c0cc... RISC-V: Allow any temp register to be used in amo tests (*)
  6343adc... RISC-V: Fix amoadd call arguments (*)
  8c944f2... RISC-V: Move amo tests into subfolder (*)
  c2f0aaf... aarch64: Use bitreverse rtl code instead of unspec [PR11517 (*)
  0256121... match: Improve gimple_bitwise_equal_p and gimple_bitwise_in (*)
  bd6bc35... Move cexpr_stree tree string build into utility function (*)
  bd3a312... libstdc++: Fix std::tr2::dynamic_bitset shift operations [P (*)
  3f2f905... libstdc++: Do not use memset in _Hashtable::clear() (*)
  adcc815... middle-end: Drop __builtin_prefetch calls in autovectorizat (*)
  1cae1a5... pretty_printer: convert chunk_info into a class (*)
  c5e3be4... pretty_printer: make all fields private (*)
  fc47393... pretty_printer: rename instances named "buffer" to "pp" (*)
  d0da347... LoongArch: Use bstrins for "value & (-1u << const)" (*)
  53c7038... LoongArch: Fix mode size comparision in loongarch_expand_co (*)
  7663154... Libatomic: Clean up AArch64 `atomic_16.S' implementation fi (*)
  1af4a84... Libatomic: Make ifunc selector behavior contingent on impor (*)
  6edf6fe... Libatomic: Define per-file identifier macros (*)
  f6b9a06... Libatomic: AArch64: Convert all lse128 assembly to .insn di (*)
  cf5f917... testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115 (*)
  65bd065... arm: Zero/Sign extends for CMSE security on Armv8-M.baselin (*)
  2d6874a... doc: Update Cygwin web link (*)
  acd2ca1... Widening-Mul: Take gsi after_labels instead of start_bb for (*)
  919e88f... doc: Simplify *-*-linux-gnu dependencies (*)
  66f4855... [tree-prof] skip if errors were seen [PR113681] (*)
  89a746f... [testsuite] [arm] test board cflags in multilib.exp (*)
  ea5c9f2... map packed field type to unpacked for debug info (*)
  da57b45... [libstdc++] drop workaround for clang<=7 (*)
  7fa4b33... Daily bump. (*)
  1d496d2... Fix ICE in rtl check due to CONST_WIDE_INT in CONST_VECTOR_ (*)
  0cf6822... c: Add -std=c2y, -std=gnu2y, -Wc23-c2y-compat, C2Y _Generic (*)
  6bc26cc... doc: Remove redundant introduction of x86-64 (*)
  e4244b8... Fix building JIT with musl libc [PR115442] (*)
  2b438a0... vect: Merge loop mask and cond_op mask in fold-left reducti (*)
  1588983... RISC-V: Add Zalrsc amo-op patterns (*)
  0fea902... RISC-V: Add Zalrsc and Zaamo testsuite support (*)
  af139b3... RISC-V: Add basic Zaamo and Zalrsc support (*)
  05b9523... i386: Use CMOV in .SAT_{ADD|SUB} expansion for TARGET_CMOV  (*)
  e7cd8ea... aarch64: Add vector floating point trunc pattern (*)
  53ac88c... C++: Support constexpr strings for asm statements (*)
  6ef8c90... Factor out static_assert constexpr string extraction for re (*)
  2f0c09c... scev query mismatch message (*)
  84c87d1... libstdc++: Add test for chrono::leap_seconds ostream insert (*)
  75299e4... rust: Do not link with libdl and libpthread unconditionally (*)
  a0004fe... PR modula2/114529 Avoid ODR violations in bootstrap transla (*)
  a797398... i386: PR target/115397: AVX512 ternlog vs. -m32 -fPIC const (*)
  8087204... RISC-V: Implement .SAT_SUB for unsigned vector int (*)
  66d6b18... fixincludes: bypass the math_exception fix on __cplusplus (*)
  95161c6... [committed] [RISC-V] Drop dead round_32 test (*)
  097bc0a... Daily bump. (*)
  ec08656... modula2: Fix typos, grammar, and a link (*)
  74ee12f... Move array_bounds warnings into a separate pass. (*)
  9aaf29b... [to-be-committed] [RISC-V] Use bext for extracting a bit in (*)
  d03ff3f... [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for (*)
  6ef8881... libstdc++: [_Hashtable] Optimize destructor (*)
  c3d1153... Fix pr115388.c: plain char could be unsigned by default [PR (*)
  3472c1b... [to-be-committed] [RISC-V] Use bext for extracting a bit in (*)
  818e760... tree-optimization/115388 - wrong DSE in irreductible region (*)
  e29af8d... Add testcase for PR ada/114708 (*)
  e1c1f12... Add testcase for PR ada/114398 (*)
  4ed9c5d... tree-optimization/115395 - wrong-code with SLP reduction in (*)
  6272444... ada: Add support for No_Implicit_Conditionals to nonbinary  (*)
  add6d89... ada: Storage_Error in indirect call to function returning l (*)
  f5e372e... ada: Derived type with convention C must override con

[gcc/aoliva/heads/testme] (130 commits) [i386] restore recompute to override opts after change [PR1

[Alexandre Oliva via Gcc-cvs]

The branch 'aoliva/heads/testme' was updated to point to:

 e75f9b7a5974... [i386] restore recompute to override opts after change [PR1

It previously pointed to:

 606e815b8427... [testsuite] add linkonly to dg-additional-sources [PR115295

Diff:

!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
---

  606e815... [testsuite] add linkonly to dg-additional-sources [PR115295
  4f96af2... map packed field type to unpacked for debug info
  bed2675... [libstdc++] [testsuite] require cmath for c++23 cmath tests
  1c784e7... [libstdc++] [testsuite] xfail double-prec from_chars for fl


Summary of changes (added commits):
---

  e75f9b7... [i386] restore recompute to override opts after change [PR1
  aa6f08f... [libstdc++] [testsuite] require cmath for [PR114359]
  5288935... [libstdc++] [testsuite] require cmath for c++23 cmath tests (*)
  6c3b01d... [libstdc++] [testsuite] xfail double-prec from_chars for fl (*)
  074c1fc... c++: repeated export using (*)
  f8356d6... c++: module std and exception_ptr (*)
  7bf072e... c++: fix testcase diagnostics (*)
  eaff4d6... Whitespace cleanup for target-supports.exp (*)
  e35f4ea... pretty_printer: unbreak build on aarch64 [PR115465] (*)
  439c0cc... RISC-V: Allow any temp register to be used in amo tests (*)
  6343adc... RISC-V: Fix amoadd call arguments (*)
  8c944f2... RISC-V: Move amo tests into subfolder (*)
  c2f0aaf... aarch64: Use bitreverse rtl code instead of unspec [PR11517 (*)
  0256121... match: Improve gimple_bitwise_equal_p and gimple_bitwise_in (*)
  bd6bc35... Move cexpr_stree tree string build into utility function (*)
  bd3a312... libstdc++: Fix std::tr2::dynamic_bitset shift operations [P (*)
  3f2f905... libstdc++: Do not use memset in _Hashtable::clear() (*)
  adcc815... middle-end: Drop __builtin_prefetch calls in autovectorizat (*)
  1cae1a5... pretty_printer: convert chunk_info into a class (*)
  c5e3be4... pretty_printer: make all fields private (*)
  fc47393... pretty_printer: rename instances named "buffer" to "pp" (*)
  d0da347... LoongArch: Use bstrins for "value & (-1u << const)" (*)
  53c7038... LoongArch: Fix mode size comparision in loongarch_expand_co (*)
  7663154... Libatomic: Clean up AArch64 `atomic_16.S' implementation fi (*)
  1af4a84... Libatomic: Make ifunc selector behavior contingent on impor (*)
  6edf6fe... Libatomic: Define per-file identifier macros (*)
  f6b9a06... Libatomic: AArch64: Convert all lse128 assembly to .insn di (*)
  cf5f917... testsuite: Fix expand-return CMSE test for Armv8.1-M [PR115 (*)
  65bd065... arm: Zero/Sign extends for CMSE security on Armv8-M.baselin (*)
  2d6874a... doc: Update Cygwin web link (*)
  acd2ca1... Widening-Mul: Take gsi after_labels instead of start_bb for (*)
  919e88f... doc: Simplify *-*-linux-gnu dependencies (*)
  66f4855... [tree-prof] skip if errors were seen [PR113681] (*)
  89a746f... [testsuite] [arm] test board cflags in multilib.exp (*)
  ea5c9f2... map packed field type to unpacked for debug info (*)
  da57b45... [libstdc++] drop workaround for clang<=7 (*)
  7fa4b33... Daily bump. (*)
  1d496d2... Fix ICE in rtl check due to CONST_WIDE_INT in CONST_VECTOR_ (*)
  0cf6822... c: Add -std=c2y, -std=gnu2y, -Wc23-c2y-compat, C2Y _Generic (*)
  6bc26cc... doc: Remove redundant introduction of x86-64 (*)
  e4244b8... Fix building JIT with musl libc [PR115442] (*)
  2b438a0... vect: Merge loop mask and cond_op mask in fold-left reducti (*)
  1588983... RISC-V: Add Zalrsc amo-op patterns (*)
  0fea902... RISC-V: Add Zalrsc and Zaamo testsuite support (*)
  af139b3... RISC-V: Add basic Zaamo and Zalrsc support (*)
  05b9523... i386: Use CMOV in .SAT_{ADD|SUB} expansion for TARGET_CMOV  (*)
  e7cd8ea... aarch64: Add vector floating point trunc pattern (*)
  53ac88c... C++: Support constexpr strings for asm statements (*)
  6ef8c90... Factor out static_assert constexpr string extraction for re (*)
  2f0c09c... scev query mismatch message (*)
  84c87d1... libstdc++: Add test for chrono::leap_seconds ostream insert (*)
  75299e4... rust: Do not link with libdl and libpthread unconditionally (*)
  a0004fe... PR modula2/114529 Avoid ODR violations in bootstrap transla (*)
  a797398... i386: PR target/115397: AVX512 ternlog vs. -m32 -fPIC const (*)
  8087204... RISC-V: Implement .SAT_SUB for unsigned vector int (*)
  66d6b18... fixincludes: bypass the math_exception fix on __cplusplus (*)
  95161c6... [committed] [RISC-V] Drop dead round_32 test (*)
  097bc0a... Daily bump. (*)
  ec08656... modula2: Fix typos, grammar, and a link (*)
  74ee12f... Move array_bounds warnings into a separate pass. (*)
  9aaf29b... [to-be-committed] [RISC-V] Use bext for extracting a bit in (*)
  d03ff3f... [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for (*)
  6ef8881... libstdc++: [_Hashtable] Optimize destructor (*)
  c3d1153... Fix pr115388.c: plain char could be unsigned by defaul

[gcc(refs/users/aoliva/heads/testme)] [libstdc++] [testsuite] require cmath for [PR114359]

[Alexandre Oliva via Gcc-cvs]

https://gcc.gnu.org/g:aa6f08f66334fdef3d0d33177698be247e1724ad

commit aa6f08f66334fdef3d0d33177698be247e1724ad
Author: Alexandre Oliva 
Date:   Wed Jun 12 21:36:42 2024 -0300

[libstdc++] [testsuite] require cmath for [PR114359]

When !_GLIBCXX_USE_C99_MATH_TR1, binomial_distribution doesn't use the
optimized algorithm that was fixed in response to PR114359.  Without
that optimized algorithm, operator() ends up looping very very long
for the test, to the point that it would time out by several orders of
magnitude, without even exercising the optimized algorithm that we're
testing for regressions.  Arrange for the test to be skipped if that
bit won't be exercised.


for  libstdc++-v3/ChangeLog

PR libstdc++/114359
* testsuite/26_numerics/random/binomial_distribution/114359.cc:
Require cmath.

Diff:
---
 .../26_numerics/random/binomial_distribution/114359.cc  | 13 +
 1 file changed, 13 insertions(+)

diff --git 
a/libstdc++-v3/testsuite/26_numerics/random/binomial_distribution/114359.cc 
b/libstdc++-v3/testsuite/26_numerics/random/binomial_distribution/114359.cc
index c1e4c380bf91..12d967dcbfd3 100644
--- a/libstdc++-v3/testsuite/26_numerics/random/binomial_distribution/114359.cc
+++ b/libstdc++-v3/testsuite/26_numerics/random/binomial_distribution/114359.cc
@@ -2,6 +2,19 @@
 
 // Bug 114359 - std::binomial_distribution hangs in infinite loop
 
+// { dg-require-cmath "" }
+
+// The requirement above is not strictly true.  The test should work
+// without cmath, and it probably does, but without cmath,
+// binomial_distribution::operator() skips the optimized algorithm and
+// calls _M_waiting to loop a gazillion times.  On aarch64-rtems6
+// qemu, that loop takes over 5 minutes to go through a small fraction
+// of the iteration space (__x at 22k, limited at 1G; __sum at 2e-5,
+// limited at 0.69).  The bug we're regression-testing here was in the
+// cmath-requiring bit, so even if this could conceivably not time out
+// on a really fast machine, there's hardly any reason to exercise
+// this extreme case.
+
 #include 
 
 int main()

[gcc(refs/users/aoliva/heads/testme)] [i386] restore recompute to override opts after change [PR113719]

[Alexandre Oliva via Gcc-cvs]

https://gcc.gnu.org/g:e75f9b7a5974b31a0e9722d507e313305a39b207

commit e75f9b7a5974b31a0e9722d507e313305a39b207
Author: Alexandre Oliva 
Date:   Thu Jun 13 00:12:47 2024 -0300

[i386] restore recompute to override opts after change [PR113719]

The first patch for PR113719 regressed gcc.dg/ipa/iinline-attr.c on
toolchains configured to --enable-frame-pointer, because the
optimization node created within handle_optimize_attribute had
flag_omit_frame_pointer incorrectly set, whereas
default_optimization_node didn't.  With this difference,
can_inline_edge_by_limits_p flagged an optimization mismatch and we
refused to inline the function that had a redundant optimization flag
into one that didn't, which is exactly what is tested for there.

This patch restores the calls to ix86_default_align and
ix86_recompute_optlev_based_flags that used to be, and ought to be,
issued during TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE, but preserves the
intent of the original change, of having those functions called at
different spots within ix86_option_override_internal.  To that end,
the remaining bits were refactored into a separate function, that was
in turn adjusted to operate on explicitly-passed opts and opts_set,
rather than going for their global counterparts.


for  gcc/ChangeLog

PR target/113719
* config/i386/i386-options.cc
(ix86_override_options_after_change_1): Add opts and opts_set
parms, operate on them, after factoring out of...
(ix86_override_options_after_change): ... this.  Restore calls
of ix86_default_align and ix86_recompute_optlev_based_flags.
(ix86_option_override_internal): Call the factored-out bits.

Diff:
---
 gcc/config/i386/i386-options.cc | 59 -
 1 file changed, 40 insertions(+), 19 deletions(-)

diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index f2cecc0e2545..7fa7f6774e9c 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -1911,37 +1911,58 @@ ix86_recompute_optlev_based_flags (struct gcc_options 
*opts,
 }
 }
 
-/* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook.  */
+/* Implement part of TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook.  */
 
-void
-ix86_override_options_after_change (void)
+static void
+ix86_override_options_after_change_1 (struct gcc_options *opts,
+ struct gcc_options *opts_set)
 {
+#define OPTS_SET_P(OPTION) opts_set->x_ ## OPTION
+#define OPTS(OPTION) opts->x_ ## OPTION
+
   /* Disable unrolling small loops when there's explicit
  -f{,no}unroll-loop.  */
-  if ((OPTION_SET_P (flag_unroll_loops))
- || (OPTION_SET_P (flag_unroll_all_loops)
-&& flag_unroll_all_loops))
+  if ((OPTS_SET_P (flag_unroll_loops))
+ || (OPTS_SET_P (flag_unroll_all_loops)
+&& OPTS (flag_unroll_all_loops)))
 {
-  if (!OPTION_SET_P (ix86_unroll_only_small_loops))
-   ix86_unroll_only_small_loops = 0;
+  if (!OPTS_SET_P (ix86_unroll_only_small_loops))
+   OPTS (ix86_unroll_only_small_loops) = 0;
   /* Re-enable -frename-registers and -fweb if funroll-loops
 enabled.  */
-  if (!OPTION_SET_P (flag_web))
-   flag_web = flag_unroll_loops;
-  if (!OPTION_SET_P (flag_rename_registers))
-   flag_rename_registers = flag_unroll_loops;
+  if (!OPTS_SET_P (flag_web))
+   OPTS (flag_web) = OPTS (flag_unroll_loops);
+  if (!OPTS_SET_P (flag_rename_registers))
+   OPTS (flag_rename_registers) = OPTS (flag_unroll_loops);
   /* -fcunroll-grow-size default follws -f[no]-unroll-loops.  */
-  if (!OPTION_SET_P (flag_cunroll_grow_size))
-   flag_cunroll_grow_size = flag_unroll_loops
-|| flag_peel_loops
-|| optimize >= 3;
+  if (!OPTS_SET_P (flag_cunroll_grow_size))
+   OPTS (flag_cunroll_grow_size)
+ = (OPTS (flag_unroll_loops)
+|| OPTS (flag_peel_loops)
+|| OPTS (optimize) >= 3);
 }
   else
 {
-  if (!OPTION_SET_P (flag_cunroll_grow_size))
-   flag_cunroll_grow_size = flag_peel_loops || optimize >= 3;
+  if (!OPTS_SET_P (flag_cunroll_grow_size))
+   OPTS (flag_cunroll_grow_size)
+ = (OPTS (flag_peel_loops)
+|| OPTS (optimize) >= 3);
 }
 
+#undef OPTS
+#undef OPTS_SET_P
+}
+
+/* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook.  */
+
+void
+ix86_override_options_after_change (void)
+{
+  ix86_default_align (&global_options);
+
+  ix86_recompute_optlev_based_flags (&global_options, &global_options_set);
+
+  ix86_override_options_after_change_1 (&global_options, &global_options_set);
 }
 
 /* Clear stack slot assignments remembered from previous functions.
@@ -2488,7 +2509,7 @@ ix86_option_override_internal (bool main_args_p,
 
   ix86_recompute_optlev_based

[gcc r15-1234] Fix ICE due to REGNO of a SUBREG.

[hongtao Liu via Gcc-cvs]

https://gcc.gnu.org/g:f8bf80a4e1682b2238baad8c44939682f96b1fe0

commit r15-1234-gf8bf80a4e1682b2238baad8c44939682f96b1fe0
Author: liuhongt 
Date:   Thu Jun 13 09:53:58 2024 +0800

Fix ICE due to REGNO of a SUBREG.

Use reg_or_subregno instead.

gcc/ChangeLog:

PR target/115452
* config/i386/i386-features.cc (scalar_chain::convert_op): Use
reg_or_subregno instead of REGNO to avoid ICE.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr115452.c: New test.

Diff:
---
 gcc/config/i386/i386-features.cc | 2 +-
 gcc/testsuite/gcc.target/i386/pr115452.c | 4 
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc
index e3e004d55267..607d19914606 100644
--- a/gcc/config/i386/i386-features.cc
+++ b/gcc/config/i386/i386-features.cc
@@ -1054,7 +1054,7 @@ scalar_chain::convert_op (rtx *op, rtx_insn *insn)
 
   if (dump_file)
fprintf (dump_file, "  Preloading operand for insn %d into r%d\n",
-INSN_UID (insn), REGNO (tmp));
+INSN_UID (insn), reg_or_subregno (tmp));
 }
   else if (REG_P (*op))
 *op = gen_rtx_SUBREG (vmode, *op, 0);
diff --git a/gcc/testsuite/gcc.target/i386/pr115452.c 
b/gcc/testsuite/gcc.target/i386/pr115452.c
new file mode 100644
index ..6c7935feb9f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr115452.c
@@ -0,0 +1,4 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-O2 -msse2 -mstv -mno-bmi -mno-stackrealign -fdump-rtl-stv2" 
} */
+
+#include "pr70322-2.c"

[gcc r15-1235] Remove const char * support for asm constexpr

[Andi Kleen via Gcc-cvs]

https://gcc.gnu.org/g:6f1f1657cd7a8472b4a4aeef60f1c59606ee011b

commit r15-1235-g6f1f1657cd7a8472b4a4aeef60f1c59606ee011b
Author: Andi Kleen 
Date:   Wed Jun 12 09:09:37 2024 -0700

Remove const char * support for asm constexpr

asm constexpr now only accepts the same string types as C++26 assert,
e.g. string_view and string. Adjust test suite and documentation.

gcc/cp/ChangeLog:

* parser.cc (cp_parser_asm_string_expression): Remove support
for const char * for asm constexpr.

gcc/ChangeLog:

* doc/extend.texi: Use std::string_view in asm constexpr
example.

gcc/testsuite/ChangeLog:

* g++.dg/cpp1z/constexpr-asm-1.C: Use std::std_string_view.
* g++.dg/cpp1z/constexpr-asm-3.C: Dito.

Diff:
---
 gcc/cp/parser.cc |  7 ---
 gcc/doc/extend.texi  |  3 ++-
 gcc/testsuite/g++.dg/cpp1z/constexpr-asm-1.C | 12 +++-
 gcc/testsuite/g++.dg/cpp1z/constexpr-asm-3.C | 12 +++-
 4 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc
index de5f0483c120..98e8ca10ac40 100644
--- a/gcc/cp/parser.cc
+++ b/gcc/cp/parser.cc
@@ -22852,13 +22852,6 @@ cp_parser_asm_string_expression (cp_parser *parser)
   tree string = cp_parser_constant_expression (parser);
   if (string != error_mark_node)
string = cxx_constant_value (string, tf_error);
-  if (TREE_CODE (string) == NOP_EXPR)
-   string = TREE_OPERAND (string, 0);
-  if (TREE_CODE (string) == ADDR_EXPR
- && TREE_CODE (TREE_OPERAND (string, 0)) == STRING_CST)
-   string = TREE_OPERAND (string, 0);
-  if (TREE_CODE (string) == VIEW_CONVERT_EXPR)
-   string = TREE_OPERAND (string, 0);
   cexpr_str cstr (string);
   if (!cstr.type_check (tok->location))
return error_mark_node;
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 17e26c5004c1..ee3644a52645 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -10716,7 +10716,8 @@ message. Any string is converted to the character set 
of the source code.
 When this feature is available the @code{__GXX_CONSTEXPR_ASM__} cpp symbol is 
defined.
 
 @example
-constexpr const char *genfoo() @{ return "foo"; @}
+#include 
+constexpr std::string_view genfoo() @{ return "foo"; @}
 
 void function()
 @{
diff --git a/gcc/testsuite/g++.dg/cpp1z/constexpr-asm-1.C 
b/gcc/testsuite/g++.dg/cpp1z/constexpr-asm-1.C
index 7cc6b37d6208..311209acb43b 100644
--- a/gcc/testsuite/g++.dg/cpp1z/constexpr-asm-1.C
+++ b/gcc/testsuite/g++.dg/cpp1z/constexpr-asm-1.C
@@ -1,22 +1,24 @@
 /* { dg-do compile } */
-/* { dg-options "-std=gnu++11" } */
+/* { dg-options "-std=gnu++17" } */
 
-constexpr const char *genfoo ()
+#include 
+
+constexpr std::string_view genfoo ()
 {
   return "foo %1,%0";
 }
 
-constexpr const char *genoutput ()
+constexpr std::string_view genoutput ()
 {
   return "=r";
 }
 
-constexpr const char *geninput ()
+constexpr std::string_view geninput ()
 {
   return "r";
 }
 
-constexpr const char *genclobber ()
+constexpr std::string_view genclobber ()
 {
   return "memory";
 }
diff --git a/gcc/testsuite/g++.dg/cpp1z/constexpr-asm-3.C 
b/gcc/testsuite/g++.dg/cpp1z/constexpr-asm-3.C
index d33631876bdc..ef8a35a0b3ba 100644
--- a/gcc/testsuite/g++.dg/cpp1z/constexpr-asm-3.C
+++ b/gcc/testsuite/g++.dg/cpp1z/constexpr-asm-3.C
@@ -1,22 +1,24 @@
 /* { dg-do compile } */
-/* { dg-options "-std=gnu++11" } */
+/* { dg-options "-std=gnu++17" } */
 
-constexpr const char *genfoo ()
+#include 
+
+constexpr std::string_view genfoo ()
 {
   return "foo %1,%0";
 }
 
-constexpr const char *genoutput ()
+constexpr std::string_view genoutput ()
 {
   return "=r";
 }
 
-constexpr const char *geninput ()
+constexpr std::string_view geninput ()
 {
   return "r";
 }
 
-constexpr const char *genclobber ()
+constexpr std::string_view genclobber ()
 {
   return "memory";
 }

[gcc r15-1236] Parse close paren even when constexpr extraction fails

[Andi Kleen via Gcc-cvs]

https://gcc.gnu.org/g:d0379809a45f77d2dedb93a443aa1dd96d13c6e5

commit r15-1236-gd0379809a45f77d2dedb93a443aa1dd96d13c6e5
Author: Andi Kleen 
Date:   Wed Jun 12 09:11:46 2024 -0700

Parse close paren even when constexpr extraction fails

To get better error recovery.

gcc/cp/ChangeLog:

* parser.cc (cp_parser_asm_string_expression): Parse close
parent when constexpr extraction fails.

Diff:
---
 gcc/cp/parser.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc
index 98e8ca10ac40..adc4e6fc1aee 100644
--- a/gcc/cp/parser.cc
+++ b/gcc/cp/parser.cc
@@ -22856,7 +22856,7 @@ cp_parser_asm_string_expression (cp_parser *parser)
   if (!cstr.type_check (tok->location))
return error_mark_node;
   if (!cstr.extract (tok->location, string))
-   return error_mark_node;
+   string = error_mark_node;
   parens.require_close (parser);
   return string;
 }

[gcc r15-1237] Fix error message

[Andi Kleen via Gcc-cvs]

https://gcc.gnu.org/g:64cd70e315ed2cf0653cfdde96ae80c3f90a07f4

commit r15-1237-g64cd70e315ed2cf0653cfdde96ae80c3f90a07f4
Author: Andi Kleen 
Date:   Wed Jun 12 09:15:47 2024 -0700

Fix error message

gcc/cp/ChangeLog:

* parser.cc (cp_parser_asm_string_expression): Use correct error
message.

gcc/testsuite/ChangeLog:

* g++.dg/cpp1z/constexpr-asm-3.C: Adjust for new message.

Diff:
---
 gcc/cp/parser.cc | 2 +-
 gcc/testsuite/g++.dg/cpp1z/constexpr-asm-3.C | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/cp/parser.cc b/gcc/cp/parser.cc
index adc4e6fc1aee..01a19080d6c7 100644
--- a/gcc/cp/parser.cc
+++ b/gcc/cp/parser.cc
@@ -22863,7 +22863,7 @@ cp_parser_asm_string_expression (cp_parser *parser)
   else if (!cp_parser_is_string_literal (tok))
 {
   error_at (tok->location,
-   "expected string-literal or constexpr in brackets");
+   "expected string-literal or constexpr in parentheses");
   return error_mark_node;
 }
   return cp_parser_string_literal (parser, false, false);
diff --git a/gcc/testsuite/g++.dg/cpp1z/constexpr-asm-3.C 
b/gcc/testsuite/g++.dg/cpp1z/constexpr-asm-3.C
index ef8a35a0b3ba..0cf8940e109c 100644
--- a/gcc/testsuite/g++.dg/cpp1z/constexpr-asm-3.C
+++ b/gcc/testsuite/g++.dg/cpp1z/constexpr-asm-3.C
@@ -26,7 +26,7 @@ constexpr std::string_view genclobber ()
 void f()
 {
   int a;
-  asm(genfoo () : /* { dg-error "expected string-literal or constexpr in 
brackets" } */
+  asm(genfoo () : /* { dg-error "expected string-literal or constexpr in 
parentheses" } */
   genoutput() (a) :
   geninput() (1) :
   genclobber());

[gcc r15-1238] tree-optimization/114107 - avoid peeling for gaps in more cases

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:1fe55a1794863b5ad9eeca5062782834716016b2

commit r15-1238-g1fe55a1794863b5ad9eeca5062782834716016b2
Author: Richard Biener 
Date:   Fri Jun 7 11:29:05 2024 +0200

tree-optimization/114107 - avoid peeling for gaps in more cases

The following refactors the code to detect necessary peeling for
gaps, in particular the PR103116 case when there is no gap but
the group size is smaller than the vector size.  The testcase in
PR114107 shows we fail to SLP

  for (int i=0; i

[gcc r15-1239] tree-optimization/115385 - handle more gaps with peeling of a single iteration

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:6669dc51515313dd1e60c493596dbc90429fc362

commit r15-1239-g6669dc51515313dd1e60c493596dbc90429fc362
Author: Richard Biener 
Date:   Fri Jun 7 14:47:12 2024 +0200

tree-optimization/115385 - handle more gaps with peeling of a single 
iteration

The following makes peeling of a single scalar iteration handle more
gaps, including non-power-of-two cases.  This can be done by rounding
up the remaining access to the next power-of-two which ensures that
the next scalar iteration will pick at least the number of excess
elements we access.

I've added a correctness testcase and one x86 specific scanning for
the optimization.

PR tree-optimization/115385
* tree-vect-stmts.cc (get_group_load_store_type): Peeling
of a single scalar iteration is sufficient if we can narrow
the access to the next power of two of the bits in the last
access.
(vectorizable_load): Ensure that the last access is narrowed.

* gcc.dg/vect/pr115385.c: New testcase.
* gcc.target/i386/vect-pr115385.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.dg/vect/pr115385.c  | 88 +++
 gcc/testsuite/gcc.target/i386/vect-pr115385.c | 53 
 gcc/tree-vect-stmts.cc| 44 --
 3 files changed, 180 insertions(+), 5 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/pr115385.c 
b/gcc/testsuite/gcc.dg/vect/pr115385.c
new file mode 100644
index ..a18cd665d7d0
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/pr115385.c
@@ -0,0 +1,88 @@
+/* { dg-require-effective-target mmap } */
+
+#include 
+#include 
+
+#define COUNT 511
+#define MMAP_SIZE 0x2
+#define ADDRESS 0x112200
+#define TYPE unsigned char
+
+#ifndef MAP_ANONYMOUS
+#define MAP_ANONYMOUS MAP_ANON
+#endif
+
+void __attribute__((noipa)) foo(TYPE * __restrict x,
+TYPE *y, int n)
+{
+  for (int i = 0; i < n; ++i)
+{
+  x[16*i+0] = y[3*i+0];
+  x[16*i+1] = y[3*i+1];
+  x[16*i+2] = y[3*i+2];
+  x[16*i+3] = y[3*i+0];
+  x[16*i+4] = y[3*i+1];
+  x[16*i+5] = y[3*i+2];
+  x[16*i+6] = y[3*i+0];
+  x[16*i+7] = y[3*i+1];
+  x[16*i+8] = y[3*i+2];
+  x[16*i+9] = y[3*i+0];
+  x[16*i+10] = y[3*i+1];
+  x[16*i+11] = y[3*i+2];
+  x[16*i+12] = y[3*i+0];
+  x[16*i+13] = y[3*i+1];
+  x[16*i+14] = y[3*i+2];
+  x[16*i+15] = y[3*i+0];
+}
+}
+
+void __attribute__((noipa)) bar(TYPE * __restrict x,
+TYPE *y, int n)
+{
+  for (int i = 0; i < n; ++i)
+{
+  x[16*i+0] = y[5*i+0];
+  x[16*i+1] = y[5*i+1];
+  x[16*i+2] = y[5*i+2];
+  x[16*i+3] = y[5*i+3];
+  x[16*i+4] = y[5*i+4];
+  x[16*i+5] = y[5*i+0];
+  x[16*i+6] = y[5*i+1];
+  x[16*i+7] = y[5*i+2];
+  x[16*i+8] = y[5*i+3];
+  x[16*i+9] = y[5*i+4];
+  x[16*i+10] = y[5*i+0];
+  x[16*i+11] = y[5*i+1];
+  x[16*i+12] = y[5*i+2];
+  x[16*i+13] = y[5*i+3];
+  x[16*i+14] = y[5*i+4];
+  x[16*i+15] = y[5*i+0];
+}
+}
+
+TYPE x[COUNT * 16];
+
+int
+main (void)
+{
+  void *y;
+  TYPE *end_y;
+
+  y = mmap ((void *) ADDRESS, MMAP_SIZE, PROT_READ | PROT_WRITE,
+MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+  if (y == MAP_FAILED)
+{
+  perror ("mmap");
+  return 1;
+}
+
+  end_y = (TYPE *) ((char *) y + MMAP_SIZE);
+
+  foo (x, end_y - COUNT * 3, COUNT);
+  bar (x, end_y - COUNT * 5, COUNT);
+
+  return 0;
+}
+
+/* We always require a scalar epilogue here but we don't know which
+   targets support vector composition this way.  */
diff --git a/gcc/testsuite/gcc.target/i386/vect-pr115385.c 
b/gcc/testsuite/gcc.target/i386/vect-pr115385.c
new file mode 100644
index ..a6be9ce4e543
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-pr115385.c
@@ -0,0 +1,53 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -msse4.1 -mno-avx -fdump-tree-vect-details" } */
+
+void __attribute__((noipa)) foo(unsigned char * __restrict x,
+unsigned char *y, int n)
+{
+  for (int i = 0; i < n; ++i)
+{
+  x[16*i+0] = y[3*i+0];
+  x[16*i+1] = y[3*i+1];
+  x[16*i+2] = y[3*i+2];
+  x[16*i+3] = y[3*i+0];
+  x[16*i+4] = y[3*i+1];
+  x[16*i+5] = y[3*i+2];
+  x[16*i+6] = y[3*i+0];
+  x[16*i+7] = y[3*i+1];
+  x[16*i+8] = y[3*i+2];
+  x[16*i+9] = y[3*i+0];
+  x[16*i+10] = y[3*i+1];
+  x[16*i+11] = y[3*i+2];
+  x[16*i+12] = y[3*i+0];
+  x[16*i+13] = y[3*i+1];
+  x[16*i+14] = y[3*i+2];
+  x[16*i+15] = y[3*i+0];
+}
+}
+
+void __attribute__((noipa)) bar(unsigned char * __restrict x,
+unsigned char *y, int n)
+{
+  for (int i = 0; i < n; ++i)
+{
+  x[16*i+0] = y[5*i+0];
+  x[16*i+1] = y[5*i+1];
+  x[16*i+2] = y[5*i+2];
+  x[16*i+3] = y[5*i+3];
+  x[16*i+4] = y[5*i+4];
+  x[16*i+5] = y[5*i

[gcc r15-1240] Improve code generation of strided SLP loads

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:e8f4d525cb320ff11dd95b985d8043fef0510878

commit r15-1240-ge8f4d525cb320ff11dd95b985d8043fef0510878
Author: Richard Biener 
Date:   Mon Jun 10 15:31:35 2024 +0200

Improve code generation of strided SLP loads

This avoids falling back to elementwise accesses for strided SLP
loads when the group size is not a multiple of the vector element
size.  Instead we can use a smaller vector or integer type for the load.

For stores we can do the same though restrictions on stores we handle
and the fact that store-merging covers up makes this mostly effective
for cost modeling which shows for gcc.target/i386/vect-strided-3.c
which we now vectorize with V4SI vectors rather than just V2SI ones.

For all of this there's still the opportunity to use non-uniform
accesses, say for a 6-element group with a VF of two do
V4SI, { V2SI, V2SI }, V4SI.  But that's for a possible followup.

* tree-vect-stmts.cc (get_group_load_store_type): Consistently
use VMAT_STRIDED_SLP for strided SLP accesses and not
VMAT_ELEMENTWISE.
(vectorizable_store): Adjust VMAT_STRIDED_SLP handling to
allow not only half-size but also smaller accesses.
(vectorizable_load): Likewise.

* gcc.target/i386/vect-strided-1.c: New testcase.
* gcc.target/i386/vect-strided-2.c: Likewise.
* gcc.target/i386/vect-strided-3.c: Likewise.
* gcc.target/i386/vect-strided-4.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/i386/vect-strided-1.c |  24 ++
 gcc/testsuite/gcc.target/i386/vect-strided-2.c |  17 +
 gcc/testsuite/gcc.target/i386/vect-strided-3.c |  20 +
 gcc/testsuite/gcc.target/i386/vect-strided-4.c |  20 +
 gcc/tree-vect-stmts.cc | 100 -
 5 files changed, 127 insertions(+), 54 deletions(-)

diff --git a/gcc/testsuite/gcc.target/i386/vect-strided-1.c 
b/gcc/testsuite/gcc.target/i386/vect-strided-1.c
new file mode 100644
index ..db4a06711f11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-strided-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mno-avx" } */
+
+void foo (int * __restrict a, int *b, int s)
+{
+  for (int i = 0; i < 1024; ++i)
+{
+  a[8*i+0] = b[s*i+0];
+  a[8*i+1] = b[s*i+1];
+  a[8*i+2] = b[s*i+2];
+  a[8*i+3] = b[s*i+3];
+  a[8*i+4] = b[s*i+4];
+  a[8*i+5] = b[s*i+5];
+  a[8*i+6] = b[s*i+4];
+  a[8*i+7] = b[s*i+5];
+}
+}
+
+/* Three two-element loads, two four-element stores.  On ia32 we elide
+   a permute and perform a redundant load.  */
+/* { dg-final { scan-assembler-times "movq" 2 } } */
+/* { dg-final { scan-assembler-times "movhps" 2 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "movhps" 1 { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-times "movups" 2 } } */
diff --git a/gcc/testsuite/gcc.target/i386/vect-strided-2.c 
b/gcc/testsuite/gcc.target/i386/vect-strided-2.c
new file mode 100644
index ..6fd64e28cf0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-strided-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mno-avx" } */
+
+void foo (int * __restrict a, int *b, int s)
+{
+  for (int i = 0; i < 1024; ++i)
+{
+  a[4*i+0] = b[s*i+0];
+  a[4*i+1] = b[s*i+1];
+  a[4*i+2] = b[s*i+0];
+  a[4*i+3] = b[s*i+1];
+}
+}
+
+/* One two-element load, one four-element store.  */
+/* { dg-final { scan-assembler-times "movq" 1 } } */
+/* { dg-final { scan-assembler-times "movups" 1 } } */
diff --git a/gcc/testsuite/gcc.target/i386/vect-strided-3.c 
b/gcc/testsuite/gcc.target/i386/vect-strided-3.c
new file mode 100644
index ..b462701a0b2e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-strided-3.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mno-avx -fno-tree-slp-vectorize" } */
+
+void foo (int * __restrict a, int *b, int s)
+{
+  if (s >= 6)
+for (int i = 0; i < 1024; ++i)
+  {
+   a[s*i+0] = b[4*i+0];
+   a[s*i+1] = b[4*i+1];
+   a[s*i+2] = b[4*i+2];
+   a[s*i+3] = b[4*i+3];
+   a[s*i+4] = b[4*i+0];
+   a[s*i+5] = b[4*i+1];
+  }
+}
+
+/* While the vectorizer generates 6 uint64 stores.  */
+/* { dg-final { scan-assembler-times "movq" 4 } } */
+/* { dg-final { scan-assembler-times "movhps" 2 } } */
diff --git a/gcc/testsuite/gcc.target/i386/vect-strided-4.c 
b/gcc/testsuite/gcc.target/i386/vect-strided-4.c
new file mode 100644
index ..dd922926a2a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-strided-4.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse4.2 -mno-avx -fno-tree-slp-vectorize" } */
+
+void foo (int * __restrict a, int * __restrict b, int *c, int s)
+{
+  if (s >= 2)
+for (int i = 0; i < 1024; ++i)
+  {
+   a[s*i+0] = c[4*i+0];
+   a[s*i+1] = c[4*i+1];
+  

[gcc(refs/users/aoliva/heads/testme)] [alpha] adjust MEM alignment for block move [PR115459]

[Alexandre Oliva via Gcc-cvs]

https://gcc.gnu.org/g:cc291d63cde41bd7d9c159ed679cabc0c34126c9

commit cc291d63cde41bd7d9c159ed679cabc0c34126c9
Author: Alexandre Oliva 
Date:   Thu Jun 13 03:52:17 2024 -0300

[alpha] adjust MEM alignment for block move [PR115459]

Before issuing loads or stores for a block move, adjust the MEM
alignments if analysis of the addresses enabled the inference of
stricter alignment.  This ensures that the MEMs are sufficiently
aligned for the corresponding insns, which avoids trouble in case of
e.g. substitutions into SUBREGs.


for  gcc/ChangeLog

PR target/115459
* config/alpha/alpha.cc (alpha_expand_block_move): Adjust
MEMs to match inferred alignment.

Diff: