[gcc r15-1308] Adjust ix86_rtx_costs for pternlog_operand_p.

[hongtao Liu via Gcc-cvs]

https://gcc.gnu.org/g:d3fae2bea034edb001cd45d1d86c5ceef146899b

commit r15-1308-gd3fae2bea034edb001cd45d1d86c5ceef146899b
Author: liuhongt 
Date:   Tue Jun 11 21:22:42 2024 +0800

Adjust ix86_rtx_costs for pternlog_operand_p.

r15-1100-gec985bc97a0157 improves handling of ternlog instructions,
now GCC can recognize lots of pternlog_operand with different
variants.

The patch adjust rtx_costs for that, so pass_combine can
reasonably generate more optimal vpternlog instructions.

.i.e
for avx512f-vpternlog-3.c, with the patch, 2 vpternlog are combined into 
one.

1532,1533c1526
<   vpternlogd  $168, %zmm1, %zmm0, %zmm2
<   vpternlogd  $0x55, %zmm2, %zmm2, %zmm2

>   vpternlogd  $87, %zmm1, %zmm0, %zmm2
1732,1733c1725,1726
<   vpand   %xmm0, %xmm1, %xmm0
<   vpternlogd  $0x55, %zmm0, %zmm0, %zmm0

>   vpternlogd  $63, %zmm1, %zmm0, %zmm1
>   vmovdqa %xmm1, %xmm0
1804,1805c1797
<   vpternlogd  $188, %zmm2, %zmm0, %zmm1
<   vpternlogd  $0x55, %zmm1, %zmm1, %zmm1

>   vpternlogd  $37, %zmm0, %zmm2, %zmm1

gcc/ChangeLog:

* config/i386/i386.cc (ix86_rtx_costs): Adjust rtx_cost for
pternlog_operand under AVX512, also adjust VEC_DUPLICATE
according since vec_dup:mem can't be that cheap.

gcc/testsuite/ChangeLog:

* gcc.target/i386/avx2-pr98461.c: Scan either notl or
vpternlog.
* gcc.target/i386/avx512f-pr96891-3.c: Also scan for inversed
condition.
* gcc.target/i386/avx512f-vpternlogd-3.c: Adjust vpternlog
number to 673.
* gcc.target/i386/avx512f-vpternlogd-4.c: Ditto.
* gcc.target/i386/avx512f-vpternlogd-5.c: Ditto.
* gcc.target/i386/sse2-v1ti-vne.c: Add -mno-avx512f.

Diff:
---
 gcc/config/i386/i386.cc| 39 +-
 gcc/testsuite/gcc.target/i386/avx2-pr98461.c   |  2 +-
 gcc/testsuite/gcc.target/i386/avx512f-pr96891-3.c  |  2 +-
 .../gcc.target/i386/avx512f-vpternlogd-3.c |  2 +-
 .../gcc.target/i386/avx512f-vpternlogd-4.c |  2 +-
 .../gcc.target/i386/avx512f-vpternlogd-5.c |  2 +-
 gcc/testsuite/gcc.target/i386/sse2-v1ti-vne.c  |  2 +-
 7 files changed, 44 insertions(+), 7 deletions(-)

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index c72f64da983d..d4ccc24be6ec 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -21571,6 +21571,31 @@ ix86_rtx_costs (rtx x, machine_mode mode, int 
outer_code_i, int opno,
 = speed ? ix86_tune_cost : &ix86_size_cost;
   int src_cost;
 
+  /* Handling different vternlog variants.  */
+  if ((GET_MODE_SIZE (mode) == 64
+   ? (TARGET_AVX512F && TARGET_EVEX512)
+   : (TARGET_AVX512VL
+ || (TARGET_AVX512F && TARGET_EVEX512 && !TARGET_PREFER_AVX256)))
+  && GET_MODE_SIZE (mode) >= 16
+  && outer_code_i == SET
+  && ternlog_operand (x, mode))
+{
+  rtx args[3];
+
+  args[0] = NULL_RTX;
+  args[1] = NULL_RTX;
+  args[2] = NULL_RTX;
+  int idx = ix86_ternlog_idx (x, args);
+  gcc_assert (idx >= 0);
+
+  *total = cost->sse_op;
+  for (int i = 0; i != 3; i++)
+   if (args[i])
+ *total += rtx_cost (args[i], GET_MODE (args[i]), UNSPEC, i, speed);
+  return true;
+}
+
+
   switch (code)
 {
 case SET:
@@ -22233,6 +22258,9 @@ ix86_rtx_costs (rtx x, machine_mode mode, int 
outer_code_i, int opno,
   else if (XINT (x, 1) == UNSPEC_VTERNLOG)
{
  *total = cost->sse_op;
+ *total += rtx_cost (XVECEXP (x, 0, 0), mode, code, 0, speed);
+ *total += rtx_cost (XVECEXP (x, 0, 1), mode, code, 1, speed);
+ *total += rtx_cost (XVECEXP (x, 0, 2), mode, code, 2, speed);
  return true;
}
   else if (XINT (x, 1) == UNSPEC_PTEST)
@@ -22260,12 +22288,21 @@ ix86_rtx_costs (rtx x, machine_mode mode, int 
outer_code_i, int opno,
 
 case VEC_SELECT:
 case VEC_CONCAT:
-case VEC_DUPLICATE:
   /* ??? Assume all of these vector manipulation patterns are
 recognizable.  In which case they all pretty much have the
 same cost.  */
  *total = cost->sse_op;
  return true;
+case VEC_DUPLICATE:
+  *total = rtx_cost (XEXP (x, 0),
+GET_MODE (XEXP (x, 0)),
+VEC_DUPLICATE, 0, speed);
+  /* It's broadcast instruction, not embedded broadcasting.  */
+  if (outer_code == SET)
+   *total += cost->sse_op;
+
+ return true;
+
 case VEC_MERGE:
   mask = XEXP (x, 2);
   /* This is masked instruction, assume the same cost,
diff --git a/gcc/testsuite/gcc.target/i386/avx2-pr98461.c 
b/gcc/testsuite/gcc.target/i386/avx2-pr98461.c
index 15f49b864daa..225f2ab00e5f 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-pr9846

[gcc r15-1309] Fix fallout of peeling for gap improvements

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:e575b5c56137b12d402d9fb39291fe20985067b7

commit r15-1309-ge575b5c56137b12d402d9fb39291fe20985067b7
Author: Richard Biener 
Date:   Fri Jun 14 07:54:15 2024 +0200

Fix fallout of peeling for gap improvements

The following hopefully addresses an observed bootstrap issue on aarch64
where maybe-uninit diagnostics occur.  It also fixes bogus napkin math
from myself when I was confusing rounded up size of a single access
with rounded up size of the group accessed in a single scalar iteration.
So the following puts in a correctness check, leaving a set of peeling
for gaps as insufficient.  This could be rectified by splitting the
last load into multiple ones but I'm leaving this for a followup, better
quickly fix the reported wrong-code.

* tree-vect-stmts.cc (get_group_load_store_type): Do not
re-use poly-int remain but re-compute with non-poly values.
Verify the shortened load is good enough to be covered with
a single scalar gap iteration before accepting it.

* gcc.dg/vect/pr115385.c: Enable AVX2 if available.

Diff:
---
 gcc/testsuite/gcc.dg/vect/pr115385.c |  1 +
 gcc/tree-vect-stmts.cc   | 12 +++-
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/pr115385.c 
b/gcc/testsuite/gcc.dg/vect/pr115385.c
index a18cd665d7d0..baea0b2473fe 100644
--- a/gcc/testsuite/gcc.dg/vect/pr115385.c
+++ b/gcc/testsuite/gcc.dg/vect/pr115385.c
@@ -1,4 +1,5 @@
 /* { dg-require-effective-target mmap } */
+/* { dg-additional-options "-mavx2" { target avx2_runtime } } */
 
 #include 
 #include 
diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index e32d44050e53..ca6052662a30 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -2148,15 +2148,17 @@ get_group_load_store_type (vec_info *vinfo, 
stmt_vec_info stmt_info,
{
  /* But peeling a single scalar iteration is enough if
 we can use the next power-of-two sized partial
-access.  */
+access and that is sufficiently small to be covered
+by the single scalar iteration.  */
  unsigned HOST_WIDE_INT cnunits, cvf, cremain, cpart_size;
  if (!nunits.is_constant (&cnunits)
  || !LOOP_VINFO_VECT_FACTOR (loop_vinfo).is_constant (&cvf)
- || ((cremain = remain.to_constant (), true)
+ || (((cremain = group_size * cvf - gap % cnunits), true)
  && ((cpart_size = (1 << ceil_log2 (cremain))) != cnunits)
- && vector_vector_composition_type
-  (vectype, cnunits / cpart_size,
-   &half_vtype) == NULL_TREE))
+ && (cremain + group_size < cpart_size
+ || vector_vector_composition_type
+  (vectype, cnunits / cpart_size,
+   &half_vtype) == NULL_TREE)))
{
  if (dump_enabled_p ())
dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,

[gcc r15-1310] ada: Remove unused name of aspect from Snames

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:2ede7e3993c90c16f28358df07ea29cd62e34447

commit r15-1310-g2ede7e3993c90c16f28358df07ea29cd62e34447
Author: Eric Botcazou 
Date:   Thu May 9 10:49:32 2024 +0200

ada: Remove unused name of aspect from Snames

gcc/ada/

* snames.ads-tmpl (Name_Storage_Model): Delete.

Diff:
---
 gcc/ada/snames.ads-tmpl | 1 -
 1 file changed, 1 deletion(-)

diff --git a/gcc/ada/snames.ads-tmpl b/gcc/ada/snames.ads-tmpl
index 6cc665669072..699b8df58515 100644
--- a/gcc/ada/snames.ads-tmpl
+++ b/gcc/ada/snames.ads-tmpl
@@ -165,7 +165,6 @@ package Snames is
Name_Relaxed_Initialization : constant Name_Id := N + $;
Name_Stable_Properties  : constant Name_Id := N + $;
Name_Static_Predicate   : constant Name_Id := N + $;
-   Name_Storage_Model  : constant Name_Id := N + $;
Name_Storage_Model_Type : constant Name_Id := N + $;
Name_String_Literal : constant Name_Id := N + $;
Name_Synchronization: constant Name_Id := N + $;

[gcc r15-1311] ada: Allow implicit dereferenced for uses of 'Super

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:d3fe0ffdd22bcabcbf03ee936d89ab971fbc74c4

commit r15-1311-gd3fe0ffdd22bcabcbf03ee936d89ab971fbc74c4
Author: Justin Squirek 
Date:   Thu May 9 19:37:44 2024 +

ada: Allow implicit dereferenced for uses of 'Super

This patch modifies the experimental 'Super attribute to allow an 
access-valued
prefix to be equivalent to Prefix.all'Super.

gcc/ada/

* sem_attr.adb:
(Analyze_Attribute): Add check for dereference.

Diff:
---
 gcc/ada/sem_attr.adb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/ada/sem_attr.adb b/gcc/ada/sem_attr.adb
index 22fbca45ac5f..2563a92f2f0d 100644
--- a/gcc/ada/sem_attr.adb
+++ b/gcc/ada/sem_attr.adb
@@ -6688,6 +6688,7 @@ package body Sem_Attr is
  Error_Msg_GNAT_Extension ("attribute %", Sloc (N));
 
  Check_E0;
+ Check_Dereference;
 
  --  Verify that we are looking at a type with ancestors

[gcc r15-1312] ada: Couple of small cleanups in semantic analysis of aspects

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:464f0cb46a17cd4b941f0b3182323a883c59dcf3

commit r15-1312-g464f0cb46a17cd4b941f0b3182323a883c59dcf3
Author: Eric Botcazou 
Date:   Thu May 9 20:18:57 2024 +0200

ada: Couple of small cleanups in semantic analysis of aspects

The first cleanup is to expose a consistent interface from Sem_Ch13 for the
analysis of aspects at various points of the program.  The second cleanup is
to fix the awkward implementation of the analysis of the specification for
the aspects Stable_Properties, Designated_Storage_Model, Storage_Model_Type
and Aggregate, which are always delayed, and the incorrect placement of that
of the aspect Local_Restrictions, which is never delayed.

gcc/ada/

* freeze.adb (Freeze_All): Call Check_Aspects_At_End_Of_Declarations
to perform the visibility check for aspects.
* sem_ch13.ads (Check_Aspects_At_End_Of_Declarations): Declare.
(Check_Aspect_At_Freeze_Point): Move to...
(Check_Aspect_At_End_Of_Declarations): Move to...
* sem_ch13.adb  (Check_Aspect_At_Freeze_Point): ...here.
(Check_Aspect_At_End_Of_Declarations): ...here.
(Analyze_Aspect_Specifications): Remove peculiar processing for
Stable_Properties, Designated_Storage_Model, Storage_Model_Type
and Aggregate.  Move that of Local_Restrictions around.  Reset
Aitem at the beginning of the loop for each aspect.
(Check_Aspects_At_End_Of_Declarations): New procedure.

Diff:
---
 gcc/ada/freeze.adb   | 17 +-
 gcc/ada/sem_ch13.adb | 87 ++--
 gcc/ada/sem_ch13.ads | 14 -
 3 files changed, 58 insertions(+), 60 deletions(-)

diff --git a/gcc/ada/freeze.adb b/gcc/ada/freeze.adb
index c4c524f4685b..523b026cc21c 100644
--- a/gcc/ada/freeze.adb
+++ b/gcc/ada/freeze.adb
@@ -2645,22 +2645,7 @@ package body Freeze is
 --  for a description of how we handle aspect visibility).
 
 elsif Has_Delayed_Aspects (E) then
-   declare
-  Ritem : Node_Id;
-
-   begin
-  Ritem := First_Rep_Item (E);
-  while Present (Ritem) loop
- if Nkind (Ritem) = N_Aspect_Specification
-   and then Entity (Ritem) = E
-   and then Is_Delayed_Aspect (Ritem)
- then
-Check_Aspect_At_End_Of_Declarations (Ritem);
- end if;
-
- Next_Rep_Item (Ritem);
-  end loop;
-   end;
+   Check_Aspects_At_End_Of_Declarations (E);
 end if;
 
 --  If an incomplete type is still not frozen, this may be a
diff --git a/gcc/ada/sem_ch13.adb b/gcc/ada/sem_ch13.adb
index d065dd8dfda8..46a359fd7d69 100644
--- a/gcc/ada/sem_ch13.adb
+++ b/gcc/ada/sem_ch13.adb
@@ -150,6 +150,15 @@ package body Sem_Ch13 is
--  is inserted before the freeze node, and the body of the function is
--  inserted after the freeze node.
 
+   procedure Check_Aspect_At_End_Of_Declarations (ASN : Node_Id);
+   --  Performs the processing of an aspect at the freeze all point and issues
+   --  appropriate error messages if the visibility has indeed changed. ASN is
+   --  the N_Aspect_Specification node for the aspect.
+
+   procedure Check_Aspect_At_Freeze_Point (ASN : Node_Id);
+   --  Performs the processing of an aspect at the freeze point. ASN is the
+   --  N_Aspect_Specification node for the aspect.
+
procedure Check_Pool_Size_Clash (Ent : Entity_Id; SP, SS : Node_Id);
--  Called if both Storage_Pool and Storage_Size attribute definition
--  clauses (SP and SS) are present for entity Ent. Issue error message.
@@ -1669,7 +1678,6 @@ package body Sem_Ch13 is
   --  Local variables
 
   Aspect : Node_Id;
-  Aitem  : Node_Id := Empty;
   Ent: Node_Id;
 
   L : constant List_Id := Aspect_Specifications (N);
@@ -1722,7 +1730,12 @@ package body Sem_Ch13 is
 Loc  : constant Source_Ptr := Sloc (Aspect);
 Nam  : constant Name_Id:= Chars (Id);
 A_Id : constant Aspect_Id  := Get_Aspect_Id (Nam);
+
+Aitem : Node_Id := Empty;
+--  The associated N_Pragma or N_Attribute_Definition_Clause
+
 Anod : Node_Id;
+--  An auxiliary node
 
 Delay_Required : Boolean;
 --  Set False if delay is not required
@@ -2949,19 +2962,6 @@ package body Sem_Ch13 is
   end if;
 end case;
 
-if Delay_Required
-   and then (A_Id = Aspect_Stable_Properties
-  or else A_Id = Aspect_Designated_Storage_Model
-  or else A_Id = Aspect_Storage_Model_Type
-  or else A_Id = Aspect_Aggregate)
-   --  ??? It seems like we should do th

[gcc r15-1313] ada: Missing initialization of multidimensional array using sliding

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:02263316169d4299df24ef91b4d469d3a3d50220

commit r15-1313-g02263316169d4299df24ef91b4d469d3a3d50220
Author: Javier Miranda 
Date:   Thu May 9 21:48:18 2024 +

ada: Missing initialization of multidimensional array using sliding

When a multidimensional array is initialized with an array
aggregate, and inner dimensions of the array are initialized
with array subaggregates using sliding, the code generated
by the compiler does not initialize the inner dimensions
of the array.

gcc/ada/

* exp_aggr.adb (Must_Slide): Add missing support for
multidimensional arrays.

Diff:
---
 gcc/ada/exp_aggr.adb | 54 
 1 file changed, 33 insertions(+), 21 deletions(-)

diff --git a/gcc/ada/exp_aggr.adb b/gcc/ada/exp_aggr.adb
index 796b0f1e0de1..2686f5b3b826 100644
--- a/gcc/ada/exp_aggr.adb
+++ b/gcc/ada/exp_aggr.adb
@@ -154,8 +154,8 @@ package body Exp_Aggr is
--  case the aggregate must slide, and we must introduce an intermediate
--  temporary to hold it.
--
-   --  The same holds in an assignment to one-dimensional array of arrays,
-   --  when a component may be given with bounds that differ from those of the
+   --  The same holds in an assignment to multi-dimensional arrays, when
+   --  components may be given with bounds that differ from those of the
--  component type.
 
function Number_Of_Choices (N : Node_Id) return Nat;
@@ -9550,32 +9550,44 @@ package body Exp_Aggr is
   elsif Is_Others_Aggregate (Aggr) then
  return False;
 
-  else
- --  Sliding can only occur along the first dimension
- --  If any the bounds of non-static sliding is required
- --  to force potential range checks.
+  --  Check if sliding is required
 
+  else
  declare
-Bounds1 : constant Range_Nodes :=
-  Get_Index_Bounds (First_Index (Typ));
-Bounds2 : constant Range_Nodes :=
-  Get_Index_Bounds (First_Index (Obj_Type));
+Obj_Index  : Node_Id := First_Index (Obj_Type);
+Obj_Bounds : Range_Nodes;
+Typ_Index  : Node_Id := First_Index (Typ);
+Typ_Bounds : Range_Nodes;
 
  begin
-if not Is_OK_Static_Expression (Bounds1.First) or else
-   not Is_OK_Static_Expression (Bounds2.First) or else
-   not Is_OK_Static_Expression (Bounds1.Last) or else
-   not Is_OK_Static_Expression (Bounds2.Last)
-then
-   return True;
+while Present (Typ_Index) loop
+   pragma Assert (Present (Obj_Index));
 
-else
-   return Expr_Value (Bounds1.First) /= Expr_Value (Bounds2.First)
-or else
-  Expr_Value (Bounds1.Last) /= Expr_Value (Bounds2.Last);
-end if;
+   Typ_Bounds := Get_Index_Bounds (Typ_Index);
+   Obj_Bounds := Get_Index_Bounds (Obj_Index);
+
+   if not Is_OK_Static_Expression (Typ_Bounds.First) or else
+ not Is_OK_Static_Expression (Obj_Bounds.First) or else
+ not Is_OK_Static_Expression (Typ_Bounds.Last) or else
+ not Is_OK_Static_Expression (Obj_Bounds.Last)
+   then
+  return True;
+
+   elsif Expr_Value (Typ_Bounds.First)
+   /= Expr_Value (Obj_Bounds.First)
+ or else Expr_Value (Typ_Bounds.Last)
+   /= Expr_Value (Obj_Bounds.Last)
+   then
+  return True;
+   end if;
+
+   Next_Index (Typ_Index);
+   Next_Index (Obj_Index);
+end loop;
  end;
   end if;
+
+  return False;
end Must_Slide;
 
-

[gcc r15-1314] ada: Minor tweaks to processing of Aggregate aspect

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:34935c45c6e13093f9e2c2b1bc36483818152e9c

commit r15-1314-g34935c45c6e13093f9e2c2b1bc36483818152e9c
Author: Eric Botcazou 
Date:   Fri May 10 17:11:24 2024 +0200

ada: Minor tweaks to processing of Aggregate aspect

The main one is to give the error for Aggregate applied to array types from
Analyze_Aspects_At_Freeze_Point instead of Check_Aspect_At_Freeze_Point, as
for the other aspects.  The message is also changed to be more direct.

gcc/ada/

* aspects.ads (Operational_Aspect): Alphabetize.
* sem_ch13.ads (Analyze_Aspects_At_Freeze_Point): Fix description.
* sem_ch13.adb (Analyze_Aspects_At_Freeze_Point) : Give
the error for array types here instead of...
(Analyze_Aspect_Specifications) : Adjust comment.
(Check_Aspect_At_Freeze_Point) : ...here.

Diff:
---
 gcc/ada/aspects.ads  |  4 ++--
 gcc/ada/sem_ch13.adb | 17 -
 gcc/ada/sem_ch13.ads |  9 +
 3 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/gcc/ada/aspects.ads b/gcc/ada/aspects.ads
index 3cc62de3411b..1acbec878248 100644
--- a/gcc/ada/aspects.ads
+++ b/gcc/ada/aspects.ads
@@ -325,12 +325,12 @@ package Aspects is
--  List is currently incomplete ???
 
Operational_Aspect : constant array (Aspect_Id) of Boolean :=
- (Aspect_Constant_Indexing  => True,
+ (Aspect_Aggregate  => True,
+  Aspect_Constant_Indexing  => True,
   Aspect_Default_Iterator   => True,
   Aspect_Iterator_Element   => True,
   Aspect_Iterable   => True,
   Aspect_Variable_Indexing  => True,
-  Aspect_Aggregate  => True,
   others=> False);
 
--  The following array indicates aspects for which multiple occurrences of
diff --git a/gcc/ada/sem_ch13.adb b/gcc/ada/sem_ch13.adb
index 46a359fd7d69..caebe2e793e4 100644
--- a/gcc/ada/sem_ch13.adb
+++ b/gcc/ada/sem_ch13.adb
@@ -1367,7 +1367,11 @@ package body Sem_Ch13 is
  Validate_Storage_Model_Type_Aspect (E, ASN);
 
   when Aspect_Aggregate =>
- null;
+ if Is_Array_Type (E) then
+Error_Msg_N
+  ("aspect Aggregate may not be applied to array type",
+   ASN);
+ end if;
 
   when others =>
  null;
@@ -1384,7 +1388,7 @@ package body Sem_Ch13 is
  Next_Rep_Item (ASN);
   end loop;
 
-  --  Make a second pass for a Full_Access_Only entry
+  --  Make a second pass for a Full_Access_Only entry, see above why
 
   ASN := First_Rep_Item (E);
   while Present (ASN) loop
@@ -4130,8 +4134,8 @@ package body Sem_Ch13 is
   end if;
 
when Aspect_Aggregate =>
-  --  We will be checking that the aspect is not specified on a
-  --  non-array type in Check_Aspect_At_Freeze_Point
+  --  We will be checking that the aspect is not specified on
+  --  an array type in Analyze_Aspects_At_Freeze_Point.
 
   Validate_Aspect_Aggregate (Expr);
 
@@ -11378,11 +11382,6 @@ package body Sem_Ch13 is
 return;
 
  when Aspect_Aggregate =>
-if Is_Array_Type (Entity (ASN)) then
-   Error_Msg_N
- ("aspect& can only be applied to non-array type",
-  Ident);
-end if;
 Resolve_Aspect_Aggregate (Entity (ASN), Expression (ASN));
 return;
 
diff --git a/gcc/ada/sem_ch13.ads b/gcc/ada/sem_ch13.ads
index 2bdca957826a..aeacda833d1e 100644
--- a/gcc/ada/sem_ch13.ads
+++ b/gcc/ada/sem_ch13.ads
@@ -312,10 +312,11 @@ package Sem_Ch13 is
--  Quite an awkward approach, but this is an awkard requirement
 
procedure Analyze_Aspects_At_Freeze_Point (E : Entity_Id);
-   --  Analyzes all the delayed aspects for entity E at freezing point. This
-   --  includes dealing with inheriting delayed aspects from the parent type
-   --  in the case where a derived type is frozen. Callers should check that
-   --  Has_Delayed_Aspects (E) is True before calling this routine.
+   --  Analyzes all the delayed aspects for entity E at the freeze point. Note
+   --  that this does not include dealing with inheriting delayed aspects from
+   --  the parent or base type in the case where a derived type or a subtype is
+   --  frozen. Callers should check that Has_Delayed_Aspects (E) is True before
+   --  calling this routine.
 
procedure Check_Aspects_At_End_Of_Declarations (E : Entity_Id);
--  Performs the processing described above at the freeze all point, and

[gcc r15-1315] ada: Crash checking accessibility level on private type

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:1feb6d81a3ab587382817cd7a39222b6c83f68ac

commit r15-1315-g1feb6d81a3ab587382817cd7a39222b6c83f68ac
Author: Justin Squirek 
Date:   Fri May 10 11:18:01 2024 +

ada: Crash checking accessibility level on private type

This patch fixes an issue in the compiler whereby calculating a static
accessibility level on a private type with an access discriminant resulted
in a compile time crash when No_Dynamic_Accessibility_Checks is enabled.

gcc/ada/

* accessibility.adb:
(Accessibility_Level): Replace call Get_Full_View with call to
Full_View since Get_Full_View only works with incomplete types.

Diff:
---
 gcc/ada/accessibility.adb | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/gcc/ada/accessibility.adb b/gcc/ada/accessibility.adb
index 47b3a7af10a5..da4d1d9ce2e2 100644
--- a/gcc/ada/accessibility.adb
+++ b/gcc/ada/accessibility.adb
@@ -2227,7 +2227,11 @@ package body Accessibility is
   --  that of the type.
 
   elsif Ekind (Def_Ent) = E_Discriminant then
- return Scope_Depth (Get_Full_View (Scope (Def_Ent)));
+ return Scope_Depth
+   (if Present (Full_View (Scope (Def_Ent))) then
+   Full_View (Scope (Def_Ent))
+else
+   Scope (Def_Ent));
   end if;
end if;

[gcc r15-1317] ada: Minor tweak in Snames

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:50c41dd34202b29983a862b5d326bab668402c17

commit r15-1317-g50c41dd34202b29983a862b5d326bab668402c17
Author: Eric Botcazou 
Date:   Sun May 12 11:06:39 2024 +0200

ada: Minor tweak in Snames

gcc/ada/

* snames.ads-tmpl (Name_Present): Move to Repinfo section.

Diff:
---
 gcc/ada/snames.ads-tmpl | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/gcc/ada/snames.ads-tmpl b/gcc/ada/snames.ads-tmpl
index 699b8df58515..d2f724f86cab 100644
--- a/gcc/ada/snames.ads-tmpl
+++ b/gcc/ada/snames.ads-tmpl
@@ -903,10 +903,6 @@ package Snames is
Name_Warn   : constant Name_Id := N + $;
Name_Working_Storage: constant Name_Id := N + $;
 
-   --  used by Repinfo JSON I/O
-
-   Name_Present: constant Name_Id := N + $;
-
--  Names of recognized attributes. The entries with the comment "Ada 83"
--  are attributes that are defined in Ada 83, but not in Ada 95. These
--  attributes are implemented in all Ada modes in GNAT.
@@ -1372,6 +1368,7 @@ package Snames is
 
Name_Discriminant : constant Name_Id := N + $;
Name_Operands : constant Name_Id := N + $;
+   Name_Present  : constant Name_Id := N + $;
 
--  Other miscellaneous names used in front end
--  Note that the UP_ prefix means use the rest of the name in uppercase,

[gcc r15-1318] ada: Simplify handling of VxWorks-specific error codes for ENOENT

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:7232be268a0a275d43225fef141cf99d2f6bbed9

commit r15-1318-g7232be268a0a275d43225fef141cf99d2f6bbed9
Author: Jerome Guitton 
Date:   Fri May 10 13:16:17 2024 +

ada: Simplify handling of VxWorks-specific error codes for ENOENT

These error codes were defined on older versions of VxWorks (5, 6, 7
SR0540) and now they are either not defined or they fallback to
ENOENT. To handle these cases without using complex tests against
vxworks versions, leverage on __has_include and provide a fallback to
ENOENT if these error codes are not defined.

gcc/ada/

* sysdep.c (S_dosFsLib_FILE_NOT_FOUND, S_nfsLib_NFSERR_NOENT):
New macros, falback to ENOENT when not already defined.
(__gnat_is_file_not_found_error): Use these new macros to remove
tests against VxWorks flavors.

Diff:
---
 gcc/ada/sysdep.c | 27 ---
 1 file changed, 20 insertions(+), 7 deletions(-)

diff --git a/gcc/ada/sysdep.c b/gcc/ada/sysdep.c
index 443b11f43023..254c736bec43 100644
--- a/gcc/ada/sysdep.c
+++ b/gcc/ada/sysdep.c
@@ -35,18 +35,35 @@
 #ifdef __vxworks
 #include "vxWorks.h"
 #include "ioLib.h"
-#if ! defined (VTHREADS)
+/* VxWorks 5, 6 and 7 SR0540 expose error codes that need to be handled
+   as ENOENT. On later versions:
+   - either they are defined as ENOENT (vx7r2);
+   - or the corresponding system includes are not provided (Helix Cert).  */
+
+#if __has_include ("dosFsLib.h")
+/* On helix-cert, this include is only provided for RTPs.  */
 #include "dosFsLib.h"
 #endif
-#if ! defined (__RTP__) && (! defined (VTHREADS) || defined (__VXWORKSMILS__))
+
+#ifndef S_dosFsLib_FILE_NOT_FOUND
+#define S_dosFsLib_FILE_NOT_FOUND ENOENT
+#endif
+
+#if __has_include ("nfsLib.h")
+/* This include is not provided for RTPs or on helix-cert.  */
 # include "nfsLib.h"
 #endif
+
+#ifndef S_nfsLib_NFSERR_NOENT
+#define S_nfsLib_NFSERR_NOENT ENOENT
+#endif
+
 #include "selectLib.h"
 #include "version.h"
 #if defined (__RTP__)
 #  include "vwModNum.h"
 #endif /* __RTP__ */
-#endif
+#endif /* __vxworks */
 
 #ifdef __ANDROID__
 #undef __linux__
@@ -912,14 +929,10 @@ __gnat_is_file_not_found_error (int errno_val)
 /* In the case of VxWorks, we also have to take into account various
  * filesystem-specific variants of this error.
  */
-#if ! defined (VTHREADS) && (_WRS_VXWORKS_MAJOR < 7)
 else if (errno_val == S_dosFsLib_FILE_NOT_FOUND)
   return 1;
-#endif
-#if ! defined (__RTP__) && (! defined (VTHREADS) || defined (__VXWORKSMILS__))
 else if (errno_val ==  S_nfsLib_NFSERR_NOENT)
   return 1;
-#endif
 #if defined (__RTP__)
 /* An RTP can return an NFS file not found, and the NFS bits must
first be masked on to check the errno.  */

[gcc r15-1319] ada: Bad tree built for Obj.Discrim_Dep_Component'Loop_Entry in assertion

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:5d429a206c0784435cf963cbfd645cb4e7733795

commit r15-1319-g5d429a206c0784435cf963cbfd645cb4e7733795
Author: Steve Baird 
Date:   Tue May 7 17:04:28 2024 -0700

ada: Bad tree built for Obj.Discrim_Dep_Component'Loop_Entry in assertion

The Etype for an N_Selected_Component node usually should not match the 
Etype
of the referenced component if the component is subject to a
discriminant-dependent constraint. Instead Build_Actual_Subtype_Of_Component
should be called. Fix a case where this rule was not being followed (because
B_A_S_O_C is not called during preanalysis of a component selection), 
resulting
in a tree that confused CodePeer because the subtype was wrong.

gcc/ada/

* exp_attr.adb
(Expand_Loop_Entry_Attribute):
Ensure that Etype of the saved expression is set correctly.

Diff:
---
 gcc/ada/exp_attr.adb | 25 ++---
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/gcc/ada/exp_attr.adb b/gcc/ada/exp_attr.adb
index 1396007a2d12..5c85b4912d27 100644
--- a/gcc/ada/exp_attr.adb
+++ b/gcc/ada/exp_attr.adb
@@ -1780,14 +1780,25 @@ package body Exp_Attr is
  begin
 Aux_Decl := Empty;
 
---  Generate a nominal type for the constant when the prefix is of
---  a constrained type. This is achieved by setting the Etype of
---  the relocated prefix to its base type. Since the prefix is now
---  the initialization expression of the constant, its freezing
---  will produce a proper nominal type.
-
 Temp_Expr := Relocate_Node (Pref);
-Set_Etype (Temp_Expr, Base_Typ);
+
+--  For Etype (Temp_Expr) in some cases we cannot use either
+--  Etype (Pref) or Base_Typ. So we set Etype (Temp_Expr) to null
+--  and mark Temp_Expr as requiring analysis. Rather than trying
+--  to sort out exactly when this is needed, we do it
+--  unconditionally.
+--  One case where this is needed is when
+-- 1) Pref is an N_Selected_Component name that
+--refers to a component which is subject to a
+--discriminant-dependent constraint; and
+-- 2) The prefix of that N_Selected_Component refers to a
+--formal parameter with an unconstrained subtype; and
+-- 3) Pref has only been preanalyzed (so that
+--Build_Actual_Subtype_Of_Component has not been called
+--and Etype (Pref) equals the Etype of the component).
+
+Set_Etype (Temp_Expr, Empty);
+Set_Analyzed (Temp_Expr, False);
 
 --  Generate:
 --Temp : constant Base_Typ := Pref;

[gcc r15-1320] ada: Fix parts of classification of aspects

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:97810ccb01b21dd8c5ed4e84d5aa2bc6c0dd8a45

commit r15-1320-g97810ccb01b21dd8c5ed4e84d5aa2bc6c0dd8a45
Author: Eric Botcazou 
Date:   Mon May 13 16:15:10 2024 +0200

ada: Fix parts of classification of aspects

Many aspects are (correctly) marked as GNAT-specific but nevertheless not
listed in the Implementation_Defined_Aspect array, so this aligns the two
sides and also removes Default_Initial_Condition and Object_Size from the
list, since they are defined in Ada 2022.

This also moves No_Controlled_Parts and No_Task_Parts to the subclass of
boolean aspects, and completes the list of nonoverridable aspects defined
in Ada 2022.

gcc/ada/

* aspects.ads (Aspect_Id): Alphabetize, remove the GNAT tag from
Default_Initial_Condition and Object_Size, move No_Controlled_Parts
and No_Task_Parts to boolean subclass.
(Nonoverridable_Aspect_Id): Add missing Ada 2022 aspects.
(Implementation_Defined_Aspect): Add all missing aspects, remove
Max_Entry_Queue_Length and Object_Size
(Aspect_Argument): Remove specific entries for No_Controlled_Parts
and No_Task_Parts, list boolean aspects last.
(Is_Representation_Aspect ): Move boolean aspects last.
(Aspect_Names): Alphabetize.
* sem_ch13.adb (Analyze_Aspect_Disable_Controlled): Adjust.
(Analyze_Aspect_Specifications): Move around processing for
No_Controlled_Parts and No_Task_Parts.
(Check_Aspect_At_Freeze_Point): Remove specific entries for
No_Controlled_Parts and No_Task_Parts

Diff:
---
 gcc/ada/aspects.ads  | 94 +---
 gcc/ada/sem_ch13.adb | 69 ++
 2 files changed, 101 insertions(+), 62 deletions(-)

diff --git a/gcc/ada/aspects.ads b/gcc/ada/aspects.ads
index d4aafb1a4f16..202d42193d13 100644
--- a/gcc/ada/aspects.ads
+++ b/gcc/ada/aspects.ads
@@ -64,10 +64,14 @@ with Types;   use Types;
 
 package Aspects is
 
-   --  Type defining recognized aspects
+   --  Type enumerating the recognized aspects. The GNAT tag must be in keeping
+   --  with the Implementation_Defined_Aspect array below.
 
type Aspect_Id is
  (No_Aspect,-- Dummy entry for no aspect
+
+  --  The following aspects do not have a (static) boolean value
+
   Aspect_Abstract_State,-- GNAT
   Aspect_Address,
   Aspect_Aggregate,
@@ -81,7 +85,7 @@ package Aspects is
   Aspect_Convention,
   Aspect_CPU,
   Aspect_Default_Component_Value,
-  Aspect_Default_Initial_Condition, -- GNAT
+  Aspect_Default_Initial_Condition,
   Aspect_Default_Iterator,
   Aspect_Default_Storage_Pool,
   Aspect_Default_Value,
@@ -104,8 +108,8 @@ package Aspects is
   Aspect_Integer_Literal,
   Aspect_Interrupt_Priority,
   Aspect_Invariant, -- GNAT
-  Aspect_Iterator_Element,
   Aspect_Iterable,  -- GNAT
+  Aspect_Iterator_Element,
   Aspect_Link_Name,
   Aspect_Linker_Section,-- GNAT
   Aspect_Local_Restrictions,-- GNAT
@@ -113,9 +117,7 @@ package Aspects is
   Aspect_Max_Entry_Queue_Depth, -- GNAT
   Aspect_Max_Entry_Queue_Length,
   Aspect_Max_Queue_Length,  -- GNAT
-  Aspect_No_Controlled_Parts,
-  Aspect_No_Task_Parts, -- GNAT
-  Aspect_Object_Size,   -- GNAT
+  Aspect_Object_Size,
   Aspect_Obsolescent,   -- GNAT
   Aspect_Output,
   Aspect_Part_Of,   -- GNAT
@@ -186,10 +188,10 @@ package Aspects is
   Aspect_Atomic,
   Aspect_Atomic_Components,
   Aspect_Constant_After_Elaboration,-- GNAT
-  Aspect_Disable_Controlled,-- GNAT
-  Aspect_Discard_Names,
   Aspect_CUDA_Device,   -- GNAT
   Aspect_CUDA_Global,   -- GNAT
+  Aspect_Disable_Controlled,-- GNAT
+  Aspect_Discard_Names,
   Aspect_Effective_Reads,   -- GNAT
   Aspect_Effective_Writes,  -- GNAT
   Aspect_Exclusive_Functions,
@@ -206,9 +208,11 @@ package Aspects is
   Aspect_Interrupt_Handler,
   Aspect_Lock_Free, -- GNAT
   Aspect_No_Caching,-- GNAT
+  Aspect_No_Controlled_Parts,
   Aspect_No_Inline, -- GNAT
   Aspect_No_Return,
   Aspect_No_Tagged_Streams, -- GNAT
+  Aspect_No_Task_Parts, -- GNAT
   Aspect_Pack,
   Aspect_Persistent_BSS,-- GNAT
   Aspect_Preelaborable_Initialization,
@@ -242,12 +246,13 @@ package Aspects is
  | Aspect_Constant_Indexing
  | Aspect_Default_Iterat

[gcc r15-1316] ada: Add prototype for mutably tagged types

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:262a5ffc41471aa4909f23279278dd37724da744

commit r15-1316-g262a5ffc41471aa4909f23279278dd37724da744
Author: Justin Squirek 
Date:   Thu May 9 05:04:03 2024 +

ada: Add prototype for mutably tagged types

This patch implements mutably tagged types via the new Size'Class aspect.

gcc/ada/

* doc/gnat_rm/gnat_language_extensions.rst: Add documentation for
mutably tagged type feature.
* aspects.ads: Add registration for 'Size'Class.
* einfo.ads: Add documentation for new components
Class_Wide_Equivalent_Type and Is_Mutably_Tagged_Type.
* exp_aggr.adb (Gen_Assign): Assume associated mutably tagged type
when class-wide equivalent type is encountered.
(Contains_Mutably_Tagged_Type): New subprogram.
(Convert_To_Positional): Assume associated mutably tagged type
when class-wide equivalent type is encountered.
(Is_Static_Element): Assume associated mutably tagged type when
class-wide equivalent type is encountered.
(Expand_Array_Aggregate): Assume associated mutably tagged type
when class-wide equivalent type is encountered.
(Expand_Record_Aggregate): Force mutably tagged records to be
expanded into assignments.
* exp_ch3.adb (Build_Array_Init_Proc): Assume associated mutably
tagged type when class-wide equivalent type is encountered.
(Simple_Initialization_OK): Disallow simple initialization for
class-wide equivalent types.
(Build_Init_Statements): Assume associated mutably tagged type
when class-wide equivalent type is encountered.
(Expand_Freeze_Array_Type): Ignore building of record init procs
for mutably tagged types.
(Expand_N_Full_Type_Declaration): Replace mutably tagged type
declarations with their associated class-wide equivalent types.
(Default_Initialize_Object): Add special handling for mutably
tagged types.
* exp_ch4.adb (Expand_N_Allocator): Add initialization for mutably
tagged types.
(Expand_Record_Equality): Generate mutably tagged unchecked
conversions.
* exp_ch5.adb (Expand_N_Assignment_Statement): Generate a special
assignment case for class-wide equivalent types which does tag
assignments and ignores certain checks.
* exp_ch6.adb (Expand_Call_Helper): Propagate constrained extra
formal actuals for mutably tagged types.
* exp_ch7.adb (Make_Init_Call): Handle mutably tagged type
initialization.
* exp_util.adb (Make_CW_Equivalent_Type): Modify to handle mutably
tagged objects which contain no initialization expression.
(Make_Subtype_From_Expr): Modify call to Make_CW_Equivalent_Type.
* exp_util.ads (Make_CW_Equivalent_Type): Move declaration from
body to spec.
* freeze.adb (Size_Known): No longer return false automatically
when a class-wide type is encountered.
(Freeze_Entity): Ignore error messages about size not being known
for mutably tagged types.
* gen_il-fields.ads: Register new fields
Class_Wide_Equivalent_Type and Is_Mutably_Tagged_Type.
* gen_il-gen-gen_entities.adb: Register new fields
Class_Wide_Equivalent_Type and Is_Mutably_Tagged_Type for type
entities.
* mutably_tagged.adb, mutably_tagged.ads
(Corresponding_Mutably_Tagged_Type): New subprogram.
(Depends_On_Mutably_Tagged_Ext_Comp): New subprogram.
(Get_Corresponding_Mutably_Tagged_Type_If_Present): New
subprogram.
(Get_Corresponding_Tagged_Type_If_Present): New subprogram.
(Is_Mutably_Tagged_Conversion): New subprogram.
(Is_Mutably_Tagged_CW_Equivalent_Type): New subprogram.
(Make_Mutably_Tagged_Conversion): New subprogram.
(Make_CW_Size_Compile_Check): New subprogram.
(Make_Mutably_Tagged_CW_Check): New subprogram.
* sem_aggr.adb (Resolve_Array_Aggregate): Skip tag checks for
class-wide equivalent types.
(Resolve_Aggr_Expr): Assume associated mutably tagged type when
class-wide equivalent type is encountered.
* sem_attr.adb (Analyze_Attribute): Allow 'Tag on mutably tagged
types.
(Resolve_Attribute): Detect errors for dependence of mutably
tagged extension type component.
* sem_ch12.adb (Instantiate_Object): Detect errors for dependence
of mutably tagged extension type component.
* sem_ch13.adb (Analyze_One_Aspect): Propagate 'Size'Class to
class-wide type.
(Analyze_Attribute_

[gcc r15-1321] ada: Typo and indentation fix

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:cac993e84ea363dc593799ad1a6d0db5d0165f16

commit r15-1321-gcac993e84ea363dc593799ad1a6d0db5d0165f16
Author: Marc Poulhiès 
Date:   Thu Feb 29 10:51:40 2024 +0100

ada: Typo and indentation fix

Fixes typo in comments and 2 instances of bad indentation.

gcc/ada/

* gcc-interface/decl.cc (gnat_to_gnu_entity): Typo fix.
(gnat_to_gnu_component_type): Indent fix.
* gcc-interface/gigi.h (build_call_alloc_dealloc): Typo fix.
* gcc-interface/utils.cc (make_dummy_type): Typo fix.
* gcc-interface/utils2.cc (gnat_protect_expr): Indent fix.

Diff:
---
 gcc/ada/gcc-interface/decl.cc   | 8 
 gcc/ada/gcc-interface/gigi.h| 2 +-
 gcc/ada/gcc-interface/utils.cc  | 2 +-
 gcc/ada/gcc-interface/utils2.cc | 2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/gcc/ada/gcc-interface/decl.cc b/gcc/ada/gcc-interface/decl.cc
index 8b72c96c4396..239837426059 100644
--- a/gcc/ada/gcc-interface/decl.cc
+++ b/gcc/ada/gcc-interface/decl.cc
@@ -1384,7 +1384,7 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, 
bool definition)
volatile_flag = false;
gnu_size = NULL_TREE;
 
-   /* In case this was a aliased object whose nominal subtype is
+   /* In case this was an aliased object whose nominal subtype is
   unconstrained, the pointer above will be a thin pointer and
   build_allocator will automatically make the template.
 
@@ -2103,7 +2103,7 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, 
bool definition)
 
   1. the array type (suffix XUA) containing the actual data,
 
-  2. the template type (suffix XUB) containng the bounds,
+  2. the template type (suffix XUB) containing the bounds,
 
   3. the fat pointer type (suffix XUP) representing a pointer or a
  reference to the unconstrained array type:
@@ -5445,8 +5445,8 @@ gnat_to_gnu_component_type (Entity_Id gnat_array, bool 
definition,
  if (gnu_comp_align > TYPE_ALIGN (gnu_type))
gnu_comp_align = 0;
}
-   else
-gnu_comp_align = 0;
+  else
+   gnu_comp_align = 0;
 
   gnu_type = maybe_pad_type (gnu_type, gnu_comp_size, gnu_comp_align,
 gnat_array, true, definition, true);
diff --git a/gcc/ada/gcc-interface/gigi.h b/gcc/ada/gcc-interface/gigi.h
index f3205a8a25d9..6ed74d6879ee 100644
--- a/gcc/ada/gcc-interface/gigi.h
+++ b/gcc/ada/gcc-interface/gigi.h
@@ -906,7 +906,7 @@ extern tree build_call_alloc_dealloc (tree gnu_obj, tree 
gnu_size,
  Entity_Id gnat_pool, Node_Id gnat_node);
 
 /* Build a GCC tree to correspond to allocating an object of TYPE whose
-   initial value if INIT, if INIT is nonzero.  Convert the expression to
+   initial value is INIT, if INIT is nonzero.  Convert the expression to
RESULT_TYPE, which must be some type of pointer.  Return the tree.
 
GNAT_PROC and GNAT_POOL optionally give the procedure to call and
diff --git a/gcc/ada/gcc-interface/utils.cc b/gcc/ada/gcc-interface/utils.cc
index ae520542ace6..771cb1a17cad 100644
--- a/gcc/ada/gcc-interface/utils.cc
+++ b/gcc/ada/gcc-interface/utils.cc
@@ -499,7 +499,7 @@ make_dummy_type (Entity_Id gnat_type)
   if (No (gnat_equiv))
 gnat_equiv = gnat_type;
 
-  /* If it there already a dummy type, use that one.  Else make one.  */
+  /* If there is already a dummy type, use that one.  Else make one.  */
   if (PRESENT_DUMMY_NODE (gnat_equiv))
 return GET_DUMMY_NODE (gnat_equiv);
 
diff --git a/gcc/ada/gcc-interface/utils2.cc b/gcc/ada/gcc-interface/utils2.cc
index 4b7e2739f6a2..70271cf28365 100644
--- a/gcc/ada/gcc-interface/utils2.cc
+++ b/gcc/ada/gcc-interface/utils2.cc
@@ -2884,7 +2884,7 @@ gnat_protect_expr (tree exp)
   if (code == NON_LVALUE_EXPR
   || CONVERT_EXPR_CODE_P (code)
   || code == VIEW_CONVERT_EXPR)
-  return build1 (code, type, gnat_protect_expr (TREE_OPERAND (exp, 0)));
+return build1 (code, type, gnat_protect_expr (TREE_OPERAND (exp, 0)));
 
   /* If we're indirectly referencing something, we only need to protect the
  address since the data itself can't change in these situations.  */

[gcc r15-1322] ada: Do not create null GCC thunks

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:55ceb87a72fee45a9a3e547a4e688f31d376a95a

commit r15-1322-g55ceb87a72fee45a9a3e547a4e688f31d376a95a
Author: Eric Botcazou 
Date:   Mon Apr 29 09:15:13 2024 +0200

ada: Do not create null GCC thunks

This prevents Gigi from creating null GCC thunks, i.e. thunks that have all
their internal parameters set to zero, replacing them with aliases.  They
can arise in degenerate cases and null thunks would trip on an assertion in
former_thunk_p when they are later optimized.

gcc/ada/

PR ada/109817
* gcc-interface/trans.cc (maybe_make_gnu_thunk): Create an alias
instead of a null thunk.

Diff:
---
 gcc/ada/gcc-interface/trans.cc | 29 +++--
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/gcc/ada/gcc-interface/trans.cc b/gcc/ada/gcc-interface/trans.cc
index 93978c0f0ba8..5256095dfeb6 100644
--- a/gcc/ada/gcc-interface/trans.cc
+++ b/gcc/ada/gcc-interface/trans.cc
@@ -11093,6 +11093,16 @@ maybe_make_gnu_thunk (Entity_Id gnat_thunk, tree 
gnu_thunk)
   tree gnu_interface_offset
 = gnu_interface_tag ? byte_position (gnu_interface_tag) : NULL_TREE;
 
+  /* But we generate a call to the Thunk_Entity in the thunk.  */
+  tree gnu_target
+= gnat_to_gnu_entity (Thunk_Entity (gnat_thunk), NULL_TREE, false);
+
+  /* If the target is local, then thunk and target must have the same context
+ because cgraph_node::expand_thunk can only forward the static chain.  */
+  if (DECL_STATIC_CHAIN (gnu_target)
+  && DECL_CONTEXT (gnu_thunk) != DECL_CONTEXT (gnu_target))
+return false;
+
   /* There are three ways to retrieve the offset between the interface view
  and the base object.  Either the controlling type covers the interface
  type and the offset of the corresponding tag is fixed, in which case it
@@ -1,6 +11121,15 @@ maybe_make_gnu_thunk (Entity_Id gnat_thunk, tree 
gnu_thunk)
   virtual_value = 0;
   virtual_offset = NULL_TREE;
   indirect_offset = 0;
+
+  /* Do not create a null thunk, instead make it an alias.  */
+  if (fixed_offset == 0)
+   {
+ SET_DECL_ASSEMBLER_NAME (gnu_thunk, DECL_ASSEMBLER_NAME (gnu_target));
+ (void) cgraph_node::get_create (gnu_target);
+ (void) cgraph_node::create_alias (gnu_thunk, gnu_target);
+ return true;
+   }
 }
   else if (!gnu_interface_offset
   && !Is_Variable_Size_Record (gnat_controlling_type))
@@ -11132,16 +11151,6 @@ maybe_make_gnu_thunk (Entity_Id gnat_thunk, tree 
gnu_thunk)
   indirect_offset = (HOST_WIDE_INT) (POINTER_SIZE / BITS_PER_UNIT);
 }
 
-  /* But we generate a call to the Thunk_Entity in the thunk.  */
-  tree gnu_target
-= gnat_to_gnu_entity (Thunk_Entity (gnat_thunk), NULL_TREE, false);
-
-  /* If the target is local, then thunk and target must have the same context
- because cgraph_node::expand_thunk can only forward the static chain.  */
-  if (DECL_STATIC_CHAIN (gnu_target)
-  && DECL_CONTEXT (gnu_thunk) != DECL_CONTEXT (gnu_target))
-return false;
-
   /* If the target returns by invisible reference and is external, apply the
  same transformation as Subprogram_Body_to_gnu here.  */
   if (TREE_ADDRESSABLE (TREE_TYPE (gnu_target))

[gcc r15-1323] ada: Skip subprogram body entities inside scopes

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:02b7f6862723fc9f3c73a38dc9b7c518cfdf5069

commit r15-1323-g02b7f6862723fc9f3c73a38dc9b7c518cfdf5069
Author: Yannick Moy 
Date:   Fri Apr 26 17:02:52 2024 +0200

ada: Skip subprogram body entities inside scopes

Entities of kind E_Subprogram_Body, used on bodies of subprograms for
which there is a separate declaration, have been added in the entities
linked from a scope in order to get the representation information on
their enclosed object and type declarations. Skip these entities in gigi.

gcc/ada/

* gcc-interface/trans.cc (elaborate_all_entities_for_package)
(process_freeze_entity): Skip entities of kind E_Subprogram_Body.

Diff:
---
 gcc/ada/gcc-interface/trans.cc | 8 
 1 file changed, 8 insertions(+)

diff --git a/gcc/ada/gcc-interface/trans.cc b/gcc/ada/gcc-interface/trans.cc
index 5256095dfeb6..e68fb3fd7769 100644
--- a/gcc/ada/gcc-interface/trans.cc
+++ b/gcc/ada/gcc-interface/trans.cc
@@ -9321,6 +9321,10 @@ elaborate_all_entities_for_package (Entity_Id 
gnat_package)
   if (kind == E_Package_Body)
continue;
 
+  /* Skip subprogram bodies.  */
+  if (kind == E_Subprogram_Body)
+   continue;
+
   /* Skip limited views that point back to the main unit.  */
   if (IN (kind, Incomplete_Kind)
  && From_Limited_With (gnat_entity)
@@ -9427,6 +9431,10 @@ process_freeze_entity (Node_Id gnat_node)
   if (Is_Subprogram (gnat_entity) && Present (Interface_Alias (gnat_entity)))
 return;
 
+  /* Skip subprogram bodies.  */
+  if (kind == E_Subprogram_Body)
+return;
+
   /* Check for an old definition if this isn't an object with address clause,
  since the saved GCC tree is the address expression in that case.  */
   gnu_old

[gcc r15-1325] ada: Do not include target-specific makefile fragments

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:f89a68a20e37fbb7c3e2dd6a9b3450294487a550

commit r15-1325-gf89a68a20e37fbb7c3e2dd6a9b3450294487a550
Author: Eric Botcazou 
Date:   Tue May 7 11:27:57 2024 +0200

ada: Do not include target-specific makefile fragments

They are unused in this context.

gcc/ada/

* gcc-interface/Makefile.in (tmake_file): Remove all references.

Diff:
---
 gcc/ada/gcc-interface/Makefile.in | 6 --
 1 file changed, 6 deletions(-)

diff --git a/gcc/ada/gcc-interface/Makefile.in 
b/gcc/ada/gcc-interface/Makefile.in
index 0666fc00bb83..29db89c6f52c 100644
--- a/gcc/ada/gcc-interface/Makefile.in
+++ b/gcc/ada/gcc-interface/Makefile.in
@@ -148,7 +148,6 @@ host_vendor=@host_vendor@
 host_os=@host_os@
 target_cpu_default = @target_cpu_default@
 xmake_file = @xmake_file@
-tmake_file = @tmake_file@
 #version=`sed -e 's/.*\"\([^ \"]*\)[ \"].*/\1/' < $(srcdir)/version.c`
 #mainversion=`sed -e 's/.*\"\([0-9]*\.[0-9]*\).*/\1/' < $(srcdir)/version.c`
 
@@ -209,11 +208,6 @@ all: all.indirect
 # This tells GNU Make version 3 not to put all variables in the environment.
 .NOEXPORT:
 
-# target overrides
-ifneq ($(tmake_file),)
-include $(tmake_file)
-endif
-
 # host overrides
 ifneq ($(xmake_file),)
 include $(xmake_file)

[gcc r15-1324] ada: Fix return mechanism reported by -gnatRm

[Marc Poulhi?s via Gcc-cvs]

https://gcc.gnu.org/g:83061c80d29f71b1aa07664fd129af6542c9fc83

commit r15-1324-g83061c80d29f71b1aa07664fd129af6542c9fc83
Author: Eric Botcazou 
Date:   Mon Apr 29 09:48:48 2024 +0200

ada: Fix return mechanism reported by -gnatRm

The return mechanism of functions is reported when the -gnatRm switch is
specified, but it is incorrect when the result type is not a by-reference
type in the language sense but is nevertheless returned by reference.

gcc/ada/

* gcc-interface/decl.cc: Include function.h.
(gnat_to_gnu_param): Minor comment tweaks.
(gnat_to_gnu_subprog_type): Take into account the default for the
computation of the return mechanism.  Give a warning if a by-copy
specified mechanism cannot be honored.

Diff:
---
 gcc/ada/gcc-interface/decl.cc | 34 +++---
 1 file changed, 27 insertions(+), 7 deletions(-)

diff --git a/gcc/ada/gcc-interface/decl.cc b/gcc/ada/gcc-interface/decl.cc
index 239837426059..aa31a18f 100644
--- a/gcc/ada/gcc-interface/decl.cc
+++ b/gcc/ada/gcc-interface/decl.cc
@@ -27,6 +27,7 @@
 #include "system.h"
 #include "coretypes.h"
 #include "target.h"
+#include "function.h"
 #include "tree.h"
 #include "gimple-expr.h"
 #include "stringpool.h"
@@ -5703,6 +5704,7 @@ gnat_to_gnu_param (Entity_Id gnat_param, tree 
gnu_param_type, bool first,
 
   input_location = saved_location;
 
+  /* Warn if we are asked to pass by copy but cannot.  */
   if (mech == By_Copy && (by_ref || by_component_ptr))
 post_error ("??cannot pass & by copy", gnat_param);
 
@@ -5735,12 +5737,13 @@ gnat_to_gnu_param (Entity_Id gnat_param, tree 
gnu_param_type, bool first,
   DECL_RESTRICTED_ALIASING_P (gnu_param) = restricted_aliasing_p;
   Sloc_to_locus (Sloc (gnat_param), &DECL_SOURCE_LOCATION (gnu_param));
 
-  /* If no Mechanism was specified, indicate what we're using, then
- back-annotate it.  */
+  /* If no Mechanism was specified, indicate what we will use.  */
   if (mech == Default)
 mech = (by_ref || by_component_ptr) ? By_Reference : By_Copy;
 
+  /* Back-annotate the mechanism in all cases.  */
   Set_Mechanism (gnat_param, mech);
+
   return gnu_param;
 }
 
@@ -6129,11 +6132,6 @@ gnat_to_gnu_subprog_type (Entity_Id gnat_subprog, bool 
definition,
  associate_subprog_with_dummy_type (gnat_subprog, gnu_return_type);
  incomplete_profile_p = true;
}
-
-  if (kind == E_Function)
-   Set_Mechanism (gnat_subprog, return_by_direct_ref_p
-|| return_by_invisi_ref_p
-? By_Reference : By_Copy);
 }
 
   /* A procedure (something that doesn't return anything) shouldn't be
@@ -6636,6 +6634,28 @@ gnat_to_gnu_subprog_type (Entity_Id gnat_subprog, bool 
definition,
  if (warn_shadow)
post_error ("'G'C'C builtin not found for&!??", gnat_subprog);
}
+
+  /* Finally deal with the return mechanism for a function.  */
+  if (kind == E_Function)
+   {
+ /* We return by reference either if this is required by the semantics
+of the language or if this is the default for the function.  */
+ const bool by_ref = return_by_direct_ref_p
+ || return_by_invisi_ref_p
+ || aggregate_value_p (gnu_return_type, gnu_type);
+ Mechanism_Type mech = Mechanism (gnat_subprog);
+
+ /* Warn if we are asked to return by copy but cannot.  */
+ if (mech == By_Copy && by_ref)
+   post_error ("??cannot return from & by copy", gnat_subprog);
+
+ /* If no mechanism was specified, indicate what we will use.  */
+ if (mech == Default)
+   mech = by_ref ? By_Reference : By_Copy;
+
+ /* Back-annotate the mechanism in all cases.  */
+ Set_Mechanism (gnat_subprog, mech);
+   }
 }
 
   *param_list = gnu_param_list;

[gcc r15-1326] doc: Remove reference to Interix

[Gerald Pfeifer via Gcc-cvs]

https://gcc.gnu.org/g:35d9b2c0d94d727a0e9be3aa9679a39077c97b1b

commit r15-1326-g35d9b2c0d94d727a0e9be3aa9679a39077c97b1b
Author: Gerald Pfeifer 
Date:   Fri Jun 14 09:52:27 2024 +0200

doc: Remove reference to Interix

This apparently was missed when support for Interix was removed in 2016.

gcc:
PR target/69374
* doc/install.texi (Specific): Remove stale reference to Interix.

Diff:
---
 gcc/doc/install.texi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 0baba5e594dc..38c93f067b55 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -5178,8 +5178,7 @@ SuperH (sh-wince-pe), and MIPS (mips-wince-pe).
 @subheading Other Windows Platforms
 GCC no longer supports Windows NT on the Alpha or PowerPC.
 
-GCC no longer supports the Windows POSIX subsystem.  However, it does
-support the Interix subsystem.  See above.
+GCC no longer supports the Windows POSIX subsystem.
 
 Old target names including *-*-winnt and *-*-windowsnt are no longer used.

[gcc r15-1327] RISC-V: Bugfix vec_extract v mode iterator restriction mismatch

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:c2c61d8902dbda017b1647252d17bce141493433

commit r15-1327-gc2c61d8902dbda017b1647252d17bce141493433
Author: Pan Li 
Date:   Fri Jun 14 14:54:22 2024 +0800

RISC-V: Bugfix vec_extract v mode iterator restriction mismatch

We have vec_extract pattern which takes ZVFHMIN as the mode
iterator of the V mode.  Aka VF_ZVFHMIN iterator.  But it will
expand to pred_extract_first pattern which takes the ZVFH as the mode
iterator of the V mode.  AKa VF.  The mismatch will result in one ICE
similar as below:

insn 30 29 31 2 (set (reg:HF 156 [ _2 ])
(unspec:HF [
(vec_select:HF (reg:RVVMF2HF 134 [ _1 ])
(parallel [
(const_int 0 [0])
]))
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)) "compress_run-2.c":22:3 -1
 (nil))
during RTL pass: vregs
compress_run-2.c:25:1: internal compiler error: in extract_insn, at
recog.cc:2812
0xb3bc47 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
../../../gcc/gcc/rtl-error.cc:108
0xb3bc69 _fatal_insn_not_found(rtx_def const*, char const*, int, char
const*)
../../../gcc/gcc/rtl-error.cc:116
0xb3a545 extract_insn(rtx_insn*)
../../../gcc/gcc/recog.cc:2812
0x1010e9e instantiate_virtual_regs_in_insn
../../../gcc/gcc/function.cc:1612
0x1010e9e instantiate_virtual_regs
../../../gcc/gcc/function.cc:1995
0x1010e9e execute
../../../gcc/gcc/function.cc:2042

The below test suites are passed for this patch.
1. The rv64gcv fully regression test.
2. The rv64gcv build with glibc.

There may be other similar issue(s) for the mismatch,  we will take care
of them by test cases one by one.

PR target/115456

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Leverage V_ZVFH instead of V
which contains the VF_ZVFHMIN for alignment.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pr115456-2.c: New test.
* gcc.target/riscv/rvv/base/pr115456-3.c: New test.

Signed-off-by: Pan Li 

Diff:
---
 gcc/config/riscv/vector-iterators.md   |  4 ++-
 .../gcc.target/riscv/rvv/base/pr115456-2.c | 31 ++
 .../gcc.target/riscv/rvv/base/pr115456-3.c | 31 ++
 3 files changed, 65 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index 47392d0da4c1..43137a2a379b 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -1578,9 +1578,11 @@
 
 (define_mode_iterator V [VI VF_ZVFHMIN])
 
+(define_mode_iterator V_ZVFH [VI VF])
+
 (define_mode_iterator V_VLS [V VLS])
 
-(define_mode_iterator V_VLS_ZVFH [V VLS_ZVFH])
+(define_mode_iterator V_VLS_ZVFH [V_ZVFH VLS_ZVFH])
 
 (define_mode_iterator V_VLSI [VI VLSI])
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c
new file mode 100644
index ..453e18b1c79c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c
@@ -0,0 +1,31 @@
+/* Test there is no ICE when compile.  */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfhmin -mrvv-vector-bits=zvl -mabi=lp64d -O3 
-ftree-vectorize" } */
+
+#include 
+#include 
+
+typedef _Float16 vnx4f __attribute__ ((vector_size (8)));
+
+vnx4f __attribute__ ((noinline, noclone))
+test_5 (vnx4f x, vnx4f y)
+{
+  return __builtin_shufflevector (x, y, 1, 3, 6, 7);
+}
+
+int
+main (void)
+{
+  vnx4f test_5_x = {0, 1, 3, 4};
+  vnx4f test_5_y = {4, 5, 6, 7};
+  vnx4f test_5_except = {1, 4, 6, 7};
+  vnx4f test_5_real;
+  test_5_real = test_5 (test_5_x, test_5_y);
+
+  for (int i = 0; i < 4; i++)
+assert (test_5_real[i] == test_5_except[i]);
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {call\s+__extendhfsf2} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c
new file mode 100644
index ..2c54f1d75387
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize" } */
+
+#include 
+#include 
+
+typedef _Float16 vnx4f __attribute__ ((vector_size (8)));
+
+vnx4f __attribute__ ((noinline, noclone))
+test_5 (vnx4f x, vnx4f y)
+{
+  return __builtin_shufflevector (x, y, 1, 3, 6, 7);
+}
+
+int
+main (void)
+{
+  vnx4f test_5_x = {0, 1, 3, 4};
+  vnx4f test_5_y = {4, 5, 6, 7};
+  vnx4f test_5_except = {1, 4, 6, 7};
+  vnx4f test_5_real;
+  test_5_real = test_5 (test_5_x, test_5_y);
+
+  for (int i = 0; i < 4; i++)
+assert (test_5_real[i] == test_5_except[i]);
+
+  return 0;
+}
+
+/* {

[gcc r15-1328] doc: Consolidate duplicate MOVBE listings for Intel CPUs

[Gerald Pfeifer via Gcc-cvs]

https://gcc.gnu.org/g:aa85a5a6792a79c28a8ee19dc5d0f01b2930c33d

commit r15-1328-gaa85a5a6792a79c28a8ee19dc5d0f01b2930c33d
Author: Gerald Pfeifer 
Date:   Fri Jun 14 10:07:37 2024 +0200

doc: Consolidate duplicate MOVBE listings for Intel CPUs

gcc:
* doc/invoke.texi (x86 Options): Consolidate duplicate MOVBE
listings for haswell, broadwell, skylake, skylake-avx512,
cannonlake, icelake-client, icelake-server, cascadelake,
cooperlake, tigerlake, sapphirerapids, rocketlake, graniterapids,
and graniterapids-d options to -march.

Diff:
---
 gcc/doc/invoke.texi | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 26e6a349d51d..5d7a87fde86c 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -34476,18 +34476,18 @@ SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, 
PCLMUL, FSGSBASE, RDRND
 and F16C instruction set support.
 
 @item haswell
-Intel Haswell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+Intel Haswell CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,
 F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE and HLE instruction set support.
 
 @item broadwell
-Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+Intel Broadwell CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,
 F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX and PREFETCHW
 instruction set support.
 
 @item skylake
-Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+Intel Skylake CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,
 F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES,
 CLFLUSHOPT, XSAVEC, XSAVES and SGX instruction set support.
@@ -34548,14 +34548,14 @@ ENQCMD, UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, 
CMPCCXADD, AVXVNNIINT16,
 SHA512, SM3, SM4, USER_MSR and PREFETCHI instruction set support.
 
 @item skylake-avx512
-Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
+Intel Skylake Server CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3,
 SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE,
 RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW,
 AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, CLWB, AVX512VL, AVX512BW,
 AVX512DQ and AVX512CD instruction set support.
 
 @item cannonlake
-Intel Cannonlake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
+Intel Cannonlake Server CPU with 64-bit extensions, MMX, SSE, SSE2,
 SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL,
 FSGSBASE, RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX,
 PREFETCHW, AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW,
@@ -34563,7 +34563,7 @@ AVX512DQ, AVX512CD, PKU, AVX512VBMI, AVX512IFMA and SHA 
instruction set
 support.
 
 @item icelake-client
-Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
+Intel Icelake Client CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3,
 SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE,
 RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW,
 AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ,
@@ -34571,7 +34571,7 @@ AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, 
GFNI, VAES, AVX512VBMI2
 , VPCLMULQDQ, AVX512BITALG, RDPID and AVX512VPOPCNTDQ instruction set support.
 
 @item icelake-server
-Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
+Intel Icelake Server CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3,
 SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE,
 RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW,
 AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ,
@@ -34580,21 +34580,21 @@ AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, 
AVX512VNNI, GFNI, VAES, AVX512VBMI2
 instruction set support.
 
 @item cascadelake
-Intel Cascadelake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, 
SSSE3,
+Intel Cascadelake CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,
 F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES,
 CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, CLWB, AVX512VL, AVX512BW, AVX512DQ,
 AVX512CD and AVX512VNNI instruction set support.
 
 @item cooperlake
-Intel cooperlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, 
SSSE3,
+Intel cooperlake CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE

[gcc r15-1329] Support single def-use cycle optimization for SLP reduction vectorization

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:d66b820f392aa9a7c34d3cddaf3d7c73bf23f82d

commit r15-1329-gd66b820f392aa9a7c34d3cddaf3d7c73bf23f82d
Author: Richard Biener 
Date:   Thu Jun 13 14:42:25 2024 +0200

Support single def-use cycle optimization for SLP reduction vectorization

We can at least mimic single def-use cycle optimization when doing
single-lane SLP reductions and that's required to avoid regressing
compared to non-SLP.

* tree-vect-loop.cc (vectorizable_reduction): Allow
single-def-use cycles with SLP.
(vect_transform_reduction): Handle SLP single def-use cycles.
(vect_transform_cycle_phi): Likewise.

* gcc.dg/vect/slp-reduc-12.c: New testcase.

Diff:
---
 gcc/testsuite/gcc.dg/vect/slp-reduc-12.c | 18 +
 gcc/tree-vect-loop.cc| 45 +++-
 2 files changed, 45 insertions(+), 18 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/slp-reduc-12.c 
b/gcc/testsuite/gcc.dg/vect/slp-reduc-12.c
new file mode 100644
index ..625f8097c545
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/slp-reduc-12.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target vect_double } */
+/* { dg-require-effective-target vect_int } */
+/* { dg-require-effective-target vect_hw_misalign } */
+/* { dg-additional-options "-Ofast" } */
+
+double foo (double *x, int * __restrict a, int n)
+{
+  double r = 0.;
+  for (int i = 0; i < n; ++i)
+{
+  a[i] = a[i] + i;
+  r += x[i];
+}
+  return r;
+}
+
+/* { dg-final { scan-tree-dump "using single def-use cycle for reduction" 
"vect" } } */
diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index bbd5d261907c..d9a2ad694843 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -8320,7 +8320,11 @@ vectorizable_reduction (loop_vec_info loop_vinfo,
participating.  When unrolling we want each unrolled iteration to have its
own reduction accumulator since one of the main goals of unrolling a
reduction is to reduce the aggregate loop-carried latency.  */
-  if (ncopies > 1
+  if ((ncopies > 1
+   || (slp_node
+  && !REDUC_GROUP_FIRST_ELEMENT (stmt_info)
+  && SLP_TREE_LANES (slp_node) == 1
+  && vect_get_num_copies (loop_vinfo, vectype_in) > 1))
   && (STMT_VINFO_RELEVANT (stmt_info) <= vect_used_only_live)
   && reduc_chain_length == 1
   && loop_vinfo->suggested_unroll_factor == 1)
@@ -8373,6 +8377,10 @@ vectorizable_reduction (loop_vec_info loop_vinfo,
single_defuse_cycle = false;
}
 }
+  if (dump_enabled_p () && single_defuse_cycle)
+dump_printf_loc (MSG_NOTE, vect_location,
+"using single def-use cycle for reduction by reducing "
+"multiple vectors to one in the loop body\n");
   STMT_VINFO_FORCE_SINGLE_CYCLE (reduc_info) = single_defuse_cycle;
 
   /* If the reduction stmt is one of the patterns that have lane
@@ -8528,9 +8536,8 @@ vect_transform_reduction (loop_vec_info loop_vinfo,
 {
   tree vectype_out = STMT_VINFO_VECTYPE (stmt_info);
   class loop *loop = LOOP_VINFO_LOOP (loop_vinfo);
-  int i;
-  int ncopies;
-  int vec_num;
+  unsigned ncopies;
+  unsigned vec_num;
 
   stmt_vec_info reduc_info = info_for_reduction (loop_vinfo, stmt_info);
   gcc_assert (reduc_info->is_reduc_info);
@@ -8577,7 +8584,6 @@ vect_transform_reduction (loop_vec_info loop_vinfo,
   auto_vec vec_oprnds0;
   auto_vec vec_oprnds1;
   auto_vec vec_oprnds2;
-  tree def0;
 
   if (dump_enabled_p ())
 dump_printf_loc (MSG_NOTE, vect_location, "transform reduction.\n");
@@ -8652,20 +8658,21 @@ vect_transform_reduction (loop_vec_info loop_vinfo,
  definition.  */
   if (single_defuse_cycle)
 {
-  gcc_assert (!slp_node);
-  vect_get_vec_defs_for_operand (loop_vinfo, stmt_info, 1,
-op.ops[reduc_index],
-reduc_index == 0 ? &vec_oprnds0
-: (reduc_index == 1 ? &vec_oprnds1
-   : &vec_oprnds2));
+  vect_get_vec_defs (loop_vinfo, stmt_info, slp_node, 1,
+reduc_index == 0 ? op.ops[0] : NULL_TREE, &vec_oprnds0,
+reduc_index == 1 ? op.ops[1] : NULL_TREE, &vec_oprnds1,
+reduc_index == 2 ? op.ops[2] : NULL_TREE,
+&vec_oprnds2);
 }
 
   bool emulated_mixed_dot_prod = vect_is_emulated_mixed_dot_prod (stmt_info);
 
-  FOR_EACH_VEC_ELT (vec_oprnds0, i, def0)
+  unsigned num = (reduc_index == 0
+ ? vec_oprnds1.length () : vec_oprnds0.length ());
+  for (unsigned i = 0; i < num; ++i)
 {
   gimple *new_stmt;
-  tree vop[3] = { def0, vec_oprnds1[i], NULL_TREE };
+  tree vop[3] = { vec_oprnds0[i], vec_oprnds1[i], NULL_TREE };
   if (masked_loop_p && !mask_by_cond_expr)
{
  /* No conditional ifns have been define

[gcc r15-1330] Adjust gcc.target/i386/vect-strided-3.c

[Richard Biener via Gcc-cvs]

https://gcc.gnu.org/g:1438b15e5430f7fab3832c35d262d6b58caba469

commit r15-1330-g1438b15e5430f7fab3832c35d262d6b58caba469
Author: Richard Biener 
Date:   Fri Jun 14 11:31:53 2024 +0200

Adjust gcc.target/i386/vect-strided-3.c

The following disables SSE4 instead of just AVX to avoid
pextrq being used, confusing the assembler scanning.  This
avoids the reported failure with -march=cascadelake but adds
a FAIL for -march=cascadelake -m32 (I've opened PR115487 for that).

* gcc.target/i386/vect-strided-3.c: Disable SSE4 instead of AVX.

Diff:
---
 gcc/testsuite/gcc.target/i386/vect-strided-3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/i386/vect-strided-3.c 
b/gcc/testsuite/gcc.target/i386/vect-strided-3.c
index b462701a0b2e..f9c54a6f7159 100644
--- a/gcc/testsuite/gcc.target/i386/vect-strided-3.c
+++ b/gcc/testsuite/gcc.target/i386/vect-strided-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -msse2 -mno-avx -fno-tree-slp-vectorize" } */
+/* { dg-options "-O2 -msse2 -mno-sse4 -fno-tree-slp-vectorize" } */
 
 void foo (int * __restrict a, int *b, int s)
 {

[gcc r15-1331] configure: adjustments for building with in-tree binutils

[Jan Beulich via Gcc-cvs]

https://gcc.gnu.org/g:4b1f486fefb3969f35ff6d49f544eb0ac9f49f1f

commit r15-1331-g4b1f486fefb3969f35ff6d49f544eb0ac9f49f1f
Author: Jan Beulich 
Date:   Fri Jun 14 13:28:40 2024 +0200

configure: adjustments for building with in-tree binutils

For one setting ld_ver in a conditional (no in-tree ld) when it's used,
for x86 at least, in unconditional ways can't be quite right. And then
prefixing relative paths to binaries with ${objdir}/, when ${objdir}
nowadays resolves to just .libs, can at best be a leftover that wasn't
properly cleaned up at some earlier point.

gcc/

* configure.ac: Drop ${objdir}/ from NM and AR. Move setting of
ld_ver out of conditional.
* configure: Re-generate.

Diff:
---
 gcc/configure| 6 +++---
 gcc/configure.ac | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/configure b/gcc/configure
index aaf5899cc039..94970e24051f 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -9066,7 +9066,7 @@ fi
 # NM
 if test x${build} = x${host} && test -f $srcdir/../binutils/nm.c \
   && test -d ../binutils ; then
-  NM='${objdir}/../binutils/nm-new'
+  NM='../binutils/nm-new'
 else
   # Extract the first word of "nm", so it can be a program name with args.
 set dummy nm; ac_word=$2
@@ -9111,7 +9111,7 @@ fi
 # AR
 if test x${build} = x${host} && test -f $srcdir/../binutils/ar.c \
   && test -d ../binutils ; then
-  AR='${objdir}/../binutils/ar'
+  AR='../binutils/ar'
 else
   # Extract the first word of "ar", so it can be a program name with args.
 set dummy ar; ac_word=$2
@@ -25919,8 +25919,8 @@ _ACEOF
 
 
 
+ld_ver=`$gcc_cv_ld --version 2>/dev/null | sed 1q`
 if test $in_tree_ld != yes ; then
-  ld_ver=`$gcc_cv_ld --version 2>/dev/null | sed 1q`
   if echo "$ld_ver" | grep GNU > /dev/null; then
 if test x"$ld_is_gold" = xyes; then
   # GNU gold --version looks like this:
diff --git a/gcc/configure.ac b/gcc/configure.ac
index f8d67efeb988..35475cf5aae3 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -1320,7 +1320,7 @@ AC_SUBST(HAVE_PYTHON)
 # NM
 if test x${build} = x${host} && test -f $srcdir/../binutils/nm.c \
   && test -d ../binutils ; then
-  NM='${objdir}/../binutils/nm-new'
+  NM='../binutils/nm-new'
 else
   AC_CHECK_PROG(NM, nm, nm, ${CONFIG_SHELL-/bin/sh} ${srcdir}/../missing nm)
 fi
@@ -1328,7 +1328,7 @@ fi
 # AR
 if test x${build} = x${host} && test -f $srcdir/../binutils/ar.c \
   && test -d ../binutils ; then
-  AR='${objdir}/../binutils/ar'
+  AR='../binutils/ar'
 else
   AC_CHECK_PROG(AR, ar, ar, ${CONFIG_SHELL-/bin/sh} ${srcdir}/../missing ar)
 fi
@@ -3108,8 +3108,8 @@ AC_DEFINE_UNQUOTED(HAVE_GNU_INDIRECT_FUNCTION, $gif,
 
 
 changequote(,)dnl
+ld_ver=`$gcc_cv_ld --version 2>/dev/null | sed 1q`
 if test $in_tree_ld != yes ; then
-  ld_ver=`$gcc_cv_ld --version 2>/dev/null | sed 1q`
   if echo "$ld_ver" | grep GNU > /dev/null; then
 if test x"$ld_is_gold" = xyes; then
   # GNU gold --version looks like this:

[gcc r15-1334] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:d0f6a1ea5363662e01c5b735fe4b19cac4c1caf2

commit r15-1334-gd0f6a1ea5363662e01c5b735fe4b19cac4c1caf2
Author: Pan Li 
Date:   Thu Jun 13 22:35:21 2024 +0800

RISC-V: Add testcases for scalar unsigned SAT_SUB form 4

After the middle-end support the form 4 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 4 of unsigned .SAT_SUB.

Form 4:
  #define SAT_SUB_U_4(T) \
  T sat_sub_u_4_##T (T x, T y) \
  { \
return x >= y ? x - y : 0; \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-13.c: New test.
* gcc.target/riscv/sat_u_sub-14.c: New test.
* gcc.target/riscv/sat_u_sub-15.c: New test.
* gcc.target/riscv/sat_u_sub-16.c: New test.
* gcc.target/riscv/sat_u_sub-run-13.c: New test.
* gcc.target/riscv/sat_u_sub-run-14.c: New test.
* gcc.target/riscv/sat_u_sub-run-15.c: New test.
* gcc.target/riscv/sat_u_sub-run-16.c: New test.

Signed-off-by: Pan Li 

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h|  8 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-13.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-14.c | 19 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-16.c | 17 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-13.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-14.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-15.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-16.c | 25 +++
 9 files changed, 180 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 50c65cdea495..b2f8478d36b6 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -99,9 +99,17 @@ sat_u_sub_##T##_fmt_3 (T x, T y)  \
   return x > y ? x - y : 0;   \
 }
 
+#define DEF_SAT_U_SUB_FMT_4(T)   \
+T __attribute__((noinline))  \
+sat_u_sub_##T##_fmt_4 (T x, T y) \
+{\
+  return x >= y ? x - y : 0; \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
 #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
+#define RUN_SAT_U_SUB_FMT_4(T, x, y) sat_u_sub_##T##_fmt_4(x, y)
 
 #define DEF_VEC_SAT_U_SUB_FMT_1(T)   \
 void __attribute__((noinline))   \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-13.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-13.c
new file mode 100644
index ..edb7017f9b1d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-13.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_4:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_4(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-14.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-14.c
new file mode 100644
index ..2aab9f65586b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-14.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_4:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_4(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c
new file mode 100644
index ..25ad702bf046
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-15.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arit

[gcc r15-1335] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:bfe92c70821bc21df5befae3a39fe6ab31d2cbb4

commit r15-1335-gbfe92c70821bc21df5befae3a39fe6ab31d2cbb4
Author: Pan Li 
Date:   Thu Jun 13 22:43:31 2024 +0800

RISC-V: Add testcases for scalar unsigned SAT_SUB form 5

After the middle-end support the form 5 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 5 of unsigned .SAT_SUB.

Form 5:
  #define SAT_SUB_U_5(T) \
  T sat_sub_u_5_##T (T x, T y) \
  { \
return x < y ? 0 : x - y; \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-17.c: New test.
* gcc.target/riscv/sat_u_sub-18.c: New test.
* gcc.target/riscv/sat_u_sub-19.c: New test.
* gcc.target/riscv/sat_u_sub-20.c: New test.
* gcc.target/riscv/sat_u_sub-run-17.c: New test.
* gcc.target/riscv/sat_u_sub-run-18.c: New test.
* gcc.target/riscv/sat_u_sub-run-19.c: New test.
* gcc.target/riscv/sat_u_sub-run-20.c: New test.

Signed-off-by: Pan Li 

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h|  8 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c | 19 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-20.c | 17 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-17.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-18.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-19.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-20.c | 25 +++
 9 files changed, 180 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index b2f8478d36b6..d08755dd8613 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -106,10 +106,18 @@ sat_u_sub_##T##_fmt_4 (T x, T y) \
   return x >= y ? x - y : 0; \
 }
 
+#define DEF_SAT_U_SUB_FMT_5(T)   \
+T __attribute__((noinline))  \
+sat_u_sub_##T##_fmt_5 (T x, T y) \
+{\
+  return x < y ? 0 : x - y;  \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
 #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
 #define RUN_SAT_U_SUB_FMT_4(T, x, y) sat_u_sub_##T##_fmt_4(x, y)
+#define RUN_SAT_U_SUB_FMT_5(T, x, y) sat_u_sub_##T##_fmt_5(x, y)
 
 #define DEF_VEC_SAT_U_SUB_FMT_1(T)   \
 void __attribute__((noinline))   \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c
new file mode 100644
index ..853ddcfd285c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-17.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_5:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_5(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c
new file mode 100644
index ..423a6f821703
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-18.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_5:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_5(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c
new file mode 100644
index ..29b9c235d976
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-19.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-

[gcc r15-1337] RISC-V: Add testcases for scalar unsigned SAT_SUB form 7

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:1d37b81cbfb4b5ead7112855ef6c215ad1042456

commit r15-1337-g1d37b81cbfb4b5ead7112855ef6c215ad1042456
Author: Pan Li 
Date:   Fri Jun 14 09:49:22 2024 +0800

RISC-V: Add testcases for scalar unsigned SAT_SUB form 7

After the middle-end support the form 7 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 7 of unsigned .SAT_SUB.

Form 7:
  #define SAT_SUB_U_7(T) \
  T sat_sub_u_7_##T (T x, T y) \
  { \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return ret & (T)(overflow - 1); \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-25.c: New test.
* gcc.target/riscv/sat_u_sub-26.c: New test.
* gcc.target/riscv/sat_u_sub-27.c: New test.
* gcc.target/riscv/sat_u_sub-28.c: New test.
* gcc.target/riscv/sat_u_sub-run-25.c: New test.
* gcc.target/riscv/sat_u_sub-run-26.c: New test.
* gcc.target/riscv/sat_u_sub-run-27.c: New test.
* gcc.target/riscv/sat_u_sub-run-28.c: New test.

Signed-off-by: Pan Li 

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h| 10 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-25.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-26.c | 19 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-27.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-28.c | 17 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-25.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-26.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-27.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-28.c | 25 +++
 9 files changed, 182 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 4296235cf628..bde054d5c9d9 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -120,12 +120,22 @@ sat_u_sub_##T##_fmt_6 (T x, T y) \
   return x <= y ? 0 : x - y; \
 }
 
+#define DEF_SAT_U_SUB_FMT_7(T)  \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_7 (T x, T y)\
+{   \
+  T ret;\
+  T overflow = __builtin_sub_overflow (x, y, &ret); \
+  return ret & (T)(overflow - 1);   \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
 #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
 #define RUN_SAT_U_SUB_FMT_4(T, x, y) sat_u_sub_##T##_fmt_4(x, y)
 #define RUN_SAT_U_SUB_FMT_5(T, x, y) sat_u_sub_##T##_fmt_5(x, y)
 #define RUN_SAT_U_SUB_FMT_6(T, x, y) sat_u_sub_##T##_fmt_6(x, y)
+#define RUN_SAT_U_SUB_FMT_7(T, x, y) sat_u_sub_##T##_fmt_7(x, y)
 
 #define DEF_VEC_SAT_U_SUB_FMT_1(T)   \
 void __attribute__((noinline))   \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-25.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-25.c
new file mode 100644
index ..8780ef0c8f11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-25.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_7:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_7(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-26.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-26.c
new file mode 100644
index ..f720f619d097
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-26.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_7:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_7(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB 

[gcc r15-1339] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:40609350e77d3fd4fac9787ff5066d723c7a6329

commit r15-1339-g40609350e77d3fd4fac9787ff5066d723c7a6329
Author: Pan Li 
Date:   Fri Jun 14 10:03:15 2024 +0800

RISC-V: Add testcases for scalar unsigned SAT_SUB form 9

After the middle-end support the form 9 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 9 of unsigned .SAT_SUB.

Form 9:
  #define SAT_SUB_U_9(T) \
  T sat_sub_u_9_##T (T x, T y) \
  { \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-33.c: New test.
* gcc.target/riscv/sat_u_sub-34.c: New test.
* gcc.target/riscv/sat_u_sub-35.c: New test.
* gcc.target/riscv/sat_u_sub-36.c: New test.
* gcc.target/riscv/sat_u_sub-run-33.c: New test.
* gcc.target/riscv/sat_u_sub-run-34.c: New test.
* gcc.target/riscv/sat_u_sub-run-35.c: New test.
* gcc.target/riscv/sat_u_sub-run-36.c: New test.

Signed-off-by: Pan Li 

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h| 10 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c | 19 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c | 17 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-33.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-34.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-35.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-36.c | 25 +++
 9 files changed, 182 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 9f901de5cdfd..ecb74e56e9ca 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -138,6 +138,15 @@ sat_u_sub_##T##_fmt_8 (T x, T y)\
   return ret & (T)-(!overflow); \
 }
 
+#define DEF_SAT_U_SUB_FMT_9(T)  \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_9 (T x, T y)\
+{   \
+  T ret;\
+  T overflow = __builtin_sub_overflow (x, y, &ret); \
+  return overflow ? 0 : ret;\
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
 #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -146,6 +155,7 @@ sat_u_sub_##T##_fmt_8 (T x, T y)\
 #define RUN_SAT_U_SUB_FMT_6(T, x, y) sat_u_sub_##T##_fmt_6(x, y)
 #define RUN_SAT_U_SUB_FMT_7(T, x, y) sat_u_sub_##T##_fmt_7(x, y)
 #define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
+#define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
 
 #define DEF_VEC_SAT_U_SUB_FMT_1(T)   \
 void __attribute__((noinline))   \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c
new file mode 100644
index ..aca4bd28b5de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_9:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_9(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c
new file mode 100644
index ..f87a51a504be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_9:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a

[gcc r15-1338] RISC-V: Add testcases for scalar unsigned SAT_SUB form 8

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:6d73bb157a7ddc8fe42fc2cb31f3e2371162a228

commit r15-1338-g6d73bb157a7ddc8fe42fc2cb31f3e2371162a228
Author: Pan Li 
Date:   Fri Jun 14 09:57:22 2024 +0800

RISC-V: Add testcases for scalar unsigned SAT_SUB form 8

After the middle-end support the form 8 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 8 of unsigned .SAT_SUB.

Form 8:
  #define SAT_SUB_U_8(T) \
  T sat_sub_u_8_##T (T x, T y) \
  { \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return ret & (T)-(!overflow); \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-29.c: New test.
* gcc.target/riscv/sat_u_sub-30.c: New test.
* gcc.target/riscv/sat_u_sub-31.c: New test.
* gcc.target/riscv/sat_u_sub-32.c: New test.
* gcc.target/riscv/sat_u_sub-run-29.c: New test.
* gcc.target/riscv/sat_u_sub-run-30.c: New test.
* gcc.target/riscv/sat_u_sub-run-31.c: New test.
* gcc.target/riscv/sat_u_sub-run-32.c: New test.

Signed-off-by: Pan Li 

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h| 10 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-29.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-30.c | 19 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-31.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-32.c | 17 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-29.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-30.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-31.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-32.c | 25 +++
 9 files changed, 182 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index bde054d5c9d9..9f901de5cdfd 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -129,6 +129,15 @@ sat_u_sub_##T##_fmt_7 (T x, T y)\
   return ret & (T)(overflow - 1);   \
 }
 
+#define DEF_SAT_U_SUB_FMT_8(T)  \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_8 (T x, T y)\
+{   \
+  T ret;\
+  T overflow = __builtin_sub_overflow (x, y, &ret); \
+  return ret & (T)-(!overflow); \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
 #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -136,6 +145,7 @@ sat_u_sub_##T##_fmt_7 (T x, T y)\
 #define RUN_SAT_U_SUB_FMT_5(T, x, y) sat_u_sub_##T##_fmt_5(x, y)
 #define RUN_SAT_U_SUB_FMT_6(T, x, y) sat_u_sub_##T##_fmt_6(x, y)
 #define RUN_SAT_U_SUB_FMT_7(T, x, y) sat_u_sub_##T##_fmt_7(x, y)
+#define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
 
 #define DEF_VEC_SAT_U_SUB_FMT_1(T)   \
 void __attribute__((noinline))   \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-29.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-29.c
new file mode 100644
index ..1a2da50256e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-29.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_8:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_8(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-30.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-30.c
new file mode 100644
index ..75aa75063690
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-30.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_8:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\

[gcc r15-1332] Match: Support more forms for the scalar unsigned .SAT_SUB

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:869af0255b648727fbd45fd3da4225069cbcb86d

commit r15-1332-g869af0255b648727fbd45fd3da4225069cbcb86d
Author: Pan Li 
Date:   Wed Jun 12 14:28:09 2024 +0800

Match: Support more forms for the scalar unsigned .SAT_SUB

After we support the scalar unsigned form 1 and 2,  we would like
to introduce more forms include the branch and branchless.  There
are forms 3-10 list as below:

Form 3:
  #define SAT_SUB_U_3(T) \
  T sat_sub_u_3_##T (T x, T y) \
  { \
return x > y ? x - y : 0; \
  }

Form 4:
  #define SAT_SUB_U_4(T) \
  T sat_sub_u_4_##T (T x, T y) \
  { \
return x >= y ? x - y : 0; \
  }

Form 5:
  #define SAT_SUB_U_5(T) \
  T sat_sub_u_5_##T (T x, T y) \
  { \
return x < y ? 0 : x - y; \
  }

Form 6:
  #define SAT_SUB_U_6(T) \
  T sat_sub_u_6_##T (T x, T y) \
  { \
return x <= y ? 0 : x - y; \
  }

Form 7:
  #define SAT_SUB_U_7(T) \
  T sat_sub_u_7_##T (T x, T y) \
  { \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return ret & (T)(overflow - 1); \
  }

Form 8:
  #define SAT_SUB_U_8(T) \
  T sat_sub_u_8_##T (T x, T y) \
  { \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return ret & (T)-(!overflow); \
  }

Form 9:
  #define SAT_SUB_U_9(T) \
  T sat_sub_u_9_##T (T x, T y) \
  { \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
  }

Form 10:
  #define SAT_SUB_U_10(T) \
  T sat_sub_u_10_##T (T x, T y) \
  { \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return !overflow ? ret : 0; \
  }

Take form 10 as example:

SAT_SUB_U_10(uint64_t);

Before this patch:
uint8_t sat_sub_u_10_uint8_t (uint8_t x, uint8_t y)
{
  unsigned char _1;
  unsigned char _2;
  uint8_t _3;
  __complex__ unsigned char _6;

;;   basic block 2, loop depth 0
;;pred:   ENTRY
  _6 = .SUB_OVERFLOW (x_4(D), y_5(D));
  _2 = IMAGPART_EXPR <_6>;
  if (_2 == 0)
goto ; [50.00%]
  else
goto ; [50.00%]
;;succ:   3
;;4

;;   basic block 3, loop depth 0
;;pred:   2
  _1 = REALPART_EXPR <_6>;
;;succ:   4

;;   basic block 4, loop depth 0
;;pred:   2
;;3
  # _3 = PHI <0(2), _1(3)>
  return _3;
;;succ:   EXIT

}

After this patch:
uint8_t sat_sub_u_10_uint8_t (uint8_t x, uint8_t y)
{
  uint8_t _3;

;;   basic block 2, loop depth 0
;;pred:   ENTRY
  _3 = .SAT_SUB (x_4(D), y_5(D)); [tail call]
  return _3;
;;succ:   EXIT

}

The below test suites are passed for this patch:
1. The rv64gcv fully regression test with newlib.
2. The rv64gcv build with glibc.
3. The x86 bootstrap test.
4. The x86 fully regression test.

gcc/ChangeLog:

* match.pd: Add more match for unsigned sat_sub.
* tree-ssa-math-opts.cc (match_unsigned_saturation_sub): Add new
func impl to match phi node for .SAT_SUB.
(math_opts_dom_walker::after_dom_children): Try match .SAT_SUB
for the phi node, MULT_EXPR, BIT_XOR_EXPR and BIT_AND_EXPR.

Signed-off-by: Pan Li 

Diff:
---
 gcc/match.pd  | 25 +++--
 gcc/tree-ssa-math-opts.cc | 33 +
 2 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/gcc/match.pd b/gcc/match.pd
index 3204cf415387..99968d316eda 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -3147,14 +3147,14 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
 /* Unsigned saturation sub, case 1 (branch with gt):
SAT_U_SUB = X > Y ? X - Y : 0  */
 (match (unsigned_integer_sat_sub @0 @1)
- (cond (gt @0 @1) (minus @0 @1) integer_zerop)
+ (cond^ (gt @0 @1) (minus @0 @1) integer_zerop)
  (if (INTEGRAL_TYPE_P (type) && TYPE_UNSIGNED (type)
   && types_match (type, @0, @1
 
 /* Unsigned saturation sub, case 2 (branch with ge):
SAT_U_SUB = X >= Y ? X - Y : 0.  */
 (match (unsigned_integer_sat_sub @0 @1)
- (cond (ge @0 @1) (minus @0 @1) integer_zerop)
+ (cond^ (ge @0 @1) (minus @0 @1) integer_zerop)
  (if (INTEGRAL_TYPE_P (type) && TYPE_UNSIGNED (type)
   && types_match (type, @0, @1
 
@@ -3172,6 +3172,27 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
  (if (INTEGRAL_TYPE_P (type) && TYPE_UNSIGNED (type)
   && types_match (type, @0, @1
 
+/* Unsigned saturation sub, case 5 (branchless bit_and with .SUB_OVERFLOW).  */
+(match (unsigned_integer_sat_sub @0 @1)
+ (bit_and:c (realpart (IFN_SUB_OVERFLOW@2 @0 @1))
+  (plus (imagpart @2) integer_minus_onep))
+ (if (INTEGRAL_TYPE_

[gcc r15-1333] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:308f87030ea0a4580c16906b948eb8996cf4f8de

commit r15-1333-g308f87030ea0a4580c16906b948eb8996cf4f8de
Author: Pan Li 
Date:   Thu Jun 13 22:06:09 2024 +0800

RISC-V: Add testcases for scalar unsigned SAT_SUB form 3

After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 3 of unsigned .SAT_SUB.

Form 3:
  #define SAT_SUB_U_3(T) \
  T sat_sub_u_3_##T (T x, T y) \
  { \
return x > y ? x - y : 0; \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-10.c: New test.
* gcc.target/riscv/sat_u_sub-11.c: New test.
* gcc.target/riscv/sat_u_sub-12.c: New test.
* gcc.target/riscv/sat_u_sub-9.c: New test.
* gcc.target/riscv/sat_u_sub-run-10.c: New test.
* gcc.target/riscv/sat_u_sub-run-11.c: New test.
* gcc.target/riscv/sat_u_sub-run-12.c: New test.
* gcc.target/riscv/sat_u_sub-run-9.c: New test.

Signed-off-by: Pan Li 

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h|  8 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c | 19 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c | 17 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c  | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c  | 25 +++
 9 files changed, 180 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index bc9a372b6df4..50c65cdea495 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -92,8 +92,16 @@ sat_u_sub_##T##_fmt_2 (T x, T y)  \
   return (x - y) & (-(T)(x > y)); \
 }
 
+#define DEF_SAT_U_SUB_FMT_3(T)\
+T __attribute__((noinline))   \
+sat_u_sub_##T##_fmt_3 (T x, T y)  \
+{ \
+  return x > y ? x - y : 0;   \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
+#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
 
 #define DEF_VEC_SAT_U_SUB_FMT_1(T)   \
 void __attribute__((noinline))   \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
new file mode 100644
index ..6e78164865f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
new file mode 100644
index ..84e34657f551
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
new file mode 100644
index ..eea282b21aef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+*

[gcc r15-1336] RISC-V: Add testcases for scalar unsigned SAT_SUB form 6

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:b781fb4fe19f00aef886b21acf57b96d52545a0c

commit r15-1336-gb781fb4fe19f00aef886b21acf57b96d52545a0c
Author: Pan Li 
Date:   Thu Jun 13 23:05:00 2024 +0800

RISC-V: Add testcases for scalar unsigned SAT_SUB form 6

After the middle-end support the form 6 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 6 of unsigned .SAT_SUB.

Form 6:
  #define SAT_SUB_U_6(T) \
  T sat_sub_u_6_##T (T x, T y) \
  { \
return x <= y ? 0 : x - y; \
  }

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-21.c: New test.
* gcc.target/riscv/sat_u_sub-22.c: New test.
* gcc.target/riscv/sat_u_sub-23.c: New test.
* gcc.target/riscv/sat_u_sub-24.c: New test.
* gcc.target/riscv/sat_u_sub-run-21.c: New test.
* gcc.target/riscv/sat_u_sub-run-22.c: New test.
* gcc.target/riscv/sat_u_sub-run-23.c: New test.
* gcc.target/riscv/sat_u_sub-run-24.c: New test.

Signed-off-by: Pan Li 

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h|  8 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-21.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-22.c | 19 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-24.c | 17 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-21.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-22.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-23.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-24.c | 25 +++
 9 files changed, 180 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index d08755dd8613..4296235cf628 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -113,11 +113,19 @@ sat_u_sub_##T##_fmt_5 (T x, T y) \
   return x < y ? 0 : x - y;  \
 }
 
+#define DEF_SAT_U_SUB_FMT_6(T)   \
+T __attribute__((noinline))  \
+sat_u_sub_##T##_fmt_6 (T x, T y) \
+{\
+  return x <= y ? 0 : x - y; \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
 #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
 #define RUN_SAT_U_SUB_FMT_4(T, x, y) sat_u_sub_##T##_fmt_4(x, y)
 #define RUN_SAT_U_SUB_FMT_5(T, x, y) sat_u_sub_##T##_fmt_5(x, y)
+#define RUN_SAT_U_SUB_FMT_6(T, x, y) sat_u_sub_##T##_fmt_6(x, y)
 
 #define DEF_VEC_SAT_U_SUB_FMT_1(T)   \
 void __attribute__((noinline))   \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-21.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-21.c
new file mode 100644
index ..9a8fb7f1c91e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-21.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_6:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_6(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-22.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-22.c
new file mode 100644
index ..6182169edc5a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-22.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_6:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_6(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c
new file mode 100644
index ..820110cdbb08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-23.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2

[gcc r15-1340] RISC-V: Add testcases for scalar unsigned SAT_SUB form 10

[Pan Li via Gcc-cvs]

https://gcc.gnu.org/g:896e043830fa4bc391db5f3cc2c33496cb8aa32e

commit r15-1340-g896e043830fa4bc391db5f3cc2c33496cb8aa32e
Author: Pan Li 
Date:   Fri Jun 14 10:08:59 2024 +0800

RISC-V: Add testcases for scalar unsigned SAT_SUB form 10

After the middle-end support the form 10 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 10 of unsigned .SAT_SUB.

Form 10:
  #define SAT_SUB_U_10(T) \
  T sat_sub_u_10_##T (T x, T y) \
  { \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return !overflow ? ret : 0; \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-37.c: New test.
* gcc.target/riscv/sat_u_sub-38.c: New test.
* gcc.target/riscv/sat_u_sub-39.c: New test.
* gcc.target/riscv/sat_u_sub-40.c: New test.
* gcc.target/riscv/sat_u_sub-run-37.c: New test.
* gcc.target/riscv/sat_u_sub-run-38.c: New test.
* gcc.target/riscv/sat_u_sub-run-39.c: New test.
* gcc.target/riscv/sat_u_sub-run-40.c: New test.

Signed-off-by: Pan Li 

Diff:
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h| 10 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c | 19 +
 gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c | 18 
 gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c | 17 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-37.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-38.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-39.c | 25 +++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-40.c | 25 +++
 9 files changed, 182 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h 
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index ecb74e56e9ca..4c02783e8457 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -147,6 +147,15 @@ sat_u_sub_##T##_fmt_9 (T x, T y)\
   return overflow ? 0 : ret;\
 }
 
+#define DEF_SAT_U_SUB_FMT_10(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_10 (T x, T y)   \
+{   \
+  T ret;\
+  T overflow = __builtin_sub_overflow (x, y, &ret); \
+  return !overflow ? ret : 0;   \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
 #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -156,6 +165,7 @@ sat_u_sub_##T##_fmt_9 (T x, T y)\
 #define RUN_SAT_U_SUB_FMT_7(T, x, y) sat_u_sub_##T##_fmt_7(x, y)
 #define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
 #define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
+#define RUN_SAT_U_SUB_FMT_10(T, x, y) sat_u_sub_##T##_fmt_10(x, y)
 
 #define DEF_VEC_SAT_U_SUB_FMT_1(T)   \
 void __attribute__((noinline))   \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c
new file mode 100644
index ..8c97a518d2c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_10:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_10(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c 
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c
new file mode 100644
index ..7e3cec2a9a72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details 
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_10:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48

[gcc r15-1341] libstdc++: Fix declaration of posix_memalign for freestanding

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:161efd677458f20d13ee1018a4d5e3964febd508

commit r15-1341-g161efd677458f20d13ee1018a4d5e3964febd508
Author: Jonathan Wakely 
Date:   Fri Jun 14 12:10:48 2024 +0100

libstdc++: Fix declaration of posix_memalign for freestanding

Thanks to Jérôme Duval for noticing this.

libstdc++-v3/ChangeLog:

* libsupc++/new_opa.cc [!_GLIBCXX_HOSTED]: Fix declaration of
posix_memalign.

Diff:
---
 libstdc++-v3/libsupc++/new_opa.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libstdc++-v3/libsupc++/new_opa.cc 
b/libstdc++-v3/libsupc++/new_opa.cc
index 35606e1c1b3d..c7c7e7946239 100644
--- a/libstdc++-v3/libsupc++/new_opa.cc
+++ b/libstdc++-v3/libsupc++/new_opa.cc
@@ -47,7 +47,7 @@ using std::size_t;
 extern "C"
 {
 # if _GLIBCXX_HAVE_POSIX_MEMALIGN
-  void *posix_memalign(void **, size_t alignment, size_t size);
+  int posix_memalign(void **, size_t alignment, size_t size);
 # elif _GLIBCXX_HAVE_ALIGNED_ALLOC
   void *aligned_alloc(size_t alignment, size_t size);
 # elif _GLIBCXX_HAVE__ALIGNED_MALLOC

[gcc r14-10311] libstdc++: Fix declaration of posix_memalign for freestanding

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:75251f5091c9b81577e031ab781d42c6cbe4a64b

commit r14-10311-g75251f5091c9b81577e031ab781d42c6cbe4a64b
Author: Jonathan Wakely 
Date:   Fri Jun 14 12:10:48 2024 +0100

libstdc++: Fix declaration of posix_memalign for freestanding

Thanks to Jérôme Duval for noticing this.

libstdc++-v3/ChangeLog:

* libsupc++/new_opa.cc [!_GLIBCXX_HOSTED]: Fix declaration of
posix_memalign.

(cherry picked from commit 161efd677458f20d13ee1018a4d5e3964febd508)

Diff:
---
 libstdc++-v3/libsupc++/new_opa.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libstdc++-v3/libsupc++/new_opa.cc 
b/libstdc++-v3/libsupc++/new_opa.cc
index 35606e1c1b3d..c7c7e7946239 100644
--- a/libstdc++-v3/libsupc++/new_opa.cc
+++ b/libstdc++-v3/libsupc++/new_opa.cc
@@ -47,7 +47,7 @@ using std::size_t;
 extern "C"
 {
 # if _GLIBCXX_HAVE_POSIX_MEMALIGN
-  void *posix_memalign(void **, size_t alignment, size_t size);
+  int posix_memalign(void **, size_t alignment, size_t size);
 # elif _GLIBCXX_HAVE_ALIGNED_ALLOC
   void *aligned_alloc(size_t alignment, size_t size);
 # elif _GLIBCXX_HAVE__ALIGNED_MALLOC

[gcc r13-8849] libstdc++: Fix declaration of posix_memalign for freestanding

[Jonathan Wakely via Gcc-cvs]

https://gcc.gnu.org/g:24dbdd20dcbd4c560f852cce51aa0754464476f5

commit r13-8849-g24dbdd20dcbd4c560f852cce51aa0754464476f5
Author: Jonathan Wakely 
Date:   Fri Jun 14 12:10:48 2024 +0100

libstdc++: Fix declaration of posix_memalign for freestanding

Thanks to Jérôme Duval for noticing this.

libstdc++-v3/ChangeLog:

* libsupc++/new_opa.cc [!_GLIBCXX_HOSTED]: Fix declaration of
posix_memalign.

(cherry picked from commit 161efd677458f20d13ee1018a4d5e3964febd508)

Diff:
---
 libstdc++-v3/libsupc++/new_opa.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libstdc++-v3/libsupc++/new_opa.cc 
b/libstdc++-v3/libsupc++/new_opa.cc
index 29767c1cfaad..3c06b5c0bcf3 100644
--- a/libstdc++-v3/libsupc++/new_opa.cc
+++ b/libstdc++-v3/libsupc++/new_opa.cc
@@ -47,7 +47,7 @@ using std::size_t;
 extern "C"
 {
 # if _GLIBCXX_HAVE_POSIX_MEMALIGN
-  void *posix_memalign(void **, size_t alignment, size_t size);
+  int posix_memalign(void **, size_t alignment, size_t size);
 # elif _GLIBCXX_HAVE_ALIGNED_ALLOC
   void *aligned_alloc(size_t alignment, size_t size);
 # elif _GLIBCXX_HAVE__ALIGNED_MALLOC

[gcc r15-1342] libstdc++: Make std::type_info::operator== always_inline for C++23 [PR110572]

[Jonathan Wakely via Libstdc++-cvs]

https://gcc.gnu.org/g:6af8d8e618ed27dae3432c96484de4360bd893ab

commit r15-1342-g6af8d8e618ed27dae3432c96484de4360bd893ab
Author: Jonathan Wakely 
Date:   Tue Jun 11 15:52:30 2024 +0100

libstdc++: Make std::type_info::operator== always_inline for C++23 
[PR110572]

Commit r12-6266-g3633cc54284450 implemented P1328 for C++23, making
std::type_info::operator== usable in constant expressions. For targets
such as mingw-w64 where that function was not previously inline, making
it constexpr required making it inline for C++23 and later. For
statically linked programs this can result in multiple definition
errors, because there's a non-inline definition in libstdc++.a as well.

For those targets make it always_inline for C++23, so that there is no
symbol generated for the inline definition, and the non-inline
definition in libstdc++.a will be the only definition.

libstdc++-v3/ChangeLog:

PR libstdc++/110572
* libsupc++/typeinfo (type_info::operator==): Add always_inline
attribute for targets where the ABI requries equality to be
non-inline.
* testsuite/18_support/type_info/110572.cc: New test.

Diff:
---
 libstdc++-v3/libsupc++/typeinfo   |  3 +++
 libstdc++-v3/testsuite/18_support/type_info/110572.cc | 11 +++
 2 files changed, 14 insertions(+)

diff --git a/libstdc++-v3/libsupc++/typeinfo b/libstdc++-v3/libsupc++/typeinfo
index fcc3077d0609..35e72bb18ee5 100644
--- a/libstdc++-v3/libsupc++/typeinfo
+++ b/libstdc++-v3/libsupc++/typeinfo
@@ -188,6 +188,9 @@ namespace std
 #endif
 
 #if __GXX_TYPEINFO_EQUALITY_INLINE || __cplusplus > 202002L
+# if ! __GXX_TYPEINFO_EQUALITY_INLINE
+  [[__gnu__::__always_inline__]]
+# endif
   _GLIBCXX23_CONSTEXPR inline bool
   type_info::operator==(const type_info& __arg) const _GLIBCXX_NOEXCEPT
   {
diff --git a/libstdc++-v3/testsuite/18_support/type_info/110572.cc 
b/libstdc++-v3/testsuite/18_support/type_info/110572.cc
new file mode 100644
index ..64081879b77d
--- /dev/null
+++ b/libstdc++-v3/testsuite/18_support/type_info/110572.cc
@@ -0,0 +1,11 @@
+// { dg-options "-static-libstdc++" }
+// { dg-require-static-libstdcxx }
+// { dg-require-cpp-feature-test __cpp_rtti }
+// { dg-do link }
+
+#include 
+
+int main()
+{
+  return typeid(0) == typeid(0u);
+}

[gcc r15-1343] AVR: target/115419 - Tie breaks are rounded-to-even.

[Georg-Johann Lay via Gcc-cvs]

https://gcc.gnu.org/g:2830b0b8655f0d1a62b416af8ade31f5b96f0ffb

commit r15-1343-g2830b0b8655f0d1a62b416af8ade31f5b96f0ffb
Author: Georg-Johann Lay 
Date:   Fri Jun 14 18:24:13 2024 +0200

AVR: target/115419 - Tie breaks are rounded-to-even.

libgcc/config/avr/libf7/
PR target/115419
* libf7.c (f7_get_double): Round tie breaks to even LSB.

Diff:
---
 libgcc/config/avr/libf7/libf7.c | 20 +++-
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/libgcc/config/avr/libf7/libf7.c b/libgcc/config/avr/libf7/libf7.c
index 375becb854c1..6fae4fc1a2de 100644
--- a/libgcc/config/avr/libf7/libf7.c
+++ b/libgcc/config/avr/libf7/libf7.c
@@ -440,11 +440,21 @@ f7_double_t f7_get_double (const f7_t *aa)
 
   mant &= 0x00ff;
 
-  // FIXME: For subnormals, rounding is premature and should be
-  //   done *after* the mantissa has been shifted into place
-  //   (or the round value be shifted left accordingly).
-  // Round.
-  mant += 1u << (F7_MANT_BITS - (1 + DBL_DIG_MANT) - 1);
+  // PR115419: The least significant nibble tells how to round:
+  // Tie breaks are rounded to even (Banker's rounding).
+  uint8_t lsn = mant & 0xff;
+  lsn &= 0xf;
+  // The LSB of the outgoing double is at bit 3.
+  if (lsn & (1 << 3))
+++lsn;
+  if (lsn > (1 << 2))
+{
+  // FIXME: For subnormals, rounding is premature and should be
+  //done *after* the mantissa has been shifted into place
+  //(or the round value be shifted left accordingly).
+  // Round.
+  mant += 1u << (F7_MANT_BITS - (1 + DBL_DIG_MANT) - 1);
+}
 
   uint8_t dex;
   register uint64_t r18 __asm ("r18") = mant;

[gcc r15-1344] testsuite: Add -Wno-psabi to vshuf-mem.C test

[Jakub Jelinek via Gcc-cvs]

https://gcc.gnu.org/g:1bb2535c7cb279e6aab731e79080d8486dd50cce

commit r15-1344-g1bb2535c7cb279e6aab731e79080d8486dd50cce
Author: Jakub Jelinek 
Date:   Fri Jun 14 19:57:59 2024 +0200

testsuite: Add -Wno-psabi to vshuf-mem.C test

The newly added test FAILs on i686-linux.
On x86_64-linux
make check-g++ 
RUNTESTFLAGS='--target_board=unix\{-m64,-m32/-msse2,-m32/-mno-sse/-mno-mmx\} 
dg-torture.exp=vshuf-mem.C'
shows that as well.

The problem is that without SSE2/MMX the vector is passed differently
than normally and so GCC warns about that.
-Wno-psabi is the usual way to shut it up.

Also wonder about the
// { dg-additional-options "-march=z14" { target s390*-*-* } }
line, doesn't that mean the test will FAIL on all pre-z14 HW?
Shouldn't it use some z14_runtime or similar effective target, or
check in main (in that case copied over to g++.target/s390) whether
z14 instructions can be actually used at runtime?

2024-06-14  Jakub Jelinek  

* g++.dg/torture/vshuf-mem.C: Add -Wno-psabi to dg-options.

Diff:
---
 gcc/testsuite/g++.dg/torture/vshuf-mem.C | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/g++.dg/torture/vshuf-mem.C 
b/gcc/testsuite/g++.dg/torture/vshuf-mem.C
index 5f1ebf65665c..6d892f876be5 100644
--- a/gcc/testsuite/g++.dg/torture/vshuf-mem.C
+++ b/gcc/testsuite/g++.dg/torture/vshuf-mem.C
@@ -1,4 +1,4 @@
-// { dg-options "-std=c++11" }
+// { dg-options "-std=c++11 -Wno-psabi" }
 // { dg-do run }
 // { dg-additional-options "-march=z14" { target s390*-*-* } }

[gcc(refs/users/meissner/heads/work168-bugs)] Little endian PowerPC without VSX cannot support IEEE 128-bit.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:9148b4679335390ce0d675482f6855328708bea6

commit 9148b4679335390ce0d675482f6855328708bea6
Author: Michael Meissner 
Date:   Fri Jun 14 14:50:13 2024 -0400

Little endian PowerPC without VSX cannot support IEEE 128-bit.

2024-06-14  Michael Meissner  

libgfortran/

* kinds-override.h: Do not enable IEEE 128-bit floating point 
support on
little endian PowerPC that does not have VSX support.

Diff:
---
 libgfortran/kinds-override.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libgfortran/kinds-override.h b/libgfortran/kinds-override.h
index f6b4956c5caa..51f440e53232 100644
--- a/libgfortran/kinds-override.h
+++ b/libgfortran/kinds-override.h
@@ -30,7 +30,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If 
not, see
 #endif
 
 /* Keep these conditions on one line so grep can filter it out.  */
-#if defined(__powerpc64__)  && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__  && 
__SIZEOF_LONG_DOUBLE__ == 16
+#if defined(__powerpc64__)  && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__  && 
__SIZEOF_LONG_DOUBLE__ == 16 && defined(__VSX__)
 typedef _Float128 GFC_REAL_17;
 typedef _Complex _Float128 GFC_COMPLEX_17;
 #define HAVE_GFC_REAL_17

[gcc(refs/users/meissner/heads/work168-bugs)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:cc1d3baa18d0600c2c58048905aa58592b64d8d6

commit cc1d3baa18d0600c2c58048905aa58592b64d8d6
Author: Michael Meissner 
Date:   Fri Jun 14 14:53:03 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 161 -
 1 file changed, 160 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index acfe9a8ee543..bdd67eed1ab2 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,6 +1,165 @@
+ Branch work168-bugs, patch #11 from work168 branch 

+
+Add -mcpu=future tuning support.
+
+This patch makes -mtune=future use the same tuning decision as -mtune=power11.
+
+2024-06-03  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/power10.md (all reservations): Add future as an
+   alterntive to power10 and power11.
+
+ Branch work168-bugs, patch #10 from work168 branch 

+
+Add -mcpu=future support.
+
+This patch adds the future option to the -mcpu= and -mtune= switches.
+
+This patch treats the future like a power11 in terms of costs and reassociation
+width.
+
+This patch issues a ".machine future" to the assembly file if you use
+-mcpu=power11.
+
+This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.
+
+This patch allows GCC to be configured with the --with-cpu=future and
+--with-tune=future options.
+
+This patch passes -mfuture to the assembler if the user uses -mcpu=future.
+
+2024-06-03  Michael Meissner  
+
+gcc/
+
+   * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
+   * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11.
+   * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/driver-rs6000.cc (asm_names): Likewise.
+   * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+   _ARCH_PWR_FUTURE if -mcpu=future.
+   * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define.
+   (POWERPC_MASKS): Add future isa bit.
+   (power11 cpu): Add future definition.
+   * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor.
+   * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
+   * config/rs6000/rs6000-tables.opt: Regenerate.
+   * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future
+   support.
+   (rs6000_machine_from_flags): Likewise.
+   (rs6000_reassociation_width): Likewise.
+   (rs6000_adjust_cost): Likewise.
+   (rs6000_issue_rate): Likewise.
+   (rs6000_sched_reorder): Likewise.
+   (rs6000_sched_reorder2): Likewise.
+   (rs6000_register_move_cost): Likewise.
+   (rs6000_opt_masks): Likewise.
+   * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
+   * config/rs6000/rs6000.md (cpu attribute): Add future.
+   * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag.
+   * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future.
+
+ Branch work168-bugs, patch #3 from work168 branch 

+
+Add -mcpu=power11 tests.
+
+This patch adds some simple tests for -mcpu=power11 support.  In order to run
+these tests, you need an assembler that supports the appropriate option for
+supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX).
+
+2024-06-03  Michael Meissner  
+
+gcc/testsuite/
+
+   * gcc.target/powerpc/power11-1.c: New test.
+   * gcc.target/powerpc/power11-2.c: Likewise.
+   * gcc.target/powerpc/power11-3.c: Likewise.
+   * lib/target-supports.exp (check_effective_target_power11_ok): Add new
+   effective target.
+
+ Branch work168-bugs, patch #2 from work168 branch 

+
+Add -mcpu=power11 tuning support.
+
+This patch makes -mtune=power11 use the same tuning decisions as 
-mtune=power10.
+
+2024-06-03  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/power10.md (all reservations): Add power11 as an
+   alternative to power10.
+
+ Branch work168-bugs, patch #1 from work168 branch 

+
+Add -mcpu=power11 support.
+
+This patch adds the power11 option to the -mcpu= and -mtune= switches.
+
+This patch treats the power11 like a power10 in terms of costs and 
reassociation
+width.
+
+This patch issues a ".machine power11" to the assembly file if you use
+-mcpu=power11.
+
+This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
+
+This patch allows GCC to be configured with the --with-cpu=power11 and
+--with-tune=power11 options.
+
+This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.
+
+This patch adds support for using "power11" in the __builtin_cpu_is built-in
+function.
+
+2024-06-03  Michael Meissner  
+
+gcc/
+
+   * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
+   * confi

[gcc(refs/users/meissner/heads/work168-test)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:3e6c5a0523a1ab70f80d25652c3cf62a0b71e56f

commit 3e6c5a0523a1ab70f80d25652c3cf62a0b71e56f
Author: Michael Meissner 
Date:   Fri Jun 14 14:53:45 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.test | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index a6f3be611739..80b7b5bdcc32 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,4 +1,4 @@
- Branch work168-test, patch #300 
+ Branch work168-test, patch #301 
 
 Possibly restrict SPRs from holding small integers or CCs.

[gcc r15-1345] Do not assume LHS of call is an ssa-name.

[Andrew Macleod via Gcc-cvs]

https://gcc.gnu.org/g:80c6b6a21b5d3e4f7c5fddbe88e344b608ffb010

commit r15-1345-g80c6b6a21b5d3e4f7c5fddbe88e344b608ffb010
Author: Andrew MacLeod 
Date:   Wed Jun 12 09:20:20 2024 -0400

Do not assume LHS of call is an ssa-name.

gimple_range_fold makes an assumption that the LHS of a call is an
ssa_name, which later in compilation may not be true.

* gimple-range-fold.cc (fold_using_range::range_of_call): Ensure
LHS is an SSA_NAME before invoking gimple_range_global.

Diff:
---
 gcc/gimple-range-fold.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/gimple-range-fold.cc b/gcc/gimple-range-fold.cc
index 6037c29ce11e..52fc3f2cb04a 100644
--- a/gcc/gimple-range-fold.cc
+++ b/gcc/gimple-range-fold.cc
@@ -1105,7 +1105,7 @@ fold_using_range::range_of_call (vrange &r, gcall *call, 
fur_source &)
 }
 
   // If there is an LHS, intersect that with what is known.
-  if (lhs)
+  if (gimple_range_ssa_p (lhs))
 {
   Value_Range def (TREE_TYPE (lhs));
   gimple_range_global (def, lhs);

[gcc r15-1346] Add merge facility to ssa_lazy_cache.

[Andrew Macleod via Gcc-cvs]

https://gcc.gnu.org/g:d40034c489c3d4ae149759ba051ef1d661a6c243

commit r15-1346-gd40034c489c3d4ae149759ba051ef1d661a6c243
Author: Andrew MacLeod 
Date:   Thu Jun 13 15:35:55 2024 -0400

Add merge facility to ssa_lazy_cache.

The ssa_lazy_cache has a routine to merge a range for an ssa-name with
an existing range in the cache.  This adds a method which will merge all
elements of another ssa_lazy_cache.

* gimple-range-cache.cc (ssa_lazy_cache::merge): New.
* gimple-range-cache.h (ssa_lazy_cache::merge): New prototype.

Diff:
---
 gcc/gimple-range-cache.cc | 18 ++
 gcc/gimple-range-cache.h  |  1 +
 2 files changed, 19 insertions(+)

diff --git a/gcc/gimple-range-cache.cc b/gcc/gimple-range-cache.cc
index a511a2c3a4c2..efaae2ed9281 100644
--- a/gcc/gimple-range-cache.cc
+++ b/gcc/gimple-range-cache.cc
@@ -729,6 +729,24 @@ ssa_lazy_cache::merge_range (tree name, const vrange &r)
   return true;
 }
 
+// Merge all elements of CACHE with this cache.
+// Any names in CACHE that are not in this one are added.
+// Any names in both are merged via merge_range..
+
+void
+ssa_lazy_cache::merge (const ssa_lazy_cache &cache)
+{
+  unsigned x;
+  bitmap_iterator bi;
+  EXECUTE_IF_SET_IN_BITMAP (cache.active_p, 0, x, bi)
+{
+  tree name = ssa_name (x);
+  Value_Range r(TREE_TYPE (name));
+  cache.get_range (r, name);
+  merge_range (ssa_name (x), r);
+}
+}
+
 // Return TRUE if NAME has a range, and return it in R.
 
 bool
diff --git a/gcc/gimple-range-cache.h b/gcc/gimple-range-cache.h
index c7499f928a94..63410d5437e6 100644
--- a/gcc/gimple-range-cache.h
+++ b/gcc/gimple-range-cache.h
@@ -87,6 +87,7 @@ public:
   virtual bool get_range (vrange &r, tree name) const;
   virtual void clear_range (tree name);
   virtual void clear ();
+  void merge (const ssa_lazy_cache &);
 protected:
   bitmap active_p;
 };

[gcc r15-1347] Dont add varying values to gori_on_edge mass calculations.

[Andrew Macleod via Gcc-cvs]

https://gcc.gnu.org/g:e5e341243bf4a8a93fc9b5776124c64015326356

commit r15-1347-ge5e341243bf4a8a93fc9b5776124c64015326356
Author: Andrew MacLeod 
Date:   Fri Jun 14 11:01:08 2024 -0400

Dont add varying values to gori_on_edge mass calculations.

gori_on_edge will return an ssa_lazy_cache with all contextual ranges
that can be generated by an edge.   This patch adjusts it so that
a VARYING range is never added.

* gimple-range-gori.cc (gori_calc_operands): Do not continue nor
add the range when VARYING is produced for an operand.

Diff:
---
 gcc/gimple-range-gori.cc | 24 +++-
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/gcc/gimple-range-gori.cc b/gcc/gimple-range-gori.cc
index d489aef312ce..4f6073c715af 100644
--- a/gcc/gimple-range-gori.cc
+++ b/gcc/gimple-range-gori.cc
@@ -1605,11 +1605,14 @@ gori_calc_operands (vrange &lhs, gimple *stmt, 
ssa_cache &r, range_query *q)
   tmp.set_type (TREE_TYPE (si.ssa1));
   if (si.calc_op1 (tmp, lhs, si.op2_range))
si.op1_range.intersect (tmp);
-  r.set_range (si.ssa1, si.op1_range);
-  gimple *src = SSA_NAME_DEF_STMT (si.ssa1);
-  // If defintion is in the same basic lock, evaluate it.
-  if (src && gimple_bb (src) == gimple_bb (stmt))
-   gori_calc_operands (si.op1_range, src, r, q);
+  if (!si.op1_range.varying_p ())
+   {
+ r.set_range (si.ssa1, si.op1_range);
+ gimple *src = SSA_NAME_DEF_STMT (si.ssa1);
+ // If defintion is in the same basic lock, evaluate it.
+ if (src && gimple_bb (src) == gimple_bb (stmt))
+   gori_calc_operands (si.op1_range, src, r, q);
+   }
 }
 
   if (si.ssa2 && !r.has_range (si.ssa2))
@@ -1617,10 +1620,13 @@ gori_calc_operands (vrange &lhs, gimple *stmt, 
ssa_cache &r, range_query *q)
   tmp.set_type (TREE_TYPE (si.ssa2));
   if (si.calc_op2 (tmp, lhs, si.op1_range))
si.op2_range.intersect (tmp);
-  r.set_range (si.ssa2, si.op2_range);
-  gimple *src = SSA_NAME_DEF_STMT (si.ssa2);
-  if (src && gimple_bb (src) == gimple_bb (stmt))
-   gori_calc_operands (si.op2_range, src, r, q);
+  if (!si.op2_range.varying_p ())
+   {
+ r.set_range (si.ssa2, si.op2_range);
+ gimple *src = SSA_NAME_DEF_STMT (si.ssa2);
+ if (src && gimple_bb (src) == gimple_bb (stmt))
+   gori_calc_operands (si.op2_range, src, r, q);
+   }
 }
 }

[gcc(refs/users/meissner/heads/work168-bugs)] Disable IEEE 128 on little endian 32-bit systems.

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:3ea2d4cac5c925398e9379e05fccb21b8266cda7

commit 3ea2d4cac5c925398e9379e05fccb21b8266cda7
Author: Michael Meissner 
Date:   Fri Jun 14 20:29:47 2024 -0400

Disable IEEE 128 on little endian 32-bit systems.

2024-06-14  Michael Meissner  

gcc/

* config/rs6000/rs6000.cc (rs6000_option_override_internal): Do not
allow IEEE 128-bit on little endian 32-bit systems.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c5c4191127e4..ea36e651b446 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4146,7 +4146,8 @@ rs6000_option_override_internal (bool global_init_p)
  the keyword as well as the type.  */
   TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
 
-  /* IEEE 128-bit floating point requires VSX support.  */
+  /* IEEE 128-bit floating point requires VSX support.  Disable IEEE 128-bit on
+ legacy 32-bit LE systems.  */
   if (TARGET_FLOAT128_KEYWORD)
 {
   if (!TARGET_VSX)
@@ -4154,6 +4155,16 @@ rs6000_option_override_internal (bool global_init_p)
  if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
error ("%qs requires VSX support", "-mfloat128");
 
+ TARGET_FLOAT128_TYPE = 0;
+ rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
+   | OPTION_MASK_FLOAT128_HW);
+   }
+  else if (!TARGET_POWERPC64 && !BYTES_BIG_ENDIAN)
+   {
+ if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
+   error ("%qs requires 64-bit support on little endian systems",
+  "-mfloat128");
+
  TARGET_FLOAT128_TYPE = 0;
  rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
| OPTION_MASK_FLOAT128_HW);

[gcc(refs/users/meissner/heads/work168-bugs)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:15e46f9dd299d97162ccffc79a43653021689ac2

commit 15e46f9dd299d97162ccffc79a43653021689ac2
Author: Michael Meissner 
Date:   Fri Jun 14 20:31:13 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index bdd67eed1ab2..5e33b15d5b7e 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,3 +1,25 @@
+ Branch work168-bugs, patch #401 
+
+Disable IEEE 128 on little endian 32-bit systems.
+
+2024-06-14  Michael Meissner  
+
+gcc/
+
+   * config/rs6000/rs6000.cc (rs6000_option_override_internal): Do not
+   allow IEEE 128-bit on little endian 32-bit systems.
+
+ Branch work168-bugs, patch #400 
+
+Little endian PowerPC without VSX cannot support IEEE 128-bit.
+
+2024-06-14  Michael Meissner  
+
+libgfortran/
+
+   * kinds-override.h: Do not enable IEEE 128-bit floating point support on
+   little endian PowerPC that does not have VSX support.
+
  Branch work168-bugs, patch #11 from work168 branch 

 
 Add -mcpu=future tuning support.

[gcc(refs/users/meissner/heads/work168-bugs)] Do not build libgcc if GCC is not configured for at least power8

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:18b148bccc683473e2545c9098ebab7d8eb96ca7

commit 18b148bccc683473e2545c9098ebab7d8eb96ca7
Author: Michael Meissner 
Date:   Sat Jun 15 02:57:27 2024 -0400

Do not build libgcc if GCC is not configured for at least power8

2024-06-15  Michael Meissner  

libgcc/

* config.host (powerpc*-linux*): Do not build the IEEE 128-bit 
support
libraries unless GCC is configured for at least power8 by default.
* configure.ac (powerpc*-linux*): Likewise.
* configure: Regenerate.

Diff:
---
 libgcc/config.host  | 14 --
 libgcc/configure|  9 -
 libgcc/configure.ac |  9 -
 3 files changed, 24 insertions(+), 8 deletions(-)

diff --git a/libgcc/config.host b/libgcc/config.host
index 9fae51d4ce7d..9e3b21e98fdd 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1290,16 +1290,18 @@ powerpc*-*-linux*)
;;
esac
 
+   # If the compiler is not configured for IEEE 128-bit, do not include the
+   # power9 and power10 hardware support libraries
if test $libgcc_cv_powerpc_float128 = yes; then
tmake_file="${tmake_file} rs6000/t-float128"
-   fi
 
-   if test $libgcc_cv_powerpc_float128_hw = yes; then
-   tmake_file="${tmake_file} rs6000/t-float128-hw"
-   fi
+   if test $libgcc_cv_powerpc_float128_hw = yes; then
+   tmake_file="${tmake_file} rs6000/t-float128-hw"
 
-   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
-   tmake_file="${tmake_file} rs6000/t-float128-p10-hw"
+   if test $libgcc_cv_powerpc_3_1_float128_hw = yes; then
+   tmake_file="${tmake_file} 
rs6000/t-float128-p10-hw"
+   fi
+   fi
fi
 
extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o"
diff --git a/libgcc/configure b/libgcc/configure
index a69d314374a3..f61c9c9b3937 100755
--- a/libgcc/configure
+++ b/libgcc/configure
@@ -5184,9 +5184,16 @@ case ${host} in
 # check if we have VSX (ISA 2.06) support to build the software libraries, and
 # whether the assembler can handle xsaddqp for hardware support.  Also check if
 # a new glibc is being used so that __builtin_cpu_supports can be used.
+#
+# Originally we added -mabi=altivec -mvsx to the tests to see if we could
+# support IEEE 128-bit.  This would mean that even if the compiler was
+# configured for power5, it would build the IEEE 128-bit libraries by adding
+# -mvsx.  Instead if you want IEEE 128-bit support, you have to configure the
+# compiler to build ISA 2.06 (power8) by default.  We do add -mfloat128 to
+# cater to systems where IEEE 128-bit might not be enabled by default.
 powerpc*-*-linux*)
   saved_CFLAGS="$CFLAGS"
-  CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128"
+  CFLAGS="$CFLAGS -mfloat128"
   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for PowerPC ISA 2.06 to 
build __float128 libraries" >&5
 $as_echo_n "checking for PowerPC ISA 2.06 to build __float128 libraries... " 
>&6; }
 if ${libgcc_cv_powerpc_float128+:} false; then :
diff --git a/libgcc/configure.ac b/libgcc/configure.ac
index c2749fe09584..d9941c0b1a6a 100644
--- a/libgcc/configure.ac
+++ b/libgcc/configure.ac
@@ -407,9 +407,16 @@ case ${host} in
 # check if we have VSX (ISA 2.06) support to build the software libraries, and
 # whether the assembler can handle xsaddqp for hardware support.  Also check if
 # a new glibc is being used so that __builtin_cpu_supports can be used.
+#
+# Originally we added -mabi=altivec -mvsx to the tests to see if we could
+# support IEEE 128-bit.  This would mean that even if the compiler was
+# configured for power5, it would build the IEEE 128-bit libraries by adding
+# -mvsx.  Instead if you want IEEE 128-bit support, you have to configure the
+# compiler to build ISA 2.06 (power8) by default.  We do add -mfloat128 to
+# cater to systems where IEEE 128-bit might not be enabled by default.
 powerpc*-*-linux*)
   saved_CFLAGS="$CFLAGS"
-  CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128"
+  CFLAGS="$CFLAGS -mfloat128"
   AC_CACHE_CHECK([for PowerPC ISA 2.06 to build __float128 libraries],
 [libgcc_cv_powerpc_float128],
 [AC_COMPILE_IFELSE(

[gcc(refs/users/meissner/heads/work168-bugs)] Update ChangeLog.*

[Michael Meissner via Gcc-cvs]

https://gcc.gnu.org/g:85b99629c243025a7cadd4d77b3135e99cd38cd1

commit 85b99629c243025a7cadd4d77b3135e99cd38cd1
Author: Michael Meissner 
Date:   Sat Jun 15 02:58:52 2024 -0400

Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.bugs | 13 +
 1 file changed, 13 insertions(+)

diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs
index 5e33b15d5b7e..33b621fd8df7 100644
--- a/gcc/ChangeLog.bugs
+++ b/gcc/ChangeLog.bugs
@@ -1,3 +1,16 @@
+ Branch work168-bugs, patch #402 
+
+Do not build libgcc if GCC is not configured for at least power8
+
+2024-06-15  Michael Meissner  
+
+libgcc/
+
+   * config.host (powerpc*-linux*): Do not build the IEEE 128-bit support
+   libraries unless GCC is configured for at least power8 by default.
+   * configure.ac (powerpc*-linux*): Likewise.
+   * configure: Regenerate.
+
  Branch work168-bugs, patch #401 
 
 Disable IEEE 128 on little endian 32-bit systems.