[PATCH] fix an uninitialized use of loc when parsing gimple switches

[tbsaunde+gcc]

From: Trevor Saunders 

gcc/c/ChangeLog:

2016-10-27  Trevor Saunders  

* gimple-parser.c (c_parser_gimple_switch_stmt): Fix
uninitialized use of loc.
---
 gcc/c/gimple-parser.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/c/gimple-parser.c b/gcc/c/gimple-parser.c
index e9e3aae..8db425f 100644
--- a/gcc/c/gimple-parser.c
+++ b/gcc/c/gimple-parser.c
@@ -1164,7 +1164,6 @@ c_parser_gimple_switch_stmt (c_parser *parser, gimple_seq 
*seq)
   auto_vec labels;
   tree default_label = NULL_TREE;
   gimple_seq switch_body = NULL;
-  location_t loc;
   c_parser_consume_token (parser);
 
   if (c_parser_require (parser, CPP_OPEN_PAREN, "expected %<(%>"))
@@ -1189,7 +1188,7 @@ c_parser_gimple_switch_stmt (c_parser *parser, gimple_seq 
*seq)
case RID_CASE:
  {
c_expr exp1;
-   loc = c_parser_peek_token (parser)->location;
+   location_t loc = c_parser_peek_token (parser)->location;
c_parser_consume_token (parser);
 
if (c_parser_next_token_is (parser, CPP_NAME)
@@ -1224,6 +1223,7 @@ c_parser_gimple_switch_stmt (c_parser *parser, gimple_seq 
*seq)
  }
case RID_DEFAULT:
  {
+   location_t loc = c_parser_peek_token (parser)->location;
c_parser_consume_token (parser);
if (c_parser_next_token_is (parser, CPP_COLON))
  {
@@ -1250,7 +1250,7 @@ c_parser_gimple_switch_stmt (c_parser *parser, gimple_seq 
*seq)
  }
case RID_GOTO:
  {
-   loc = c_parser_peek_token (parser)->location;
+   location_t loc = c_parser_peek_token (parser)->location;
c_parser_consume_token (parser);
if (c_parser_next_token_is (parser, CPP_NAME))
  {
-- 
2.10.1

Re: [PATCH][GIMPLE FE] Split out parser into separate file

[Trevor Saunders]

On Tue, Oct 25, 2016 at 03:33:36PM +0200, Richard Biener wrote:
> 
> Hi,
> 
> so I did the massaging to split out the GIMPLE parsing routines out
> to a separate file (quite tricky to get the gengtype issues correctly
> so I thought to help out here and get things started).

actually it looks like you didn't get the gengtype issues quiet right :(
stage 1 is fine, but when doing a bootstrap stage 2 dies trying to build
cc1obj.  That's because objc pulls in c-parser.o, but not c-lang.o which
means that the gengtype routines for c_parser which are in
gt-c-c-parser.h (included by c-parser.c) are included in cc1obj, but the
routines for vec are not because they get put in
gengtype-c.h which is included in c-lang.c.  Unfortunately I'm not sure
how to fix that off hand.

Killing pch and moving c_parser out of gc memory would of course be one
answer, but that's a rather massive hammer to use.

Trev

[RFC PATCH] expand_strn_compare should attempt expansion even if neither string is constant

[Aaron Sawdey]

I'm currently working on a builtin expansion of strncmp for powerpc
similar to the one for memcmp I checked recently. One thing I
encountered is that the code in expand_strn_compare will not attempt to
expand the cmpstrnsi pattern at all if neither string parameter is a
constant string. This doesn't make a lot of sense in light of the fact
that expand_str_compare starts with an attempt to expand cmpstrsi and
then if that does not work, looks at the string args to see if one is
constant so it can use cmpstrnsi with the known length.

The attached patch is my attempt to add this fallback path to
expand_strn_compare, i.e. if neither length is known, just attempt
expansion of cmpstrnsi using the given 3 arguments.

It looks like in addition to rs6000, there are 3 other targets that
have cmpstrnsi patterns: i386, sh, and rx. 

Is this a reasonable approach to take with this? If so I'll
bootstrap/regtest on i386 as rs6000 does not as yet have an expansion
for cmpstrsi or cmpstrnsi.

Thanks,
   Aaron

-- 
Aaron Sawdey, Ph.D.  acsaw...@linux.vnet.ibm.com
050-2/C113  (507) 253-7520 home: 507/263-0782
IBM Linux Technology Center - PPC ToolchainIndex: builtins.c
===
--- builtins.c	(revision 241593)
+++ builtins.c	(working copy)
@@ -3932,46 +3932,53 @@
 len1 = c_strlen (arg1, 1);
 len2 = c_strlen (arg2, 1);
 
-if (len1)
-  len1 = size_binop_loc (loc, PLUS_EXPR, ssize_int (1), len1);
-if (len2)
-  len2 = size_binop_loc (loc, PLUS_EXPR, ssize_int (1), len2);
+if (!len1 && !len2)
+  {
+	len = arg3;
+  }
+else
+  {
+	if (len1)
+	  len1 = size_binop_loc (loc, PLUS_EXPR, ssize_int (1), len1);
+	if (len2)
+	  len2 = size_binop_loc (loc, PLUS_EXPR, ssize_int (1), len2);
 
-/* If we don't have a constant length for the first, use the length
-   of the second, if we know it.  We don't require a constant for
-   this case; some cost analysis could be done if both are available
-   but neither is constant.  For now, assume they're equally cheap,
-   unless one has side effects.  If both strings have constant lengths,
-   use the smaller.  */
+	/* If we don't have a constant length for the first, use the length
+	   of the second, if we know it.  We don't require a constant for
+	   this case; some cost analysis could be done if both are available
+	   but neither is constant.  For now, assume they're equally cheap,
+	   unless one has side effects.  If both strings have constant lengths,
+	   use the smaller.  */
 
-if (!len1)
-  len = len2;
-else if (!len2)
-  len = len1;
-else if (TREE_SIDE_EFFECTS (len1))
-  len = len2;
-else if (TREE_SIDE_EFFECTS (len2))
-  len = len1;
-else if (TREE_CODE (len1) != INTEGER_CST)
-  len = len2;
-else if (TREE_CODE (len2) != INTEGER_CST)
-  len = len1;
-else if (tree_int_cst_lt (len1, len2))
-  len = len1;
-else
-  len = len2;
+	if (!len1)
+	  len = len2;
+	else if (!len2)
+	  len = len1;
+	else if (TREE_SIDE_EFFECTS (len1))
+	  len = len2;
+	else if (TREE_SIDE_EFFECTS (len2))
+	  len = len1;
+	else if (TREE_CODE (len1) != INTEGER_CST)
+	  len = len2;
+	else if (TREE_CODE (len2) != INTEGER_CST)
+	  len = len1;
+	else if (tree_int_cst_lt (len1, len2))
+	  len = len1;
+	else
+	  len = len2;
 
-/* If both arguments have side effects, we cannot optimize.  */
-if (!len || TREE_SIDE_EFFECTS (len))
-  return NULL_RTX;
+	/* If both arguments have side effects, we cannot optimize.  */
+	if (!len || TREE_SIDE_EFFECTS (len))
+	  return NULL_RTX;
 
-/* The actual new length parameter is MIN(len,arg3).  */
-len = fold_build2_loc (loc, MIN_EXPR, TREE_TYPE (len), len,
-		   fold_convert_loc (loc, TREE_TYPE (len), arg3));
+	/* The actual new length parameter is MIN(len,arg3).  */
+	len = fold_build2_loc (loc, MIN_EXPR, TREE_TYPE (len), len,
+			   fold_convert_loc (loc, TREE_TYPE (len), arg3));
 
-/* If we don't have POINTER_TYPE, call the function.  */
-if (arg1_align == 0 || arg2_align == 0)
-  return NULL_RTX;
+	/* If we don't have POINTER_TYPE, call the function.  */
+	if (arg1_align == 0 || arg2_align == 0)
+	  return NULL_RTX;
+  }
 
 /* Stabilize the arguments in case gen_cmpstrnsi fails.  */
 arg1 = builtin_save_expr (arg1);

Re: [PATCH 7/7] make targetm.gen_ccmp{first,next} take rtx_insn **

[Trevor Saunders]

On Tue, Oct 18, 2016 at 01:25:55PM +0200, Bernd Schmidt wrote:
> On 10/17/2016 09:46 PM, tbsaunde+...@tbsaunde.org wrote:
> > From: Trevor Saunders 
> > 
> > gcc/ChangeLog:
> > 
> > 2016-10-17  Trevor Saunders  
> > 
> > * ccmp.c (expand_ccmp_expr_1): Adjust.
> > (expand_ccmp_expr): Likewise.
> > (expand_ccmp_next): Likewise.
> > * config/aarch64/aarch64.c (aarch64_gen_ccmp_next): Likewise.
> > (aarch64_gen_ccmp_first): Likewise.
> > * doc/tm.texi: Regenerate.
> > * target.def (gen_ccmp_first): Change argument types to rtx_insn *.
> > (gen_ccmp_next): Likewise.
> 
> Looks reasonable, but has this been tested on aarch64? I think that's a
> prerequisite for this patch.

I just bootstrapped and regtested this against recent trunk on
aarch64-linux-gnu without regressions.

Thanks!

Trev

> 
> 
> Bernd

Re: [PATCH], Allow SImode to go into VSX registers on PowerPC ISA 2.07 (power8) and above

[Michael Meissner]

I forgot to mention, I will be working on a follow-on patch to this that
enables QImode and HImode to go in the vector registers for ISA 3.0, since ISA
3.0 now adds load (with zero extend) and store instructions for those types.

I probably also will update vector extract for the case where the small
integers can go in vector registers.

After this, I plan to work on setting vector elements, which will be easier if
the small integer types can go in vector registers.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

[PATCH], Allow SImode to go into VSX registers on PowerPC ISA 2.07 (power8) and above

[Michael Meissner]

PowerPC GCC has traditionally only allowed DImode to go into FPR registers (and
now VSX registers) in order to allow floating point conversions.  Conversions
to/from SImode have always had to deal with special UNSPECs to allow the
generation of the LFIWAX, LXSIWAX, LFIWZX, LXSIWZX, STFIWX, and STXSIWX
instructions, since SImode was not allowed in the registers.

This patch adds support for ISA 2.07 (power8) and above to allow SImode values
in the vector registers.  It adds a new debug switch (-mvsx-small-integer) that
can turn off this support.

I have built a boostrap build on a little endian 64-bit Power8 computer, and a
big endian 64-bit Power8 compiler, and both runs compiled and had no regression
in the test suite.  I have started a big endian 64-bit Power7 build right now
that supports both 32-bit and 64-bit calls.  If the power7 build finishes
without regressions, can I check in this patch?

In addition, I did a full Spec 2006 run with an earlier version of the patch
that did not make -mvsx-small-integer default using an explicit switch.  All 29
benchmarks in the 2006 CPU suite ran.  The 436.cactusADM benchmark had a 3%
improvement with -mvsx-small-integer, and all of the other benchmarks were
performance neutral.  The difference is it eliminates some load/store of GPRs
and move directs in favor of doing the load/store 32-bit integer instructions
to the FPRs.

[gcc]
2016-10-26  Michael Meissner  

* config/rs6000/constraints.md (wH constraint): Add new
constraints for allowing 32-bit integers (and eventually 8/16-bit
integers) into the vector registers.
(wI constraint): Likewise.
(wJ constraint): Likewise.
(wK constraint): Likewise.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add
-mvsx-small-integer as a default option for ISA 2.07
(i.e. power8).
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.opt (-mvsx-small-integer): Add new debug
switch to turn off small integer support in vector registers.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Eliminate
test for -mupper-regs-di, since it is already done with the
reg_add[mode].scalar_in_vsx_p.  Add support for the switch
-mvsx-small-integer.
(rs6000_debug_reg_global): Add support for wH, wI, wJ, and wK
constraints.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_option_override_internal): Add consistency checks for
-mvsx-small-integer.
(rs6000_secondary_reload_simple_move): SImode is a simple move if
-mvsx-small-integer.
(rs6000_secondary_reload): Use std::swap.
(rs6000_preferred_reload_class): Don't prefer FLOAT_REGS over
VSX_REGS for small integers in vector registers, since there is no
D-FORM address mode for such types.
(rs6000_register_move_cost): Use FIRST_FPR_REGNO instead of 32.
(rs6000_opt_masks): Add -mvsx-small-integer.
* config/rs6000/vsx.md (VSINT_84): Add SImode for small integer
support.
(VSX_EXTRACT_I2): Clone VSX_EXTRACT_I, but drop V4SI since SImode
extracts can be done on ISA 2.07.
(vsx_extract_): Add support for small integers in vsx
registers.
(vsx_extract__p9): Use 'v' instead of VSX_EX, since we no
longer support V4SImode in this pattern.
(vsx_extract_si): New insn to support extraction of SImode in ISA
2.07 using either xxextractuw or vspltw.
(vsx_extract__p8): Use 'v' instead of VSX_EX, since we no
longer support V4SImode in this pattern.
* config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wH, wI,
wJ, and wK constraints.
* config/rs6000/rs6000.md (f32_sv): Use correct instruction for
storing SDmode with VSX instructions.
(zero_extendsi2): Reorder pattern, so RLDICL comes before
the FPR and VSX loads, but before MTVSRWZ.  Remove ??, ! from the
constraints.  Add MFVSRWZ and XXEXTRACTUW instructions to support
small integers in vector registers.
(extendsi2): Reorder pattern, so EXTSW comes before the FPR
and VSX loads, but before MTVSRWA.  Remove ??, ! from the
constraints.  Add VEXTSW2D support for small integers in vector
registers.
(lfiwax): Remove ! constraint.  Add VEXTSW2D support for small
integers in vector registers.
(floatsi2_lfiwax): If -mvsx-small-integer issue a normal
move instead of using an UNSPEC.
(lfiwzx): Remove ! constraint.  Add XXEXTRACTUW support for small
integers in vector registers.
(floatunssi2_lfiwzx): If -mvsx-small-integer issue a normal
move instead of using an UNSPEC.
(movsi_internal1): Add support for -mvsx-small-integer.  Align
columns so that it is more readable.
(SImode splitter for 

[nvptx] propagating conditionals in worker-vector partitioned loops

[Cesar Philippidis]

Currently, the nvptx backend is only neutering the worker axis when
propagating variables used in conditional expressions across the worker
and vector axes. That's a problem with the worker-state spill and fill
propagation implementation because all of the vector threads in worker 0
all write the the same address location being spilled. As the attached
test case demonstrates, this might cause an infinite loop depending on
the values in the vector threads being propagated.

This patch fixes this issue by introducing a new worker-vector
predicate, so that both the worker and vector threads can be predicated
together, not separately. I.e., instead of first neutering worker axis,
then neutering the vector axis, this patch uses a single predicate for
tid.x == 0 && tid.y == 0.

Is this patch ok for trunk?

Cesar
2016-10-26  Cesar Philippidis  

	gcc/
	* config/nvptx/nvptx.c (nvptx_single): Use a single predicate
	for loops partitioned across both worker and vector axes.

	libgomp/
	* testsuite/libgomp.oacc-c-c++-common/broadcast-1.c: New test.


diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c
index 7bf5987..4e6ed60 100644
--- a/gcc/config/nvptx/nvptx.c
+++ b/gcc/config/nvptx/nvptx.c
@@ -3507,11 +3507,38 @@ nvptx_single (unsigned mask, basic_block from, basic_block to)
   /* Insert the vector test inside the worker test.  */
   unsigned mode;
   rtx_insn *before = tail;
+  rtx wvpred = NULL_RTX;
+  bool skip_vector = false;
+
+  /* Create a single predicate for loops containing both worker and
+ vectors.  */
+  if (cond_branch
+  && (GOMP_DIM_MASK (GOMP_DIM_WORKER) & mask)
+  && (GOMP_DIM_MASK (GOMP_DIM_VECTOR) & mask))
+{
+  rtx regx = gen_reg_rtx (SImode);
+  rtx regy = gen_reg_rtx (SImode);
+  rtx tmp = gen_reg_rtx (SImode);
+  wvpred = gen_reg_rtx (BImode);
+
+  emit_insn_before (gen_oacc_dim_pos (regx, const1_rtx), head);
+  emit_insn_before (gen_oacc_dim_pos (regy, const2_rtx), head);
+  emit_insn_before (gen_rtx_SET (tmp, gen_rtx_IOR (SImode, regx, regy)),
+			head);
+  emit_insn_before (gen_rtx_SET (wvpred, gen_rtx_NE (BImode, tmp,
+			 const0_rtx)),
+			head);
+
+  skip_mask &= ~(GOMP_DIM_MASK (GOMP_DIM_VECTOR));
+  skip_vector = true;
+}
+
   for (mode = GOMP_DIM_WORKER; mode <= GOMP_DIM_VECTOR; mode++)
 if (GOMP_DIM_MASK (mode) & skip_mask)
   {
 	rtx_code_label *label = gen_label_rtx ();
-	rtx pred = cfun->machine->axis_predicate[mode - GOMP_DIM_WORKER];
+	rtx pred = skip_vector ? wvpred
+	  : cfun->machine->axis_predicate[mode - GOMP_DIM_WORKER];
 
 	if (!pred)
 	  {
diff --git a/libgomp/testsuite/libgomp.oacc-c-c++-common/broadcast-1.c b/libgomp/testsuite/libgomp.oacc-c-c++-common/broadcast-1.c
new file mode 100644
index 000..4dcb60d
--- /dev/null
+++ b/libgomp/testsuite/libgomp.oacc-c-c++-common/broadcast-1.c
@@ -0,0 +1,49 @@
+/* Ensure that worker-vector state conditional expressions are
+   properly handled by the nvptx backend.  */
+
+#include 
+#include 
+
+
+#define N 1024
+
+int A[N][N] ;
+
+void test(int x)
+{
+#pragma acc parallel  num_gangs(16) num_workers(4) vector_length(32) copyout(A)
+  {
+#pragma acc loop gang
+for(int j=0;j

RE: Fix MIPS port WRT sprintf and fallthru warnings

[Matthew Fortune]

Jeff Law  writes:
> The fallthrus in mips16_constant_cost are pretty obvious.  One buffer
> overflow in mips16_build_call_stub and one obvious fallthru comment
> adjustment in mips16_build_call_stub.
> 
> The usual stuff.  Installing.

Thanks Jeff.

Matthew

Re: [RFC PATCH] avoid printing type suffix with %E

[Joseph Myers]

On Wed, 26 Oct 2016, Martin Sebor wrote:

> The attached patch implements one such approach by having the pretty
> printer recognize the space format flag to suppress the type suffix,
> so "%E" still prints the suffix but "% E" does not.  I did this to
> preserve the existing output but I think it would be nicer to avoid
> printing the suffix with %E and treat (for instance) the pound sign
> as a request to add the suffix.  I have tested the attached patch
> but not the alternative.

I think printing the suffixes is a relic of %E being used to print full 
expressions.

It's established by now that printing expressions reconstructed from trees 
is a bad idea; we can get better results by having precise location ranges 
and underlining the relevant part of the source.  So if we could make sure 
nowhere is trying the use %E (or %qE, etc.) with expressions that might 
not be constants, where the type might be relevant, then we'd have 
confidence that stopping printing the suffix is safe.  But given the low 
quality of the reconstructed expressions, it's probably safe anyway.

(Most %qE uses are for identifiers not expressions.  If we give 
identifiers a different static type from "tree" - and certainly there 
isn't much reason for them to have the same type as expressions - then 
we'll need to change the format for either identifiers or expressions.)

-- 
Joseph S. Myers
jos...@codesourcery.com

Fix sh port WRT fallthru

[Jeff Law]

This adjusts existing fallthru comments and adds some new ones.  I 
couldn't convince myself the original code in movsicc was correct,  It 
looks like we properly reverse the condition, but not the operands in 
the case of LT/LE/LEU/LTU.  But then we do almost the same th ing in 
sh_emit_scc_to_t as well.   So I just kept the existing semantics and 
added fallthru comments.


In gen_shl_and, I'm pretty sure we ended to fallthru.

Installing on the trunk.

Jeff
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3e7704c..0eb5f88 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
 2016-10-26  Jeff Law  
 
+   * config/sh/sh.c (output_branch): Add missing fallthru comments.
+   (gen_shl_and): Likewise.
+   * config/sh/sh.md (movsicc): Add missing fallthru comments.
+
* config/mips/mips.c (mips16_constant_cost): Add missing
fallthru comments.
(mips16_build_call_stub): Increase buffer size.  Adjust
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index cf5231e..4ca4b74 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -2665,6 +2665,7 @@ output_branch (int logic, rtx_insn *insn, rtx *operands)
 
  return "";
}
+  /* FALLTHRU */
   /* When relaxing, handle this like a short branch.  The linker
 will fix it up if it still doesn't fit after relaxation.  */
 case 2:
@@ -2690,7 +2691,7 @@ output_branch (int logic, rtx_insn *insn, rtx *operands)
 
  return "";
}
-  /* When relaxing, fall through.  */
+  /* FALLTHRU */
 case 4:
   {
char buffer[10];
@@ -3461,7 +3462,7 @@ sh_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, 
int outer_code,
  *total = COSTS_N_INSNS (1);
  return true;
}
-  /* Fall through to shiftcosts.  */
+  /* FALLTHRU */
 case ASHIFT:
 case ASHIFTRT:
   {
@@ -4069,12 +4070,14 @@ gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx 
source)
   }
 case 4:
   shift_gen_fun = gen_shifty_op;
+  /* FALLTHRU */
 case 3:
   /* If the topmost bit that matters is set, set the topmost bits
 that don't matter.  This way, we might be able to get a shorter
 signed constant.  */
   if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
mask |= (HOST_WIDE_INT) ((HOST_WIDE_INT_M1U) << (31 - total_shift));
+  /* FALLTHRU */
 case 2:
   /* Don't expand fine-grained when combining, because that will
  make the pattern fail.  */
@@ -4647,6 +4650,7 @@ dump_table (rtx_insn *start, rtx_insn *barrier)
  align_insn = scan;
  need_align = false;
}
+ /* FALLTHRU */
case DImode:
  for (lab = p->label; lab; lab = LABEL_REFS (lab))
scan = emit_label_after (lab, scan);
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index dcb31eb..e80ef58 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -1509,6 +1509,7 @@
   case LT: case LE: case LEU: case LTU:
if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT)
  break;
+   /* FALLTHRU */
   case NE:
new_code = reverse_condition (code);
break;

Fix MIPS port WRT sprintf and fallthru warnings

[Jeff Law]

The fallthrus in mips16_constant_cost are pretty obvious.  One buffer 
overflow in mips16_build_call_stub and one obvious fallthru comment 
adjustment in mips16_build_call_stub.


The usual stuff.  Installing.

jeff
commit c03f0de027e1079edd02e3494601c6def50dbac1
Author: law 
Date:   Wed Oct 26 20:16:57 2016 +

* config/mips/mips.c (mips16_constant_cost): Add missing
fallthru comments.
(mips16_build_call_stub): Increase buffer size.  Adjust
fallthru comment.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241597 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 02a37f6..3e7704c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2016-10-26  Jeff Law  
+
+   * config/mips/mips.c (mips16_constant_cost): Add missing
+   fallthru comments.
+   (mips16_build_call_stub): Increase buffer size.  Adjust
+   fallthru comment.
+
 2016-10-26  David Malcolm  
 
* print-rtl.c (rtx_writer::print_rtx_operand_code_u): Print
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index ebec68e..5c1a35a 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -3828,9 +3828,11 @@ mips16_constant_cost (int code, HOST_WIDE_INT x)
   /* Like LE, but reject the always-true case.  */
   if (x == -1)
return -1;
+  /* FALLTHRU */
 case LE:
   /* We add 1 to the immediate and use SLT.  */
   x += 1;
+  /* FALLTHRU */
 case XOR:
   /* We can use CMPI for an xor with an unsigned 16-bit X.  */
 case LT:
@@ -7439,7 +7441,7 @@ mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx 
args_size, int fp_code)
   if (GET_CODE (fn) != SYMBOL_REF
   || !call_insn_operand (fn, VOIDmode))
 {
-  char buf[30];
+  char buf[32];
   rtx stub_fn, addr;
   rtx_insn *insn;
   bool lazy_p;
@@ -7635,7 +7637,7 @@ mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx 
args_size, int fp_code)
case DCmode:
  mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
  FP_REG_FIRST + 2);
- /* Fall though.  */
+ /* FALLTHRU */
case DFmode:
case V2SFmode:
  gcc_assert (TARGET_PAIRED_SINGLE_FLOAT

[PR debug/77773] segfault when compiling __simd64_float16_t with -g

[Aldy Hernandez]

The following one-liner segfaults on arm-eabi when compiled with 
-mfloat-abi=hard -g:


__simd64_float16_t usingit;

The problem is that the pretty printer (in simple_type_specificer()) is 
dereferencing a NULL result from c_common_type_for_mode:


  int prec = TYPE_PRECISION (t);
  if (ALL_FIXED_POINT_MODE_P (TYPE_MODE (t)))
t = c_common_type_for_mode (TYPE_MODE (t), TYPE_SATURATING (t));
  else
t = c_common_type_for_mode (TYPE_MODE (t), TYPE_UNSIGNED (t));
  if (TYPE_NAME (t))

The type in question is:



which corresponds to HFmode and which AFAICT, does not have a type by 
design.


I see that other uses of *type_for_node() throughout the compiler check 
the result for NULL, so perhaps we should do the same here.


The attached patch fixes the problem.

OK for trunk?
commit 10c5a54cb1bf4684864b01cb965d83f3fe474797
Author: Aldy Hernandez 
Date:   Wed Oct 26 12:06:09 2016 -0700

PR debug/3
* c-pretty-print.c (simple_type_specifier): Do not dereference `t'
if NULL.

diff --git a/gcc/c-family/c-pretty-print.c b/gcc/c-family/c-pretty-print.c
index 90428ca..6bb38a9 100644
--- a/gcc/c-family/c-pretty-print.c
+++ b/gcc/c-family/c-pretty-print.c
@@ -348,7 +348,7 @@ c_pretty_printer::simple_type_specifier (tree t)
t = c_common_type_for_mode (TYPE_MODE (t), TYPE_SATURATING (t));
  else
t = c_common_type_for_mode (TYPE_MODE (t), TYPE_UNSIGNED (t));
- if (TYPE_NAME (t))
+ if (t && TYPE_NAME (t))
{
  simple_type_specifier (t);
  if (TYPE_PRECISION (t) != prec)
@@ -362,6 +362,7 @@ c_pretty_printer::simple_type_specifier (tree t)
  switch (code)
{
case INTEGER_TYPE:
+ gcc_assert (t != NULL);
  translate_string (TYPE_UNSIGNED (t)
 ? "

Re: [PATCH, wwwdocs] Add link to GCC 7 changes.html

[Peter Bergner]

On 10/26/16 1:10 PM, Gerald Pfeifer wrote:

On Tue, 25 Oct 2016, Peter Bergner wrote:

Perhaps add a disclaimer at the top of changes.html that this
is still work in progress as part of that commit?

Do you mean like the following?  If so, we'd have to remember to
remove the last hunk when GCC 7 is released.


Yep, something like that.


Ok, I committed that.  Thanks.

Peter

Re: [PATCH] Show INSN_UIDs in compact mode

[Bernd Schmidt]

On 10/26/2016 08:50 PM, David Malcolm wrote:


The following patch adds back in the INSN_UID for all insns.

Successfully bootstrapped on x86_64-pc-linux-gnu.

OK for trunk?


Yes.

Bernd

[PATCH] Show INSN_UIDs in compact mode

[David Malcolm]

On Thu, 2016-10-20 at 16:11 +0200, Bernd Schmidt wrote:
> On 10/20/2016 03:55 PM, David Malcolm wrote:
> > Currently the jump insn in question looks like this:
> > 
> >   (cjump_insn (set (pc)
> > (label_ref 20))
> >  (nil))
> > 
> > With explicit INSN_UIDs it would look like this:
> > 
> >   (cjump_insn 13 (set (pc)
> > (label_ref 20))
> >  (nil))
> 
> Yeah, that wouldn't be so bad. It would also make it easier to make a
> -fdump-rtl-compact flag that changes the debugging dumps to use the
> compact format (we'd still need slightly different output for
> pseudos).

[...snip...]

The following patch adds back in the INSN_UID for all insns.

Successfully bootstrapped on x86_64-pc-linux-gnu.

OK for trunk?

gcc/ChangeLog:
* print-rtl.c (rtx_writer::print_rtx_operand_code_u): Print
INSN_UIDs for all insns in compact mode.
(rtx_writer::print_rtx): Likewise.
* print-rtl.h (rtx_writer::flag_compact): Update comment.
* rtl-tests.c (selftest::test_dumping_insns): Update expected
output to include INSN_UID.
(selftest::test_uncond_jump): Likewise.
---
 gcc/print-rtl.c | 10 --
 gcc/print-rtl.h |  2 +-
 gcc/rtl-tests.c |  4 ++--
 3 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/gcc/print-rtl.c b/gcc/print-rtl.c
index d0ba896..341ecdf 100644
--- a/gcc/print-rtl.c
+++ b/gcc/print-rtl.c
@@ -423,8 +423,8 @@ rtx_writer::print_rtx_operand_code_r (const_rtx in_rtx)
 void
 rtx_writer::print_rtx_operand_code_u (const_rtx in_rtx, int idx)
 {
-  /* Don't print insn UIDs in compact mode, apart from in LABEL_REFs.  */
-  if (m_compact && GET_CODE (in_rtx) != LABEL_REF)
+  /* Don't print insn UIDs for PREV/NEXT_INSN in compact mode.  */
+  if (m_compact && INSN_CHAIN_CODE_P (GET_CODE (in_rtx)) && idx < 2)
 return;
 
   if (XEXP (in_rtx, idx) != NULL)
@@ -672,10 +672,8 @@ rtx_writer::print_rtx (const_rtx in_rtx)
 idx = 5;
 #endif
 
-  /* For insns, print the INSN_UID.
- In compact mode, we only print the INSN_UID of CODE_LABELs.  */
-  if (INSN_CHAIN_CODE_P (GET_CODE (in_rtx))
-  && (!m_compact || GET_CODE (in_rtx) == CODE_LABEL))
+  /* For insns, print the INSN_UID.  */
+  if (INSN_CHAIN_CODE_P (GET_CODE (in_rtx)))
 {
   if (flag_dump_unnumbered)
fprintf (m_outfile, " #");
diff --git a/gcc/print-rtl.h b/gcc/print-rtl.h
index 4ebfcf9..8496ffa 100644
--- a/gcc/print-rtl.h
+++ b/gcc/print-rtl.h
@@ -50,7 +50,7 @@ class rtx_writer
   bool m_simple;
 
   /* If true, use compact dump format:
- - INSN_UIDs are omitted, except for jumps and CODE_LABELs,
+ - PREV/NEXT_INSN UIDs are omitted
  - INSN_CODEs are omitted,
  - register numbers are omitted for hard and virtual regs, and
non-virtual pseudos are offset relative to the first such reg, and
diff --git a/gcc/rtl-tests.c b/gcc/rtl-tests.c
index 43665ba..4e534b2 100644
--- a/gcc/rtl-tests.c
+++ b/gcc/rtl-tests.c
@@ -121,7 +121,7 @@ test_dumping_insns ()
   /* Barriers.  */
   rtx_barrier *barrier = as_a  (rtx_alloc (BARRIER));
   SET_NEXT_INSN (barrier) = NULL;
-  ASSERT_RTL_DUMP_EQ ("(cbarrier)\n", barrier);
+  ASSERT_RTL_DUMP_EQ ("(cbarrier 0)\n", barrier);
 
   /* Labels.  */
   rtx_insn *label = gen_label_rtx ();
@@ -179,7 +179,7 @@ test_uncond_jump ()
   ASSERT_TRUE (onlyjump_p (jump_insn));
   ASSERT_TRUE (control_flow_insn_p (jump_insn));
 
-  ASSERT_RTL_DUMP_EQ ("(cjump_insn (set (pc)\n"
+  ASSERT_RTL_DUMP_EQ ("(cjump_insn 1 (set (pc)\n"
  "(label_ref 0))\n"
  " (nil))\n",
  jump_insn);
-- 
1.8.5.3

Re: [PATCH, wwwdocs] Add link to GCC 7 changes.html

[Gerald Pfeifer]

On Tue, 25 Oct 2016, Peter Bergner wrote:
>> Perhaps add a disclaimer at the top of changes.html that this
>> is still work in progress as part of that commit?
> Do you mean like the following?  If so, we'd have to remember to 
> remove the last hunk when GCC 7 is released.

Yep, something like that.

On Wed, 26 Oct 2016, Peter Bergner wrote:
> ...unless we want to add a little PHP (would need to rename changes.html
> to changes.php) to test for a file that is created upon release.  Thoughts?

I'm not sure gcc.gnu.org actually supports PHP, but even if it
does, I'm even less sure about www.gnu.org/software/gcc.

So, while I usually like automation, the manual approach probably
is the way to go here for now.  (Clever approach, though!)

Gerald

[PATCH] PR target/78098: Properly handle interrupt/no_caller_saved_registers attributes

[H.J. Lu]

Functions with interrupt or no_caller_saved_registers attribute should
have different function pointer types from those without the attribute
since they require different prologue and epilogue.  2 functions with
different interrupt or no_caller_saved_registers attribute, which are
otherwise equivalent, aren't identical.

In case of 2 identical functions with interrupt attribute, we issue an
error after the ICF merge to detect duplicated interrupt handlers to
reduce code size which is very important in embedded environment.  The
alternatives are

1. Disable the ICF merge, which leads to duplicated codes.
2. Allow the ICF merge and convert the ICF tail call to a jump, which
requires codegen changes in prologue and epilogue of interrupt handlers
as well as an extra jump.

OK for trunk if there is no regression on i686 and x86-64?

H.J.
---
gcc/

PR target/78098
* config/i386/i386.c (ix86_comp_type_attributes): Return 0 if
interrupt or no_caller_saved_registers attribute is different.
(ix86_expand_call): Issue a note when interrupt handler is
merged.
(ix86_attribute_table): Change the affects_type_identity field
to true for interrupt and no_caller_saved_registers attributes.

gcc/testsuite/

PR target/78098
* gcc.target/i386/interrupt-1.c: Updated.
* gcc.target/i386/interrupt-6.c: Likewise.
* gcc.target/i386/interrupt-7.c: Likewise.
* gcc.target/i386/interrupt-16.c: Likewise.
* gcc.target/i386/interrupt-17.c: Likewise.
* gcc.target/i386/interrupt-iamcu.c: Likewise.
* gcc.target/i386/interrupt-sibcall-1.c: Likewise.
* gcc.target/i386/interrupt-sibcall-2.c: Likewise.
* gcc.target/i386/pr78098-1.c: New test.
* gcc.target/i386/pr78098-2.c: Likewise.
* gcc.target/i386/pr78098-3.c: Likewise.
* gcc.target/i386/pr78098-4.c: Likewise.
* gcc.target/i386/pr78098-5.c: Likewise.
* gcc.target/i386/pr78098-6.c: Likewise.
* gcc.target/i386/pr78098-7.c: Likewise.
* gcc.target/i386/pr78098-8.c: Likewise.
* gcc.target/i386/pr78098-9.c: Likewise.
---
 gcc/config/i386/i386.c | 30 +++---
 gcc/testsuite/gcc.target/i386/interrupt-1.c|  1 +
 gcc/testsuite/gcc.target/i386/interrupt-16.c   |  1 +
 gcc/testsuite/gcc.target/i386/interrupt-17.c   |  1 +
 gcc/testsuite/gcc.target/i386/interrupt-6.c|  3 ++-
 gcc/testsuite/gcc.target/i386/interrupt-iamcu.c|  1 +
 .../gcc.target/i386/interrupt-sibcall-1.c  |  1 +
 .../gcc.target/i386/interrupt-sibcall-2.c  |  1 +
 gcc/testsuite/gcc.target/i386/pr78098-1.c  | 18 +
 gcc/testsuite/gcc.target/i386/pr78098-2.c  | 19 ++
 gcc/testsuite/gcc.target/i386/pr78098-3.c  | 19 ++
 gcc/testsuite/gcc.target/i386/pr78098-4.c  | 19 ++
 gcc/testsuite/gcc.target/i386/pr78098-5.c  | 19 ++
 gcc/testsuite/gcc.target/i386/pr78098-6.c  | 13 ++
 gcc/testsuite/gcc.target/i386/pr78098-7.c  | 12 +
 gcc/testsuite/gcc.target/i386/pr78098-8.c  | 13 ++
 gcc/testsuite/gcc.target/i386/pr78098-9.c  | 12 +
 17 files changed, 179 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr78098-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr78098-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr78098-3.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr78098-4.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr78098-5.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr78098-6.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr78098-7.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr78098-8.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr78098-9.c

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index f70eb43..2dbabf5 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -7729,6 +7729,18 @@ ix86_comp_type_attributes (const_tree type1, const_tree 
type2)
   && TREE_CODE (type1) != METHOD_TYPE)
 return 1;
 
+  if ((lookup_attribute ("interrupt",
+TYPE_ATTRIBUTES (type1)) != NULL)
+   != (lookup_attribute ("interrupt",
+TYPE_ATTRIBUTES (type2)) != NULL))
+return 0;
+
+  if ((lookup_attribute ("no_caller_saved_registers",
+TYPE_ATTRIBUTES (type1)) != NULL)
+   != (lookup_attribute ("no_caller_saved_registers",
+TYPE_ATTRIBUTES (type2)) != NULL))
+return 0;
+
   ccvt1 = ix86_get_callcvt (type1);
   ccvt2 = ix86_get_callcvt (type2);
   if (ccvt1 != ccvt2)
@@ -28019,7 +28031,19 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
   if (fndecl
  && (lookup_attribute ("interrupt",
TYPE_ATTRIBUTES (TREE_TYPE (fndecl)
-   error 

Re: [PATCH] sched: Do not reorder RTX_FRAME_RELATED_P insns (PR78029)

[Bernd Schmidt]

On 10/26/2016 07:27 PM, Segher Boessenkool wrote:

On Wed, Oct 26, 2016 at 03:13:06PM +0200, Bernd Schmidt wrote:

On 10/26/2016 03:05 PM, Segher Boessenkool wrote:

2) We do not necessarily have all notes yet, if the port lets dwarf2cfi
create notes by itself.  Most (or even all?) ports do.


Hmm. Are you recording the insns in prologue_contains etc.? You could
add dependencies for a prologue insn following an epilogue insn.


I am trying this, but should then every prologue insn following epilogue
depend on all insns in that epilogue?  That goes quadratic, and we can
have at least 30 or so insns in each :-/


The scheduler copes with worse when dealing with things like memory 
references. But yes, you need lists tracking all epilogue insns.



Bernd

Re: [PATCH] sched: Do not reorder RTX_FRAME_RELATED_P insns (PR78029)

[Segher Boessenkool]

On Wed, Oct 26, 2016 at 03:13:06PM +0200, Bernd Schmidt wrote:
> On 10/26/2016 03:05 PM, Segher Boessenkool wrote:
> >2) We do not necessarily have all notes yet, if the port lets dwarf2cfi
> >create notes by itself.  Most (or even all?) ports do.
> 
> Hmm. Are you recording the insns in prologue_contains etc.? You could 
> add dependencies for a prologue insn following an epilogue insn.

I am trying this, but should then every prologue insn following epilogue
depend on all insns in that epilogue?  That goes quadratic, and we can
have at least 30 or so insns in each :-/


Segher

[v3 PATCH] Use constexpr addressof in optional, SFINAE housekeeping for any, optional and tuple.

[Ville Voutilainen]

Tested on Linux-PPC64.

2016-10-26  Ville Voutilainen  

Use constexpr addressof in optional, SFINAE housekeeping
for any, optional and tuple.
* include/std/any (__do_emplace(_Args&&...)): New.
(__do_emplace(initializer_list<_Up>, _Args&&...)): Likewise.
(__any_constructible): Likewise.
(__any_constructible_t): Use __any_constructible.
(operator=(_ValueType&&)): SFINAE in the return type.
(emplace(_Args&&...)): Likewise.
(emplace(initializer_list<_Up>, _Args&&...)): Likewise.
* include/std/optional (_Has_addressof_mem): Remove.
(_Has_addressof_free): Likewise.
(_Has_addressof): Likewise.
(__constexpr_addressof(_Tp&)): Likewise.
(operator->): Use std::__addressof.
* include/std/tuple (operator=(const tuple<_UElements...>&)):
SFINAE in return type.
(operator=(tuple<_UElements...>&&)): Likewise.
* testsuite/20_util/any/misc/any_cast_neg.cc: Adjust.
diff --git a/libstdc++-v3/include/std/any b/libstdc++-v3/include/std/any
index 45a2145..719e683 100644
--- a/libstdc++-v3/include/std/any
+++ b/libstdc++-v3/include/std/any
@@ -108,6 +108,27 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 template>
   using _Decay = enable_if_t::value, _Decayed>;
 
+/// Emplace with an object created from @p __args as the contained object.
+template >
+  void __do_emplace(_Args&&... __args)
+  {
+   reset();
+   _M_manager = &_Mgr::_S_manage;
+_Mgr::_S_create(_M_storage, std::forward<_Args>(__args)...);
+  }
+
+/// Emplace with an object created from @p __il and @p __args as
+/// the contained object.
+template >
+  void __do_emplace(initializer_list<_Up> __il, _Args&&... __args)
+  {
+   reset();
+   _M_manager = &_Mgr::_S_manage;
+_Mgr::_S_create(_M_storage, __il, std::forward<_Args>(__args)...);
+  }
+
   public:
 // construct/destruct
 
@@ -144,11 +165,15 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
}
 }
 
+template 
+using __any_constructible =
+  enable_if<__and_,
+is_constructible<_Tp, _Args...>>::value,
+ _Res>;
+
 template 
 using __any_constructible_t =
-  enable_if_t<__and_,
-is_constructible<_Tp, _Args...>>::value,
- bool>;
+  typename __any_constructible::type;
 
 /// Construct with a copy of @p __value as the contained object.
 template ,
@@ -233,9 +258,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 }
 
 /// Store a copy of @p __rhs as the contained object.
-template>
-  enable_if_t::value, any&>
+template
+  enable_if_t>::value, any&>
   operator=(_ValueType&& __rhs)
   {
*this = any(std::forward<_ValueType>(__rhs));
@@ -243,29 +267,26 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   }
 
 /// Emplace with an object created from @p __args as the contained object.
-template ,
- typename _Mgr = _Manager<_Tp>,
-  __any_constructible_t<_Tp, _Args&&...> = false>
-  void emplace(_Args&&... __args)
+template 
+  typename __any_constructible, _Args&&...>::type
+  emplace(_Args&&... __args)
   {
-   reset();
-   _M_manager = &_Mgr::_S_manage;
-_Mgr::_S_create(_M_storage, std::forward<_Args>(__args)...);
+   __do_emplace<_Decay<_ValueType>>
+ (std::forward<_Args>(__args)...);
   }
 
 /// Emplace with an object created from @p __il and @p __args as
 /// the contained object.
-template ,
- typename _Mgr = _Manager<_Tp>,
-  __any_constructible_t<_Tp, initializer_list<_Up>,
-   _Args&&...> = false>
-  void emplace(initializer_list<_Up> __il, _Args&&... __args)
+template 
+  typename __any_constructible,
+  initializer_list<_Up>,
+  _Args&&...>::type
+  emplace(initializer_list<_Up> __il, _Args&&... __args)
   {
-   reset();
-   _M_manager = &_Mgr::_S_manage;
-_Mgr::_S_create(_M_storage, __il, std::forward<_Args>(__args)...);
+   __do_emplace<_Decay<_ValueType>, _Up>
+ (__il, std::forward<_Args>(__args)...);
   }
 
 // modifiers
diff --git a/libstdc++-v3/include/std/optional 
b/libstdc++-v3/include/std/optional
index f272876..35b6932 100644
--- a/libstdc++-v3/include/std/optional
+++ b/libstdc++-v3/include/std/optional
@@ -96,53 +96,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   __throw_bad_optional_access(const char* __s)
   { _GLIBCXX_THROW_OR_ABORT(bad_optional_access(__s)); }
 
-  template
-struct _Has_addressof_mem : std::false_type { };
-
-  template
-struct _Has_addressof_mem<_Tp,

Missed hunk in microblaze.c changes

[Jeff Law]

This should have been in the microblaze.c changes, but was missed.

Essentially it had a fallthru path, but using fallthru didn't really 
simplify the code in a meaningful way.  So I just added the return to 
avoid the fallthru path.


Installed on the trunk.

Jeff
commit 370f943246c079efebe323b4a77eaaf2482292a0
Author: law 
Date:   Wed Oct 26 17:00:18 2016 +

* config/microblaze/microblaze.c (tls_mentioned_p): Avoid
fallthru.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241587 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 106a3a3..dc4fd27 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -41,6 +41,9 @@
 
 2016-10-26  Jeff Law  
 
+   * config/microblaze/microblaze.c (tls_mentioned_p): Avoid
+   fallthru.
+
* config/arc/arc.c (acr_print_operand): Adjust fallthru comment.
(check_if_valid_sleep_operand): Add missing fallthru comment.
(arc_register_move_cost): Increase buffer size.
diff --git a/gcc/config/microblaze/microblaze.c 
b/gcc/config/microblaze/microblaze.c
index 4b7a9ba..be90796 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -543,6 +543,7 @@ tls_mentioned_p (rtx x)
   case UNSPEC:
 if (XINT (x, 1) == UNSPEC_TLS)
   return 1;
+   return 0;
 
   default:
 return 0;

Re: [patch,testsuite] Support dg-require-effective-target label_offsets.

[Bernd Schmidt]

On 10/26/2016 04:46 PM, Georg-Johann Lay wrote:

+if { [istarget avr-*-*] } {
+   # If the value of a label does not fit into 16 bits, the linker
+   # will generate a stub (containing a direct jump) and we end up
+   # with the address of the stub instead of the address of the very
+   # label.  Whereas it is legitimate to use such addresses for
+   # indirect jumps, it makes no sense to perform any arithmetic
+   # on such addresses.
+   return [check_no_compiler_messages label_offsets assembly {
+   #ifdef __AVR_3_BYTE_PC__
+   #error NO
+   #endif
+   }]
+}
+return 1;


I'm not sure I understand the failure mode. Sure, you're not getting the 
address of the actual label, but the address of one that's equivalent - 
so why can't you do arithmetic on it? Where does it go wrong?


Am I right in thinking that only the execution test actually fails?


Bernd

[PATCH VECT]Swap operands for cond_reduction when necessary

[Bin Cheng]

Hi,
For stmt defining reduction, GCC vectorizer assumes that the reduction variable 
is always the last (second) operand.  Another fact is that vectorizer doesn't 
swap operands for cond_reduction during analysis stage.  The problem is GCC 
middle-end may canonicalize cond_expr into a form that reduction variable is 
not the last one.  At the moment, such case cannot be vectorized.
The patch fixes this issue by swapping operands in cond_reduction when it's 
necessary.  The patch also swaps it back if vectorization fails.  The patch 
resolves failures introduced by previous match.pd patches.  In addition, couple 
cases are XPASSed on AArch64 now, which means more loops are vectorized.  I 
will send following patch addressing those XPASS tests.
Bootstrap and test on x86_64 and AArch64 ongoing, is it OK?

Thanks,
bin

2016-10-25  Bin Cheng  

* tree-vect-loop.c (destroy_loop_vec_info): Handle cond_expr.
(vect_is_simple_reduction): Swap cond_reduction by inversion.diff --git a/gcc/tree-vect-loop.c b/gcc/tree-vect-loop.c
index 9cca9b7..4a5946b 100644
--- a/gcc/tree-vect-loop.c
+++ b/gcc/tree-vect-loop.c
@@ -1225,6 +1225,20 @@ destroy_loop_vec_info (loop_vec_info loop_vinfo, bool 
clean_stmts)
swap_ssa_operands (stmt,
   gimple_assign_rhs1_ptr (stmt),
   gimple_assign_rhs2_ptr (stmt));
+ else if (code == COND_EXPR
+  && CONSTANT_CLASS_P (gimple_assign_rhs2 (stmt)))
+   {
+ tree cond_expr = gimple_assign_rhs1 (stmt);
+ enum tree_code cond_code = TREE_CODE (cond_expr);
+
+ gcc_assert (TREE_CODE_CLASS (cond_code) == tcc_comparison);
+ /* HONOR_NANS doesn't matter when inverting it back.  */
+ cond_code = invert_tree_comparison (cond_code, false);
+ gcc_assert (cond_code != ERROR_MARK);
+ TREE_SET_CODE (cond_expr, cond_code);
+ swap_ssa_operands (stmt, gimple_assign_rhs2_ptr (stmt),
+gimple_assign_rhs3_ptr (stmt));
+   }
}
 
  /* Free stmt_vec_info.  */
@@ -3006,38 +3020,56 @@ vect_is_simple_reduction (loop_vec_info loop_info, 
gimple *phi,
   && (code == COND_EXPR
  || !def2 || gimple_nop_p (def2)
  || !flow_bb_inside_loop_p (loop, gimple_bb (def2))
-  || (def2 && flow_bb_inside_loop_p (loop, gimple_bb (def2))
- && (is_gimple_assign (def2)
+ || (def2 && flow_bb_inside_loop_p (loop, gimple_bb (def2))
+ && (is_gimple_assign (def2)
  || is_gimple_call (def2)
- || STMT_VINFO_DEF_TYPE (vinfo_for_stmt (def2))
-  == vect_induction_def
- || (gimple_code (def2) == GIMPLE_PHI
+ || STMT_VINFO_DEF_TYPE (vinfo_for_stmt (def2))
+  == vect_induction_def
+ || (gimple_code (def2) == GIMPLE_PHI
  && STMT_VINFO_DEF_TYPE (vinfo_for_stmt (def2))
-  == vect_internal_def
+  == vect_internal_def
  && !is_loop_header_bb_p (gimple_bb (def2)))
 {
-  if (check_reduction
- && orig_code != MINUS_EXPR)
-{
+  if (check_reduction && orig_code != MINUS_EXPR)
+   {
+ /* Check if we can swap operands (just for simplicity - so that
+the rest of the code can assume that the reduction variable
+is always the last (second) argument).  */
  if (code == COND_EXPR)
{
- /* No current known use where this case would be useful.  */
- if (dump_enabled_p ())
-   report_vect_op (MSG_NOTE, def_stmt,
-   "detected reduction: cannot currently swap "
-   "operands for cond_expr");
- return NULL;
+ /* Swap cond_expr by inverting the condition.  */
+ tree cond_expr = gimple_assign_rhs1 (def_stmt);
+ enum tree_code invert_code = ERROR_MARK;
+ enum tree_code cond_code = TREE_CODE (cond_expr);
+
+ if (TREE_CODE_CLASS (cond_code) == tcc_comparison)
+   {
+ bool honor_nans = HONOR_NANS (TREE_OPERAND (cond_expr, 0));
+ invert_code = invert_tree_comparison (cond_code, honor_nans);
+   }
+ if (invert_code != ERROR_MARK)
+   {
+ TREE_SET_CODE (cond_expr, invert_code);
+ swap_ssa_operands (def_stmt,
+gimple_assign_rhs2_ptr (def_stmt),
+gimple_assign_rhs3_ptr (def_stmt));
+   }
+ else
+   {
+ if (dump_enabled_p ())
+   report_vect_op (MSG_NOTE, def_stmt,
+   

[PATCH, gcc/ARM] Add support for Cortex-M23

[Thomas Preudhomme]

Hi,

This patch adds support for the Cortex-M23 processor launched by ARM [1]. The 
patch adds support for the name and wires it up to the ARMv8-M Baseline 
architecture and arm_v6m_tune tuning parameters for the time being. It also 
updates documentation to mention this new processor.


[1] http://www.arm.com/products/processors/cortex-m/cortex-m23-processor.php

ChangeLog entry is as follows:

*** gcc/Changelog ***

2016-10-26  Thomas Preud'homme  

* config/arm/arm-arches.def (armv8-m.base): Set Cortex-M23 as
representative core for this architecture.
* config/arm/arm-cores.def (cortex-m23): Define new processor.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Likewise.
* config/arm/arm.c (arm_v6m_tune): Add Cortex-M23 to the list of cores
this tuning parameters apply to in the comment.
* config/arm/bpabi.h (BE8_LINK_SPEC): Add Cortex-M23 to the list of
valid -mcpu options.
* doc/invoke.texi (ARM Options): Document new Cortex-M23 processor.


Tested by building libgcc and libstdc++ for Cortex-M23 and running a hello world 
compiled for it.


Is this ok for master?

Best regards,

Thomas
diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index 4b196a7d1188de5eca028e5c2597bbc20835201f..9293429b3f9a026bcdacc1651c534bdf14d4df1e 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -69,7 +69,7 @@ ARM_ARCH ("armv8.2-a", cortexa53,  8A,
 ARM_ARCH ("armv8.2-a+fp16", cortexa53,  8A,
 	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
 			 FL2_FOR_ARCH8_2A | FL2_FP16INST))
-ARM_ARCH("armv8-m.base", cortexm0, 8M_BASE,
+ARM_ARCH("armv8-m.base", cortexm23, 8M_BASE,
 	 ARM_FSET_MAKE_CPU1 (			  FL_FOR_ARCH8M_BASE))
 ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN,
 	 ARM_FSET_MAKE_CPU1(FL_CO_PROC |	  FL_FOR_ARCH8M_MAIN))
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 2072e1e6f8d84533deead24e6fb0b6aff7603f24..940b5de82f0340fc0c26be80d47729bc1f193db0 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -166,6 +166,7 @@ ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_
 ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
 
 /* V8 Architecture Processors */
+ARM_CORE("cortex-m23",	cortexm23, cortexm23,	8M_BASE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8M_BASE), v6m)
 ARM_CORE("cortex-a32",	cortexa32, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
 ARM_CORE("cortex-a35",	cortexa35, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
 ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index ee9e3bb7ec57e0e8f2f15b83442711b9faf82d20..de712924afd33ba1e6e65cb56a5b260858d0cc4f 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -307,6 +307,9 @@ EnumValue
 Enum(processor_type) String(cortex-a17.cortex-a7) Value(cortexa17cortexa7)
 
 EnumValue
+Enum(processor_type) String(cortex-m23) Value(cortexm23)
+
+EnumValue
 Enum(processor_type) String(cortex-a32) Value(cortexa32)
 
 EnumValue
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index 594ce9d1734451f89812200191cb35f1f579289e..46c2c9258bcad43618a50f6201414fa084cb5b56 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -32,9 +32,9 @@
 	cortexr4f,cortexr5,cortexr7,
 	cortexr8,cortexm7,cortexm4,
 	cortexm3,marvell_pj4,cortexa15cortexa7,
-	cortexa17cortexa7,cortexa32,cortexa35,
-	cortexa53,cortexa57,cortexa72,
-	cortexa73,exynosm1,qdf24xx,
-	xgene1,cortexa57cortexa53,cortexa72cortexa53,
-	cortexa73cortexa35,cortexa73cortexa53"
+	cortexa17cortexa7,cortexm23,cortexa32,
+	cortexa35,cortexa53,cortexa57,
+	cortexa72,cortexa73,exynosm1,
+	qdf24xx,xgene1,cortexa57cortexa53,
+	cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 022c1d72a1272e56397dc7e2018483e77f18b90d..39b2da05d2135c68032231bb7780104061355786 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2243,7 +2243,8 @@ const struct tune_params arm_cortex_m7_tune =
 };
 
 /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than
-   arm_v6t2_tune. It is used for cortex-m0, cortex-m1 and cortex-m0plus.  */
+   arm_v6t2_tune.  It is used for cortex-m0, cortex-m1, cortex-m0plus and
+   cortex-m23.  */
 const struct tune_params arm_v6m_tune =
 {
   arm_9e_rtx_costs,
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index 0da98fb711bdcaf5add6e392060f4edaddf6cf05..302302f0d2d522fe282bb1d12687b53de72cae25 100644
--- 

[PATCH, gcc/ARM] Add support for Cortex-M33

[Thomas Preudhomme]

Hi,

This patch adds support for the Cortex-M33 processor launched by ARM [1]. The 
patch adds support for the name and wires it up to the ARMv8-M Mainline with DSP 
extensions architecture and arm_v7m_tune tuning parameters for the time being. 
It also updates documentation to mention this new processor.


[1] http://www.arm.com/products/processors/cortex-m/cortex-m33-processor.php

ChangeLog entry is as follows:

*** gcc/Changelog ***

2016-10-26  Thomas Preud'homme  

* config/arm/arm-arches.def (armv8-m.main+dsp): Set Cortex-M33 as
representative core for this architecture.
* config/arm/arm-cores.def (cortex-m33): Define new processor.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Likewise.
* config/arm/bpabi.h (BE8_LINK_SPEC): Add Cortex-M33 to the list of
valid -mcpu options.
* doc/invoke.texi (ARM Options): Document new Cortex-M33 processor.


Tested by building libgcc and libstdc++ for Cortex-M33 and running a hello world 
compiled for it.


Is this ok for master?

Best regards,

Thomas
diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index 9293429b3f9a026bcdacc1651c534bdf14d4df1e..cd79bc505853d4dda6cf2e58bdc2d129032befef 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -73,7 +73,7 @@ ARM_ARCH("armv8-m.base", cortexm23, 8M_BASE,
 	 ARM_FSET_MAKE_CPU1 (			  FL_FOR_ARCH8M_BASE))
 ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN,
 	 ARM_FSET_MAKE_CPU1(FL_CO_PROC |	  FL_FOR_ARCH8M_MAIN))
-ARM_ARCH("armv8-m.main+dsp", cortexm7, 8M_MAIN,
+ARM_ARCH("armv8-m.main+dsp", cortexm33, 8M_MAIN,
 	 ARM_FSET_MAKE_CPU1(FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN))
 ARM_ARCH("iwmmxt",  iwmmxt, 5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
 ARM_ARCH("iwmmxt2", iwmmxt2,5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 940b5de82f0340fc0c26be80d47729bc1f193db0..ec63ee4abe54af06cd5531486f294f9a8dae71a1 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -168,6 +168,7 @@ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	7A,	ARM_FSET_MAKE_
 /* V8 Architecture Processors */
 ARM_CORE("cortex-m23",	cortexm23, cortexm23,	8M_BASE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8M_BASE), v6m)
 ARM_CORE("cortex-a32",	cortexa32, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
+ARM_CORE("cortex-m33",	cortexm33, cortexm33,	8M_MAIN, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m)
 ARM_CORE("cortex-a35",	cortexa35, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
 ARM_CORE("cortex-a53",	cortexa53, cortexa53,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
 ARM_CORE("cortex-a57",	cortexa57, cortexa57,	8A,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index de712924afd33ba1e6e65cb56a5b260858d0cc4f..f7886b94be779fcba91506e77574662fe7188876 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -313,6 +313,9 @@ EnumValue
 Enum(processor_type) String(cortex-a32) Value(cortexa32)
 
 EnumValue
+Enum(processor_type) String(cortex-m33) Value(cortexm33)
+
+EnumValue
 Enum(processor_type) String(cortex-a35) Value(cortexa35)
 
 EnumValue
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index 46c2c9258bcad43618a50f6201414fa084cb5b56..e782baccf424e51ac19ef5f02d25ed4f4eb0541d 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -33,8 +33,9 @@
 	cortexr8,cortexm7,cortexm4,
 	cortexm3,marvell_pj4,cortexa15cortexa7,
 	cortexa17cortexa7,cortexm23,cortexa32,
-	cortexa35,cortexa53,cortexa57,
-	cortexa72,cortexa73,exynosm1,
-	qdf24xx,xgene1,cortexa57cortexa53,
-	cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53"
+	cortexm33,cortexa35,cortexa53,
+	cortexa57,cortexa72,cortexa73,
+	exynosm1,qdf24xx,xgene1,
+	cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
+	cortexa73cortexa53"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
index 302302f0d2d522fe282bb1d12687b53de72cae25..d45a1ca421901da25e16d965a9474438ea10f349 100644
--- a/gcc/config/arm/bpabi.h
+++ b/gcc/config/arm/bpabi.h
@@ -97,7 +97,7 @@
|march=armv8.2-a+fp16\
|march=armv8-m.base|mcpu=cortex-m23			\
|march=armv8-m.main	\
-   |march=armv8-m.main+dsp\
+   |march=armv8-m.main+dsp|mcpu=cortex-m33		\
:%{!r:--be8}}}"
 #else
 #define BE8_LINK_SPEC \
@@ -136,7 +136,7 @@
|march=armv8.2-a+fp16\
|march=armv8-m.base|mcpu=cortex-m23			\
|march=armv8-m.main	\
-   |march=armv8-m.main+dsp\
+   

[RFC PATCH] avoid printing type suffix with %E

[Martin Sebor]

When formatting an integer constant using the %E directive GCC
includes a suffix that indicates its type.  This can perhaps be
useful in some situations but in my experience it's distracting
and gets in the way when writing tests.

Here's an example:

  $ cat b.c && gcc b.c
  constexpr __SIZE_TYPE__ x = 2;

  enum E: bool { e = x };
  b.c:3:20: error: enumerator value 2ul is outside the range of 
underlying type ‘bool’

   enum E: bool { e = x };
  ^

Notice the "2ul" in the error message.

As far as I can tell, Clang avoids printing the suffix and I think
it would be nice if the GCC pretty printer made it possible to avoid
it as well.

The attached patch implements one such approach by having the pretty
printer recognize the space format flag to suppress the type suffix,
so "%E" still prints the suffix but "% E" does not.  I did this to
preserve the existing output but I think it would be nicer to avoid
printing the suffix with %E and treat (for instance) the pound sign
as a request to add the suffix.  I have tested the attached patch
but not the alternative.

Does anyone have any comments/suggestions for which of the two
approaches would be preferable (or what I may have missed here)?
I CC David as the diagnostic maintainer.

Thanks
Martin

gcc/c/ChangeLog:
2016-10-26  Martin Sebor  

	* c-objc-common.c (c_tree_printer::get_flag): Declare new function
	(c_tree_printer::set_flag): Same.

gcc/c-family/ChangeLog:
2016-10-26  Martin Sebor  

	* c-pretty-print.c (c_tree_printer::get_flag): Define.
	(c_tree_printer::set_flag): Define.
	(pp_c_integer_constant): Don't print type suffix when space
	is set in flags.
	* c-pretty-print.h (pp_c_flag_space): Add enumerator.

gcc/cp/ChangeLog:
2016-10-26  Martin Sebor  

	* error.c (cp_printer): Set space in flags.

gcc/ChangeLog:
2016-10-26  Martin Sebor  

	* pretty-print.c (pp_format): Recognize space.
	* pretty-print.h (pretty_printer::get_flag): New function.
	 (pretty_printer::set_flag): Same.

diff --git a/gcc/c-family/c-pretty-print.c b/gcc/c-family/c-pretty-print.c
index 90428ca..7d9375d 100644
--- a/gcc/c-family/c-pretty-print.c
+++ b/gcc/c-family/c-pretty-print.c
@@ -292,6 +292,26 @@ pp_c_pointer (c_pretty_printer *pp, tree t)
 }
 }
 
+bool
+c_pretty_printer::get_flag (char flag)
+{
+  return ' ' == flag && (flags & pp_c_flag_space);
+}
+
+bool
+c_pretty_printer::set_flag (char flag, bool value)
+{
+  gcc_assert (flag == ' ');
+
+  bool previous = c_pretty_printer::get_flag (flag);
+  if (value)
+flag |= pp_c_flag_space;
+  else
+flag &= ~pp_c_flag_space;
+
+  return previous;
+}
+
 /* simple-type-specifier:
  type-specifier
 
@@ -926,24 +946,34 @@ pp_c_integer_constant (c_pretty_printer *pp, tree i)
   print_hex (wi, pp_buffer (pp)->digit_buffer);
   pp_string (pp, pp_buffer (pp)->digit_buffer);
 }
-  if (TYPE_UNSIGNED (type))
-pp_character (pp, 'u');
-  if (type == long_integer_type_node || type == long_unsigned_type_node)
-pp_character (pp, 'l');
-  else if (type == long_long_integer_type_node
-	   || type == long_long_unsigned_type_node)
-pp_string (pp, "ll");
-  else for (idx = 0; idx < NUM_INT_N_ENTS; idx ++)
-if (int_n_enabled_p[idx])
-  {
-	char buf[2+20];
-	if (type == int_n_trees[idx].signed_type
-	|| type == int_n_trees[idx].unsigned_type)
-	  {
-	sprintf (buf, "I%d", int_n_data[idx].bitsize);
-	pp_string (pp, buf);
-	  }
-  }
+
+  if (pp->get_flag (' '))
+{
+  if (TYPE_UNSIGNED (type))
+	pp_character (pp, 'u');
+
+  if (type == long_integer_type_node || type == long_unsigned_type_node)
+	pp_character (pp, 'l');
+  else if (type == long_long_integer_type_node
+	   || type == long_long_unsigned_type_node)
+	pp_string (pp, "ll");
+  else
+	{
+	  for (idx = 0; idx < NUM_INT_N_ENTS; idx ++)
+	{
+	  if (int_n_enabled_p[idx])
+		{
+		  char buf[2+20];
+		  if (type == int_n_trees[idx].signed_type
+		  || type == int_n_trees[idx].unsigned_type)
+		{
+		  sprintf (buf, "I%d", int_n_data[idx].bitsize);
+		  pp_string (pp, buf);
+		}
+		}
+	}
+	}
+}
 }
 
 /* Print out a CHARACTER literal.  */
diff --git a/gcc/c-family/c-pretty-print.h b/gcc/c-family/c-pretty-print.h
index 253f192..10ad5d9 100644
--- a/gcc/c-family/c-pretty-print.h
+++ b/gcc/c-family/c-pretty-print.h
@@ -30,7 +30,8 @@ enum pp_c_pretty_print_flags
   {
  pp_c_flag_abstract = 1 << 1,
  pp_c_flag_gnu_v3 = 1 << 2,
- pp_c_flag_last_bit = 3
+ pp_c_flag_space = 1 << 3,
+ pp_c_flag_last_bit = 4
   };
 
 
@@ -51,6 +52,10 @@ struct c_pretty_printer : pretty_printer
 {
   c_pretty_printer ();
 
+  /* Get and set the format flag.  */
+  virtual bool get_flag (char);
+  virtual bool set_flag (char, bool);
+
   // Format string, possibly translated.
   void translate_string (const char *);
 
diff --git a/gcc/c/c-objc-common.c b/gcc/c/c-objc-common.c
index 

Fix ARC port WRT fallthru and sprintf warnings

[Jeff Law]

The usuall fallthru and sprintf stuff.  These required a bit more 
thought, but nothing terribly taxing.


Installing on the trunk.

jeff
commit 7227c03164300c5f5188a1261b3c57f0b7072394
Author: law 
Date:   Wed Oct 26 16:33:22 2016 +

* config/arc/arc.c (acr_print_operand): Adjust fallthru comment.
(check_if_valid_sleep_operand): Add missing fallthru comment.
(arc_register_move_cost): Increase buffer size.
* config/arc/arc.md (cbranch4si_scratch): Add missing fallthru
comment.
* config/arc/predicates.md (move_str_operand): Avoid fallthru.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241585 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ce2693b..1aa397e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,12 @@
 2016-10-26  Jeff Law  
 
+   * config/arc/arc.c (acr_print_operand): Adjust fallthru comment.
+   (check_if_valid_sleep_operand): Add missing fallthru comment.
+   (arc_register_move_cost): Increase buffer size.
+   * config/arc/arc.md (cbranch4si_scratch): Add missing fallthru
+   comment.
+   * config/arc/predicates.md (move_str_operand): Avoid fallthru.
+
* config/cr16/cr16.c (cr16_print_operand): Add missing fallthru
comment.  Add gcc_unreachable for path that should never happen.
 
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 21bba0c..0e7b63d 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -3459,7 +3459,8 @@ arc_print_operand (FILE *file, rtx x, int code)
  fprintf (file, "0x%08lx", l);
  break;
}
-  /* Fall through.  Let output_addr_const deal with it.  */
+  /* FALLTHRU */
+  /* Let output_addr_const deal with it.  */
 default :
   if (flag_pic
  || (GET_CODE (x) == CONST
@@ -6197,6 +6198,7 @@ check_if_valid_sleep_operand (rtx *operands, int opno)
 case CONST_INT :
if( UNSIGNED_INT6 (INTVAL (operands[opno])))
return true;
+/* FALLTHRU */
 default:
fatal_error (input_location,
 "operand for sleep instruction must be an unsigned 6 bit 
compile-time constant");
@@ -7284,7 +7286,7 @@ arc_register_move_cost (machine_mode,
 int
 arc_output_addsi (rtx *operands, bool cond_p, bool output_p)
 {
-  char format[32];
+  char format[35];
 
   int match = operands_match_p (operands[0], operands[1]);
   int match2 = operands_match_p (operands[0], operands[2]);
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 3c531d9..e127d5b 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -4891,6 +4891,7 @@
case 4: return \"br%d0%* %1, %B2, %^%l3\";
case 8: if (!brcc_nolimm_operator (operands[0], VOIDmode))
 return \"br%d0%* %1, %B2, %^%l3\";
+   /* FALLTHRU */
case 6: case 10:
case 12:return \"cmp%? %1, %B2\\n\\tb%d0%* %^%l3%&;br%d0 out of range\";
default: fprintf (stderr, \"unexpected length %d\\n\", get_attr_length 
(insn)); fflush (stderr); gcc_unreachable ();
diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index f85f931..cb75dbc 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -266,6 +266,7 @@
 case SYMBOL_REF :
   if (SYMBOL_REF_TLS_MODEL (op))
return 0;
+  return 1;
 case LABEL_REF :
   return 1;
 case CONST :

Re: [PATCH] Fix build problem with eCos/newlib (PR 78110)

[Jonathan Wakely]

On 26/10/16 16:26 +, Bernd Edlinger wrote:

* libsupc++/new_opa.cc: Don't include  in a free standing
environmnet.  Declare memalign directly in that case.


Typo "environmnet".

OK for trunk, thanks.

We might actually want to avoid  in other cases, as some
systems have a #warning in  saying it's deprecated ...
although they probably have aligned_alloc or posix_memalign anyway so
we won't try to use memalign.

Re: [PATCHv2 4/7, GCC, ARM, V8M] ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers

[Kyrill Tkachov]

On 26/10/16 17:26, Andre Vieira (lists) wrote:

On 26/10/16 13:51, Kyrill Tkachov wrote:

Hi Andre,

On 25/10/16 17:29, Andre Vieira (lists) wrote:

On 24/08/16 12:01, Andre Vieira (lists) wrote:

On 25/07/16 14:23, Andre Vieira (lists) wrote:

This patch extends support for the ARMv8-M Security Extensions
'cmse_nonsecure_entry' attribute to safeguard against leak of
information through unbanked registers.

When returning from a nonsecure entry function we clear all
caller-saved
registers that are not used to pass return values, by writing either
the
LR, in case of general purpose registers, or the value 0, in case of FP
registers. We use the LR to write to APSR and FPSCR too. We
currently do
not support entry functions that pass arguments or return variables on
the stack and we diagnose this. This patch relies on the existing code
to make sure callee-saved registers used in cmse_nonsecure_entry
functions are saved and restored thus retaining their nonsecure mode
value, this should be happening already as it is required by AAPCS.

This patch also clears padding bits for cmse_nonsecure_entry functions
with struct and union return types. For unions a bit is only considered
a padding bit if it is an unused bit in every field of that union. The
function that calculates these is used in a later patch to do the same
for arguments of cmse_nonsecure_call's.

*** gcc/ChangeLog ***
2016-07-25  Andre Vieira
  Thomas Preud'homme  

  * config/arm/arm.c (output_return_instruction): Clear
  registers.
  (thumb2_expand_return): Likewise.
  (thumb1_expand_epilogue): Likewise.
  (thumb_exit): Likewise.
  (arm_expand_epilogue): Likewise.
  (cmse_nonsecure_entry_clear_before_return): New.
  (comp_not_to_clear_mask_str_un): New.
  (compute_not_to_clear_mask): New.
  * config/arm/thumb1.md (*epilogue_insns): Change length
attribute.
  * config/arm/thumb2.md (*thumb2_return): Likewise.

*** gcc/testsuite/ChangeLog ***
2016-07-25  Andre Vieira
  Thomas Preud'homme  

  * gcc.target/arm/cmse/cmse.exp: Test different multilibs
separate.
  * gcc.target/arm/cmse/struct-1.c: New.
  * gcc.target/arm/cmse/bitfield-1.c: New.
  * gcc.target/arm/cmse/bitfield-2.c: New.
  * gcc.target/arm/cmse/bitfield-3.c: New.
  * gcc.target/arm/cmse/baseline/cmse-2.c: Test that
registers are
cleared.
  * gcc.target/arm/cmse/mainline/soft/cmse-5.c: New.
  * gcc.target/arm/cmse/mainline/hard/cmse-5.c: New.
  * gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: New.
  * gcc.target/arm/cmse/mainline/softfp/cmse-5.c: New.
  * gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: New.


Updated this patch to correctly clear only the cumulative
exception-status (0-4,7) and the condition code bits (28-31) of the
FPSCR. I also adapted the code to be handle the bigger floating point
register files.



This patch extends support for the ARMv8-M Security Extensions
'cmse_nonsecure_entry' attribute to safeguard against leak of
information through unbanked registers.

When returning from a nonsecure entry function we clear all caller-saved
registers that are not used to pass return values, by writing either the
LR, in case of general purpose registers, or the value 0, in case of FP
registers. We use the LR to write to APSR. For FPSCR we clear only the
cumulative exception-status (0-4, 7) and the condition code bits
(28-31). We currently do not support entry functions that pass arguments
or return variables on the stack and we diagnose this. This patch relies
on the existing code to make sure callee-saved registers used in
cmse_nonsecure_entry functions are saved and restored thus retaining
their nonsecure mode value, this should be happening already as it is
required by AAPCS.

This patch also clears padding bits for cmse_nonsecure_entry functions
with struct and union return types. For unions a bit is only considered
a padding bit if it is an unused bit in every field of that union. The
function that calculates these is used in a later patch to do the same
for arguments of cmse_nonsecure_call's.

*** gcc/ChangeLog ***
2016-07-xx  Andre Vieira
  Thomas Preud'homme  

  * config/arm/arm.c (output_return_instruction): Clear
  registers.
  (thumb2_expand_return): Likewise.
  (thumb1_expand_epilogue): Likewise.
  (thumb_exit): Likewise.
  (arm_expand_epilogue): Likewise.
  (cmse_nonsecure_entry_clear_before_return): New.
  (comp_not_to_clear_mask_str_un): New.
  (compute_not_to_clear_mask): New.
  * config/arm/thumb1.md (*epilogue_insns): Change length
attribute.
  * 

Re: [PATCHv2 2/7, GCC, ARM, V8M] Handling ARMv8-M Security Extension's cmse_nonsecure_entry attribute

[Kyrill Tkachov]

On 26/10/16 17:28, Andre Vieira (lists) wrote:

On 26/10/16 10:33, Kyrill Tkachov wrote:

+static tree
+arm_handle_cmse_nonsecure_entry (tree *node, tree name,
+ tree /* args */,
+ int /* flags */,
+ bool *no_add_attrs)
+{
+  tree fndecl;
+
+  if (!use_cmse)
+{
+  *no_add_attrs = true;
+  return NULL_TREE;
+}

Do you also want to warn the user here that the attribute will be ignored?
This looks ok to me otherwise.


Can easily do and might be more user friendly. How about
" attribute ignored without -mcmse option."


Yes, that's fine (without the full stop at the end)
Kyrill


Cheers,
Andre

Re: [PATCHv2 2/7, GCC, ARM, V8M] Handling ARMv8-M Security Extension's cmse_nonsecure_entry attribute

[Andre Vieira (lists)]

On 26/10/16 10:33, Kyrill Tkachov wrote:
> 
> +static tree
> +arm_handle_cmse_nonsecure_entry (tree *node, tree name,
> + tree /* args */,
> + int /* flags */,
> + bool *no_add_attrs)
> +{
> +  tree fndecl;
> +
> +  if (!use_cmse)
> +{
> +  *no_add_attrs = true;
> +  return NULL_TREE;
> +}
> 
> Do you also want to warn the user here that the attribute will be ignored?
> This looks ok to me otherwise.
> 

Can easily do and might be more user friendly. How about
" attribute ignored without -mcmse option."

Cheers,
Andre

And now for the cr16

[Jeff Law]

Clearly a desired fallthru in cr16_pritn_operand handling of 'g'.

Shortly thereafter there's another fallthru, but AFAICT it shouldn't 
ever happen.  I've added a gcc_unreachable in that case.


Installing on the trunk.


Jeff
commit 24e65f049fd63325296b4172fc175633a2cde8d0
Author: law 
Date:   Wed Oct 26 16:27:44 2016 +

* config/cr16/cr16.c (cr16_print_operand): Add missing fallthru
comment.  Add gcc_unreachable for path that should never happen.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241584 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bf5080a..ce2693b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 2016-10-26  Jeff Law  
 
+   * config/cr16/cr16.c (cr16_print_operand): Add missing fallthru
+   comment.  Add gcc_unreachable for path that should never happen.
+
* config/epiphany/epiphany.c (epiphany_print_operand): Adjust
fallthru comment.
 
diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c
index 530ccba..cc24fa5 100644
--- a/gcc/config/cr16/cr16.c
+++ b/gcc/config/cr16/cr16.c
@@ -1476,6 +1476,7 @@ cr16_print_operand (FILE * file, rtx x, int code)
 case 'g':
   /* 'g' is used for implicit mem: dereference.  */
   ptr_dereference = 1;
+  /* FALLTHRU */
 case 'f':
 case 0:
   /* default.  */
@@ -1528,6 +1529,7 @@ cr16_print_operand (FILE * file, rtx x, int code)
  cr16_print_operand_address (file, VOIDmode, x);
  return;
}
+  gcc_unreachable ();
 default:
   output_operand_lossage ("invalid %%xn code");
 }

Re: [PATCH, wwwdocs] Add link to GCC 7 changes.html

[Peter Bergner]

On 10/25/16 12:50 PM, Peter Bergner wrote:
> On 10/25/16 12:17 PM, Gerald Pfeifer wrote:
>> Perhaps add a disclaimer at the top of changes.html that this
>> is still work in progress as part of that commit?
> 
> Do you mean like the following?  If so, we'd have to remember to remove
> the last hunk when GCC 7 is released.

...unless we want to add a little PHP (would need to rename changes.html
to changes.php) to test for a file that is created upon release.  Thoughts?

Peter


Index: changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-7/changes.html,v
retrieving revision 1.20
diff -u -r1.20 changes.html
--- changes.html25 Oct 2016 02:04:00 -  1.20
+++ changes.html26 Oct 2016 16:22:51 -
@@ -19,6 +19,14 @@
 
 
 
+Disclaimer: GCC 7 has not been released yet, so this document is
+a work-in-progress.";
+}
+?> 
+
+
 Caveats
 
   GCC now uses https://gcc.gnu.org/wiki/LRAIsDefault;>LRA by

Re: [PATCHv2 4/7, GCC, ARM, V8M] ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers

[Andre Vieira (lists)]

On 26/10/16 13:51, Kyrill Tkachov wrote:
> Hi Andre,
> 
> On 25/10/16 17:29, Andre Vieira (lists) wrote:
>> On 24/08/16 12:01, Andre Vieira (lists) wrote:
>>> On 25/07/16 14:23, Andre Vieira (lists) wrote:
 This patch extends support for the ARMv8-M Security Extensions
 'cmse_nonsecure_entry' attribute to safeguard against leak of
 information through unbanked registers.

 When returning from a nonsecure entry function we clear all
 caller-saved
 registers that are not used to pass return values, by writing either
 the
 LR, in case of general purpose registers, or the value 0, in case of FP
 registers. We use the LR to write to APSR and FPSCR too. We
 currently do
 not support entry functions that pass arguments or return variables on
 the stack and we diagnose this. This patch relies on the existing code
 to make sure callee-saved registers used in cmse_nonsecure_entry
 functions are saved and restored thus retaining their nonsecure mode
 value, this should be happening already as it is required by AAPCS.

 This patch also clears padding bits for cmse_nonsecure_entry functions
 with struct and union return types. For unions a bit is only considered
 a padding bit if it is an unused bit in every field of that union. The
 function that calculates these is used in a later patch to do the same
 for arguments of cmse_nonsecure_call's.

 *** gcc/ChangeLog ***
 2016-07-25  Andre Vieira
  Thomas Preud'homme  

  * config/arm/arm.c (output_return_instruction): Clear
  registers.
  (thumb2_expand_return): Likewise.
  (thumb1_expand_epilogue): Likewise.
  (thumb_exit): Likewise.
  (arm_expand_epilogue): Likewise.
  (cmse_nonsecure_entry_clear_before_return): New.
  (comp_not_to_clear_mask_str_un): New.
  (compute_not_to_clear_mask): New.
  * config/arm/thumb1.md (*epilogue_insns): Change length
 attribute.
  * config/arm/thumb2.md (*thumb2_return): Likewise.

 *** gcc/testsuite/ChangeLog ***
 2016-07-25  Andre Vieira
  Thomas Preud'homme  

  * gcc.target/arm/cmse/cmse.exp: Test different multilibs
 separate.
  * gcc.target/arm/cmse/struct-1.c: New.
  * gcc.target/arm/cmse/bitfield-1.c: New.
  * gcc.target/arm/cmse/bitfield-2.c: New.
  * gcc.target/arm/cmse/bitfield-3.c: New.
  * gcc.target/arm/cmse/baseline/cmse-2.c: Test that
 registers are
 cleared.
  * gcc.target/arm/cmse/mainline/soft/cmse-5.c: New.
  * gcc.target/arm/cmse/mainline/hard/cmse-5.c: New.
  * gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: New.
  * gcc.target/arm/cmse/mainline/softfp/cmse-5.c: New.
  * gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: New.

>>> Updated this patch to correctly clear only the cumulative
>>> exception-status (0-4,7) and the condition code bits (28-31) of the
>>> FPSCR. I also adapted the code to be handle the bigger floating point
>>> register files.
>>>
>>> 
>>>
>>> This patch extends support for the ARMv8-M Security Extensions
>>> 'cmse_nonsecure_entry' attribute to safeguard against leak of
>>> information through unbanked registers.
>>>
>>> When returning from a nonsecure entry function we clear all caller-saved
>>> registers that are not used to pass return values, by writing either the
>>> LR, in case of general purpose registers, or the value 0, in case of FP
>>> registers. We use the LR to write to APSR. For FPSCR we clear only the
>>> cumulative exception-status (0-4, 7) and the condition code bits
>>> (28-31). We currently do not support entry functions that pass arguments
>>> or return variables on the stack and we diagnose this. This patch relies
>>> on the existing code to make sure callee-saved registers used in
>>> cmse_nonsecure_entry functions are saved and restored thus retaining
>>> their nonsecure mode value, this should be happening already as it is
>>> required by AAPCS.
>>>
>>> This patch also clears padding bits for cmse_nonsecure_entry functions
>>> with struct and union return types. For unions a bit is only considered
>>> a padding bit if it is an unused bit in every field of that union. The
>>> function that calculates these is used in a later patch to do the same
>>> for arguments of cmse_nonsecure_call's.
>>>
>>> *** gcc/ChangeLog ***
>>> 2016-07-xx  Andre Vieira
>>>  Thomas Preud'homme  
>>>
>>>  * config/arm/arm.c (output_return_instruction): Clear
>>>  registers.
>>>  (thumb2_expand_return): Likewise.
>>>  

[PATCH] Fix build problem with eCos/newlib (PR 78110)

[Bernd Edlinger]

Hi,

this patch avoids including malloc.h in free standing builds with
eCos/newlib, and declares the memalign directly.


Successfully built a cross compiler for eCos.
Is it OK for trunk?


Thanks
Bernd.
2016-10-26  Bernd Edlinger  

	* libsupc++/new_opa.cc: Don't include  in a free standing
	environmnet.  Declare memalign directly in that case.

--- libstdc++-v3/libsupc++/new_opa.cc.orig	2016-09-16 20:09:14.0 +0200
+++ libstdc++-v3/libsupc++/new_opa.cc	2016-10-26 09:40:41.722542566 +0200
@@ -48,7 +48,11 @@
   return nullptr;
 }
 #elif _GLIBCXX_HAVE_MEMALIGN
+#if _GLIBCXX_HOSTED
 #include 
+#else
+extern "C" void *memalign(std::size_t boundary, std::size_t size);
+#endif
 #define aligned_alloc memalign
 #else
 // The C library doesn't provide any aligned allocation functions, declare

[committed] Fix OpenMP implicit map fortran ICE (PR fortran/77973)

[Jakub Jelinek]

Hi!

The Fortran omp_finish_clause langhook can add OMP_CLAUSE_MAP clauses with
VAR_DECL OMP_CLAUSE_SIZE (or change one with constant into non-constant
one), if that appears in another OpenMP region, we need to notice the
variables there so that they can be properly shared/firstprivatized etc.

Bootstrapped/regtested on x86_64-linux and i686-linux, committed to trunk.

2016-10-26  Jakub Jelinek  
Martin Liska  

PR fortran/77973
* gimplify.c (gimplify_adjust_omp_clauses_1): For all added map
clauses with OMP_CLAUSE_SIZE being a decl, call omp_notice_variable
on outer context if any.

* gfortran.dg/gomp/pr77973.f90: New test.

--- gcc/gimplify.c.jj   2016-10-21 17:09:19.0 +0200
+++ gcc/gimplify.c  2016-10-26 13:54:45.822854763 +0200
@@ -8421,9 +8421,10 @@ gimplify_adjust_omp_clauses_1 (splay_tre
   && omp_shared_to_firstprivate_optimizable_decl_p (decl))
 omp_mark_stores (gimplify_omp_ctxp->outer_context, decl);
 
+  tree chain = *list_p;
   clause = build_omp_clause (input_location, code);
   OMP_CLAUSE_DECL (clause) = decl;
-  OMP_CLAUSE_CHAIN (clause) = *list_p;
+  OMP_CLAUSE_CHAIN (clause) = chain;
   if (private_debug)
 OMP_CLAUSE_PRIVATE_DEBUG (clause) = 1;
   else if (code == OMP_CLAUSE_PRIVATE && (flags & GOVD_PRIVATE_OUTER_REF))
@@ -8450,7 +8451,7 @@ gimplify_adjust_omp_clauses_1 (splay_tre
   OMP_CLAUSE_SET_MAP_KIND (clause, GOMP_MAP_ALLOC);
   OMP_CLAUSE_MAP_MAYBE_ZERO_LENGTH_ARRAY_SECTION (clause) = 1;
   OMP_CLAUSE_SET_MAP_KIND (nc, GOMP_MAP_FIRSTPRIVATE_POINTER);
-  OMP_CLAUSE_CHAIN (nc) = *list_p;
+  OMP_CLAUSE_CHAIN (nc) = chain;
   OMP_CLAUSE_CHAIN (clause) = nc;
   struct gimplify_omp_ctx *ctx = gimplify_omp_ctxp;
   gimplify_omp_ctxp = ctx->outer_context;
@@ -8520,7 +8521,7 @@ gimplify_adjust_omp_clauses_1 (splay_tre
   tree nc = build_omp_clause (input_location, OMP_CLAUSE_LASTPRIVATE);
   OMP_CLAUSE_DECL (nc) = decl;
   OMP_CLAUSE_LASTPRIVATE_FIRSTPRIVATE (nc) = 1;
-  OMP_CLAUSE_CHAIN (nc) = *list_p;
+  OMP_CLAUSE_CHAIN (nc) = chain;
   OMP_CLAUSE_CHAIN (clause) = nc;
   struct gimplify_omp_ctx *ctx = gimplify_omp_ctxp;
   gimplify_omp_ctxp = ctx->outer_context;
@@ -8531,6 +8532,12 @@ gimplify_adjust_omp_clauses_1 (splay_tre
   struct gimplify_omp_ctx *ctx = gimplify_omp_ctxp;
   gimplify_omp_ctxp = ctx->outer_context;
   lang_hooks.decls.omp_finish_clause (clause, pre_p);
+  if (gimplify_omp_ctxp)
+for (; clause != chain; clause = OMP_CLAUSE_CHAIN (clause))
+  if (OMP_CLAUSE_CODE (clause) == OMP_CLAUSE_MAP
+ && DECL_P (OMP_CLAUSE_SIZE (clause)))
+   omp_notice_variable (gimplify_omp_ctxp, OMP_CLAUSE_SIZE (clause),
+true);
   gimplify_omp_ctxp = ctx;
   return 0;
 }
--- gcc/testsuite/gfortran.dg/gomp/pr77973.f90.jj   2016-10-26 
13:59:47.817076712 +0200
+++ gcc/testsuite/gfortran.dg/gomp/pr77973.f90  2016-10-26 13:59:28.0 
+0200
@@ -0,0 +1,12 @@
+! PR fortran/77973
+! { dg-do compile }
+
+subroutine s(x)
+  integer :: x(:)
+  integer :: i
+!$omp parallel
+!$omp target
+  x(1) = 1
+!$omp end target
+!$omp end parallel
+end

Jakub

Fix epiphany WRT fallthru

[Jeff Law]

And the same code again, this time in the epiphany port...

Installing on the trunk.

Jeff
commit c4bc8d8761d31e34e26958bbc3c33f371690edf2
Author: law 
Date:   Wed Oct 26 16:23:27 2016 +

* config/epiphany/epiphany.c (epiphany_print_operand): Adjust
fallthru comment.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241582 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4f5c3c2..bf5080a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2016-10-26  Jeff Law  
+
+   * config/epiphany/epiphany.c (epiphany_print_operand): Adjust
+   fallthru comment.
+
 2016-10-26  Jakub Jelinek  
Martin Liska  
 
diff --git a/gcc/config/epiphany/epiphany.c b/gcc/config/epiphany/epiphany.c
index a7854e7..e1f7a47 100644
--- a/gcc/config/epiphany/epiphany.c
+++ b/gcc/config/epiphany/epiphany.c
@@ -1354,7 +1354,8 @@ epiphany_print_operand (FILE *file, rtx x, int code)
  fprintf (file, "%s0x%08lx", IMMEDIATE_PREFIX, l);
  break;
}
-  /* Fall through.  Let output_addr_const deal with it.  */
+  /* FALLTHRU */
+  /* Let output_addr_const deal with it.  */
 case CONST_INT:
   fprintf(file,"%s",IMMEDIATE_PREFIX);
   if (code == 'C' || code == 'X')

Fix fr30 WRT fallthru

[Jeff Law]

Exact same code as in another port.  Just adjusting the comment so we 
don't warn on a desired fallthru.  Installing on the trunk.


Jeff
commit f1203ee28fdad66269ad0d0b761629f50dc3449b
Author: law 
Date:   Wed Oct 26 16:19:55 2016 +

* config/fr30/fr30.c (fr30_print_operand): Adjust fallthru comment.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241579 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 12f9c02..45ae4ea 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -35,6 +35,8 @@
 
 2016-10-26  Jeff Law  
 
+   * config/fr30/fr30.c (fr30_print_operand): Adjust fallthru comment.
+
* config/frv/frv.c (comparison_string): Do not fall through after
an error.
 
diff --git a/gcc/config/fr30/fr30.c b/gcc/config/fr30/fr30.c
index 187302b..d8e95cb 100644
--- a/gcc/config/fr30/fr30.c
+++ b/gcc/config/fr30/fr30.c
@@ -688,7 +688,8 @@ fr30_print_operand (FILE *file, rtx x, int code)
  break;
}
 
-  /* Fall through.  Let output_addr_const deal with it.  */
+  /* FALLTHRU */
+  /* Let output_addr_const deal with it.  */
 default:
   output_addr_const (file, x);
   break;

Fix frv port WRT fallthru

[Jeff Law]

We will return garbage from comparison_string in the event of an error 
in an ASM due to unintentional fallthru.  My first through was to have 
output_operand_lossage declared as non-returning, but returning in the 
case of a user ASM is what it's designed to do AFAICT.


So we just avoid the fallthru and return an empty string after issuing 
the error.


Installing on the trunk.

Jeff
commit ff166102929f47c8bffb5aa8699066d9fafa8bb2
Author: law 
Date:   Wed Oct 26 16:15:38 2016 +

* config/frv/frv.c (comparison_string): Do not fall through after
an error.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241576 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index afa4562..53d751d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 2016-10-26  Jeff Law  
 
+   * config/frv/frv.c (comparison_string): Do not fall through after
+   an error.
+
* config/iq2000/iq2000.c (iq2000_function_arg): Adjust fallthru
comment.
(expand_one_builtin): Add missing break.
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index 352bcff..50899a7 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -2688,7 +2688,7 @@ comparison_string (enum rtx_code code, rtx op0)
   bool is_nz_p = GET_MODE (op0) == CC_NZmode;
   switch (code)
 {
-default:  output_operand_lossage ("bad condition code");
+default:  output_operand_lossage ("bad condition code"); return "";
 case EQ:  return "eq";
 case NE:  return "ne";
 case LT:  return is_nz_p ? "n" : "lt";

FIx iq2000 WRT fallthru

[Jeff Law]

So the comment change in iq2000_function_arg is trivial.

expand_one_builtin is pretty obvious once you look at the code.  We're 
currently falling through from the zero-operand case to the one operand 
case.  That results in reading from op[0], which is almost certainly 
wrong.  So rather than falling through a break is appropriate.


Installing on the trunk.

Jeff
commit a9d7639464a003c55952014c44914182a6a8754f
Author: law 
Date:   Wed Oct 26 16:10:40 2016 +

* config/iq2000/iq2000.c (iq2000_function_arg): Adjust fallthru
comment.
(expand_one_builtin): Add missing break.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241573 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4aec3eb..afa4562 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
 2016-10-26  Jeff Law  
 
+   * config/iq2000/iq2000.c (iq2000_function_arg): Adjust fallthru
+   comment.
+   (expand_one_builtin): Add missing break.
+
* config/m32c/m32c.c (encode_pattern_1): Add fallthru comment.
(m32c_legitimate_address_p): Likewise.
 
diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c
index 7be7ee5..2c936da 100644
--- a/gcc/config/iq2000/iq2000.c
+++ b/gcc/config/iq2000/iq2000.c
@@ -1244,7 +1244,7 @@ iq2000_function_arg (cumulative_args_t cum_v, 
machine_mode mode,
   gcc_assert (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
  || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT);
 
-  /* Drops through.  */
+  /* FALLTHRU */
 case BLKmode:
   if (type != NULL_TREE && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
cum->arg_words += (cum->arg_words & 1);
@@ -2620,6 +2620,7 @@ expand_one_builtin (enum insn_code icode, rtx target, 
tree exp,
 {
 case 0:
pat = GEN_FCN (icode) (target);
+   break;
 case 1:
   if (target)
pat = GEN_FCN (icode) (target, op[0]);

Fix m32c WRT fallthrus

[Jeff Law]

In encode_pattern_1, we stuff the 'm' into the pattern for the memory 
operand, then want to recurse on the address.  So A fallthru seems 
reasonable.


In m32c_legitimate_address_p we have a special case for certain 
registers, but which does not apply to A0.  So we've got


  case ...
  case ...
special handling
  case A0_REGNO:
common handling

So fallthru is what we wanted here too.

Installing on the trunk.

Jeff
commit 90189036e0ed5752b5bb448962bda507b97c18c5
Author: law 
Date:   Wed Oct 26 16:08:30 2016 +

* config/m32c/m32c.c (encode_pattern_1): Add fallthru comment.
(m32c_legitimate_address_p): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241572 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1e03936..4aec3eb 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 2016-10-26  Jeff Law  
 
+   * config/m32c/m32c.c (encode_pattern_1): Add fallthru comment.
+   (m32c_legitimate_address_p): Likewise.
+
* config/m32r/m32r.c (m32r_print_operand): Adjust fallthru comment.
 
* config/mcore/mcore.c (mcore_gen_compare): Adjust fallthru comments.
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index 7d64c49..ccd9675 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -176,6 +176,7 @@ encode_pattern_1 (rtx x)
   break;
 case MEM:
   *patternp++ = 'm';
+  /* FALLTHRU */
 case CONST:
   encode_pattern_1 (XEXP (x, 0));
   break;
@@ -1696,6 +1697,7 @@ m32c_legitimate_address_p (machine_mode mode, rtx x, bool 
strict)
case SP_REGNO:
  if (TARGET_A16 && GET_MODE (x) == SImode)
return 0;
+ /* FALLTHRU */
case A0_REGNO:
  return 1;
 

[PATCH] DWARF5 - Emit DW_AT_rank and DW_TAG_generic_subrange for assumed-rank arrays

[Jakub Jelinek]

Hi!

The following patch starts emitting another new DWARF5 feature - DW_AT_rank
and DW_TAG_generic_subrange for Fortran assumed-rank arrays.
Unlike DW_TAG_subrange_type, the expressions in DW_TAG_generic_subrange
attributes have a magic 0 to rank-1 values pushed onto the DWARF stack
first; rather than allocating yet another DEBUG_EXPR_DECL for that,
I've used a PLACEHOLDER_EXPR with integral type.

Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?

BTW, DWARF5 also has DW_TAG_coarray_type support, guess the
gfc_get_array_descr_info lang hook interface should be extended for that
(perhaps just as little as including ncodimensions next to dimensions
and filling the rest of the coranges, but I'm afraid I don't know enough
about the coarray stuff to be able to write the Fortran side of it.
So, Tobias or others, if you could come up with the trans-types.c side
and some examples, I can help with the dwarf2out.c side.

2016-10-26  Jakub Jelinek  

* dwarf2out.h (struct dw_loc_descr_node): Adjust comment
for frame_offset_rel bit.
(struct array_descr_info): Add rank field.
* dwarf2out.c (struct loc_descr_context): Add placeholder_arg
and placeholder_seen fields.
(resolve_args_picking_1): Handle also frame_offset_rel DW_OP_dup
and DW_OP_over.  Optimize DW_OP_pick 0 into DW_OP_dup and
DW_OP_pick 1 into DW_OP_over.
(function_to_dwarf_procedure, type_byte_size, field_byte_offset,
gen_variant_part): Clear placeholder_{arg,seen}.
(loc_list_from_tree_1): Drop const from context argument.
Handle integral PLACEHOLDER_EXPR if context->placeholder_arg.
(loc_list_for_address_of_addr_expr_of_indirect_ref,
loc_list_from_tree, loc_descriptor_from_tree): Drop const from
context argument.
(add_scalar_info): Drop const from context argument.  Handle
context->placeholder_arg.
(add_bound_info): Drop const from context argument.
(gen_descr_array_type_die): Drop const from ctx variable.
Initialize placeholder_arg and placeholder_seen.  Add DW_AT_rank
attribute and use a single DW_TAG_generic_subrange instead of
7 DW_TAG_subrange_type for assumed rank arrays.
fortran/
* trans-types.c (gfc_get_array_descr_info): For -gdwarf-5 or
-gno-strict-dwarf, handle assumed rank arrays the way dwarf2out
expects.
ada/
* gcc-interface/misc.c (gnat_get_array_descr_info): Clear rank
field.

--- gcc/dwarf2out.h.jj  2016-10-22 18:57:43.0 +0200
+++ gcc/dwarf2out.h 2016-10-26 10:45:44.104651085 +0200
@@ -234,9 +234,9 @@ struct GTY((chain_next ("%h.dw_loc_next"
   /* Used to distinguish DW_OP_addr with a direct symbol relocation
  from DW_OP_addr with a dtp-relative symbol relocation.  */
   unsigned int dtprel : 1;
-  /* For DW_OP_pick operations: true iff. it targets a DWARF prodecure
- argument.  In this case, it needs to be relocated according to the current
- frame offset.  */
+  /* For DW_OP_pick, DW_OP_dup and DW_OP_over operations: true iff.
+ it targets a DWARF prodecure argument.  In this case, it needs to be
+ relocated according to the current frame offset.  */
   unsigned int frame_offset_rel : 1;
   int dw_loc_addr;
   dw_val_node dw_loc_oprnd1;
@@ -322,6 +322,7 @@ struct array_descr_info
   tree allocated;
   tree associated;
   tree stride;
+  tree rank;
   bool stride_in_bits;
   struct array_descr_dimen
 {
--- gcc/dwarf2out.c.jj  2016-10-25 22:13:57.0 +0200
+++ gcc/dwarf2out.c 2016-10-26 10:49:31.041820289 +0200
@@ -3293,9 +3293,9 @@ struct loc_descr_context;
 static void add_loc_descr_to_each (dw_loc_list_ref list, dw_loc_descr_ref ref);
 static void add_loc_list (dw_loc_list_ref *ret, dw_loc_list_ref list);
 static dw_loc_list_ref loc_list_from_tree (tree, int,
-  const struct loc_descr_context *);
+  struct loc_descr_context *);
 static dw_loc_descr_ref loc_descriptor_from_tree (tree, int,
- const struct 
loc_descr_context *);
+ struct loc_descr_context *);
 static HOST_WIDE_INT ceiling (HOST_WIDE_INT, unsigned int);
 static tree field_type (const_tree);
 static unsigned int simple_type_align_in_bits (const_tree);
@@ -3320,9 +3320,9 @@ static void add_name_attribute (dw_die_r
 static void add_gnat_descriptive_type_attribute (dw_die_ref, tree, dw_die_ref);
 static void add_comp_dir_attribute (dw_die_ref);
 static void add_scalar_info (dw_die_ref, enum dwarf_attribute, tree, int,
-const struct loc_descr_context *);
+struct loc_descr_context *);
 static void add_bound_info (dw_die_ref, enum dwarf_attribute, tree,
-   const struct loc_descr_context *);
+   struct 

FIx m32r port WRT fallthru

[Jeff Law]

And the same for m32r.  Again, it's got the fallthru marked, just not in 
a way we handle.  Installing on the trunk.


Jeff
commit 024d7f4c44ddf36bf76658937abf9da039228ce8
Author: law 
Date:   Wed Oct 26 16:02:58 2016 +

* config/m32r/m32r.c (m32r_print_operand): Adjust fallthru comment.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241571 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 560ec37..1e03936 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,7 @@
 2016-10-26  Jeff Law  
 
+   * config/m32r/m32r.c (m32r_print_operand): Adjust fallthru comment.
+
* config/mcore/mcore.c (mcore_gen_compare): Adjust fallthru comments.
 
* config/microblaze/microblaze.c (microblaze_function_arg): Adjust
diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c
index 17e48f5..41c6b60 100644
--- a/gcc/config/m32r/m32r.c
+++ b/gcc/config/m32r/m32r.c
@@ -2278,7 +2278,8 @@ m32r_print_operand (FILE * file, rtx x, int code)
  break;
}
 
-  /* Fall through.  Let output_addr_const deal with it.  */
+  /* FALLTHRU */
+  /* Let output_addr_const deal with it.  */
 
 default :
   output_addr_const (file, x);

Re: [PATCH, ARM 4/7, ping3] Adapt atomic compare and swap to ARMv8-M Baseline

[Kyrill Tkachov]

Hi Thomas,

On 24/10/16 09:05, Thomas Preudhomme wrote:

Ping?

Best regards,

Thomas

On 14/10/16 14:50, Thomas Preudhomme wrote:

Ping?

Best regards,

Thomas

On 03/10/16 17:45, Thomas Preudhomme wrote:

Ping?

Best regards,

Thomas

On 22/09/16 14:46, Thomas Preudhomme wrote:

Hi,

This patch is part of a patch series to add support for atomic operations on
ARMv8-M Baseline targets in GCC. This specific patch makes the necessary change
for compare and swap to work for ARMv8-M Baseline, doubleword integers excepted.
Namely, it adds Thumb-1 specific constraints to compare_and_swap. The
constraints are chosen so that once the pattern is splitted, the individual
instructions have their constraints respected. In particular, the constraints
for the cbranchsi4_* pattern must be duplicated here, which explains the use of
several alternatives.

Note: changes to enable other atomic operation are in the next patch of the
series.

ChangeLog entry is as follows:

*** gcc/ChangeLog ***

2016-07-05  Thomas Preud'homme 

* config/arm/sync.md (atomic_compare_and_swap_1): Add new ARMv8-M
Baseline only alternatives to (i) hold store atomic success value in a
return register rather than a scratch register, (ii) use a low register
for it and to (iii) ensure the cbranchsi insn generated by the split
respect the constraints of Thumb-1 cbranchsi4_insn and
cbranchsi4_scratch.
* config/arm/thumb1.md (cbranchsi4_insn): Add comment to indicate
constraints must match those in atomic_compare_and_swap.
(cbranchsi4_scratch): Likewise.


Testing: No code generation difference for ARMv7-A, ARMv7VE and ARMv8-A on all
atomic and synchronization testcases in the testsuite [2]. Patchset was also
bootstrapped with --enable-itm --enable-gomp on ARMv8-A in ARM and Thumb mode at
optimization level -O1 and above [1] without any regression in the testsuite and
no code generation difference in libitm and libgomp.

Code generation for ARMv8-M Baseline has been manually examined and compared
against ARMv8-A Thumb-2 for the following configuration without finding any
issue:

gcc.dg/atomic-op-2.c at -Os
gcc.dg/atomic-compare-exchange-2.c at -Os
gcc.dg/atomic-compare-exchange-3.c at -O3


Is this ok for trunk?



This is ok.
Thanks,
Kyrill


Best regards,

Thomas

[1] CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET were set to "-O1 -g", "-O3 -g" and
undefined ("-O2 -g")
[2] The exact list is:

gcc/testsuite/gcc.dg/atomic-compare-exchange-1.c
gcc/testsuite/gcc.dg/atomic-compare-exchange-2.c
gcc/testsuite/gcc.dg/atomic-compare-exchange-3.c
gcc/testsuite/gcc.dg/atomic-exchange-1.c
gcc/testsuite/gcc.dg/atomic-exchange-2.c
gcc/testsuite/gcc.dg/atomic-exchange-3.c
gcc/testsuite/gcc.dg/atomic-fence.c
gcc/testsuite/gcc.dg/atomic-flag.c
gcc/testsuite/gcc.dg/atomic-generic.c
gcc/testsuite/gcc.dg/atomic-generic-aux.c
gcc/testsuite/gcc.dg/atomic-invalid-2.c
gcc/testsuite/gcc.dg/atomic-load-1.c
gcc/testsuite/gcc.dg/atomic-load-2.c
gcc/testsuite/gcc.dg/atomic-load-3.c
gcc/testsuite/gcc.dg/atomic-lockfree.c
gcc/testsuite/gcc.dg/atomic-lockfree-aux.c
gcc/testsuite/gcc.dg/atomic-noinline.c
gcc/testsuite/gcc.dg/atomic-noinline-aux.c
gcc/testsuite/gcc.dg/atomic-op-1.c
gcc/testsuite/gcc.dg/atomic-op-2.c
gcc/testsuite/gcc.dg/atomic-op-3.c
gcc/testsuite/gcc.dg/atomic-op-6.c
gcc/testsuite/gcc.dg/atomic-store-1.c
gcc/testsuite/gcc.dg/atomic-store-2.c
gcc/testsuite/gcc.dg/atomic-store-3.c
gcc/testsuite/g++.dg/ext/atomic-1.C
gcc/testsuite/g++.dg/ext/atomic-2.C
gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c
gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c
gcc/testsuite/gcc.target/arm/atomic-op-acquire.c
gcc/testsuite/gcc.target/arm/atomic-op-char.c
gcc/testsuite/gcc.target/arm/atomic-op-consume.c
gcc/testsuite/gcc.target/arm/atomic-op-int.c
gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c
gcc/testsuite/gcc.target/arm/atomic-op-release.c
gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c
gcc/testsuite/gcc.target/arm/atomic-op-short.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_1.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_2.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_3.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_4.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_5.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_6.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_9.c
gcc/testsuite/gcc.target/arm/sync-1.c
gcc/testsuite/gcc.target/arm/synchronize.c
gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c
gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c
gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c
gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c
libstdc++-v3/testsuite/29_atomics/atomic/60658.cc
libstdc++-v3/testsuite/29_atomics/atomic/62259.cc
libstdc++-v3/testsuite/29_atomics/atomic/64658.cc
libstdc++-v3/testsuite/29_atomics/atomic/65147.cc

Fix mcore WRT fallthru

[Jeff Law]

And similarly for mcore.  Installing on the trunk.

Jeff
commit 71ab5ec1fc6e513112580bfe9c14a6cc1a2ad649
Author: law 
Date:   Wed Oct 26 15:59:34 2016 +

* config/mcore/mcore.c (mcore_gen_compare): Adjust fallthru comments.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241569 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f4a4be0..560ec37 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,7 @@
 2016-10-26  Jeff Law  
 
+   * config/mcore/mcore.c (mcore_gen_compare): Adjust fallthru comments.
+
* config/microblaze/microblaze.c (microblaze_function_arg): Adjust
fallthru comment.
 
diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c
index b8dc2d0..bdb8431 100644
--- a/gcc/config/mcore/mcore.c
+++ b/gcc/config/mcore/mcore.c
@@ -611,7 +611,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
 case EQ:   /* Use inverted condition, cmpne.  */
   code = NE;
   invert = true;
-  /* Drop through.  */
+  /* FALLTHRU */
   
 case NE:   /* Use normal condition, cmpne.  */
   if (GET_CODE (op1) == CONST_INT && ! CONST_OK_FOR_K (INTVAL (op1)))
@@ -621,7 +621,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
 case LE:   /* Use inverted condition, reversed cmplt.  */
   code = GT;
   invert = true;
-  /* Drop through.  */
+  /* FALLTHRU */
   
 case GT:   /* Use normal condition, reversed cmplt.  */
   if (GET_CODE (op1) == CONST_INT)
@@ -631,7 +631,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
 case GE:   /* Use inverted condition, cmplt.  */
   code = LT;
   invert = true;
-  /* Drop through.  */
+  /* FALLTHRU */
   
 case LT:   /* Use normal condition, cmplt.  */
   if (GET_CODE (op1) == CONST_INT && 
@@ -646,7 +646,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
   gcc_assert (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0);
   code = LEU;
   invert = true;
-  /* Drop through.  */
+  /* FALLTHRU */
   
 case LEU:  /* Use normal condition, reversed cmphs.  */
   if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
@@ -656,7 +656,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
 case LTU:  /* Use inverted condition, cmphs.  */
   code = GEU;
   invert = true;
-  /* Drop through.  */
+  /* FALLTHRU */
   
 case GEU:  /* Use normal condition, cmphs.  */
   if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)

Fix microblaze port WRT fallthru

[Jeff Law]

Just tweaking a fallthru comment.  Installing on the trunk.

Jeff
commit b357502f77b0f6fbc79e216479bee47eab1741a8
Author: law 
Date:   Wed Oct 26 15:52:41 2016 +

* config/microblaze/microblaze.c (microblaze_function_arg): Adjust
fallthru comment.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241568 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2076d69..f4a4be0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 2016-10-26  Jeff Law  
 
+   * config/microblaze/microblaze.c (microblaze_function_arg): Adjust
+   fallthru comment.
+
* config/msp430/msp430.c (msp430_legitimate_address_p): Adjust
fallthru comment.
 
diff --git a/gcc/config/microblaze/microblaze.c 
b/gcc/config/microblaze/microblaze.c
index 0fb273f..4b7a9ba 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -1553,7 +1553,7 @@ microblaze_function_arg (cumulative_args_t cum_v, 
machine_mode mode,
 default:
   gcc_assert (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
  || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT);
-  /* Drops through.  */
+  /* FALLTHRU */
 case BLKmode:
   regbase = GP_ARG_FIRST;
   break;

Fix msp430 port WRT fallthru

[Jeff Law]

This patch just tweaks a comment so that we no longer warn.  Installing 
on the trunk.


Jeff
commit 7aa35b20124373889e039a054076dd8d5288c9e2
Author: law 
Date:   Wed Oct 26 15:49:25 2016 +

* config/msp430/msp430.c (msp430_legitimate_address_p): Adjust
fallthru comment.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241567 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 448aaa7..2076d69 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 2016-10-26  Jeff Law  
 
+   * config/msp430/msp430.c (msp430_legitimate_address_p): Adjust
+   fallthru comment.
+
* config/nios2/nios2.c (nios2_rtx_costs): Avoid fallthru.
 
* config/rl78/rl78.c (rl78_calculate_death_notes): Add fallthru
diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c
index 50f6815..fb1978b 100644
--- a/gcc/config/msp430/msp430.c
+++ b/gcc/config/msp430/msp430.c
@@ -1545,7 +1545,7 @@ msp430_legitimate_address_p (machine_mode mode 
ATTRIBUTE_UNUSED,
 case REG:
   if (!reg_ok_for_addr (x, strict))
return false;
-  /* else... */
+  /* FALLTHRU */
 case CONST:
 case SYMBOL_REF:
 case CONST_INT:

Fix nios2 port WRT fallthru

[Jeff Law]

Inserts a suitable return rather than falling through.  Installing on 
the trunk.


Jeff
commit 7a2cc4bd5ebbc3133fa1c89320ca82bb4b3b4a71
Author: law 
Date:   Wed Oct 26 15:47:48 2016 +

* config/nios2/nios2.c (nios2_rtx_costs): Avoid fallthru.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241566 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5214b9d..448aaa7 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,7 @@
 2016-10-26  Jeff Law  
 
+   * config/nios2/nios2.c (nios2_rtx_costs): Avoid fallthru.
+
* config/rl78/rl78.c (rl78_calculate_death_notes): Add fallthru
comment.
(rl78_asm_ctor_dtor): Increase buffer size.
diff --git a/gcc/config/nios2/nios2.c b/gcc/config/nios2/nios2.c
index 8afb468..2a28fad 100644
--- a/gcc/config/nios2/nios2.c
+++ b/gcc/config/nios2/nios2.c
@@ -1493,6 +1493,7 @@ nios2_rtx_costs (rtx x, machine_mode mode 
ATTRIBUTE_UNUSED,
   *total = COSTS_N_INSNS (1);
   return true;
}
+  return false;
 
   default:
 return false;

Re: [PATCH, ARM 3/7, ping3] Refactor atomic compare_and_swap to make it fit for ARMv8-M Baseline

[Kyrill Tkachov]

Hi Thomas,

On 24/10/16 09:05, Thomas Preudhomme wrote:

Ping?

Best regards,

Thomas

On 14/10/16 14:50, Thomas Preudhomme wrote:

Ping?

Best regards,

Thomas

On 03/10/16 17:44, Thomas Preudhomme wrote:

Ping?

Best regards,

Thomas

On 22/09/16 14:44, Thomas Preudhomme wrote:

Hi,

This patch is part of a patch series to add support for atomic operations on
ARMv8-M Baseline targets in GCC. This specific patch refactors the expander and
splitter for atomics to make the logic work with ARMv8-M Baseline which has
limitation of Thumb-1 in terms of CC flag setting and different conditional
compare insn patterns.

ChangeLog entry is as follows:

*** gcc/ChangeLog ***

2016-09-02  Thomas Preud'homme 

* config/arm/arm.c (arm_expand_compare_and_swap): Add new bdst local
variable.  Add the new parameter to the insn generator.  Set that
parameter to be CC flag for 32-bit targets, bval otherwise.  Set the
return value from the negation of that parameter for Thumb-1, keeping
the logic unchanged otherwise except for using bdst as the destination
register of the compare_and_swap insn.
(arm_split_compare_and_swap): Add explanation about how is the value
returned to the function comment.  Rename scratch variable to
neg_bval.  Adapt initialization of variables holding operands to the
new operand numbers.  Use return register to hold result of store
exclusive for Thumb-1, scratch register otherwise. Construct the
appropriate cbranch for Thumb-1 targets, keeping the logic unchanged
for 32-bit targets.  Guard Z flag setting to restrict to 32bit targets.
Use gen_cbranchsi4 rather than hand-written conditional branch to loop
for strongly ordered compare_and_swap.
* config/arm/predicates.md (cc_register_operand): New predicate.
* config/arm/sync.md (atomic_compare_and_swap_1): Use a
match_operand with the new predicate to accept either the CC flag or a
destination register for the boolean return value, restricting it to
CC flag only via constraint.  Adapt operand numbers accordingly.


Testing: No code generation difference for ARMv7-A, ARMv7VE and ARMv8-A on all
atomic and synchronization testcases in the testsuite [2]. Patchset was also
bootstrapped with --enable-itm --enable-gomp on ARMv8-A in ARM and Thumb mode at
optimization level -O1 and above [1] without any regression in the testsuite and
no code generation difference in libitm and libgomp.

Code generation for ARMv8-M Baseline has been manually examined and compared
against ARMv8-A Thumb-2 for the following configuration without finding any
issue:

gcc.dg/atomic-op-2.c at -Os
gcc.dg/atomic-compare-exchange-2.c at -Os
gcc.dg/atomic-compare-exchange-3.c at -O3


Is this ok for trunk?



This is ok.
Thanks,
Kyrill



Best regards,

Thomas

[1] CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET were set to "-O1 -g", "-O3 -g" and
undefined ("-O2 -g")
[2] The exact list is:

gcc/testsuite/gcc.dg/atomic-compare-exchange-1.c
gcc/testsuite/gcc.dg/atomic-compare-exchange-2.c
gcc/testsuite/gcc.dg/atomic-compare-exchange-3.c
gcc/testsuite/gcc.dg/atomic-exchange-1.c
gcc/testsuite/gcc.dg/atomic-exchange-2.c
gcc/testsuite/gcc.dg/atomic-exchange-3.c
gcc/testsuite/gcc.dg/atomic-fence.c
gcc/testsuite/gcc.dg/atomic-flag.c
gcc/testsuite/gcc.dg/atomic-generic.c
gcc/testsuite/gcc.dg/atomic-generic-aux.c
gcc/testsuite/gcc.dg/atomic-invalid-2.c
gcc/testsuite/gcc.dg/atomic-load-1.c
gcc/testsuite/gcc.dg/atomic-load-2.c
gcc/testsuite/gcc.dg/atomic-load-3.c
gcc/testsuite/gcc.dg/atomic-lockfree.c
gcc/testsuite/gcc.dg/atomic-lockfree-aux.c
gcc/testsuite/gcc.dg/atomic-noinline.c
gcc/testsuite/gcc.dg/atomic-noinline-aux.c
gcc/testsuite/gcc.dg/atomic-op-1.c
gcc/testsuite/gcc.dg/atomic-op-2.c
gcc/testsuite/gcc.dg/atomic-op-3.c
gcc/testsuite/gcc.dg/atomic-op-6.c
gcc/testsuite/gcc.dg/atomic-store-1.c
gcc/testsuite/gcc.dg/atomic-store-2.c
gcc/testsuite/gcc.dg/atomic-store-3.c
gcc/testsuite/g++.dg/ext/atomic-1.C
gcc/testsuite/g++.dg/ext/atomic-2.C
gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c
gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c
gcc/testsuite/gcc.target/arm/atomic-op-acquire.c
gcc/testsuite/gcc.target/arm/atomic-op-char.c
gcc/testsuite/gcc.target/arm/atomic-op-consume.c
gcc/testsuite/gcc.target/arm/atomic-op-int.c
gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c
gcc/testsuite/gcc.target/arm/atomic-op-release.c
gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c
gcc/testsuite/gcc.target/arm/atomic-op-short.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_1.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_2.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_3.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_4.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_5.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_6.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c
gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c

Fix rl78 port WRT fallthru and sprintf warnings

[Jeff Law]

rl78_calclate_death_nodes, with one exception wants to treat JUMP_INSNs 
and CALL_INSNs the same.  Naturally it's implemented with a case 
statement like


  case JUMP_INSN:

  case CALL_INSN:


We're just missing the fallthru comment to silence the warning.

Like the stormy16, rl78 gets the buffer size wrong for ctor/dtor sections.

This patch fixes both issues.  Installed on the trunk.

Jeff
commit 7432dcb6fb3b23ce80d6631691d0a8150255cd93
Author: law 
Date:   Wed Oct 26 15:42:11 2016 +

* config/rl78/rl78.c (rl78_calculate_death_notes): Add fallthru
comment.
(rl78_asm_ctor_dtor): Increase buffer size.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241565 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d778e95..5214b9d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
 2016-10-26  Jeff Law  
 
+   * config/rl78/rl78.c (rl78_calculate_death_notes): Add fallthru
+   comment.
+   (rl78_asm_ctor_dtor): Increase buffer size.
+
* config/stormy16/stormy16.c (xstormy16_asm_output_destrutor): Increase
buffer size.
(xstormy16_asm_output_constructor): Likewise.
diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c
index 08ab899..5375e18 100644
--- a/gcc/config/rl78/rl78.c
+++ b/gcc/config/rl78/rl78.c
@@ -3863,6 +3863,7 @@ rtx_insn *insn;
 after this pass.  */
  break;
}
+ /* FALLTHRU */
case CALL_INSN:
  memset (dead, 0, sizeof (dead));
  break;
@@ -4657,7 +4658,7 @@ rl78_asm_ctor_dtor (rtx symbol, int priority, bool 
is_ctor)
 {
   /* This section of the function is based upon code copied
 from: gcc/varasm.c:get_cdtor_priority_section().  */
-  char buf[16];
+  char buf[18];
 
   sprintf (buf, "%s.%.5u", is_ctor ? ".ctors" : ".dtors",
   MAX_INIT_PRIORITY - priority);

Re: [RFA] Patch to allow SPU port to build with current trunk

[Jeff Law]

On 10/26/2016 01:34 AM, Ulrich Weigand wrote:

Jeff Law wrote:


First, there's a missing fallthru comment in spu_sched_reorder for
TYPE_LOAD/TYPE_STORE cases.  If I'm reading the SPU docs properly a
load/store insn is handled by pipe_1 and we're also trying to model some
aspects of the load-store unit.  So we should be setting pipe_ls and pipe_1:

  case TYPE_LOAD:
   case TYPE_STORE:
 pipe_ls = i;
   case TYPE_LNOP:
   case TYPE_SHUF:
   case TYPE_BR:
   case TYPE_MULTI1:
   case TYPE_HBR:
 pipe_1 = i;
 break;

This looks like intentional fallthru and should just have an appropriate
comment to silence the warning.


Agreed.


spu_legitimate_address looks far more interesting and I think it's buggy
as written:


 case SUBREG:
   x = XEXP (x, 0);
   if (REG_P (x))
 return 0;

 case REG:
   return INT_REG_OK_FOR_BASE_P (x, reg_ok_strict);

I think the test is inverted.  We want to consider (subreg (reg)) a
valid memory address and reject all other (subreg (...)) expressions.
But this code does the opposite.


Oops, it looks like this has been broken since this commit:
https://gcc.gnu.org/ml/gcc-patches/2009-05/msg01505.html
It happens :-)And I'm encouraged to see these new warnings exposing 
real problems.


FWIW, I forgot there's a target independent patch necessary to build SPU 
with the current trunk.  I'll get to pushing those forward soon enough.


jeff

Re: Add uniform_inside_sphere_distribution

[Ed Smith-Rowland]

On 10/26/2016 05:01 AM, Jonathan Wakely wrote:

On 25/10/16 08:20 -0400, Ed Smith-Rowland wrote:

+explicit
+param_type(_RealType __radius = _RealType(1))
+: _M_radius(__radius)
+{
+  _GLIBCXX_DEBUG_ASSERT(_M_radius > _RealType(0));


Nowadays we're able to do cheaper assertions when _GLIBCXX_ASSERTIONS
is defined, without the full debug mode (i.e. _GLIBCXX_DEBUG).

The macro above is only active for the full debug mode, but it looks
like a cheap check, should it use __glibcxx_assert instead?

It looks like we're not consistent about which one to use in
, which is probably my fault. Expensive checks like using
std::distance on forward iterators should use _GLIBCXX_DEBUG_ASSERT
but some of them look like they could use __glibcxx_assert.


This parameter check could definitely use __glibcxx_assert.

In fact, these two features look like 2/3 of the contracts proposal for 
C++ almost.  Or at least they could help.


Index: 
testsuite/ext/random/uniform_inside_sphere_distribution/cons/default.cc

===
--- 
testsuite/ext/random/uniform_inside_sphere_distribution/cons/default.cc 
(nonexistent)
+++ 
testsuite/ext/random/uniform_inside_sphere_distribution/cons/default.cc 
(working copy)

@@ -0,0 +1,43 @@
+// { dg-options "-std=gnu++11" }


In all the new tests please replace this dg-options directive with:

 { dg-do run { target cxx11 } }

so it can be tested for C++14 and C++17 too.

Done.

+// { dg-require-cstdint "" }
+//
+// Copyright (C) 2014 Free Software Foundation, Inc.


And update the dates to 2014-2016. 

Done.

Committed as 241562 with the attached .


Index: include/ext/random
===
--- include/ext/random  (revision 241499)
+++ include/ext/random  (working copy)
@@ -3493,6 +3493,218 @@
   _RealType>& __d2)
 { return !(__d1 == __d2); }
 
+
+  /**
+   * @brief A distribution for random coordinates inside a unit sphere.
+   */
+  template
+class uniform_inside_sphere_distribution
+{
+  static_assert(std::is_floating_point<_RealType>::value,
+   "template argument not a floating point type");
+  static_assert(_Dimen != 0, "dimension is zero");
+
+public:
+  /** The type of the range of the distribution. */
+  using result_type = std::array<_RealType, _Dimen>;
+
+  /** Parameter type. */
+  struct param_type
+  {
+   using distribution_type
+ = uniform_inside_sphere_distribution<_Dimen, _RealType>;
+   friend class uniform_inside_sphere_distribution<_Dimen, _RealType>;
+
+   explicit
+   param_type(_RealType __radius = _RealType(1))
+   : _M_radius(__radius)
+   {
+ __glibcxx_assert(_M_radius > _RealType(0));
+   }
+
+   _RealType
+   radius() const
+   { return _M_radius; }
+
+   friend bool
+   operator==(const param_type& __p1, const param_type& __p2)
+   { return __p1._M_radius == __p2._M_radius; }
+
+  private:
+   _RealType _M_radius;
+  };
+
+  /**
+   * @brief Constructors.
+   */
+  explicit
+  uniform_inside_sphere_distribution(_RealType __radius = _RealType(1))
+  : _M_param(__radius), _M_uosd()
+  { }
+
+  explicit
+  uniform_inside_sphere_distribution(const param_type& __p)
+  : _M_param(__p), _M_uosd()
+  { }
+
+  /**
+   * @brief Resets the distribution state.
+   */
+  void
+  reset()
+  { _M_uosd.reset(); }
+
+  /**
+   * @brief Returns the @f$radius@f$ of the distribution.
+   */
+  _RealType
+  radius() const
+  { return _M_param.radius(); }
+
+  /**
+   * @brief Returns the parameter set of the distribution.
+   */
+  param_type
+  param() const
+  { return _M_param; }
+
+  /**
+   * @brief Sets the parameter set of the distribution.
+   * @param __param The new parameter set of the distribution.
+   */
+  void
+  param(const param_type& __param)
+  { _M_param = __param; }
+
+  /**
+   * @brief Returns the greatest lower bound value of the distribution.
+   * This function makes no sense for this distribution.
+   */
+  result_type
+  min() const
+  {
+   result_type __res;
+   __res.fill(0);
+   return __res;
+  }
+
+  /**
+   * @brief Returns the least upper bound value of the distribution.
+   * This function makes no sense for this distribution.
+   */
+  result_type
+  max() const
+  {
+   result_type __res;
+   __res.fill(0);
+   return __res;
+  }
+
+  /**
+   * @brief Generating functions.
+   */
+  template
+   result_type
+   operator()(_UniformRandomNumberGenerator& __urng)
+   { return this->operator()(__urng, _M_param); }
+
+  template
+   result_type
+   operator()(_UniformRandomNumberGenerator& __urng,
+  

Fix stormy16 WRT sprintf warnings

[Jeff Law]

[ There's at least one more port that has the exact same problem. ]

stormy16's ctor/dtor output routines have this:

  char buf[16];

 sprintf (buf, ".ctors.%.5u",
   /* Invert the numbering so the linker puts us in the proper
  order; constructors are run from right to left, and the
  linker sorts in increasing order.  */
   MAX_INIT_PRIORITY - priority);

Which can overflow if depending on MAX_INIT_PRIORITY - priority.  The 
given formatting string does _not_ limit the total number of characters 
printed!  If that was the intent, the formatting string is wrong.


Anyway, the fix is trivial, increase the buffer.  Installed on the trunk.

Jeff

commit 41beb61397a504733a64fc6ad317d657f6b556c5
Author: law 
Date:   Wed Oct 26 15:36:48 2016 +

* config/stormy16/stormy16.c (xstormy16_asm_output_destrutor): Increase
buffer size.
(xstormy16_asm_output_constructor): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241564 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7d869b1..d778e95 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
 2016-10-26  Jeff Law  
 
+   * config/stormy16/stormy16.c (xstormy16_asm_output_destrutor): Increase
+   buffer size.
+   (xstormy16_asm_output_constructor): Likewise.
+
* config/pa/pa.c (pa_asm_output_mi_thunk): Increase buffer
size.
 
diff --git a/gcc/config/stormy16/stormy16.c b/gcc/config/stormy16/stormy16.c
index 531a7e9..f74b4d9 100644
--- a/gcc/config/stormy16/stormy16.c
+++ b/gcc/config/stormy16/stormy16.c
@@ -1618,7 +1618,7 @@ static void
 xstormy16_asm_out_destructor (rtx symbol, int priority)
 {
   const char *section = ".dtors";
-  char buf[16];
+  char buf[18];
 
   /* ??? This only works reliably with the GNU linker.  */
   if (priority != DEFAULT_INIT_PRIORITY)
@@ -1640,7 +1640,7 @@ static void
 xstormy16_asm_out_constructor (rtx symbol, int priority)
 {
   const char *section = ".ctors";
-  char buf[16];
+  char buf[18];
 
   /* ??? This only works reliably with the GNU linker.  */
   if (priority != DEFAULT_INIT_PRIORITY)

Re: [PATCH] Add recursive_directory_iterator::pop(error_code&)

[Jonathan Wakely]

On 26/10/16 16:19 +0100, Jonathan Wakely wrote:

Another Filesystem TS change, implementing LWG 2706.

* include/experimental/bits/fs_dir.h (recursive_directory_iterator):
Overload pop (LWG 2706).
* src/filesystem/dir.cc (recursive_directory_iterator::pop): Define
new overload.
* testsuite/experimental/filesystem/iterators/pop.cc: New test.



This new test isn't reliable, it depends on directory order. This
simplifies it so it behaves reliably.

Committed to trunk.


commit a16b18039731f450dfb4a8c4fff8db8b8da41817
Author: Jonathan Wakely 
Date:   Wed Oct 26 16:31:19 2016 +0100

Fix test for recursive_directory_iterator::pop

	* testsuite/experimental/filesystem/iterators/pop.cc: Remove
	unreliable dependency on directory order.

diff --git a/libstdc++-v3/testsuite/experimental/filesystem/iterators/pop.cc b/libstdc++-v3/testsuite/experimental/filesystem/iterators/pop.cc
index fa1ae62..d247ab4 100644
--- a/libstdc++-v3/testsuite/experimental/filesystem/iterators/pop.cc
+++ b/libstdc++-v3/testsuite/experimental/filesystem/iterators/pop.cc
@@ -78,13 +78,11 @@ test03()
   create_directories(p / "d1/d2/d3");
   create_directories(p / "d1/d2/e3");
   create_directories(p / "d1/e2/d3");
-  create_directories(p / "e1");
-  __gnu_test::scoped_file f(p / "d1/d2/d3/f");
-  for (int i = 0; i < 4; ++i)
+  for (int i = 0; i < 3; ++i)
   {
 fs::recursive_directory_iterator dir(p);
 std::advance(dir, i);
-int expected_depth = std::min(i, 3); // fourth entry is a file, not dir
+int expected_depth = i;
 VERIFY( dir.depth() == expected_depth );
 __builtin_printf("%d %d %s\n", i, dir.depth(), dir->path().c_str());
 dir.pop(ec);
@@ -102,7 +100,6 @@ test03()
 if (dir != end(dir))
   VERIFY( dir.depth() == (i -1) );
   }
-  f.path.clear();
   remove_all(p, ec);
 }
 

Fix PA buglet with sprintf formatting

[Jeff Law]

If we have enough thunks we could potentially overwrite the output 
buffer in pa_asm_output_mi_thunk:


  ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);

In reality we're unlikely to get enough thunks to cause a problem, but 
fixing this is easy by just increasing the size of the buffer.


Installed on the trunk.

Jeff
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c9b72bc..7d869b1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 2016-10-26  Jeff Law  
 
+   * config/pa/pa.c (pa_asm_output_mi_thunk): Increase buffer
+   size.
+
* config/h8300/h8300.c (h8300_print_operand): Adjust FALLTHRU
comment to silence warning.
 
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index e04abd4..c8ce083 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -8345,7 +8345,7 @@ pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, 
HOST_WIDE_INT delta,
   static unsigned int current_thunk_number;
   int val_14 = VAL_14_BITS_P (delta);
   unsigned int old_last_address = last_address, nbytes = 0;
-  char label[16];
+  char label[17];
   rtx xoperands[4];
 
   xoperands[0] = XEXP (DECL_RTL (function), 0);

Re: [PATCH GCC][1/4]Simplify (convert1 (minmax ((convert2 (x) c)))) into minmax (x c)

[Bin.Cheng]

On Wed, Oct 26, 2016 at 4:05 PM, Marc Glisse  wrote:
> On Wed, 26 Oct 2016, Bin.Cheng wrote:
>
>> On Wed, Oct 26, 2016 at 3:10 PM, Bin.Cheng  wrote:
>>>
>>> On Wed, Oct 26, 2016 at 3:04 PM, Marc Glisse 
>>> wrote:

 On Wed, 26 Oct 2016, Bin.Cheng wrote:

> Thanks for reviewing, updated patch attached.  Is it OK?



 +/* (convert (minmax ((convert (x) c -> minmax (x c) if x is
 promoted
 +   and the outer convert demotes the expression back to x's type.  */
 +(for minmax (min max)
 + (simplify
 +  (convert (minmax@0 (convert @1) INTEGER_CST@2))
 +  (if (types_match (@1, type) && int_fits_type_p (@2, type)
 +   && TYPE_PRECISION (TREE_TYPE (@0)) > TYPE_PRECISION (TREE_TYPE
 (@1)))
 +   (minmax @1 (convert @2)

 Don't you have a problem if @1 is signed but not @0?
 (int)max((unsigned long)(-2),3ul)
 seems to satisfy your conditions, but is not the same as
 max(-2,3)
>>>
>>> Ah, yes.  I falsely removed sign check from the original patch.  Will
>>> update that.
>>>
>> Here it is.  Sorry for the mistake.
>
>
> I expect the issues are only with signed @1 and unsigned @0, the reverse
> should be safe. But conservatively requiring the same TYPE_SIGN works if you
> think the that covers enough cases.
It covers the motivation test case, but relaxed condition is of course
more useful.  I will address this in followup patch extending this
pattern for non-const @2.  Does this make sense?

Thanks,
bin

Trivial H8 fallthru comment fix

[Jeff Law]

This fixes problems building the H8 port with the current trunk.  Just a 
trivial fix to the format of a fallthru comment.  Installed on the trunk.


Jeff
commit 356e50be8376f57e4f872ebc5a67b5ed41c98ab7
Author: law 
Date:   Wed Oct 26 15:20:33 2016 +

* config/h8300/h8300.c (h8300_print_operand): Adjust FALLTHRU
comment to silence warning.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@241560 
138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3780ba0..c9b72bc 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 2016-10-26  Jeff Law  
 
+   * config/h8300/h8300.c (h8300_print_operand): Adjust FALLTHRU
+   comment to silence warning.
+
* config/spu/spu.c (spu_sched_reorder): Add missing fallthru comment.
(spu_legitimate_address_p): Fix logic error and add missing fallthru
comment.
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index 3d06014..7c30292 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -1741,10 +1741,12 @@ h8300_print_operand (FILE *file, rtx x, int code)
  break;
}
 
- /* Fall through.  We should not get here if we are
-processing bit operations on H8/300 or H8/300H
-because 'U' constraint does not allow bit
-operations on the tiny area on these machines.  */
+ /* FALLTHRU */
+
+ /* We should not get here if we are processing bit
+operations on H8/300 or H8/300H because 'U'
+constraint does not allow bit operations on the
+tiny area on these machines.  */
 
case 'X':
case 'T':

[PATCH] Add recursive_directory_iterator::pop(error_code&)

[Jonathan Wakely]

Another Filesystem TS change, implementing LWG 2706.

* include/experimental/bits/fs_dir.h (recursive_directory_iterator):
Overload pop (LWG 2706).
* src/filesystem/dir.cc (recursive_directory_iterator::pop): Define
new overload.
* testsuite/experimental/filesystem/iterators/pop.cc: New test.

Tested x86_64-linux, committed to trunk.

commit aee4c6e7734b41b23d199c0c23ffc4e7fb1ccf8f
Author: Jonathan Wakely 
Date:   Thu Oct 20 19:48:41 2016 +0100

Add recursive_directory_iterator::pop(error_code&)

* include/experimental/bits/fs_dir.h (recursive_directory_iterator):
Overload pop (LWG 2706).
* src/filesystem/dir.cc (recursive_directory_iterator::pop): Define
new overload.
* testsuite/experimental/filesystem/iterators/pop.cc: New test.

diff --git a/libstdc++-v3/include/experimental/bits/fs_dir.h 
b/libstdc++-v3/include/experimental/bits/fs_dir.h
index 70a95eb..818e7ff 100644
--- a/libstdc++-v3/include/experimental/bits/fs_dir.h
+++ b/libstdc++-v3/include/experimental/bits/fs_dir.h
@@ -312,6 +312,7 @@ _GLIBCXX_BEGIN_NAMESPACE_CXX11
 }
 
 void pop();
+void pop(error_code&);
 
 void disable_recursion_pending() { _M_pending = false; }
 
diff --git a/libstdc++-v3/src/filesystem/dir.cc 
b/libstdc++-v3/src/filesystem/dir.cc
index bcd7dd0..9a63c4a 100644
--- a/libstdc++-v3/src/filesystem/dir.cc
+++ b/libstdc++-v3/src/filesystem/dir.cc
@@ -364,19 +364,33 @@ fs::recursive_directory_iterator::increment(error_code& 
ec) noexcept
 }
 
 void
-fs::recursive_directory_iterator::pop()
+fs::recursive_directory_iterator::pop(error_code& ec)
 {
   if (!_M_dirs)
-_GLIBCXX_THROW_OR_ABORT(filesystem_error(
- "cannot pop non-dereferenceable recursive directory iterator",
- std::make_error_code(errc::invalid_argument)));
+{
+  ec = std::make_error_code(errc::invalid_argument);
+  return;
+}
 
   do {
 _M_dirs->pop();
 if (_M_dirs->empty())
   {
_M_dirs.reset();
+   ec.clear();
return;
   }
-  } while (!_M_dirs->top().advance(nullptr, _M_options));
+  } while (!_M_dirs->top().advance(, _M_options));
+}
+
+void
+fs::recursive_directory_iterator::pop()
+{
+  error_code ec;
+  pop(ec);
+  if (ec)
+_GLIBCXX_THROW_OR_ABORT(filesystem_error(_M_dirs
+ ? "recursive directory iterator cannot pop"
+ : "non-dereferenceable recursive directory iterator cannot pop",
+ ec));
 }
diff --git a/libstdc++-v3/testsuite/experimental/filesystem/iterators/pop.cc 
b/libstdc++-v3/testsuite/experimental/filesystem/iterators/pop.cc
new file mode 100644
index 000..fa1ae62
--- /dev/null
+++ b/libstdc++-v3/testsuite/experimental/filesystem/iterators/pop.cc
@@ -0,0 +1,115 @@
+// Copyright (C) 2016 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 3, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING3.  If not see
+// .
+
+// { dg-options "-lstdc++fs" }
+// { dg-do run { target c++11 } }
+// { dg-require-filesystem-ts "" }
+
+#include 
+#include 
+#include 
+
+namespace fs = std::experimental::filesystem;
+
+void
+test01()
+{
+  std::error_code ec;
+  fs::recursive_directory_iterator dir;
+  dir.pop(ec);  // This is undefined, but our implementation
+  VERIFY( ec ); // checks and returns an error.
+  VERIFY( dir == end(dir) );
+
+  std::error_code ec2;
+  try
+  {
+dir.pop();
+  }
+  catch (const fs::filesystem_error& ex)
+  {
+ec2 = ex.code();
+  }
+  VERIFY( ec2 == ec );
+}
+
+void
+test02()
+{
+  std::error_code ec = make_error_code(std::errc::interrupted);
+  const auto p = __gnu_test::nonexistent_path();
+  create_directories(p / "d1/d2/d3");
+  for (int i = 0; i < 3; ++i)
+  {
+fs::recursive_directory_iterator dir(p);
+std::advance(dir, i);
+VERIFY( dir.depth() == i );
+dir.pop(ec);
+VERIFY( !ec );
+VERIFY( dir == end(dir) );
+
+dir = fs::recursive_directory_iterator(p);
+std::advance(dir, i);
+VERIFY( dir.depth() == i );
+dir.pop();
+VERIFY( dir == end(dir) );
+  }
+  remove_all(p, ec);
+}
+
+void
+test03()
+{
+  std::error_code ec = make_error_code(std::errc::interrupted);
+  const auto p = __gnu_test::nonexistent_path();
+  create_directories(p / "d1/d2/d3");
+  create_directories(p / "d1/d2/e3");
+  create_directories(p / "d1/e2/d3");
+  create_directories(p / 

Re: [PATCH GCC][1/4]Simplify (convert1 (minmax ((convert2 (x) c)))) into minmax (x c)

[Marc Glisse]

On Wed, 26 Oct 2016, Bin.Cheng wrote:


On Wed, Oct 26, 2016 at 3:10 PM, Bin.Cheng  wrote:

On Wed, Oct 26, 2016 at 3:04 PM, Marc Glisse  wrote:

On Wed, 26 Oct 2016, Bin.Cheng wrote:


Thanks for reviewing, updated patch attached.  Is it OK?



+/* (convert (minmax ((convert (x) c -> minmax (x c) if x is promoted
+   and the outer convert demotes the expression back to x's type.  */
+(for minmax (min max)
+ (simplify
+  (convert (minmax@0 (convert @1) INTEGER_CST@2))
+  (if (types_match (@1, type) && int_fits_type_p (@2, type)
+   && TYPE_PRECISION (TREE_TYPE (@0)) > TYPE_PRECISION (TREE_TYPE
(@1)))
+   (minmax @1 (convert @2)

Don't you have a problem if @1 is signed but not @0?
(int)max((unsigned long)(-2),3ul)
seems to satisfy your conditions, but is not the same as
max(-2,3)

Ah, yes.  I falsely removed sign check from the original patch.  Will
update that.


Here it is.  Sorry for the mistake.


I expect the issues are only with signed @1 and unsigned @0, the reverse 
should be safe. But conservatively requiring the same TYPE_SIGN works if 
you think the that covers enough cases.

(not a reviewer)

--
Marc Glisse

Re: [PATCH v2][AArch32][NEON] Implementing vmaxnmQ_ST and vminnmQ_ST intrinsincs.

[Tamar Christina]

Hi Christophe,

Here's the updated patch.

Cheers,
Tamar

From: Christophe Lyon 
Sent: Wednesday, October 19, 2016 11:23:56 AM
To: Tamar Christina
Cc: GCC Patches; Kyrylo Tkachov; nd
Subject: Re: [PATCH v2][AArch32][NEON] Implementing vmaxnmQ_ST and vminnmQ_ST 
intrinsincs.

On 19 October 2016 at 11:36, Tamar Christina  wrote:
> Hi All,
>
> This patch implements the vmaxnmQ_ST and vminnmQ_ST intrinsics. The
> current builtin registration code is deficient since it can't access
> standard pattern names, to which vmaxnmQ_ST and vminnmQ_ST map
> directly. Thus, to enable the vectoriser to have access to these
> intrinsics, we implement them using builtin functions, which we
> expand to the proper standard pattern using a define_expand.
>
> This patch also implements the __ARM_FEATURE_NUMERIC_MAXMIN macro,
> which is defined when __ARM_ARCH >= 8, and which enables the
> intrinsics.
>
> Regression tested on arm-none-eabi and no regressions.
>
> This patch is a rework of a previous patch:
> https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01971.html
>
> OK for trunk?
>
> Thanks,
> Tamar
>
> ---
>
> gcc/
>
> 2016-10-19  Bilyan Borisov  
> Tamar Christina 
>
> * config/arm/arm-c.c (arm_cpu_builtins): New macro definition.
> * config/arm/arm_neon.h (vmaxnm_f32): New intrinsinc.
> (vmaxnmq_f32): Likewise.
> (vminnm_f32): Likewise.
> (vminnmq_f32): Likewise.
> * config/arm/arm_neon_builtins.def (vmaxnm): New builtin.
> (vminnm): Likewise.
> * config/arm/neon.md (neon_, VCVTF): New
> expander.
>
> gcc/testsuite/
>
> 2016-10-19  Bilyan Borisov  
>
> * gcc.target/arm/simd/vmaxnm_f32_1.c: New.
> * gcc.target/arm/simd/vmaxnmq_f32_1.c: Likewise.
> * gcc.target/arm/simd/vminnm_f32_1.c: Likewise.
> * gcc.target/arm/simd/vminnmq_f32_1.c: Likewise.
>

I think you forgot to attach the new tests.

Christophe

diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index 72837001d1011e366233236a6ba3d1e5775583b1..dcb883d750506a02257e6e2e49880f2d1b9888fa 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -86,6 +86,9 @@ arm_cpu_builtins (struct cpp_reader* pfile)
 		  ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB)
 		   || TARGET_ARM_ARCH_ISA_THUMB >=2));
 
+  def_or_undef_macro (pfile, "__ARM_FEATURE_NUMERIC_MAXMIN",
+		  TARGET_ARM_ARCH >= 8 && TARGET_NEON && TARGET_FPU_ARMV8);
+
   def_or_undef_macro (pfile, "__ARM_FEATURE_SIMD32", TARGET_INT_SIMD);
 
   builtin_define_with_int_value ("__ARM_SIZEOF_MINIMAL_ENUM",
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 54bbc7dd83cf979b6fad7724ba1d4b327b311f5c..3898ff7302dc3f21e6b50a8a7b835033c1ae2021 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -2956,6 +2956,34 @@ vmaxq_f32 (float32x4_t __a, float32x4_t __b)
   return (float32x4_t)__builtin_neon_vmaxfv4sf (__a, __b);
 }
 
+#pragma GCC push_options
+#pragma GCC target ("fpu=neon-fp-armv8")
+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+vmaxnm_f32 (float32x2_t a, float32x2_t b)
+{
+  return (float32x2_t)__builtin_neon_vmaxnmv2sf (a, b);
+}
+
+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+vmaxnmq_f32 (float32x4_t a, float32x4_t b)
+{
+  return (float32x4_t)__builtin_neon_vmaxnmv4sf (a, b);
+}
+
+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+vminnm_f32 (float32x2_t a, float32x2_t b)
+{
+  return (float32x2_t)__builtin_neon_vminnmv2sf (a, b);
+}
+
+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+vminnmq_f32 (float32x4_t a, float32x4_t b)
+{
+  return (float32x4_t)__builtin_neon_vminnmv4sf (a, b);
+}
+#pragma GCC pop_options
+
+
 __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
 vmaxq_u8 (uint8x16_t __a, uint8x16_t __b)
 {
diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
index b29aa91a64ecb85dfb5eb9661ed67d4fa326062f..58b10207c1f5c0380cb01fdb4a92a3f0b4dec591 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -147,12 +147,12 @@ VAR6 (BINOP, vmaxs, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
 VAR6 (BINOP, vmaxu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
 VAR2 (BINOP, vmaxf, v2sf, v4sf)
 VAR2 (BINOP, vmaxf, v8hf, v4hf)
-VAR2 (BINOP, vmaxnm, v4hf, v8hf)
+VAR4 (BINOP, vmaxnm, v2sf, v4sf, v4hf, v8hf)
 VAR6 (BINOP, vmins, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
 VAR6 (BINOP, vminu, v8qi, v4hi, v2si, v16qi, v8hi, v4si)
 VAR2 (BINOP, vminf, v2sf, v4sf)
 VAR2 (BINOP, vminf, v4hf, v8hf)
-VAR2 (BINOP, vminnm, v8hf, v4hf)
+VAR4 (BINOP, vminnm, v2sf, v4sf, v8hf, v4hf)
 
 VAR3 (BINOP, vpmaxs, v8qi, v4hi, v2si)
 VAR3 (BINOP, vpmaxu, v8qi, v4hi, v2si)
diff --git 

Re: [PATCH, Fortran] DEC Compatibility: Logical operations on integers become bitwise ops with -fdec

[Andreas Schwab]

On Okt 26 2016, Fritz Reese  wrote:

> If so, I am not sure how to narrow down the issue without more debug
> info like a traceback or memory dump at the point of error.

Tell me more, I don't know anything about fortran.

Andreas.

-- 
Andreas Schwab, SUSE Labs, sch...@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."

Re: [PATCH, Fortran] DEC Compatibility: Logical operations on integers become bitwise ops with -fdec

[Fritz Reese]

On Wed, Oct 26, 2016 at 10:32 AM, Andreas Schwab  wrote:
> On Okt 26 2016, Fritz Reese  wrote:
>
>> I can't seem to reproduce this on x86-64. Did you fully apply the
>> patch?
>
> I don't have any patches.
>

Sorry for the confusion, I meant the originally attached
dec_bitwise_ops.diff. I am just wondering whether your compiler build
is up-to-date with trunk.

If so, I am not sure how to narrow down the issue without more debug
info like a traceback or memory dump at the point of error. It looks
to be working for me, and the code path executes as I expect for me
with a manual trace through the compilation.

---
Fritz Reese

[patch,testsuite] Support dg-require-effective-target label_offsets.

[Georg-Johann Lay]

There are targets that support taking values of labels but where any arithmetic 
on such values might produce garbage.


This patch introduces new dg-require-effective-target label_offsets which is a 
subset of label_values, and adjusts respective test cases to the more 
restricted predicate.


Run tests against avr-unknown-none ATmega2560 where it makes actually a 
difference between label_values and label_offsets.


Ok for trunk?

Johann

gcc/testsuite/
* lib/target-supports.exp (check_effective_target_label_offsets):
New proc.
* gcc.dg/20021029-1.c (dg-require-effective-target): Require
more restrict label_offsets instead of label_values.
* gcc.dg/pr16973.c: Dito.
* gcc.dg/torture/pr66123.c: Dito.
* gcc.dg/torture/pr66178.c: Dito.
* gcc.c-torture/compile/20021108-1.c: Dito.
* gcc.c-torture/compile/920501-7.c: Dito.
* gcc.c-torture/compile/labels-2.c: Dito.
* gcc.c-torture/compile/labels-3.c: Dito.
* gcc.c-torture/execute/pr70460.c: Dito.
Index: gcc.c-torture/compile/20021108-1.c
===
--- gcc.c-torture/compile/20021108-1.c	(revision 241546)
+++ gcc.c-torture/compile/20021108-1.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target label_values } */
+/* { dg-require-effective-target label_offsets } */
 
 int
 main()
Index: gcc.c-torture/compile/920501-7.c
===
--- gcc.c-torture/compile/920501-7.c	(revision 241546)
+++ gcc.c-torture/compile/920501-7.c	(working copy)
@@ -1,3 +1,3 @@
-/* { dg-require-effective-target label_values } */
+/* { dg-require-effective-target label_offsets } */
 
 x(){if(&&<0)x();b:goto*&e:;}
Index: gcc.c-torture/compile/labels-2.c
===
--- gcc.c-torture/compile/labels-2.c	(revision 241546)
+++ gcc.c-torture/compile/labels-2.c	(working copy)
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target label_values } */
+/* { dg-require-effective-target label_offsets } */
 
 struct bp { void *v, *b, *e; };
 f ()
Index: gcc.c-torture/compile/labels-3.c
===
--- gcc.c-torture/compile/labels-3.c	(revision 241546)
+++ gcc.c-torture/compile/labels-3.c	(working copy)
@@ -1,6 +1,6 @@
 /* Verify that we can narrow the storage associated with label diffs.  */
 /* { dg-require-effective-target indirect_jumps } */
-/* { dg-require-effective-target label_values } */
+/* { dg-require-effective-target label_offsets } */
 
 int foo (int a)
 {
Index: gcc.c-torture/execute/pr70460.c
===
--- gcc.c-torture/execute/pr70460.c	(revision 241546)
+++ gcc.c-torture/execute/pr70460.c	(working copy)
@@ -1,5 +1,5 @@
 /* { dg-require-effective-target indirect_jumps } */
-/* { dg-require-effective-target label_values } */
+/* { dg-require-effective-target label_offsets } */
 
 /* PR rtl-optimization/70460 */
 
Index: gcc.dg/20021029-1.c
===
--- gcc.dg/20021029-1.c	(revision 241546)
+++ gcc.dg/20021029-1.c	(working copy)
@@ -3,7 +3,7 @@
 /* { dg-do compile { target fpic } } */
 /* { dg-options "-O2 -fpic" } */
 /* { dg-final { scan-assembler-not ".data.rel.ro.local" } } */
-/* { dg-require-effective-target label_values } */
+/* { dg-require-effective-target label_offsets } */
 /* { dg-require-effective-target indirect_jumps } */
 
 int foo (int a)
Index: gcc.dg/pr16973.c
===
--- gcc.dg/pr16973.c	(revision 241546)
+++ gcc.dg/pr16973.c	(working copy)
@@ -3,7 +3,7 @@
to add back the label.   */
 
 /* { dg-options "" } */
-/* { dg-require-effective-target label_values } */
+/* { dg-require-effective-target label_offsets } */
 
 void
 f (void)
Index: gcc.dg/torture/pr66123.c
===
--- gcc.dg/torture/pr66123.c	(revision 241546)
+++ gcc.dg/torture/pr66123.c	(working copy)
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target label_values } */
+/* { dg-require-effective-target label_offsets } */
 
 int
 test (int foo)
Index: gcc.dg/torture/pr66178.c
===
--- gcc.dg/torture/pr66178.c	(revision 241546)
+++ gcc.dg/torture/pr66178.c	(working copy)
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target label_values } */
+/* { dg-require-effective-target label_offsets } */
 
 int test(void)
 {
Index: lib/target-supports.exp
===
--- lib/target-supports.exp	(revision 241546)
+++ lib/target-supports.exp	(working copy)
@@ -740,6 +740,31 @@ proc check_effective_target_label_values
 }]
 }
 
+# Return 1 if offsetting label values is supported, 0 otherwise.
+# A typical 

Re: [PATCH, Fortran] DEC Compatibility: Logical operations on integers become bitwise ops with -fdec

[Andreas Schwab]

On Okt 26 2016, Fritz Reese  wrote:

> I can't seem to reproduce this on x86-64. Did you fully apply the
> patch?

I don't have any patches.

Andreas.

-- 
Andreas Schwab, SUSE Labs, sch...@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."

Re: [PATCH GCC][1/4]Simplify (convert1 (minmax ((convert2 (x) c)))) into minmax (x c)

[Bin.Cheng]

On Wed, Oct 26, 2016 at 3:10 PM, Bin.Cheng  wrote:
> On Wed, Oct 26, 2016 at 3:04 PM, Marc Glisse  wrote:
>> On Wed, 26 Oct 2016, Bin.Cheng wrote:
>>
>>> Thanks for reviewing, updated patch attached.  Is it OK?
>>
>>
>> +/* (convert (minmax ((convert (x) c -> minmax (x c) if x is promoted
>> +   and the outer convert demotes the expression back to x's type.  */
>> +(for minmax (min max)
>> + (simplify
>> +  (convert (minmax@0 (convert @1) INTEGER_CST@2))
>> +  (if (types_match (@1, type) && int_fits_type_p (@2, type)
>> +   && TYPE_PRECISION (TREE_TYPE (@0)) > TYPE_PRECISION (TREE_TYPE
>> (@1)))
>> +   (minmax @1 (convert @2)
>>
>> Don't you have a problem if @1 is signed but not @0?
>> (int)max((unsigned long)(-2),3ul)
>> seems to satisfy your conditions, but is not the same as
>> max(-2,3)
> Ah, yes.  I falsely removed sign check from the original patch.  Will
> update that.
>
Here it is.  Sorry for the mistake.

Thanks,
bin
diff --git a/gcc/match.pd b/gcc/match.pd
index 767d23a..73bee34 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -1337,6 +1337,17 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
&& TYPE_MIN_VALUE (type)
&& operand_equal_p (@1, TYPE_MIN_VALUE (type), OEP_ONLY_CONST))
@0)))
+
+/* (convert (minmax ((convert (x) c -> minmax (x c) if x is promoted
+   and the outer convert demotes the expression back to x's type.  */
+(for minmax (min max)
+ (simplify
+  (convert (minmax@0 (convert @1) INTEGER_CST@2))
+  (if (types_match (@1, type) && int_fits_type_p (@2, type)
+   && TYPE_SIGN (TREE_TYPE (@0)) == TYPE_SIGN (type)
+   && TYPE_PRECISION (TREE_TYPE (@0)) > TYPE_PRECISION (type))
+   (minmax @1 (convert @2)
+
 (for minmax (FMIN FMAX)
  /* If either argument is NaN, return the other one.  Avoid the
 transformation if we get (and honor) a signalling NaN.  */
diff --git a/gcc/testsuite/gcc.dg/fold-convmaxconv-1.c 
b/gcc/testsuite/gcc.dg/fold-convmaxconv-1.c
new file mode 100644
index 000..38b
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/fold-convmaxconv-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O -fdump-tree-optimized" } */
+
+int foo (short a[], int x)
+{
+  unsigned int i;
+  for (i = 0; i < 1000; i++)
+{
+  x = a[i];
+  a[i] = (x <= 0 ? 0 : x);
+}
+  return x;
+}
+
+/* { dg-final { scan-tree-dump-not " = MAX_EXPR = 255 ? 255 : x);
+}
+  return x;
+}
+
+/* { dg-final { scan-tree-dump-not " = MIN_EXPR 

Re: [PATCHv2 4/7, GCC, ARM, V8M] ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers

[Kyrill Tkachov]

Hi Andre,

On 25/10/16 17:29, Andre Vieira (lists) wrote:

On 24/08/16 12:01, Andre Vieira (lists) wrote:

On 25/07/16 14:23, Andre Vieira (lists) wrote:

This patch extends support for the ARMv8-M Security Extensions
'cmse_nonsecure_entry' attribute to safeguard against leak of
information through unbanked registers.

When returning from a nonsecure entry function we clear all caller-saved
registers that are not used to pass return values, by writing either the
LR, in case of general purpose registers, or the value 0, in case of FP
registers. We use the LR to write to APSR and FPSCR too. We currently do
not support entry functions that pass arguments or return variables on
the stack and we diagnose this. This patch relies on the existing code
to make sure callee-saved registers used in cmse_nonsecure_entry
functions are saved and restored thus retaining their nonsecure mode
value, this should be happening already as it is required by AAPCS.

This patch also clears padding bits for cmse_nonsecure_entry functions
with struct and union return types. For unions a bit is only considered
a padding bit if it is an unused bit in every field of that union. The
function that calculates these is used in a later patch to do the same
for arguments of cmse_nonsecure_call's.

*** gcc/ChangeLog ***
2016-07-25  Andre Vieira
 Thomas Preud'homme  

 * config/arm/arm.c (output_return_instruction): Clear
 registers.
 (thumb2_expand_return): Likewise.
 (thumb1_expand_epilogue): Likewise.
 (thumb_exit): Likewise.
 (arm_expand_epilogue): Likewise.
 (cmse_nonsecure_entry_clear_before_return): New.
 (comp_not_to_clear_mask_str_un): New.
 (compute_not_to_clear_mask): New.
 * config/arm/thumb1.md (*epilogue_insns): Change length attribute.
 * config/arm/thumb2.md (*thumb2_return): Likewise.

*** gcc/testsuite/ChangeLog ***
2016-07-25  Andre Vieira
 Thomas Preud'homme  

 * gcc.target/arm/cmse/cmse.exp: Test different multilibs separate.
 * gcc.target/arm/cmse/struct-1.c: New.
 * gcc.target/arm/cmse/bitfield-1.c: New.
 * gcc.target/arm/cmse/bitfield-2.c: New.
 * gcc.target/arm/cmse/bitfield-3.c: New.
 * gcc.target/arm/cmse/baseline/cmse-2.c: Test that registers are
cleared.
 * gcc.target/arm/cmse/mainline/soft/cmse-5.c: New.
 * gcc.target/arm/cmse/mainline/hard/cmse-5.c: New.
 * gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: New.
 * gcc.target/arm/cmse/mainline/softfp/cmse-5.c: New.
 * gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: New.


Updated this patch to correctly clear only the cumulative
exception-status (0-4,7) and the condition code bits (28-31) of the
FPSCR. I also adapted the code to be handle the bigger floating point
register files.



This patch extends support for the ARMv8-M Security Extensions
'cmse_nonsecure_entry' attribute to safeguard against leak of
information through unbanked registers.

When returning from a nonsecure entry function we clear all caller-saved
registers that are not used to pass return values, by writing either the
LR, in case of general purpose registers, or the value 0, in case of FP
registers. We use the LR to write to APSR. For FPSCR we clear only the
cumulative exception-status (0-4, 7) and the condition code bits
(28-31). We currently do not support entry functions that pass arguments
or return variables on the stack and we diagnose this. This patch relies
on the existing code to make sure callee-saved registers used in
cmse_nonsecure_entry functions are saved and restored thus retaining
their nonsecure mode value, this should be happening already as it is
required by AAPCS.

This patch also clears padding bits for cmse_nonsecure_entry functions
with struct and union return types. For unions a bit is only considered
a padding bit if it is an unused bit in every field of that union. The
function that calculates these is used in a later patch to do the same
for arguments of cmse_nonsecure_call's.

*** gcc/ChangeLog ***
2016-07-xx  Andre Vieira
 Thomas Preud'homme  

 * config/arm/arm.c (output_return_instruction): Clear
 registers.
 (thumb2_expand_return): Likewise.
 (thumb1_expand_epilogue): Likewise.
 (thumb_exit): Likewise.
 (arm_expand_epilogue): Likewise.
 (cmse_nonsecure_entry_clear_before_return): New.
 (comp_not_to_clear_mask_str_un): New.
 (compute_not_to_clear_mask): New.
 * config/arm/thumb1.md (*epilogue_insns): Change length attribute.
 * config/arm/thumb2.md (*thumb2_return): Duplicate pattern for
 cmse_nonsecure_entry functions.

*** gcc/testsuite/ChangeLog ***

[PATCH, Fortran] DEC Compatibility: Default missing exponents to 0 with -fdec

[Fritz Reese]

All,

Attached is a patch to the GNU Fortran front-end and runtime library
(libgfortran) which accepts real numbers with missing exponents as if
'0' was given as the exponent when the compile flag -fdec is given,
for further compatibility with legacy compilers. By default, GNU
Fortran will reject real constants such as '9e' or '15.2e'. With the
patch and -fdec, such numbers are accepted and treated as '9e0' (9) or
'15.2e0' (15.2), both at compile-time through the front-end and at
runtime through libgfortran.

For compile-time this is trivial. For runtime, An IOPARM_DT flag bit
is added to the usual flags to track whether a program was compiled
with the "default exponent" behavior, which the library can detect at
runtime for programs individually. No space is required in the
st_parameter_dt structure, and the behavior should be
backwards-compatible (by design of the IOPARM structures/flags).

Bootstraps and regtests on x86_64-redhat-linux. OK for trunk?

---
Fritz Reese

From: Fritz Reese 
Date: Wed, 5 Oct 2016 18:27:56 -0400
Subject: [PATCH] Default missing exponents to 0 with -fdec.

gcc/fortran/
* gfortran.texi: Document.
* gfortran.h (gfc_dt): New field default_exp.
* primary.c (match_real_constant): Default exponent with -fdec.
* io.c (match_io): Set dt.default_exp with -fdec.
* ioparm.def (IOPARM_dt_default_exp): New.
* trans-io.c (build_dt): Set IOPARM_dt_default_exp with -fdec.

libgfortran/io/
* io.h (IOPARM_DT_DEFAULT_EXP): New flag bit.
* list_read.c (parse_real, read_real): Allow omission of exponent with
IOPARM_DT_DEFAULT_EXP.
* read.c (read_f): Ditto.

gcc/testsuite/gfortran.dg/
* dec_exp_1.f90, dec_exp_2.f90, dec_exp_3.f90: New testcases.
---
 gcc/fortran/gfortran.h  |1 +
 gcc/fortran/gfortran.texi   |   10 
 gcc/fortran/io.c|4 +++
 gcc/fortran/ioparm.def  |1 +
 gcc/fortran/primary.c   |   19 
 gcc/fortran/trans-io.c  |3 ++
 gcc/testsuite/gfortran.dg/dec_exp_1.f90 |   35 +++
 gcc/testsuite/gfortran.dg/dec_exp_2.f90 |   13 +++
 gcc/testsuite/gfortran.dg/dec_exp_3.f90 |   15 +
 libgfortran/io/io.h |1 +
 libgfortran/io/list_read.c  |   22 +-
 libgfortran/io/read.c   |8 ++-
 12 files changed, 124 insertions(+), 8 deletions(-)
 create mode 100644 gcc/testsuite/gfortran.dg/dec_exp_1.f90
 create mode 100644 gcc/testsuite/gfortran.dg/dec_exp_2.f90
 create mode 100644 gcc/testsuite/gfortran.dg/dec_exp_3.f90
diff --git a/gcc/fortran/gfortran.h b/gcc/fortran/gfortran.h
index ea4437c..a0dcf6d 100644
--- a/gcc/fortran/gfortran.h
+++ b/gcc/fortran/gfortran.h
@@ -2336,6 +2336,7 @@ typedef struct
   gfc_expr *io_unit, *format_expr, *rec, *advance, *iostat, *size, *iomsg,
   *id, *pos, *asynchronous, *blank, *decimal, *delim, *pad, *round,
   *sign, *extra_comma, *dt_io_kind, *udtio;
+  char default_exp;
 
   gfc_symbol *namelist;
   /* A format_label of `format_asterisk' indicates the "*" format */
diff --git a/gcc/fortran/gfortran.texi b/gcc/fortran/gfortran.texi
index e65c2de..85ab31b 100644
--- a/gcc/fortran/gfortran.texi
+++ b/gcc/fortran/gfortran.texi
@@ -1471,6 +1471,7 @@ compatibility extensions along with those enabled by 
@option{-std=legacy}.
 * .XOR. operator::
 * Bitwise logical operators::
 * Extended I/O specifiers::
+* Default exponents::
 @end menu
 
 @node Old-style kind specifications
@@ -2696,6 +2697,15 @@ supported on other systems.
 
 @end table
 
+@node Default exponents
+@subsection Default exponents
+@cindex exponent
+
+For compatibility, GNU Fortran supports a default exponent of zero in real
+constants with @option{-fdec}.  For example, @code{9e} would be
+interpreted as @code{9e0}, rather than an error.
+
+
 @node Extensions not implemented in GNU Fortran
 @section Extensions not implemented in GNU Fortran
 @cindex extensions, not implemented
diff --git a/gcc/fortran/io.c b/gcc/fortran/io.c
index dce0f7c..5f50969 100644
--- a/gcc/fortran/io.c
+++ b/gcc/fortran/io.c
@@ -4163,6 +4163,10 @@ get_io_list:
goto syntax;
 }
 
+  /* See if we want to use defaults for missing exponents in real transfers.  
*/
+  if (flag_dec)
+dt->default_exp = 1;
+
   /* A full IO statement has been matched.  Check the constraints.  spec_end is
  supplied for cases where no locus is supplied.  */
   m = check_io_constraints (k, dt, io_code, _end);
diff --git a/gcc/fortran/ioparm.def b/gcc/fortran/ioparm.def
index f1bf733..4669187 100644
--- a/gcc/fortran/ioparm.def
+++ b/gcc/fortran/ioparm.def
@@ -118,4 +118,5 @@ IOPARM (dt,  round, 1 << 23, char2)
 IOPARM (dt,  sign, 1 << 24, char1)
 #define IOPARM_dt_f2003  (1 << 25)
 #define 

Re: [PATCH] Introduce class rtx_writer

[Bernd Schmidt]

On 10/26/2016 04:10 PM, David Malcolm wrote:

The following patch moves various global state in print-rtl.c into
a new "rtx_writer" class, giving us a place to stash additional state
relating to dumping (and the possibility of putting extra
setup/cleanup in ctor/dtor).

I didn't bother renaming the variables (e.g. converting "indent" to
"m_indent"), to minimize churn, but I could do that also if you
prefer.


I do like avoiding churn, but at the same time - our guidelines suggest 
that we name members with m_. So the patch is OK if you do the conversion.



Bernd

Re: [PATCH GCC][1/4]Simplify (convert1 (minmax ((convert2 (x) c)))) into minmax (x c)

[Bin.Cheng]

On Wed, Oct 26, 2016 at 3:04 PM, Marc Glisse  wrote:
> On Wed, 26 Oct 2016, Bin.Cheng wrote:
>
>> Thanks for reviewing, updated patch attached.  Is it OK?
>
>
> +/* (convert (minmax ((convert (x) c -> minmax (x c) if x is promoted
> +   and the outer convert demotes the expression back to x's type.  */
> +(for minmax (min max)
> + (simplify
> +  (convert (minmax@0 (convert @1) INTEGER_CST@2))
> +  (if (types_match (@1, type) && int_fits_type_p (@2, type)
> +   && TYPE_PRECISION (TREE_TYPE (@0)) > TYPE_PRECISION (TREE_TYPE
> (@1)))
> +   (minmax @1 (convert @2)
>
> Don't you have a problem if @1 is signed but not @0?
> (int)max((unsigned long)(-2),3ul)
> seems to satisfy your conditions, but is not the same as
> max(-2,3)
Ah, yes.  I falsely removed sign check from the original patch.  Will
update that.

Thanks,
bin
>
> --
> Marc Glisse

Re: [PATCH] PR78056: Fix build failure on Power7

[Segher Boessenkool]

On Wed, Oct 26, 2016 at 08:57:11AM -0500, Bill Schmidt wrote:
> On Oct 26, 2016, at 8:29 AM, Segher Boessenkool  
> wrote:
> > 
> > So, you do not want to create the builtins that we expand to machine insns
> > that are not supported with the -mcpu= (or other flags) in use.  What does
> > the ABI have to say about this?
> 
> The ABI is silent on this point.  The appendix of builtin functions for 
> vector processing
> tags these as POWER ISA 3.0, but that's the extent of it.  I don't see a 
> problem with
> disabling built-ins that generate code that won't assemble provided we 
> diagnose the
> error properly (the follow-up work that Kelvin mentioned).

Okay, so let's do the sane thing then :-)

The patch is okay for trunk (with the changelog fixed).  Thanks Kelvin!


Segher

Re: [PATCH GCC][1/4]Simplify (convert1 (minmax ((convert2 (x) c)))) into minmax (x c)

[Marc Glisse]

On Wed, 26 Oct 2016, Bin.Cheng wrote:


Thanks for reviewing, updated patch attached.  Is it OK?


+/* (convert (minmax ((convert (x) c -> minmax (x c) if x is promoted
+   and the outer convert demotes the expression back to x's type.  */
+(for minmax (min max)
+ (simplify
+  (convert (minmax@0 (convert @1) INTEGER_CST@2))
+  (if (types_match (@1, type) && int_fits_type_p (@2, type)
+   && TYPE_PRECISION (TREE_TYPE (@0)) > TYPE_PRECISION (TREE_TYPE (@1)))
+   (minmax @1 (convert @2)

Don't you have a problem if @1 is signed but not @0?
(int)max((unsigned long)(-2),3ul)
seems to satisfy your conditions, but is not the same as
max(-2,3)

--
Marc Glisse

Re: [PATCH GCC][3/4]Add support for constant operand in pattern (convert (op:s (convert@2 @0) (convert?@3 @1)))

[Bin.Cheng]

On Tue, Oct 25, 2016 at 1:00 PM, Richard Biener
 wrote:
> On Tue, Oct 25, 2016 at 1:21 PM, Bin Cheng  wrote:
>> Hi,
>> This is an update patch for 
>> https://gcc.gnu.org/ml/gcc-patches/2016-10/msg00738.html .  In this version, 
>> existing pattern (convert (op:s (convert@2 @0) (convert?@3 @1))) is 
>> extended.  It allows narrowing of arithmetic operation which has constant 
>> integer as its second operand.  It also simplifies next patch handling 
>> cond_expr.
>> Bootstrap and test on x86_64 and AArch64 for whole patch set.  Is it OK?
>
> +&& types_match (@0, type)
> +&& (types_match (@0, @1)
> +/* Or the second operand must be constant integer.  */
> +|| (@3 == @1
> +&& types_match (@1, @2)
> +&& TREE_CODE (@1) == INTEGER_CST)))
>
> So this fails to match the pattern if we get into it via valueization
> and get, say,
> (short)((int)a + (int)7).  I believe for plus and minus we're always safe so
> I suggest to simply do
>
>   && (types_match (@0, @1)
> || TREE_CODE (@1) == INTEGER_CST)
>
>(if (TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0)))
> -   (convert (op @0 @1))
> +   (convert (op @0 (convert:type @1)))
>
> :type shouldn't be necessary -- it also shows the outer (convert ..)
> is not required,
> please remove it while you're here.
>
> (with { tree utype = unsigned_type_for (TREE_TYPE (@0)); }
> -(convert (op (convert:utype @0) (convert:utype @1
> +(convert (op (convert:utype @0)
> + (convert:utype (convert:type @1)
>
> Why do you need the intermediate conversion?

Thanks for reviewing, updated patch attached.  Is it OK?

Thanks,
bin
diff --git a/gcc/match.pd b/gcc/match.pd
index 01d088d..dbe11bc 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -3328,7 +3328,7 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
operation and convert the result to the desired type.  */
 (for op (plus minus)
   (simplify
-(convert (op:s (convert@2 @0) (convert@3 @1)))
+(convert (op:s (convert@2 @0) (convert?@3 @1)))
 (if (INTEGRAL_TYPE_P (type)
 /* We check for type compatibility between @0 and @1 below,
so there's no need to check that @1/@3 are integral types.  */
@@ -3344,12 +3344,16 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
 && TYPE_PRECISION (type) == GET_MODE_PRECISION (TYPE_MODE (type))
 /* The inner conversion must be a widening conversion.  */
 && TYPE_PRECISION (TREE_TYPE (@2)) > TYPE_PRECISION (TREE_TYPE (@0))
-&& types_match (@0, @1)
-&& types_match (@0, type))
+&& types_match (@0, type)
+&& (types_match (@0, @1)
+/* Or the second operand is const integer or converted const
+   integer from valueize.  */
+|| TREE_CODE (@1) == INTEGER_CST))
   (if (TYPE_OVERFLOW_WRAPS (TREE_TYPE (@0)))
-   (convert (op @0 @1))
+   (op @0 (convert @1))
(with { tree utype = unsigned_type_for (TREE_TYPE (@0)); }
-(convert (op (convert:utype @0) (convert:utype @1
+(convert (op (convert:utype @0)
+ (convert:utype @1
 
 /* This is another case of narrowing, specifically when there's an outer
BIT_AND_EXPR which masks off bits outside the type of the innermost
diff --git a/gcc/testsuite/gcc.dg/fold-narrowbopcst-1.c 
b/gcc/testsuite/gcc.dg/fold-narrowbopcst-1.c
new file mode 100644
index 000..8a33677
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/fold-narrowbopcst-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -fdump-tree-optimized" } */
+
+int foo1 (unsigned char a[], unsigned int x)
+{
+  unsigned int i;
+  for (i = 0; i < 1000; i++)
+{
+  x = a[i];
+  a[i] = (unsigned char)(x >= 100 ? x - 100 : 0);
+}
+  return x;
+}
+/* { dg-final { scan-tree-dump " = _.* \\+ 156" "optimized" } } */

Re: [PATCH] PR78056: Fix build failure on Power7

[Bill Schmidt]

On Oct 26, 2016, at 8:29 AM, Segher Boessenkool  
wrote:
> 
> So, you do not want to create the builtins that we expand to machine insns
> that are not supported with the -mcpu= (or other flags) in use.  What does
> the ABI have to say about this?

The ABI is silent on this point.  The appendix of builtin functions for vector 
processing
tags these as POWER ISA 3.0, but that's the extent of it.  I don't see a 
problem with
disabling built-ins that generate code that won't assemble provided we diagnose 
the
error properly (the follow-up work that Kelvin mentioned).

I'll take any blame for suggesting that Kelvin go forward with a patch to get 
bootstrap
fixed and defer the error detection till afterwards...

Bill

Re: [PATCH GCC][1/4]Simplify (convert1 (minmax ((convert2 (x) c)))) into minmax (x c)

[Bin.Cheng]

On Tue, Oct 25, 2016 at 12:48 PM, Richard Biener
 wrote:
> On Tue, Oct 25, 2016 at 1:21 PM, Bin Cheng  wrote:
>> Hi,
>> This is a patch set adding various match.pd patterns in order to generate 
>> simplified MIN/MAX_EXPR mostly from COND_EXPR.  This is the first one 
>> optimizing (convert1 (minmax ((convert2 (x) c to minmax (x c), if 
>> convert2 promotes x and convert1 demotes back to x's type.  With this patch, 
>> generated assembly for test:
>> .L4:
>> ldr q0, [x3, x1]
>> add w2, w2, 1
>> cmp w0, w2
>> ushll   v2.4s, v0.4h, 0
>> ushll2  v1.4s, v0.8h, 0
>> uminv2.4s, v2.4s, v3.4s
>> uminv1.4s, v1.4s, v3.4s
>> xtn v4.4h, v2.4s
>> xtn2v4.8h, v1.4s
>> str q4, [x3, x1]
>> add x1, x1, 16
>> bhi .L4
>>
>> can be improved to:
>> .L4:
>> ldr q0, [x3, x1]
>> add w2, w2, 1
>> cmp w0, w2
>> uminv1.8h, v0.8h, v2.8h
>> str q1, [x3, x1]
>> add x1, x1, 16
>> bhi .L4
>>
>> Bootstrap and test on x86_64 and AArch64 for whole patch set.  Is it OK?
>
> Why restrict to GIMPLE?
>
> +/* (convert1 (minmax ((convert2 (x) c -> minmax (x c) if convert2
> +   promotes x and convert1 demotes back to x's type.  */
> +
> +(for minmax (min max)
> + (simplify
> +  (convert (minmax@0 (convert @1) INTEGER_CST@2))
> +  (if (types_compatible_p (TREE_TYPE (@1), type))
>
> comment mentions convert1 and convert2, just convert is correct I think.
>
> Please use types_match instead of types_compatible_p, this is a
> wrapper that does the correct thing for both GENERIC and GIMPLE.
>
> +   (with
> +{
> +  tree minmax_type = TREE_TYPE (@0);
> +  signop sgn = TYPE_SIGN (type);
> +  widest_int type_min = widest_int::from (wi::min_value (type), sgn);
> +  widest_int type_max = widest_int::from (wi::max_value (type), sgn);
> +}
> +(if (sgn == TYPE_SIGN (minmax_type)
> +&& TYPE_PRECISION (minmax_type) >= TYPE_PRECISION (type)
> +&& wi::to_widest (@2) >= type_min && wi::to_widest (@2) <= type_max)
>
> instead of this you can use int_fits_type_p (type, @2)
>
> + (minmax @1 { fold_convert (type, @2); }))
>
> use
>
>  (minmax @1 (convert @2))
>
> I believe the transform is also a win if @2 is not a constant but similarly
> promoted as @1.  This slightly complicates the patter and thus can
> be done as followup (if we think it's useful at this point).
>
> With the simplification you should get rid of the with{}

Thanks for reviewing, updated patch attached.  Is it OK?

Thanks,
bin
diff --git a/gcc/match.pd b/gcc/match.pd
index 767d23a..086709f 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -1337,6 +1337,16 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
&& TYPE_MIN_VALUE (type)
&& operand_equal_p (@1, TYPE_MIN_VALUE (type), OEP_ONLY_CONST))
@0)))
+
+/* (convert (minmax ((convert (x) c -> minmax (x c) if x is promoted
+   and the outer convert demotes the expression back to x's type.  */
+(for minmax (min max)
+ (simplify
+  (convert (minmax@0 (convert @1) INTEGER_CST@2))
+  (if (types_match (@1, type) && int_fits_type_p (@2, type)
+   && TYPE_PRECISION (TREE_TYPE (@0)) > TYPE_PRECISION (TREE_TYPE (@1)))
+   (minmax @1 (convert @2)
+
 (for minmax (FMIN FMAX)
  /* If either argument is NaN, return the other one.  Avoid the
 transformation if we get (and honor) a signalling NaN.  */
diff --git a/gcc/testsuite/gcc.dg/fold-convmaxconv-1.c 
b/gcc/testsuite/gcc.dg/fold-convmaxconv-1.c
new file mode 100644
index 000..38b
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/fold-convmaxconv-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O -fdump-tree-optimized" } */
+
+int foo (short a[], int x)
+{
+  unsigned int i;
+  for (i = 0; i < 1000; i++)
+{
+  x = a[i];
+  a[i] = (x <= 0 ? 0 : x);
+}
+  return x;
+}
+
+/* { dg-final { scan-tree-dump-not " = MAX_EXPR = 255 ? 255 : x);
+}
+  return x;
+}
+
+/* { dg-final { scan-tree-dump-not " = MIN_EXPR 

Re: [PATCH, Fortran] DEC Compatibility: Logical operations on integers become bitwise ops with -fdec

[Fritz Reese]

On Wed, Oct 26, 2016 at 6:16 AM, Andreas Schwab <sch...@suse.de> wrote:
> On Okt 25 2016, Fritz Reese <fritzore...@gmail.com> wrote:
>
>> * dec_bitwise_ops_1.f90, dec_bitwise_ops_2.f90: New testcases.
>
> I'm getting these errors on ia64:
>
> FAIL: gfortran.dg/dec_bitwise_ops_1.f90   -O0  (test for excess errors)
> Excess errors:
> /usr/local/gcc/gcc-20161026/gcc/testsuite/gfortran.dg/dec_bitwise_ops_1.f90:33:16:
>  Error: Can't convert INTEGER(4) to INTEGER(4) at (1)
> /usr/local/gcc/gcc-20161026/gcc/testsuite/gfortran.dg/dec_bitwise_ops_1.f90:34:16:
>  Error: Can't convert INTEGER(4) to INTEGER(4) at (1)
> /usr/local/gcc/gcc-20161026/gcc/testsuite/gfortran.dg/dec_bitwise_ops_1.f90:35:24:
>  Error: Can't convert INTEGER(4) to INTEGER(4) at (1)
...

Andreas,

I can't seem to reproduce this on x86-64. Did you fully apply the
patch? I think this section of code in resolve.c should be guarding
against type to same-type conversions in this case:

>>> resolve.c:3719 (resolve_operator)
  /* Logical ops on integers become bitwise ops with -fdec.  */
  else if (flag_dec
   && (op1->ts.type == BT_INTEGER || op2->ts.type == BT_INTEGER))
{
  e->ts.type = BT_INTEGER;
  e->ts.kind = gfc_kind_max (op1, op2);
  if (op1->ts.type != e->ts.type || op1->ts.kind != e->ts.kind)
gfc_convert_type (op1, >ts, 1);
  if (op2->ts.type != e->ts.type || op2->ts.kind != e->ts.kind)
gfc_convert_type (op2, >ts, 1);
  e = logical_to_bitwise (e);
  return resolve_function (e);
}
<<<

---
Fritz Reese

Re: [PATCH] sched: Do not reorder RTX_FRAME_RELATED_P insns (PR78029)

[Segher Boessenkool]

On Wed, Oct 26, 2016 at 03:13:06PM +0200, Bernd Schmidt wrote:
> On 10/26/2016 03:05 PM, Segher Boessenkool wrote:
> >2) We do not necessarily have all notes yet, if the port lets dwarf2cfi
> >create notes by itself.  Most (or even all?) ports do.
> 
> Hmm. Are you recording the insns in prologue_contains etc.?

I had a patch for that, I can resurrect it.

> You could 
> add dependencies for a prologue insn following an epilogue insn.

Good idea.  I'll have to think if that catches all cases though.
And it won't do anything for PR77687 (oh well).


Segher

[PATCH] Introduce class rtx_writer

[David Malcolm]

On Tue, 2016-10-25 at 14:47 +0200, Bernd Schmidt wrote:
> On 10/21/2016 10:27 PM, David Malcolm wrote:
> > Thanks.  I attemped to use those fields of recog_data, but it
> > doesn't
> > seem to be exactly what's needed here.
> 
> Yeah, I may have been confused. I'm not sure that just looking at
> SCRATCHes is the right thing either, but I think you're on the right
> track, and we can use something like your patch for now and extend it
> later if necessary.
> 
> > + public:
> > +  rtx_reuse_manager ();
> > +  ~rtx_reuse_manager ();
> > +  static rtx_reuse_manager *get () { return singleton; }
> 
> OTOH, this setup looks a bit odd to me. Are you trying to avoid
> converting the print_rtx stuff to its own class, or avoid passing the
> reuse manager as an argument to a lot of functions?

[...snip...]

I attempted to convert the print_rtx stuff to its own class, but ran
into a bug which stumped me for a while, hence I was trying to avoid
the need for it.

I've now fixed that bug.

The following patch moves various global state in print-rtl.c into
a new "rtx_writer" class, giving us a place to stash additional state
relating to dumping (and the possibility of putting extra
setup/cleanup in ctor/dtor).

I didn't bother renaming the variables (e.g. converting "indent" to
"m_indent"), to minimize churn, but I could do that also if you
prefer.

Various functions become methods, but everything labelled as
DEBUG_FUNCTION remains a function after the patch.

Successfully bootstrapped on x86_64-pc-linux-gnu.

OK for trunk?

If so, then I can try to rewrite the proposed rtx-reuse code using
rtx_writer.

gcc/ChangeLog:
* print-rtl-function.c (flag_compact): Delete global.
(print_rtx_function): Rewrite in terms of class rtx_writer.
* print-rtl.c (outfile): Delete global.
(sawclose): Likewise.
(indent): Likewise.
(in_call_function_usage): Likewise.
(flag_compact): Likewise.
(flag_simple): Likewise.
(rtx_writer::rtx_writer): New ctor.
(print_rtx_operand_code_0): Convert to...
(rtx_writer::print_rtx_operand_code_0): ...this.
(print_rtx_operand_code_e): Convert to...
(rtx_writer::print_rtx_operand_code_e): ...this.
(print_rtx_operand_codes_E_and_V): Convert to...
(rtx_writer::print_rtx_operand_codes_E_and_V): ...this.
(print_rtx_operand_code_i): Convert to...
(rtx_writer::print_rtx_operand_code_i): ...this.
(print_rtx_operand_code_r): Convert to...
(rtx_writer::print_rtx_operand_code_r): ...this.
(print_rtx_operand_code_u): Convert to...
(rtx_writer::print_rtx_operand_code_u): ...this.
(print_rtx_operand): Convert to...
(rtx_writer::print_rtx_operand): ...this.
(print_rtx): Convert to...
(rtx_writer::print_rtx): ...this.
(print_inline_rtx): Rewrite in terms of class rtx_writer.
(debug_rtx): Likewise.
(print_rtl): Convert to...
(rtx_writer::print_rtl): ...this.
(print_rtl): Reimplement in terms of class rtx_writer.
(print_rtl_single): Rewrite in terms of class rtx_writer.
(print_rtl_single_with_indent): Convert to..
(rtx_writer::print_rtl_single_with_indent): ...this.
(print_simple_rtl): Rewrite in terms of class rtx_writer.
* print-rtl.h (flag_compact): Delete decl.
(class rtx_writer): New class.
---
 gcc/print-rtl-function.c |   8 ++--
 gcc/print-rtl.c  | 121 +--
 gcc/print-rtl.h  |  39 ++-
 gcc/rtl-tests.c  |   5 +-
 4 files changed, 98 insertions(+), 75 deletions(-)

diff --git a/gcc/print-rtl-function.c b/gcc/print-rtl-function.c
index 7ce1b90..f37e1b7 100644
--- a/gcc/print-rtl-function.c
+++ b/gcc/print-rtl-function.c
@@ -189,7 +189,7 @@ can_have_basic_block_p (const rtx_insn *insn)
 DEBUG_FUNCTION void
 print_rtx_function (FILE *outfile, function *fn, bool compact)
 {
-  flag_compact = compact;
+  rtx_writer w (outfile, 0, false, compact);
 
   tree fdecl = fn->decl;
 
@@ -213,7 +213,7 @@ print_rtx_function (FILE *outfile, function *fn, bool 
compact)
  curr_bb = insn_bb;
  begin_any_block (outfile, curr_bb);
}
-  print_rtl_single_with_indent (outfile, insn, curr_bb ? 6 : 4);
+  w.print_rtl_single_with_indent (insn, curr_bb ? 6 : 4);
 }
   end_any_block (outfile, curr_bb);
   fprintf (outfile, "  ) ;; insn-chain\n");
@@ -221,11 +221,9 @@ print_rtx_function (FILE *outfile, function *fn, bool 
compact)
   /* Additional RTL state.  */
   fprintf (outfile, "  (crtl\n");
   fprintf (outfile, "(return_rtx \n");
-  print_rtl_single_with_indent (outfile, crtl->return_rtx, 6);
+  w.print_rtl_single_with_indent (crtl->return_rtx, 6);
   fprintf (outfile, ") ;; return_rtx\n");
   fprintf (outfile, "  ) ;; crtl\n");
 
   fprintf (outfile, ") ;; function \"%s\"\n", dname);
-
-  flag_compact = false;
 }
diff --git 

Re: [PATCH] Five patches for std::experimental::filesystem

[Jonathan Wakely]

On 24/10/16 17:50 +0100, Jonathan Wakely wrote:

  Make directory iterators become end iterator on error
  * src/filesystem/dir.cc (open_dir): Return same value for errors
  whether ignored or not.
  (_Dir::advance(error_code*, directory_options)): Return false on
  error.
  (directory_iterator(const path&, directory_options, error_code*)):
  Create end iterator on error (LWG 2723).
  (recursive_directory_iterator(const path&, directory_options,
  error_code*)): Likewise.
  * testsuite/experimental/filesystem/iterators/directory_iterator.cc:
  Update expected behaviour on error.
  * testsuite/experimental/filesystem/iterators/
  recursive_directory_iterator.cc: Likewise.


I missed the case where recursing into a sub-directory fails, and that
happened to be the one bit of the test where I didn't add a new check.

Tested x86_64-linux, committed to trunk.

commit a38bbf551b4f49e47fe1da03b779edba66240d5f
Author: Jonathan Wakely 
Date:   Wed Oct 26 13:34:15 2016 +0100

Fix error handling in recursive_directory_iterator::increment

	* src/filesystem/dir.cc (recursive_directory_iterator::increment):
	Reset state on error.
	* testsuite/experimental/filesystem/iterators/
	recursive_directory_iterator.cc: Check state after increment error.

diff --git a/libstdc++-v3/src/filesystem/dir.cc b/libstdc++-v3/src/filesystem/dir.cc
index 4640d75..bcd7dd0 100644
--- a/libstdc++-v3/src/filesystem/dir.cc
+++ b/libstdc++-v3/src/filesystem/dir.cc
@@ -343,7 +343,10 @@ fs::recursive_directory_iterator::increment(error_code& ec) noexcept
 {
   _Dir dir = open_dir(top.entry.path(), _M_options, );
   if (ec)
-	return *this;
+	{
+	  _M_dirs.reset();
+	  return *this;
+	}
   if (dir.dirp)
 	  _M_dirs->push(std::move(dir));
 }
diff --git a/libstdc++-v3/testsuite/experimental/filesystem/iterators/recursive_directory_iterator.cc b/libstdc++-v3/testsuite/experimental/filesystem/iterators/recursive_directory_iterator.cc
index b41c394..79aa178 100644
--- a/libstdc++-v3/testsuite/experimental/filesystem/iterators/recursive_directory_iterator.cc
+++ b/libstdc++-v3/testsuite/experimental/filesystem/iterators/recursive_directory_iterator.cc
@@ -81,6 +81,7 @@ test01()
   VERIFY( iter->path() == p/"d1/d2" );
   iter.increment(ec);  // should fail to recurse into p/d1/d2
   VERIFY( ec );
+  VERIFY( iter == fs::recursive_directory_iterator() );
 
   // Test inaccessible sub-directory, skipping permission denied.
   iter = fs::recursive_directory_iterator(p, opts, ec);

Re: [PATCH] PR78056: Fix build failure on Power7

[Segher Boessenkool]

Hi Kelvin,

On Wed, Oct 26, 2016 at 02:41:43PM +0200, Segher Boessenkool wrote:
>   PR target/78056
>   * config/rs6000/rs6000.c (spe_init_builtins): Modify loops to not
>   define builtin functions from the bdesc_spe_predicates or
>   bdesc_spe_evsel arrays if the builtin mask is not compatible with
>   the current compiler configuration.
>   (paired_init_builtins): Modify loop to not define define builtin
>   functions from the bdesc_paried_preds array if the builtin mask is
>   not compatible with the current compiler configuration.

Why do you change the SPE and PS builtins init as well?  Were they buggy
in the same way, we just never noticed?

>   (altivec_init_builtins): Modify loops to not define the
>   __builtin_altivec_stxvl function nor the builtin functions from
>   the bdesc_dst or bdesc_altivec_preds, bdesc_abs

I think you lost the last line(s) here?

So, you do not want to create the builtins that we expand to machine insns
that are not supported with the -mcpu= (or other flags) in use.  What does
the ABI have to say about this?


Segher

Re: RFC [2/3] divmod transform v2 - override expand_divmod_libfunc for ARM port

[Kyrill Tkachov]

On 16/10/16 07:00, Prathamesh Kulkarni wrote:

Hi,
This patch overrides expand_divmod_libfunc hook for ARM port.
I separated the SImode tests into separate file from DImode tests
because certain arm configs (cortex-15) have hardware div insn for
SImode but not for DImode, and for that config we want SImode tests to
be disabled but not DImode tests. The patch therefore has two
target-effective checks: divmod and divmod_simode.
Cross-tested on arm*-*-*.
OK to commit ?


Looks ok to me, the implementation of the hook is straightforward though
I have a question.
arm_expand_divmod_libfunc is not supposed to ever be called for SImode 
TARGET_IDIV.
It asserts it rather than just failing the expansion in some way.
How does the midend know not to call TARGET_EXPAND_DIVMOD_LIBFUNC in that case, 
does it
just check if the relevant sdiv optab is not available?

If so, this is ok for trunk assuming a bootstrap and test run on 
arm-none-linux-gnueabihf
shows no issues. Would be good to try one for --with-cpu=cortex-a15 and one 
with a !TARGET_IDIV
target, say --with-cpu=cortex-a9.

Sorry for the delay.

Thanks,
Kyrill



Thanks,
Prathamesh

[PATCH][GIMPLE FE] Fix parsing of switch stmts

[Richard Biener]

This fixes parsing and dumping of switch stmts as well as dumping of
PHI nodes in case a src BB has a label.  It also fixes PHI lowering
(the gsi_remove already does the gsi_next).

Tested on x86_64-unknown-linux-gnu.

New testcase is

/* { dg-do run } */
/* { dg-options "-O -fgimple" } */

int __GIMPLE ()
main (int argc, char * * argv)
{
  int a;

  bb_2:
  switch (argc_2(D)) {default: L2; case 1: L0; case 2: L1; }

L0:
  a_4 = 0;
  goto bb_6;

L1:
  a_3 = 3;
  goto bb_6;

L2:
  a_5 = -1;

  bb_6:
  a_1 = __PHI (L0: a_4, L1: a_3, L2: a_5);
  return a_1;

}

Richard.

2016-10-26  Richard Biener  

c/
* gimple-parser.c (c_parser_gimple_switch_stmt): Fix.

* gimple-pretty-print.c (dump_gimple_switch): Add missing semicolon.
(dump_gimple_phi): Dump BB label instead of artificial one.  Add
missing semicolon.
* tree-cfg.c (lower_phi_internal_fn): Properly do stmt removal.
(dump_function_to_file): Dump __GIMPLE ().

* gcc.dg/gimplefe-14.c: New testcase.

diff --git a/gcc/c/gimple-parser.c b/gcc/c/gimple-parser.c
index a1e8988..e9e3aae 100644
--- a/gcc/c/gimple-parser.c
+++ b/gcc/c/gimple-parser.c
@@ -1201,13 +1201,21 @@ c_parser_gimple_switch_stmt (c_parser *parser, 
gimple_seq *seq)
if (c_parser_next_token_is (parser, CPP_COLON))
  {
c_parser_consume_token (parser);
-   label = create_artificial_label (loc);
-   case_label = build_case_label (exp1.value, NULL_TREE,
-  label);
-   labels.safe_push (case_label);
-   gimple_seq_add_stmt (_body,
-gimple_build_label
-(CASE_LABEL (case_label)));
+   if (c_parser_next_token_is (parser, CPP_NAME))
+ {
+   label = c_parser_peek_token (parser)->value;
+   c_parser_consume_token (parser);
+   tree decl = lookup_label_for_goto (loc, label);
+   case_label = build_case_label (exp1.value, NULL_TREE,
+  decl);
+   labels.safe_push (case_label);
+   if (! c_parser_require (parser, CPP_SEMICOLON,
+   "expected %<;%>"))
+ return;
+ }
+   else if (! c_parser_require (parser, CPP_NAME,
+"expected label"))
+ return;
  }
else if (! c_parser_require (parser, CPP_SEMICOLON,
"expected %<:%>"))
@@ -1220,12 +1228,20 @@ c_parser_gimple_switch_stmt (c_parser *parser, 
gimple_seq *seq)
if (c_parser_next_token_is (parser, CPP_COLON))
  {
c_parser_consume_token (parser);
-   default_label = build_case_label (NULL_TREE, NULL_TREE,
- create_artificial_label
- (UNKNOWN_LOCATION));
-   gimple_seq_add_stmt (_body,
-gimple_build_label
-(CASE_LABEL (default_label)));
+   if (c_parser_next_token_is (parser, CPP_NAME))
+ {
+   label = c_parser_peek_token (parser)->value;
+   c_parser_consume_token (parser);
+   tree decl = lookup_label_for_goto (loc, label);
+   default_label = build_case_label (NULL_TREE, NULL_TREE,
+ decl);
+   if (! c_parser_require (parser, CPP_SEMICOLON,
+   "expected %<;%>"))
+ return;
+ }
+   else if (! c_parser_require (parser, CPP_NAME,
+"expected label"))
+ return;
  }
else if (! c_parser_require (parser, CPP_SEMICOLON,
"expected %<:%>"))
diff --git a/gcc/gimple-pretty-print.c b/gcc/gimple-pretty-print.c
index 9914adf..9d47f7f 100644
--- a/gcc/gimple-pretty-print.c
+++ b/gcc/gimple-pretty-print.c
@@ -909,7 +909,7 @@ dump_gimple_switch (pretty_printer *buffer, gswitch *gs, 
int spc,
}
 }
   if (flags & TDF_GIMPLE)
-pp_right_brace (buffer);
+pp_string (buffer, "; }");
   else
 pp_greater (buffer);
 }
@@ -2057,8 +2057,16 @@ dump_gimple_phi (pretty_printer *buffer, gphi *phi, int 
spc, bool comment,
dump_location (buffer, gimple_phi_arg_location (phi, i));
   if (flags & 

Re: [PATCH] sched: Do not reorder RTX_FRAME_RELATED_P insns (PR78029)

[Bernd Schmidt]

On 10/26/2016 03:05 PM, Segher Boessenkool wrote:

2) We do not necessarily have all notes yet, if the port lets dwarf2cfi
create notes by itself.  Most (or even all?) ports do.


Hmm. Are you recording the insns in prologue_contains etc.? You could 
add dependencies for a prologue insn following an epilogue insn.



Bernd

Re: [PATCH] sched: Do not reorder RTX_FRAME_RELATED_P insns (PR78029)

[Segher Boessenkool]

On Wed, Oct 26, 2016 at 02:30:04PM +0200, Bernd Schmidt wrote:
> On 10/26/2016 01:19 PM, Segher Boessenkool wrote:
> >Separate shrink-wrapping creates this not-all-that-smart code because
> >the profile is quite messed up, and spread_components isn't super smart
> >to begin with.  I'll have a patch for that soon, but even with it (and
> >also without separate shrink-wrapping as far as I see) sched should not
> >reorder insns that have CFI notes that conflict.
> 
> I think I agree with this as long as we really do prevent movement only 
> if notes conflict. For example, I see no reason to forbid swapping 
> normal register saves/restores, and doing so may well cost performance. 
> So I think the patch needs to do better than just check RTX_FRAME_RELATED_P.

That's what I thought first as well, but two things:

1) As I wrote in the original mail: "I originally was a bit worried
that this would degrade code quality, but it seems to even improve it:
more other insns are scheduled between the prologue insns."

OTOH I now set true output dependencies, which probably explains all
that, hrm.

2) We do not necessarily have all notes yet, if the port lets dwarf2cfi
create notes by itself.  Most (or even all?) ports do.


Segher

Re: [PATCH][AArch64] Add a SHA1H pattern

[James Greenhalgh]

On Wed, Oct 26, 2016 at 12:11:44PM +, Wilco Dijkstra wrote:
> Add a SHA1H pattern with a V2SI input.  This avoids unnecessary
> DUPs when using intrinsics like vsha1h_u32 (vgetq_lane_u32 (x, 0)).

I think this is incorrect for big endian - element 0 of a vec_select in
big-endian for V4SImode is the high 32-bits (i.e. bits 96-127 of the
architected register). I think you'd need two patterns, one as below for
!BYTES_BIG_ENDIAN, and one selecting element 3 for BYTES_BIG_ENDIAN.

Thanks,
James

> ChangeLog:
> 2016-10-26  Wilco Dijkstra  
> 
>   * config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hv4si): New 
> pattern.
> --
> diff --git a/gcc/config/aarch64/aarch64-simd.md 
> b/gcc/config/aarch64/aarch64-simd.md
> index 
> 9ce7f00050913aebd9f83ae9c4ce4ad469dd0d98..47f1740aa8bcab948607e00c2503a34aafb5ba0e
>  100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -5705,6 +5705,16 @@
>[(set_attr "type" "crypto_sha1_fast")]
>  )
>  
> +(define_insn "aarch64_crypto_sha1hv4si"
> +  [(set (match_operand:SI 0 "register_operand" "=w")
> + (unspec:SI [(vec_select:SI (match_operand:V4SI 1 "register_operand" "w")
> +  (parallel [(const_int 0)]))]
> +  UNSPEC_SHA1H))]
> +  "TARGET_SIMD && TARGET_CRYPTO"
> +  "sha1h\\t%s0, %s1"
> +  [(set_attr "type" "crypto_sha1_fast")]
> +)
> +
>  (define_insn "aarch64_crypto_sha1su1v4si"
>[(set (match_operand:V4SI 0 "register_operand" "=w")
>  (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
> 

Re: [PATCHv2 1/7, GCC, ARM, V8M] Add support for ARMv8-M's Secure Extensions flag and intrinsics

[Kyrill Tkachov]

On 26/10/16 10:12, Kyrill Tkachov wrote:

Hi Andre, thanks for resending them.

On 25/10/16 17:26, Andre Vieira (lists) wrote:

On 24/08/16 12:00, Andre Vieira (lists) wrote:

On 25/07/16 14:19, Andre Vieira (lists) wrote:

This patch adds the support of the '-mcmse' option to enable ARMv8-M's
Security Extensions and supports the following intrinsics:
cmse_TT
cmse_TT_fptr
cmse_TTT
cmse_TTT_fptr
cmse_TTA
cmse_TTA_fptr
cmse_TTAT
cmse_TTAT_fptr
cmse_check_address_range
cmse_check_pointed_object
cmse_is_nsfptr
cmse_nsfptr_create

It also defines the mandatory cmse_address_info struct and the
__ARM_FEATURE_CMSE macro.
See Chapter 4, Sections 5.2, 5.3 and 5.6 of ARM®v8-M Security
Extensions: Requirements on Development Tools
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

*** gcc/ChangeLog ***
2016-07-25  Andre Vieira 
 Thomas Preud'homme 

 * config.gcc (extra_headers): Added arm_cmse.h.
 * config/arm/arm-arches.def (ARM_ARCH):
 (armv8-m): Add FL2_CMSE.
 (armv8-m.main): Likewise.
 (armv8-m.main+dsp): Likewise.
 * config/arm/arm-c.c
 (arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro.
 * config/arm/arm-protos.h
 (arm_is_constant_pool_ref): Define FL2_CMSE.
 * config/arm.c (arm_arch_cmse): New.
 (arm_option_override): New error for unsupported cmse target.
 * config/arm/arm.h (arm_arch_cmse): New.
 * config/arm/arm.opt (mcmse): New.
 * doc/invoke.texi (ARM Options): Add -mcmse.
 * config/arm/arm_cmse.h: New file.

*** libgcc/ChangeLog ***
2016-07-25  Andre Vieira 
 Thomas Preud'homme 

 * config/arm/cmse.c: Likewise.
 * config/arm/t-arm (HAVE_CMSE): New.

*** gcc/testsuite/ChangeLog ***
2016-07-25  Andre Vieira 
 Thomas Preud'homme 

 * gcc.target/arm/cmse/cmse.exp: New.
 * gcc.target/arm/cmse/cmse-1.c: New.
 * gcc.target/arm/cmse/cmse-12.c: New.
 * lib/target-supports.exp
 (check_effective_target_arm_cmse_ok): New.



Just remembered, new effective target checks should be documented in 
sourcebuild.texi
Kyrill




Added more documentation as requested.

This patch adds the support of the '-mcmse' option to enable ARMv8-M's
Security Extensions and supports the following intrinsics:
cmse_TT
cmse_TT_fptr
cmse_TTT
cmse_TTT_fptr
cmse_TTA
cmse_TTA_fptr
cmse_TTAT
cmse_TTAT_fptr
cmse_check_address_range
cmse_check_pointed_object
cmse_is_nsfptr
cmse_nsfptr_create

It also defines the mandatory cmse_address_info struct and the
__ARM_FEATURE_CMSE macro.
See Chapter 4, Sections 5.2, 5.3 and 5.6 of ARM®v8-M Security
Extensions: Requirements on Development Tools
(http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/index.html).

*** gcc/ChangeLog ***
2016-07-xx  Andre Vieira 
 Thomas Preud'homme 

 * config.gcc (extra_headers): Added arm_cmse.h.
 * config/arm/arm-arches.def (ARM_ARCH):
 (armv8-m): Add FL2_CMSE.
 (armv8-m.main): Likewise.
 (armv8-m.main+dsp): Likewise.
 * config/arm/arm-c.c
 (arm_cpu_builtins): Added __ARM_FEATURE_CMSE macro.
 * config/arm/arm-protos.h
 (arm_is_constant_pool_ref): Define FL2_CMSE.
 * config/arm.c (arm_arch_cmse): New.
 (arm_option_override): New error for unsupported cmse target.
 * config/arm/arm.h (arm_arch_cmse): New.
 * config/arm/arm.opt (mcmse): New.
 * doc/invoke.texi (ARM Options): Add -mcmse.
 * doc/extend.texi (ARM ARMv8-M Security Extensions): Add section.
 * config/arm/arm_cmse.h: New file.

*** libgcc/ChangeLog ***
2016-07-xx  Andre Vieira 
 Thomas Preud'homme 
 * config/arm/cmse.c: Likewise.
 * config/arm/t-arm (HAVE_CMSE): New.


*** gcc/testsuite/ChangeLog ***
2016-07-xx  Andre Vieira 
 Thomas Preud'homme 

 * gcc.target/arm/cmse/cmse.exp: New.
 * gcc.target/arm/cmse/cmse-1.c: New.
 * gcc.target/arm/cmse/cmse-12.c: New.
 * lib/target-supports.exp
 (check_effective_target_arm_cmse_ok): New.


Hi,

Rebased previous patch on top of trunk as requested. No changes to
ChangeLog.

Cheers,
Andre


diff --git a/gcc/config/arm/arm_cmse.h b/gcc/config/arm/arm_cmse.h
new file mode 100644
index 
..b4232937c6ae04754a6bbc513b143672a4be5530
--- /dev/null
+++ b/gcc/config/arm/arm_cmse.h



+
+#if __ARM_FEATURE_CMSE & 2
+
+#define cmse_TTA_fptr(p) (__cmse_TTA_fptr ((__cmse_fptr)(p)))
+
+__extension__ static __inline __attribute__ 

Re: [PATCHv2 4/7, GCC, ARM, V8M] ARMv8-M Security Extension's cmse_nonsecure_entry: clear registers

[Kyrill Tkachov]

Hi Andre,

On 25/10/16 17:29, Andre Vieira (lists) wrote:

On 24/08/16 12:01, Andre Vieira (lists) wrote:

On 25/07/16 14:23, Andre Vieira (lists) wrote:

This patch extends support for the ARMv8-M Security Extensions
'cmse_nonsecure_entry' attribute to safeguard against leak of
information through unbanked registers.

When returning from a nonsecure entry function we clear all caller-saved
registers that are not used to pass return values, by writing either the
LR, in case of general purpose registers, or the value 0, in case of FP
registers. We use the LR to write to APSR and FPSCR too. We currently do
not support entry functions that pass arguments or return variables on
the stack and we diagnose this. This patch relies on the existing code
to make sure callee-saved registers used in cmse_nonsecure_entry
functions are saved and restored thus retaining their nonsecure mode
value, this should be happening already as it is required by AAPCS.

This patch also clears padding bits for cmse_nonsecure_entry functions
with struct and union return types. For unions a bit is only considered
a padding bit if it is an unused bit in every field of that union. The
function that calculates these is used in a later patch to do the same
for arguments of cmse_nonsecure_call's.

*** gcc/ChangeLog ***
2016-07-25  Andre Vieira
 Thomas Preud'homme  

 * config/arm/arm.c (output_return_instruction): Clear
 registers.
 (thumb2_expand_return): Likewise.
 (thumb1_expand_epilogue): Likewise.
 (thumb_exit): Likewise.
 (arm_expand_epilogue): Likewise.
 (cmse_nonsecure_entry_clear_before_return): New.
 (comp_not_to_clear_mask_str_un): New.
 (compute_not_to_clear_mask): New.
 * config/arm/thumb1.md (*epilogue_insns): Change length attribute.
 * config/arm/thumb2.md (*thumb2_return): Likewise.

*** gcc/testsuite/ChangeLog ***
2016-07-25  Andre Vieira
 Thomas Preud'homme  

 * gcc.target/arm/cmse/cmse.exp: Test different multilibs separate.
 * gcc.target/arm/cmse/struct-1.c: New.
 * gcc.target/arm/cmse/bitfield-1.c: New.
 * gcc.target/arm/cmse/bitfield-2.c: New.
 * gcc.target/arm/cmse/bitfield-3.c: New.
 * gcc.target/arm/cmse/baseline/cmse-2.c: Test that registers are
cleared.
 * gcc.target/arm/cmse/mainline/soft/cmse-5.c: New.
 * gcc.target/arm/cmse/mainline/hard/cmse-5.c: New.
 * gcc.target/arm/cmse/mainline/hard-sp/cmse-5.c: New.
 * gcc.target/arm/cmse/mainline/softfp/cmse-5.c: New.
 * gcc.target/arm/cmse/mainline/softfp-sp/cmse-5.c: New.


Updated this patch to correctly clear only the cumulative
exception-status (0-4,7) and the condition code bits (28-31) of the
FPSCR. I also adapted the code to be handle the bigger floating point
register files.



This patch extends support for the ARMv8-M Security Extensions
'cmse_nonsecure_entry' attribute to safeguard against leak of
information through unbanked registers.

When returning from a nonsecure entry function we clear all caller-saved
registers that are not used to pass return values, by writing either the
LR, in case of general purpose registers, or the value 0, in case of FP
registers. We use the LR to write to APSR. For FPSCR we clear only the
cumulative exception-status (0-4, 7) and the condition code bits
(28-31). We currently do not support entry functions that pass arguments
or return variables on the stack and we diagnose this. This patch relies
on the existing code to make sure callee-saved registers used in
cmse_nonsecure_entry functions are saved and restored thus retaining
their nonsecure mode value, this should be happening already as it is
required by AAPCS.

This patch also clears padding bits for cmse_nonsecure_entry functions
with struct and union return types. For unions a bit is only considered
a padding bit if it is an unused bit in every field of that union. The
function that calculates these is used in a later patch to do the same
for arguments of cmse_nonsecure_call's.

*** gcc/ChangeLog ***
2016-07-xx  Andre Vieira
 Thomas Preud'homme  

 * config/arm/arm.c (output_return_instruction): Clear
 registers.
 (thumb2_expand_return): Likewise.
 (thumb1_expand_epilogue): Likewise.
 (thumb_exit): Likewise.
 (arm_expand_epilogue): Likewise.
 (cmse_nonsecure_entry_clear_before_return): New.
 (comp_not_to_clear_mask_str_un): New.
 (compute_not_to_clear_mask): New.
 * config/arm/thumb1.md (*epilogue_insns): Change length attribute.
 * config/arm/thumb2.md (*thumb2_return): Duplicate pattern for
 cmse_nonsecure_entry functions.

*** gcc/testsuite/ChangeLog ***

Re: [PATCH, Fortran] DEC Compatibility: Logical operations on integers become bitwise ops with -fdec

[Fritz Reese]

On Wed, Oct 26, 2016 at 6:16 AM, Andreas Schwab <sch...@suse.de> wrote:
> On Okt 25 2016, Fritz Reese <fritzore...@gmail.com> wrote:
>
>> * dec_bitwise_ops_1.f90, dec_bitwise_ops_2.f90: New testcases.
>
> I'm getting these errors on ia64:
>
> FAIL: gfortran.dg/dec_bitwise_ops_1.f90   -O0  (test for excess errors)
> Excess errors:
> /usr/local/gcc/gcc-20161026/gcc/testsuite/gfortran.dg/dec_bitwise_ops_1.f90:33:16:
>  Error: Can't convert INTEGER(4) to INTEGER(4) at (1)
...

Looking into this.

---
Fritz Reese

Re: [PATCH] sched: Do not reorder RTX_FRAME_RELATED_P insns (PR78029)

[Bernd Schmidt]

On 10/26/2016 01:19 PM, Segher Boessenkool wrote:

Separate shrink-wrapping creates this not-all-that-smart code because
the profile is quite messed up, and spread_components isn't super smart
to begin with.  I'll have a patch for that soon, but even with it (and
also without separate shrink-wrapping as far as I see) sched should not
reorder insns that have CFI notes that conflict.


I think I agree with this as long as we really do prevent movement only 
if notes conflict. For example, I see no reason to forbid swapping 
normal register saves/restores, and doing so may well cost performance. 
So I think the patch needs to do better than just check RTX_FRAME_RELATED_P.



Bernd

Re: [PATCH, Fortran] DEC Compatibility: New I/O Specifiers CARRIAGECONTROL, READONLY, SHARE with -fdec

[Fritz Reese]

On Tue, Oct 25, 2016 at 11:36 PM, Jerry DeLisle  wrote:
> On 10/25/2016 11:52 AM, Fritz Reese wrote:
>>
>> All,
>>
>> Here's the big one. This patch proposes an extension to both the GNU
>> Fortran front-end and runtime library (libgfortran) to support three
>> additional I/O specifiers: CARRIAGECONTROL, READONLY, and SHARE for
>> compatibility with legacy compilers/code.
...
>> OK for trunk?
>>
>
> Patch applies with a few minor offsets, regression tests OK, indentation
> looks good. Test cases are thorough. I appreciate that you guarded the
> open_share and close_share with the #if defined(HAVE_FCNTL) &&
> defined(F_SETLK) && defined(F_UNLCK). I am pretty sure not all platforms
> will support these.
>
> Good Job,
>
> Yes, OK to commit.
>
> Jerry
>

Thanks- committed r241550.

((big sigh of relief))

---
Fritz Reese

[PATCH][AArch64] Add a SHA1H pattern

[Wilco Dijkstra]

Add a SHA1H pattern with a V2SI input.  This avoids unnecessary
DUPs when using intrinsics like vsha1h_u32 (vgetq_lane_u32 (x, 0)).

ChangeLog:
2016-10-26  Wilco Dijkstra  

* config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hv4si): New 
pattern.
--
diff --git a/gcc/config/aarch64/aarch64-simd.md 
b/gcc/config/aarch64/aarch64-simd.md
index 
9ce7f00050913aebd9f83ae9c4ce4ad469dd0d98..47f1740aa8bcab948607e00c2503a34aafb5ba0e
 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -5705,6 +5705,16 @@
   [(set_attr "type" "crypto_sha1_fast")]
 )
 
+(define_insn "aarch64_crypto_sha1hv4si"
+  [(set (match_operand:SI 0 "register_operand" "=w")
+   (unspec:SI [(vec_select:SI (match_operand:V4SI 1 "register_operand" "w")
+(parallel [(const_int 0)]))]
+UNSPEC_SHA1H))]
+  "TARGET_SIMD && TARGET_CRYPTO"
+  "sha1h\\t%s0, %s1"
+  [(set_attr "type" "crypto_sha1_fast")]
+)
+
 (define_insn "aarch64_crypto_sha1su1v4si"
   [(set (match_operand:V4SI 0 "register_operand" "=w")
 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")

Re: [Patch, fortran] PR78108 Generic type-bound operator conflicts

[Andre Vehreschild]

Hi Paul,

looks ok to me. At least I couldn't break it with the most devious codes I
could fathom.

Ok for trunk and if applicable to gcc-6.

- Andre


On Wed, 26 Oct 2016 13:28:15 +0200
Paul Richard Thomas  wrote:

> Dear All,
> 
> The comment in the patch more than adequately describes how this patch
> works. The first testcase checks that correctly functioning code is
> produced, when the spurious error is suppressed, and the second checks
> that genuine errors are caught.
> 
> Bootstraps and regtests on FC21/x86_64 - OK for trunk and, in a week
> or so time, 6-branch?
> 
> I intend to commit as 'obvious' at 17:00 CET today if there are no objections.
> 
> Best regards
> 
> Paul
> 
> 2016-10-26  Paul Thomas  
> 
> PR fortran/78108
> * resolve.c (resolve_typebound_intrinsic_op): For submodules
> suppress the error and return if the same procedure symbol
> is added more than once to the interface.
> 
> 2016-10-26  Paul Thomas  
> 
> PR fortran/78108
> * gfortran.dg/submodule_18.f08: New test.
> * gfortran.dg/submodule_19.f08: New test.


-- 
Andre Vehreschild * Email: vehre ad gmx dot de 

[PATCH] libstdc++/78111 fix fallback code for filesystem::canonical

[Jonathan Wakely]

The configure test for realpath() is missing a header, and the
fallback version of filesystem::canonical() that gets used if
realpath() fails was not setting an error.

Tested powerpc64le-linux, committed to trunk.


commit f36dd7f817590c618884e14433dd70c03334c288
Author: Jonathan Wakely 
Date:   Wed Oct 26 12:16:18 2016 +0100

PR78111 fix fallback code for filesystem::canonical

	PR libstdc++/78111
	* src/filesystem/ops.cc (canonical): Set error for non-existent path.

diff --git a/libstdc++-v3/src/filesystem/ops.cc b/libstdc++-v3/src/filesystem/ops.cc
index 32c9c5e..9abcee0 100644
--- a/libstdc++-v3/src/filesystem/ops.cc
+++ b/libstdc++-v3/src/filesystem/ops.cc
@@ -142,7 +142,11 @@ fs::canonical(const path& p, const path& base, error_code& ec)
 #endif
 
   if (!exists(pa, ec))
-return result;
+{
+  if (!ec)
+	ec = make_error_code(std::errc::no_such_file_or_directory);
+  return result;
+}
   // else: we know there are (currently) no unresolvable symlink loops
 
   result = pa.root_path();

commit 16b33e71b6b247d3936cddbddac982082e802894
Author: Jonathan Wakely 
Date:   Wed Oct 26 12:14:53 2016 +0100

Add missing header in Filesystem TS configure tests

2016-10-26  Uros Bizjak  

	* acinclude.m4 (GLIBCXX_CHECK_FILESYSTEM_DEPS): Include 
	for PATH_MAX in realpath test.
	* configure: Regenerate.

diff --git a/libstdc++-v3/acinclude.m4 b/libstdc++-v3/acinclude.m4
index d0ee45f..1fc4de1 100644
--- a/libstdc++-v3/acinclude.m4
+++ b/libstdc++-v3/acinclude.m4
@@ -4290,6 +4290,7 @@ dnl
   AC_CACHE_VAL(glibcxx_cv_realpath, [dnl
 GCC_TRY_COMPILE_OR_LINK(
   [
+   #include 
#include 
#include 
   ],

[Patch, fortran] PR78108 Generic type-bound operator conflicts

[Paul Richard Thomas]

Dear All,

The comment in the patch more than adequately describes how this patch
works. The first testcase checks that correctly functioning code is
produced, when the spurious error is suppressed, and the second checks
that genuine errors are caught.

Bootstraps and regtests on FC21/x86_64 - OK for trunk and, in a week
or so time, 6-branch?

I intend to commit as 'obvious' at 17:00 CET today if there are no objections.

Best regards

Paul

2016-10-26  Paul Thomas  

PR fortran/78108
* resolve.c (resolve_typebound_intrinsic_op): For submodules
suppress the error and return if the same procedure symbol
is added more than once to the interface.

2016-10-26  Paul Thomas  

PR fortran/78108
* gfortran.dg/submodule_18.f08: New test.
* gfortran.dg/submodule_19.f08: New test.
Index: gcc/fortran/resolve.c
===
*** gcc/fortran/resolve.c   (revision 241539)
--- gcc/fortran/resolve.c   (working copy)
*** resolve_typebound_intrinsic_op (gfc_symb
*** 12797,12803 
  && p->access != ACCESS_PRIVATE && derived->ns == gfc_current_ns)
{
  gfc_interface *head, *intr;
! if (!gfc_check_new_interface (derived->ns->op[op], target_proc, 
p->where))
return false;
  head = derived->ns->op[op];
  intr = gfc_get_interface ();
--- 12797,12813 
  && p->access != ACCESS_PRIVATE && derived->ns == gfc_current_ns)
{
  gfc_interface *head, *intr;
! 
! /* Preempt 'gfc_check_new_interface' for submodules, where the
!mechanism for handling module procedures winds up resolving
!operator interfaces twice and would otherwise cause an error.  */
! for (intr = derived->ns->op[op]; intr; intr = intr->next)
!   if (intr->sym == target_proc
!   && target_proc->attr.used_in_submodule)
! return true;
! 
! if (!gfc_check_new_interface (derived->ns->op[op],
!   target_proc, p->where))
return false;
  head = derived->ns->op[op];
  intr = gfc_get_interface ();
Index: gcc/testsuite/gfortran.dg/submodule_18.f08
===
*** gcc/testsuite/gfortran.dg/submodule_18.f08  (revision 0)
--- gcc/testsuite/gfortran.dg/submodule_18.f08  (working copy)
***
*** 0 
--- 1,49 
+ ! { dg-do run }
+ !
+ ! Tests the fix for PR78108 in which an error was
+ ! triggered by the module procedures being added twice
+ ! to the operator interfaces.
+ !
+ ! Contributed by Damian Rouson  
+ !
+ module foo_interface
+   implicit none
+   type foo
+ integer :: x
+   contains
+ procedure :: add
+ generic :: operator(+) => add
+ procedure :: mult
+ generic :: operator(*) => mult
+   end type
+   interface
+ integer module function add(lhs,rhs)
+   implicit none
+   class(foo), intent(in) :: lhs,rhs
+ end function
+ integer module function mult(lhs,rhs)
+   implicit none
+   class(foo), intent(in) :: lhs,rhs
+ end function
+   end interface
+ end module
+ submodule(foo_interface) foo_implementation
+ contains
+ integer module function add(lhs,rhs)
+   implicit none
+   class(foo), intent(in) :: lhs,rhs
+   add = lhs % x + rhs % x
+ end function
+ integer module function mult(lhs,rhs)
+   implicit none
+   class(foo), intent(in) :: lhs,rhs
+   mult = lhs % x * rhs % x
+ end function
+ end submodule
+ 
+   use foo_interface
+   type(foo) :: a = foo (42)
+   type(foo) :: b = foo (99)
+   if (a + b .ne. 141) call abort
+   if (a * b .ne. 4158) call abort
+ end
Index: gcc/testsuite/gfortran.dg/submodule_19.f08
===
*** gcc/testsuite/gfortran.dg/submodule_19.f08  (revision 0)
--- gcc/testsuite/gfortran.dg/submodule_19.f08  (working copy)
***
*** 0 
--- 1,59 
+ ! { dg-do compile }
+ !
+ ! Tests the fix for PR78108 in which an error was triggered by the
+ ! generic operator being resolved more than once in submodules. This
+ ! test checks that the error is triggered when the specific procedure
+ ! really is inserted more than once in the interface.
+ !
+ ! Note that adding the extra interface to the module produces two
+ ! errors; the one below and 'Duplicate EXTERNAL attribute specified at (1)'
+ !
+ ! Contributed by Damian Rouson  
+ !
+ module foo_interface
+   implicit none
+   type foo
+ integer :: x
+   contains
+ procedure :: add
+ generic :: operator(+) => add
+ procedure :: mult
+ generic :: operator(*) => mult
+   end type
+   interface
+ integer module function add(lhs,rhs)
+   implicit none
+   class(foo), intent(in) :: lhs,rhs
+ end function
+ integer module 

Re: [PATCH] sched: Do not reorder RTX_FRAME_RELATED_P insns (PR78029)

[Segher Boessenkool]

On Wed, Oct 26, 2016 at 12:48:54PM +0200, Bernd Schmidt wrote:
> On 10/25/2016 06:57 PM, Segher Boessenkool wrote:
> >This patch makes scheduling not reorder any RTX_FRAME_RELATED_P insns
> >(relative to each other), to fix PR78029.  I originally was a bit worried
> >that this would degrade code quality, but it seems to even improve it:
> >more other insns are scheduled between the prologue insns.
> >
> >The problem in PR78029:
> >We have two insns, in this order:
> >
> >(insn/f 300 299 267 8 (set (reg:DI 65 lr)
> >(reg:DI 0 0)) 579 {*movdi_internal64}
> > (expr_list:REG_DEAD (reg:DI 0 0)
> >(expr_list:REG_CFA_RESTORE (reg:DI 65 lr)
> >(nil
> >...
> >(insn/f 310 268 134 8 (set (mem/c:DI (plus:DI (reg/f:DI 1 1)
> >(const_int 144 [0x90])) [6  S8 A8])
> >(reg:DI 0 0)) 579 {*movdi_internal64}
> > (expr_list:REG_DEAD (reg:DI 0 0)
> >(expr_list:REG_CFA_OFFSET (set (mem/c:DI (plus:DI (reg/f:DI 1 1)
> >(const_int 144 [0x90])) [6  S8 A8])
> >(reg:DI 65 lr))
> >(nil
> >
> >and sched swaps them (when compiling for power6, it tries to put memory
> >stores together, so insn 310 is moved up past 300 to go together with
> >some other store).  But the REG_CFA_RESTORE and REG_CFA_OFFSET cannot be
> >swapped (they both say where the orig value of LR now lives).
> 
> How are these two insns generated, and how does this differ from a 
> normal prologue? Can you post the entire dump (maybe to bugzilla) so we 
> can verify whether the code generation makes sense?

The first is a piece of epilogue and the second a piece of prologue
(both those components need two insns, we cannot store LR to memory
directly, so it is moved via GPR0).  These are generated by separate
shrink-wrapping.  PR78029 has a testcase (also not the compilation
options).

This patch will also most likely fix PR77687, a problem that has been
plaguing us for ages.

Separate shrink-wrapping creates this not-all-that-smart code because
the profile is quite messed up, and spread_components isn't super smart
to begin with.  I'll have a patch for that soon, but even with it (and
also without separate shrink-wrapping as far as I see) sched should not
reorder insns that have CFI notes that conflict.

I attached a dump (before sched2) to PR78029.

Thanks,


Segher

Re: [patch,committed] Work around problem in gen-pass-instances.awk

[Richard Biener]

On Wed, 26 Oct 2016, Jakub Jelinek wrote:

> On Wed, Oct 26, 2016 at 11:54:36AM +0200, Georg-Johann Lay wrote:
> > gen-pass-instances.awk is sensitive to the order in which directives are
> > written down, e.g. in target-pass.def: If a pass that runs first is added
> > first, then the last pass is skipped and not added to pass-instances.def.
> > 
> > Work around is to add the 2nd pass before adding the 1st pass...
> > 
> > http://gcc.gnu.org/r241547
> > 
> > No so obvious, but committed anyway...
> 
> We shouldn't be working around bugs, but fixing them.
> 
> Here is a fix (so far tested only with running
> for i in alpha avr i386 sparc aarch64; do 
>   awk -f ./gen-pass-instances.awk.jj passes.def config/$i/${i}-passes.def > 
> /tmp/1
>   awk -f ./gen-pass-instances.awk passes.def config/$i/${i}-passes.def > 
> /tmp/2
>   diff -up /tmp/1 /tmp/2 # and diff -upb
> done
> ), for avr for both avr-passes.def before your workaround and after it.
> Except for the desirable whitespace changes, the only change is in the
> pre-workaround avr-passes.def having the same output as after-workaround
> (except for the comments at the end of file).
> 
> The fix for the avr issue is just the first hunk, the first part of the
> second hunk attempts to deal with
> NEXT_PASS ( avr_pass_casesi, 1);
> instead of the desirable
> NEXT_PASS (avr_pass_casesi, 1);
> (all arguments have the whitespace they have in *.def before them (after ,
> or ( characters).  So the first part of the second hunk strips away
> whitespace, so that one doesn't need to type
> INSERT_PASS_BEFORE (pass_free_cfg, 1,avr_pass_casesi);
> and the second part of the second hunk and third hunk deal with similar
> issue for the optional argument, we used to emit
> NEXT_PASS_WITH_ARG (pass_dominator, 1,  false /* may_peel_loop_headers_p */);
> rather than
> NEXT_PASS_WITH_ARG (pass_dominator, 1, false /* may_peel_loop_headers_p */);
> because the space from
> NEXT_PASS (pass_dominator, false /* may_peel_loop_headers_p */);
> (in between , and false) is already there and we add another one.
> 
> Ok for trunk if it passes bootstrap/regtest (though, as it doesn't change
> anything but whitespace on x86_64, it shouldn't make a difference)?

Ok.

Richard.

> 2016-10-26  Jakub Jelinek  
> 
>   * gen-pass-instances.awk (adjust_linenos): INcrement pass_lines[p]
>   by increment rather than double it.
>   (insert_remove_pass): Strip leading whitespace from args[3].  Don't
>   emit a space before args[4].
>   (END): Don't emit a space before with_arg.
> 
> --- gcc/gen-pass-instances.awk.jj 2016-10-10 10:41:32.0 +0200
> +++ gcc/gen-pass-instances.awk2016-10-26 12:30:20.637310242 +0200
> @@ -90,7 +90,7 @@ function adjust_linenos(above, increment
>  {
>for (p in pass_lines)
>  if (pass_lines[p] >= above)
> -  pass_lines[p] += pass_lines[p];
> +  pass_lines[p] += increment;
>if (increment > 0)
>  for (i = lineno - 1; i >= above; i--)
>lines[i + increment] = lines[i];
> @@ -100,16 +100,18 @@ function adjust_linenos(above, increment
>lineno += increment;
>  }
>  
> -function insert_remove_pass(line, fnname)
> +function insert_remove_pass(line, fnname,arg3)
>  {
>parse_line($0, fnname);
>pass_name = args[1];
>if (pass_name == "PASS")
>  return 1;
>pass_num = args[2] + 0;
> -  new_line = prefix "NEXT_PASS (" args[3];
> +  arg3 = args[3];
> +  sub(/^[ \t]*/, "", arg3);
> +  new_line = prefix "NEXT_PASS (" arg3;
>if (args[4])
> -new_line = new_line ", " args[4];
> +new_line = new_line "," args[4];
>new_line = new_line ")" postfix;
>if (!pass_lines[pass_name, pass_num])
>  {
> @@ -218,7 +220,7 @@ END {
>   printf "NEXT_PASS";
> printf " (%s, %s", pass_name, pass_num;
> if (with_arg)
> - printf ", %s", with_arg;
> + printf ",%s", with_arg;
> printf ")%s\n", postfix;
>   }
>else
> 
> 
>   Jakub
> 
> 

-- 
Richard Biener 
SUSE LINUX GmbH, GF: Felix Imendoerffer, Jane Smithard, Graham Norton, HRB 
21284 (AG Nuernberg)

Re: [PATCH] sched: Do not reorder RTX_FRAME_RELATED_P insns (PR78029)

[Bernd Schmidt]

On 10/25/2016 06:57 PM, Segher Boessenkool wrote:

This patch makes scheduling not reorder any RTX_FRAME_RELATED_P insns
(relative to each other), to fix PR78029.  I originally was a bit worried
that this would degrade code quality, but it seems to even improve it:
more other insns are scheduled between the prologue insns.

The problem in PR78029:
We have two insns, in this order:

(insn/f 300 299 267 8 (set (reg:DI 65 lr)
(reg:DI 0 0)) 579 {*movdi_internal64}
 (expr_list:REG_DEAD (reg:DI 0 0)
(expr_list:REG_CFA_RESTORE (reg:DI 65 lr)
(nil
...
(insn/f 310 268 134 8 (set (mem/c:DI (plus:DI (reg/f:DI 1 1)
(const_int 144 [0x90])) [6  S8 A8])
(reg:DI 0 0)) 579 {*movdi_internal64}
 (expr_list:REG_DEAD (reg:DI 0 0)
(expr_list:REG_CFA_OFFSET (set (mem/c:DI (plus:DI (reg/f:DI 1 1)
(const_int 144 [0x90])) [6  S8 A8])
(reg:DI 65 lr))
(nil

and sched swaps them (when compiling for power6, it tries to put memory
stores together, so insn 310 is moved up past 300 to go together with
some other store).  But the REG_CFA_RESTORE and REG_CFA_OFFSET cannot be
swapped (they both say where the orig value of LR now lives).


How are these two insns generated, and how does this differ from a 
normal prologue? Can you post the entire dump (maybe to bugzilla) so we 
can verify whether the code generation makes sense?



Bernd

Re: [patch,committed] Work around problem in gen-pass-instances.awk

[Jakub Jelinek]

On Wed, Oct 26, 2016 at 11:54:36AM +0200, Georg-Johann Lay wrote:
> gen-pass-instances.awk is sensitive to the order in which directives are
> written down, e.g. in target-pass.def: If a pass that runs first is added
> first, then the last pass is skipped and not added to pass-instances.def.
> 
> Work around is to add the 2nd pass before adding the 1st pass...
> 
> http://gcc.gnu.org/r241547
> 
> No so obvious, but committed anyway...

We shouldn't be working around bugs, but fixing them.

Here is a fix (so far tested only with running
for i in alpha avr i386 sparc aarch64; do 
  awk -f ./gen-pass-instances.awk.jj passes.def config/$i/${i}-passes.def > 
/tmp/1
  awk -f ./gen-pass-instances.awk passes.def config/$i/${i}-passes.def > /tmp/2
  diff -up /tmp/1 /tmp/2 # and diff -upb
done
), for avr for both avr-passes.def before your workaround and after it.
Except for the desirable whitespace changes, the only change is in the
pre-workaround avr-passes.def having the same output as after-workaround
(except for the comments at the end of file).

The fix for the avr issue is just the first hunk, the first part of the
second hunk attempts to deal with
NEXT_PASS ( avr_pass_casesi, 1);
instead of the desirable
NEXT_PASS (avr_pass_casesi, 1);
(all arguments have the whitespace they have in *.def before them (after ,
or ( characters).  So the first part of the second hunk strips away
whitespace, so that one doesn't need to type
INSERT_PASS_BEFORE (pass_free_cfg, 1,avr_pass_casesi);
and the second part of the second hunk and third hunk deal with similar
issue for the optional argument, we used to emit
NEXT_PASS_WITH_ARG (pass_dominator, 1,  false /* may_peel_loop_headers_p */);
rather than
NEXT_PASS_WITH_ARG (pass_dominator, 1, false /* may_peel_loop_headers_p */);
because the space from
NEXT_PASS (pass_dominator, false /* may_peel_loop_headers_p */);
(in between , and false) is already there and we add another one.

Ok for trunk if it passes bootstrap/regtest (though, as it doesn't change
anything but whitespace on x86_64, it shouldn't make a difference)?

2016-10-26  Jakub Jelinek  

* gen-pass-instances.awk (adjust_linenos): INcrement pass_lines[p]
by increment rather than double it.
(insert_remove_pass): Strip leading whitespace from args[3].  Don't
emit a space before args[4].
(END): Don't emit a space before with_arg.

--- gcc/gen-pass-instances.awk.jj   2016-10-10 10:41:32.0 +0200
+++ gcc/gen-pass-instances.awk  2016-10-26 12:30:20.637310242 +0200
@@ -90,7 +90,7 @@ function adjust_linenos(above, increment
 {
   for (p in pass_lines)
 if (pass_lines[p] >= above)
-  pass_lines[p] += pass_lines[p];
+  pass_lines[p] += increment;
   if (increment > 0)
 for (i = lineno - 1; i >= above; i--)
   lines[i + increment] = lines[i];
@@ -100,16 +100,18 @@ function adjust_linenos(above, increment
   lineno += increment;
 }
 
-function insert_remove_pass(line, fnname)
+function insert_remove_pass(line, fnname,  arg3)
 {
   parse_line($0, fnname);
   pass_name = args[1];
   if (pass_name == "PASS")
 return 1;
   pass_num = args[2] + 0;
-  new_line = prefix "NEXT_PASS (" args[3];
+  arg3 = args[3];
+  sub(/^[ \t]*/, "", arg3);
+  new_line = prefix "NEXT_PASS (" arg3;
   if (args[4])
-new_line = new_line ", " args[4];
+new_line = new_line "," args[4];
   new_line = new_line ")" postfix;
   if (!pass_lines[pass_name, pass_num])
 {
@@ -218,7 +220,7 @@ END {
printf "NEXT_PASS";
  printf " (%s, %s", pass_name, pass_num;
  if (with_arg)
-   printf ", %s", with_arg;
+   printf ",%s", with_arg;
  printf ")%s\n", postfix;
}
   else


Jakub

Re: RFC [1/3] divmod transform v2

[Richard Biener]

On Wed, 26 Oct 2016, Prathamesh Kulkarni wrote:

> On 25 October 2016 at 18:47, Richard Biener  wrote:
> > On Tue, 25 Oct 2016, Prathamesh Kulkarni wrote:
> >
> >> On 25 October 2016 at 16:17, Richard Biener  wrote:
> >> > On Tue, 25 Oct 2016, Prathamesh Kulkarni wrote:
> >> >
> >> >> On 25 October 2016 at 13:43, Richard Biener 
> >> >>  wrote:
> >> >> > On Sun, Oct 16, 2016 at 7:59 AM, Prathamesh Kulkarni
> >> >> >  wrote:
> >> >> >> Hi,
> >> >> >> After approval from Bernd Schmidt, I committed the patch to remove
> >> >> >> optab functions for
> >> >> >> sdivmod_optab and udivmod_optab in optabs.def, which removes the 
> >> >> >> block
> >> >> >> for divmod patch.
> >> >> >>
> >> >> >> This patch is mostly the same as previous one, except it drops
> >> >> >> targeting __udivmoddi4() because
> >> >> >> it gave undefined reference link error for calling __udivmoddi4() on
> >> >> >> aarch64-linux-gnu.
> >> >> >> It appears aarch64 has hardware insn for DImode div, so 
> >> >> >> __udivmoddi4()
> >> >> >> isn't needed for the target
> >> >> >> (it was a bug in my patch that called __udivmoddi4() even though
> >> >> >> aarch64 supported hardware div).
> >> >> >>
> >> >> >> However this makes me wonder if it's guaranteed that __udivmoddi4()
> >> >> >> will be available for a target if it doesn't have hardware div and
> >> >> >> divmod insn and doesn't have target-specific libfunc for
> >> >> >> DImode divmod ? To be conservative, the attached patch doesn't
> >> >> >> generate call to __udivmoddi4.
> >> >> >>
> >> >> >> Passes bootstrap+test on x86_64-unknown-linux.
> >> >> >> Cross-tested on arm*-*-*, aarch64*-*-*.
> >> >> >> Verified that there are no regressions with SPEC2006 on
> >> >> >> x86_64-unknown-linux-gnu.
> >> >> >> OK to commit ?
> >> >> >
> >> >> > I think the searching is still somewhat wrong - it's been some time
> >> >> > since my last look at the
> >> >> > patch so maybe I've said this already.  Please bail out early for
> >> >> > stmt_can_throw_internal (stmt),
> >> >> > otherwise the top stmt search might end up not working.  So
> >> >> >
> >> >> > +
> >> >> > +  if (top_stmt == stmt && stmt_can_throw_internal (top_stmt))
> >> >> > +return false;
> >> >> >
> >> >> > can go.
> >> >> >
> >> >> > top_stmt may end up as a TRUNC_DIV_EXPR so it's pointless to only look
> >> >> > for another
> >> >> > TRUNC_DIV_EXPR later ... you may end up without a single 
> >> >> > TRUNC_MOD_EXPR.
> >> >> > Which means you want a div_seen and a mod_seen, or simply record the 
> >> >> > top_stmt
> >> >> > code and look for the opposite in the 2nd loop.
> >> >> Um sorry I don't quite understand how we could end up without a 
> >> >> trunc_mod stmt ?
> >> >> The 2nd loop adds both trunc_div and trunc_mod to stmts vector, and
> >> >> checks if we have
> >> >> come across at least a single trunc_div stmt (and we bail out if no
> >> >> div is seen).
> >> >>
> >> >> At 2nd loop I suppose we don't need mod_seen, because stmt is
> >> >> guaranteed to be trunc_mod_expr.
> >> >> In the 2nd loop the following condition will never trigger for stmt:
> >> >>   if (stmt_can_throw_internal (use_stmt))
> >> >> continue;
> >> >> since we checked before hand if stmt could throw and chose to bail out
> >> >> in that case.
> >> >>
> >> >> and the following condition would also not trigger for stmt:
> >> >> if (!dominated_by_p (CDI_DOMINATORS, gimple_bb (use_stmt), top_bb))
> >> >>   {
> >> >> end_imm_use_stmt_traverse (_iter);
> >> >> return false;
> >> >>   }
> >> >> since gimple_bb (stmt) is always dominated by gimple_bb (top_stmt).
> >> >>
> >> >> The case where top_stmt == stmt, we wouldn't reach the above
> >> >> condition, since we have above it:
> >> >> if (top_stmt == stmt)
> >> >>   continue;
> >> >>
> >> >> So IIUC, top_stmt and stmt would always get added to stmts vector.
> >> >> Am I missing something ?
> >> >
> >> > Ah, indeed.  Maybe add a comment then, it wasn't really obvious ;)
> >> >
> >> > Please still move the stmt_can_throw_internal (stmt) check up.
> >> Sure, I will move that up and do the other suggested changes.
> >>
> >> I was wondering if this condition in 2nd loop is too restrictive ?
> >> if (!dominated_by_p (CDI_DOMINATORS, gimple_bb (use_stmt), top_bb))
> >>   {
> >> end_imm_use_stmt_traverse (_iter);
> >> return false;
> >>   }
> >>
> >> Should we rather "continue" in this case by not adding use_stmt to
> >> stmts vector rather than dropping
> >> the transform all-together if gimple_bb (use_stmt) is not dominated by
> >> gimple_bb (top_stmt) ?
> >
> > Ah, yes - didn't spot that.
> Hi,
> Is this version OK ?

Yes.

Thanks,
Richard.

[PATCH][GIMPLE FE] Guard dump changes with TDF_GIMPLE (-gimple)

[Richard Biener]

This adds a dump modifier, -gimple (TDF_GIMPLE) and guards the dumping
changes with it (in the case of dump_function_header simply not calling 
it).  It also adjusts label dumping in another place (when dumping
switch statements which btw do not yet parse correctly it seems).

Tested on x86_64-unknown-linux-gnu, will commit after bootstrap.

Richard.

2016-10-26  Richard Biener  

* dumpfile.h (TDF_GIMPLE): Add.
* dumpfile.c (dump_options): Add gimple.
* gimple-pretty-print.c: Guard changes with flags & TDF_GIMPLE.
* passes.c (pass_init_dump_file): Do not dump function header
for TDF_GIMPLE.
* tree-cfg.c (dump_function_to_file): Guard changes.
* tree-pretty-print.c (dump_decl_name): Likewise.
(dump_generic_node): Dump labels in parseable form.
(dump_function_header): Undo changes.

diff --git a/gcc/c/c-parser.c b/gcc/c/c-parser.c
index 542b83b..ad80b16 100644
--- a/gcc/c/c-parser.c
+++ b/gcc/c/c-parser.c
@@ -1467,7 +1467,7 @@ static void c_finish_oacc_routine (struct 
oacc_routine_data *, tree, bool);
  threadprivate-directive
 
GIMPLE:
- 
+
gimple-function-definition:
  declaration-specifiers[opt] __GIMPLE (gimple-pass-list) declarator
declaration-list[opt] compound-statement  */
diff --git a/gcc/c/gimple-parser.c b/gcc/c/gimple-parser.c
index c19f417..a1e8988 100644
--- a/gcc/c/gimple-parser.c
+++ b/gcc/c/gimple-parser.c
@@ -230,7 +230,7 @@ c_parser_gimple_compound_statement (c_parser *parser, 
gimple_seq *seq)
}
 }
   c_parser_consume_token (parser);
-  return return_p; 
+  return return_p;
 }
 
 /* Parse a gimple expression.
diff --git a/gcc/cgraphunit.c b/gcc/cgraphunit.c
index b1812b2..e315a77 100644
--- a/gcc/cgraphunit.c
+++ b/gcc/cgraphunit.c
@@ -2052,7 +2052,6 @@ cgraph_node::expand (void)
 
   /* Make sure that BE didn't give up on compiling.  */
   gcc_assert (TREE_ASM_WRITTEN (decl));
-
   if (cfun)
 pop_cfun ();
 
diff --git a/gcc/dumpfile.c b/gcc/dumpfile.c
index 74522a6..e9483bc 100644
--- a/gcc/dumpfile.c
+++ b/gcc/dumpfile.c
@@ -108,13 +108,15 @@ static const struct dump_option_value_info dump_options[] 
=
   {"nouid", TDF_NOUID},
   {"enumerate_locals", TDF_ENUMERATE_LOCALS},
   {"scev", TDF_SCEV},
+  {"gimple", TDF_GIMPLE},
   {"optimized", MSG_OPTIMIZED_LOCATIONS},
   {"missed", MSG_MISSED_OPTIMIZATION},
   {"note", MSG_NOTE},
   {"optall", MSG_ALL},
   {"all", ~(TDF_RAW | TDF_SLIM | TDF_LINENO | TDF_TREE | TDF_RTL | TDF_IPA
| TDF_STMTADDR | TDF_GRAPH | TDF_DIAGNOSTIC | TDF_VERBOSE
-   | TDF_RHS_ONLY | TDF_NOUID | TDF_ENUMERATE_LOCALS | TDF_SCEV)},
+   | TDF_RHS_ONLY | TDF_NOUID | TDF_ENUMERATE_LOCALS | TDF_SCEV
+   | TDF_GIMPLE)},
   {NULL, 0}
 };
 
diff --git a/gcc/dumpfile.h b/gcc/dumpfile.h
index 3f08b16..b7d70f2 100644
--- a/gcc/dumpfile.h
+++ b/gcc/dumpfile.h
@@ -82,9 +82,10 @@ enum tree_dump_index
 #define TDF_CSELIB (1 << 23)   /* Dump cselib details.  */
 #define TDF_SCEV   (1 << 24)   /* Dump SCEV details.  */
 #define TDF_COMMENT(1 << 25)   /* Dump lines with prefix ";;"  */
-#define MSG_OPTIMIZED_LOCATIONS  (1 << 26)  /* -fopt-info optimized sources */
-#define MSG_MISSED_OPTIMIZATION  (1 << 27)  /* missed opportunities */
-#define MSG_NOTE (1 << 28)  /* general optimization info */
+#define TDF_GIMPLE (1 << 26)   /* Dump in GIMPLE FE syntax  */
+#define MSG_OPTIMIZED_LOCATIONS  (1 << 27)  /* -fopt-info optimized sources */
+#define MSG_MISSED_OPTIMIZATION  (1 << 28)  /* missed opportunities */
+#define MSG_NOTE (1 << 29)  /* general optimization info */
 #define MSG_ALL (MSG_OPTIMIZED_LOCATIONS | MSG_MISSED_OPTIMIZATION \
  | MSG_NOTE)
 
diff --git a/gcc/gimple-pretty-print.c b/gcc/gimple-pretty-print.c
index 66cec25..9914adf 100644
--- a/gcc/gimple-pretty-print.c
+++ b/gcc/gimple-pretty-print.c
@@ -887,7 +887,10 @@ dump_gimple_switch (pretty_printer *buffer, gswitch *gs, 
int spc,
 {
   pp_string (buffer, "switch (");
   dump_generic_node (buffer, gimple_switch_index (gs), spc, flags, true);
-  pp_string (buffer, ") {");
+  if (flags & TDF_GIMPLE)
+   pp_string (buffer, ") {");
+  else
+   pp_string (buffer, ") <");
 }
 
   for (i = 0; i < gimple_switch_num_labels (gs); i++)
@@ -898,9 +901,17 @@ dump_gimple_switch (pretty_printer *buffer, gswitch *gs, 
int spc,
   pp_space (buffer);
   dump_generic_node (buffer, CASE_LABEL (case_label), spc, flags, false);
   if (i < gimple_switch_num_labels (gs) - 1)
-pp_string (buffer, "; ");
+   {
+ if (flags & TDF_GIMPLE)
+   pp_string (buffer, "; ");
+ else
+   pp_string (buffer, ", ");
+   }
 }
-  pp_string (buffer, "}");
+  if (flags & TDF_GIMPLE)
+pp_right_brace (buffer);
+  else
+pp_greater (buffer);
 }
 
 
@@ -956,11 +967,18 @@ dump_gimple_label 

Re: Patch, Split powerpc -mfloat128 into 2 parts

[Richard Sandiford]

Hi Mike,

Sorry if this has already been asked, but:

Michael Meissner  writes:
> +  else if (TARGET_FLOAT128_TYPE)
>  {
> -  /* All types must be nonzero, or self-test barfs during bootstrap.  */
> -  ieee128_float_type_node = long_double_type_node;
> -  ibm128_float_type_node = long_double_type_node;
> +  ieee128_float_type_node = make_node (REAL_TYPE);
> +  TYPE_PRECISION (ibm128_float_type_node) = 128;
 ^^
> +  layout_type (ieee128_float_type_node);
> +  SET_TYPE_MODE (ieee128_float_type_node, KFmode);

is this deliberate?  It looks like it might be a typo for ieee128.

Thanks,
Richard