Re: [PATCH] combine ignoring a check

[Segher Boessenkool]

On Tue, Jan 10, 2017 at 09:12:38AM -0500, Nathan Sidwell wrote:
> Segher commented on IRC that a single loop would be slower.  I disagree. 

Slower *and less readable*, which is the main point.  Oh well.

> -  /* Make sure this PARALLEL is not an asm.  We do not allow combining
> +  Neither can this PARALLEL be not an asm.  We do not allow combining

Delete the first "not" here please.  Okay for trunk with that change.
Thanks for the patch!


Segher

Re: [PATCH][GIMPLE FE] Add parsing of MEM_REFs

[Joseph Myers]

On Wed, 11 Jan 2017, Richard Biener wrote:

> As you can see I adjusted dumping of pointer constants (we can't
> parse the B suffix and large unsigned numbers get a warning so
> add 'U').  There's the general issue that we dump
> 
>   short x;
>   x = 1;
> 
> and then lex the '1' as type int and there's no suffixes for integer
> types smaller than int which means we can't write those constants
> type correct :/  Suggestions welcome (currently we ICE with type
> mismatches in those cases, we can avoid that by auto-fixing during
> parsing but I'd like to be explicit somehow).

You could always dump as ((short) 1); that's valid C.

-- 
Joseph S. Myers
jos...@codesourcery.com

Re: [PATCH, rs6000] Fix PR79044 (ICE in swap optimization)

[Segher Boessenkool]

On Tue, Jan 10, 2017 at 02:18:38PM -0600, Bill Schmidt wrote:
> PR79044 reports a situation where swap optimization ICEs in GCC 6 and in 
> trunk.  The
> problem is that swap optimization doesn't properly recognize that 
> element-reversing
> loads and stores (e.g., lxvw4x) cannot be treated as "swappable" 
> instructions.  These
> arise from the __builtin_vec_xl and __builtin_vec_xst interfaces that were 
> added in 
> GCC 6.  The surrounding code is slightly different, so the fix is slightly 
> different
> for the two releases.
> 
> The fix is obvious, and bootstraps on powerpc64le-unknown-linux-gnu with no 
> regressions.
> Are these patches ok for trunk and GCC 6, respectively?

Okay for both.  Is this needed for GCC 5 as well?

Thanks,


Segher

Re: [PATCH, gcc, wwwdocs] Document upcoming Qualcomm Falkor processor support

[Andrew Pinski]

On Wed, Jan 11, 2017 at 8:29 AM, Richard Earnshaw (lists)
 wrote:
> On 06/01/17 12:11, Siddhesh Poyarekar wrote:
>> Hi,
>>
>> This patch documents the newly added flag in gcc 7 for the upcoming
>> Qualcomm Falkor processor core.
>>
>> Siddhesh
>>
>> Index: htdocs/gcc-7/changes.html
>> ===
>> RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-7/changes.html,v
>> retrieving revision 1.33
>> diff -u -r1.33 changes.html
>> --- htdocs/gcc-7/changes.html 3 Jan 2017 10:55:03 -   1.33
>> +++ htdocs/gcc-7/changes.html 6 Jan 2017 12:09:53 -
>> @@ -390,7 +390,8 @@
>>   
>> Support has been added for the following processors
>> (GCC identifiers in parentheses): ARM Cortex-A73
>> -   (cortex-a73) and Broadcom Vulcan (vulcan).
>> +   (cortex-a73), Broadcom Vulcan (vulcan) and
>> +   Qualcomm Falkor (falkor).
>> The GCC identifiers can be used
>> as arguments to the -mcpu or -mtune 
>> options,
>> for example: -mcpu=cortex-a73 or
>>
>
> Thanks.  The file had changed again, but I've merged this in.

Yes that was my fault, I was just adding the Cavium ThunderX SOCs that
are now supported by GCC.

Thanks,
Andrew

>
> R.

RE: Make MIPS soft-fp preserve NaN payloads for NAN2008

[Joseph Myers]

On Wed, 11 Jan 2017, Maciej W. Rozycki wrote:

> > > In any case, the soft-fp change is relevant in the hard-float case as
> > > well, to make software TFmode behave consistently with hardware SFmode
> > > and DFmode regarding NaN payload preservation.
> 
>  Is mixing TFmode, DFmode and SFmode operations with the two latters 
> handled in hardware and the former deferred to soft-fp a supported 
> configuration?  Do we have any MIPS ABI which provides for using all these 

Yes.

> data types?  AFAIK all MIPS/Linux ABIs use DFmode for `long double' and 

n32 and n64 use TFmode (unconditionally; unlike on some architectures, 
there is no -mlong-double-64 option).  From GCC 4.9 onwards this uses 
soft-fp rather than fp-bit, with integration with hardware exceptions and 
rounding modes.

-- 
Joseph S. Myers
jos...@codesourcery.com

New Port for RISC-V

[Palmer Dabbelt]

We'd like to submit for inclusion in GCC a port for the RISC-V architecture.
The port suffices to build a substantial body of software (including Linux and
some 2,000 Fedora packages) and passes most of the gcc and g++ test suites; so,
while it is doubtlessly not complete, we think it is far enough along to start
the upstreaming process.  It is our understanding that it is OK to submit this
port during stage 3 because it does not touch any shared code.  Our binutils
port has already been accepted for the 2.28 release, and we plan on submitting
glibc and Linux patch sets soon.

This port targets Version 2.0 of the RV32I and RV64I base user ISAs, and the
five standard extensions M, A, F, D, and C, all of which are frozen and will
not change over time.  The RISC-V community and the 50-some member companies of
the RISC-V Foundation are quite eager to have a single, standard GCC port.  We
thank you in advance for your help in this process and for your feedback on the
software contribution itself.

These patches build on top of cac3398e5f378549d84bc2ebb6af97cfd0189b25, the
latest commit in the GCC git mirror as of last night.

Andrew and I will volunteer to maintain this port if it's OK with everyone.
Our understanding is that the GCC steering committee decides this, and this is
the correct place to contact them.

We'd like to thank the various members of the RISC-V software community who
have helped us with the port.  Specifically we'd like to thank Kito Cheng for
his work getting the GCC test suite running (and running correctly).

Thanks!

[PATCH 1/6] RISC-V Port: gcc/config/riscv/riscv.c
[PATCH 2/6] RISC-V Port: gcc
[PATCH 3/6] RISC-V Port: libgcc
[PATCH 4/6] RISC-V Port: libsanitizer
[PATCH 5/6] RISC-V Port: libatomic
[PATCH 6/6] RISC-V Port: gcc/testsuite

[PATCH 6/6] RISC-V Port: gcc/testsuite

[Palmer Dabbelt]

From: Kito Cheng 

---
 gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C| 2 +-
 gcc/testsuite/gcc.c-torture/execute/20101011-1.c  | 3 +++
 gcc/testsuite/gcc.dg/20020312-2.c | 2 ++
 gcc/testsuite/gcc.dg/builtin-apply2.c | 1 +
 gcc/testsuite/gcc.dg/ifcvt-4.c| 2 +-
 gcc/testsuite/gcc.dg/loop-8.c | 2 +-
 gcc/testsuite/gcc.dg/sibcall-9.c  | 2 ++
 gcc/testsuite/gcc.dg/stack-usage-1.c  | 2 ++
 gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c | 2 +-
 gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c| 2 +-
 gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c | 2 +-
 gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c | 2 +-
 gcc/testsuite/lib/target-supports.exp | 1 +
 13 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C 
b/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C
index 80a571a..2e0ef68 100644
--- a/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C
+++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C
@@ -2,7 +2,7 @@
 // { dg-do compile { target c++11 } }
 // { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-* 
lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* nios2-*-* powerpc*-*-* 
rs6000*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } }
 // { dg-final { scan-assembler "\\.rdata" { target mips*-*-* } } }
-// { dg-final { scan-assembler "rodata" { target { { *-*-linux-gnu *-*-gnu* 
*-*-elf } && { ! mips*-*-* } } } } }
+// { dg-final { scan-assembler "rodata" { target { { *-*-linux-gnu *-*-gnu* 
*-*-elf } && { ! { mips*-*-* riscv*-*-* } } } } } }
 
 struct Data
 {
diff --git a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c 
b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
index 744763f..899a401 100644
--- a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
+++ b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
@@ -6,6 +6,9 @@
 #elif defined (__powerpc__) || defined (__PPC__) || defined (__ppc__) || 
defined (__POWERPC__) || defined (__ppc)
   /* On PPC division by zero does not trap.  */
 # define DO_TEST 0
+#elif defined (__riscv)
+  /* On RISC-V division by zero does not trap.  */
+# define DO_TEST 0
 #elif defined (__SPU__)
   /* On SPU division by zero does not trap.  */
 # define DO_TEST 0
diff --git a/gcc/testsuite/gcc.dg/20020312-2.c 
b/gcc/testsuite/gcc.dg/20020312-2.c
index 5fce50d..f5929e0 100644
--- a/gcc/testsuite/gcc.dg/20020312-2.c
+++ b/gcc/testsuite/gcc.dg/20020312-2.c
@@ -67,6 +67,8 @@ extern void abort (void);
 # else
 #  define PIC_REG  "30"
 # endif
+#elif defined(__riscv)
+/* No pic register.  */
 #elif defined(__RX__)
 /* No pic register.  */
 #elif defined(__s390__)
diff --git a/gcc/testsuite/gcc.dg/builtin-apply2.c 
b/gcc/testsuite/gcc.dg/builtin-apply2.c
index b6cbe39..ad61d3b 100644
--- a/gcc/testsuite/gcc.dg/builtin-apply2.c
+++ b/gcc/testsuite/gcc.dg/builtin-apply2.c
@@ -1,6 +1,7 @@
 /* { dg-do run } */
 /* { dg-require-effective-target untyped_assembly } */
 /* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args 
in registers." { "avr-*-* nds32*-*-*" } { "*" } { "" } } */
+/* { dg-skip-if "Variadic funcs use different argument passing from normal 
funcs." { "riscv*-*-*" } { "*" } { "" } } */
 /* { dg-skip-if "Variadic funcs use Base AAPCS.  Normal funcs use VFP 
variant." { arm*-*-* && arm_hf_eabi } { "*" } { "" } } */
 
 /* PR target/12503 */
diff --git a/gcc/testsuite/gcc.dg/ifcvt-4.c b/gcc/testsuite/gcc.dg/ifcvt-4.c
index 0d1671c..466ad15 100644
--- a/gcc/testsuite/gcc.dg/ifcvt-4.c
+++ b/gcc/testsuite/gcc.dg/ifcvt-4.c
@@ -1,6 +1,6 @@
 /* { dg-options "-fdump-rtl-ce1 -O2 --param max-rtl-if-conversion-insns=3 
--param max-rtl-if-conversion-unpredictable-cost=100" } */
 /* { dg-additional-options "-misel" { target { powerpc*-*-* } } } */
-/* { dg-skip-if "Multiple set if-conversion not guaranteed on all subtargets" 
{ "arm*-*-* hppa*64*-*-* visium-*-*" } }  */
+/* { dg-skip-if "Multiple set if-conversion not guaranteed on all subtargets" 
{ "arm*-*-* hppa*64*-*-* visium-*-*" riscv*-*-* } }  */
 
 typedef int word __attribute__((mode(word)));
 
diff --git a/gcc/testsuite/gcc.dg/loop-8.c b/gcc/testsuite/gcc.dg/loop-8.c
index 8a4b209..fd4fa62 100644
--- a/gcc/testsuite/gcc.dg/loop-8.c
+++ b/gcc/testsuite/gcc.dg/loop-8.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-O1 -fdump-rtl-loop2_invariant" } */
-/* { dg-skip-if "unexpected IV" { "hppa*-*-* mips*-*-* visium-*-*" } { "*" } { 
"" } } */
+/* { dg-skip-if "unexpected IV" { "hppa*-*-* mips*-*-* visium-*-* riscv*-*-*" 
} { "*" } { "" } } */
 
 void
 f (int *a, int *b)
diff --git a/gcc/testsuite/gcc.dg/sibcall-9.c b/gcc/testsuite/gcc.dg/sibcall-9.c
index 34e7053..8e30952 100644
--- a/gcc/testsuite/gcc.dg/sibcall-9.c
+++ b/gcc/testsuite/gcc.dg/sibcall-9.c
@@ -8,6 +8,8 @@
 /* { dg-do run { xfail { { cris-*-* crisv32-*-* h8300

[PATCH 5/6] RISC-V Port: libatomic

[Palmer Dabbelt]

From: Andrew Waterman 

---
 libatomic/configure.tgt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/libatomic/configure.tgt b/libatomic/configure.tgt
index 6d77c94..b8af3ab 100644
--- a/libatomic/configure.tgt
+++ b/libatomic/configure.tgt
@@ -37,6 +37,7 @@ case "${target_cpu}" in
ARCH=alpha
;;
   rs6000 | powerpc*)   ARCH=powerpc ;;
+  riscv*)  ARCH=riscv ;;
   sh*) ARCH=sh ;;
 
   arm*)
-- 
2.10.2

[PATCH 3/6] RISC-V Port: libgcc

[Palmer Dabbelt]

From: Andrew Waterman 

---
 libgcc/config.host |  12 ++
 libgcc/config/riscv/atomic.c   | 111 +
 libgcc/config/riscv/crti.S |   1 +
 libgcc/config/riscv/crtn.S |   1 +
 libgcc/config/riscv/div.S  | 146 ++
 libgcc/config/riscv/linux-unwind.h |  89 ++
 libgcc/config/riscv/muldi3.S   |  46 +++
 libgcc/config/riscv/multi3.S   |  81 
 libgcc/config/riscv/save-restore.S | 245 +
 libgcc/config/riscv/sfp-machine.h  | 156 +++
 libgcc/config/riscv/t-elf  |   6 +
 libgcc/config/riscv/t-elf32|   1 +
 libgcc/config/riscv/t-elf64|   1 +
 libgcc/config/riscv/t-softfp32 |   3 +
 libgcc/config/riscv/t-softfp64 |   4 +
 15 files changed, 903 insertions(+)
 create mode 100644 libgcc/config/riscv/atomic.c
 create mode 100644 libgcc/config/riscv/crti.S
 create mode 100644 libgcc/config/riscv/crtn.S
 create mode 100644 libgcc/config/riscv/div.S
 create mode 100644 libgcc/config/riscv/linux-unwind.h
 create mode 100644 libgcc/config/riscv/muldi3.S
 create mode 100644 libgcc/config/riscv/multi3.S
 create mode 100644 libgcc/config/riscv/save-restore.S
 create mode 100644 libgcc/config/riscv/sfp-machine.h
 create mode 100644 libgcc/config/riscv/t-elf
 create mode 100644 libgcc/config/riscv/t-elf32
 create mode 100644 libgcc/config/riscv/t-elf64
 create mode 100644 libgcc/config/riscv/t-softfp32
 create mode 100644 libgcc/config/riscv/t-softfp64

diff --git a/libgcc/config.host b/libgcc/config.host
index 6f2e458..bb6d5370e 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -167,6 +167,9 @@ powerpc*-*-*)
;;
 rs6000*-*-*)
;;
+riscv*)
+   cpu_type=riscv
+   ;;
 sparc64*-*-*)
cpu_type=sparc
;;
@@ -1091,6 +1094,15 @@ powerpcle-*-eabi*)
tmake_file="${tmake_file} rs6000/t-ppccomm rs6000/t-crtstuff 
t-crtstuff-pic t-fdpbit"
extra_parts="$extra_parts crtbegin.o crtend.o crtbeginS.o crtendS.o 
crtbeginT.o ecrti.o ecrtn.o ncrti.o ncrtn.o"
;;
+riscv*-*-linux*)
+   tmake_file="${tmake_file} t-softfp-sfdf riscv/t-softfp${host_address} 
t-softfp riscv/t-elf riscv/t-elf${host_address}"
+   extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o crtendS.o 
crtbeginT.o"
+   md_unwind_header=riscv/linux-unwind.h
+   ;;
+riscv*-*-*)
+   tmake_file="${tmake_file} t-softfp-sfdf riscv/t-softfp${host_address} 
t-softfp riscv/t-elf riscv/t-elf${host_address}"
+   extra_parts="$extra_parts crtbegin.o crtend.o crti.o crtn.o"
+   ;;
 rs6000-ibm-aix4.[3456789]* | powerpc-ibm-aix4.[3456789]*)
md_unwind_header=rs6000/aix-unwind.h
tmake_file="t-fdpbit rs6000/t-ppc64-fp rs6000/t-slibgcc-aix 
rs6000/t-ibm-ldouble"
diff --git a/libgcc/config/riscv/atomic.c b/libgcc/config/riscv/atomic.c
new file mode 100644
index 000..448b0e5
--- /dev/null
+++ b/libgcc/config/riscv/atomic.c
@@ -0,0 +1,111 @@
+/* Legacy sub-word atomics for RISC-V.
+ 
+   Copyright (C) 2016-2017 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+.  */
+
+#ifdef __riscv_atomic
+
+#include 
+
+#define INVERT "not %[tmp1], %[tmp1]\n\t"
+#define DONT_INVERT""
+
+#define GENERATE_FETCH_AND_OP(type, size, opname, insn, invert, cop)   \
+  type __sync_fetch_and_ ## opname ## _ ## size (type *p, type v)  \
+  {\
+unsigned long aligned_addr = ((unsigned long) p) & ~3UL;   \
+int shift = (((unsigned long) p) & 3) * 8; \
+unsigned mask = ((1U << ((sizeof v) * 8)) - 1) << shift;   \
+unsigned old, tmp1, tmp2;  \
+   \
+asm volatile ("1:\n\t" \
+ "lr.w.aq %[old], %[mem]\n\t"  \
+ #insn " %[tmp1], %[old], %[value]\n\t"\
+ invert

[PATCH 4/6] RISC-V Port: libsanitizer

[Palmer Dabbelt]

---
 libsanitizer/sanitizer_common/sanitizer_linux.cc | 5 +
 libsanitizer/sanitizer_common/sanitizer_platform.h   | 4 ++--
 libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc | 2 +-
 libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h  | 7 +--
 4 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/libsanitizer/sanitizer_common/sanitizer_linux.cc 
b/libsanitizer/sanitizer_common/sanitizer_linux.cc
index 806fcd5..4de9d16 100644
--- a/libsanitizer/sanitizer_common/sanitizer_linux.cc
+++ b/libsanitizer/sanitizer_common/sanitizer_linux.cc
@@ -1369,6 +1369,11 @@ void GetPcSpBp(void *context, uptr *pc, uptr *sp, uptr 
*bp) {
   *pc = ucontext->uc_mcontext.pc;
   *bp = ucontext->uc_mcontext.gregs[30];
   *sp = ucontext->uc_mcontext.gregs[29];
+#elif defined(__riscv)
+  ucontext_t *ucontext = (ucontext_t*)context;
+  *pc = ucontext->uc_mcontext.gregs[REG_PC];
+  *bp = ucontext->uc_mcontext.gregs[REG_S0];
+  *sp = ucontext->uc_mcontext.gregs[REG_SP];
 #elif defined(__s390__)
   ucontext_t *ucontext = (ucontext_t*)context;
 # if defined(__s390x__)
diff --git a/libsanitizer/sanitizer_common/sanitizer_platform.h 
b/libsanitizer/sanitizer_common/sanitizer_platform.h
index 428709d..5519bc6 100644
--- a/libsanitizer/sanitizer_common/sanitizer_platform.h
+++ b/libsanitizer/sanitizer_common/sanitizer_platform.h
@@ -188,9 +188,9 @@
 
 // The AArch64 linux port uses the canonical syscall set as mandated by
 // the upstream linux community for all new ports. Other ports may still
-// use legacy syscalls.
+// use legacy syscalls.  The RISC-V port also does this.
 #ifndef SANITIZER_USES_CANONICAL_LINUX_SYSCALLS
-# if defined(__aarch64__) && SANITIZER_LINUX
+# if (defined(__aarch64__) || defined(__riscv)) && SANITIZER_LINUX
 # define SANITIZER_USES_CANONICAL_LINUX_SYSCALLS 1
 # else
 # define SANITIZER_USES_CANONICAL_LINUX_SYSCALLS 0
diff --git a/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc 
b/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
index 23a0148..11a3850 100644
--- a/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
+++ b/libsanitizer/sanitizer_common/sanitizer_platform_limits_linux.cc
@@ -64,7 +64,7 @@ namespace __sanitizer {
 
 #if !defined(__powerpc64__) && !defined(__x86_64__) && !defined(__aarch64__)\
 && !defined(__mips__) && !defined(__s390__)\
-&& !defined(__sparc__)
+&& !defined(__sparc__) && && !defined(__riscv)
 COMPILER_CHECK(struct___old_kernel_stat_sz == sizeof(struct 
__old_kernel_stat));
 #endif
 
diff --git a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h 
b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
index c139322..dddcef2 100644
--- a/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
+++ b/libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.h
@@ -83,6 +83,9 @@ namespace __sanitizer {
  SANITIZER_ANDROID ? FIRST_32_SECOND_64(104, 128) :
  FIRST_32_SECOND_64(144, 216);
   const unsigned struct_kernel_stat64_sz = 104;
+#elif defined(__riscv)
+  const unsigned struct_kernel_stat_sz = 128;
+  const unsigned struct_kernel_stat64_sz = 128;
 #elif defined(__s390__) && !defined(__s390x__)
   const unsigned struct_kernel_stat_sz = 64;
   const unsigned struct_kernel_stat64_sz = 104;
@@ -117,7 +120,7 @@ namespace __sanitizer {
 
 #if SANITIZER_LINUX || SANITIZER_FREEBSD
 
-#if defined(__powerpc64__) || defined(__s390__)
+#if defined(__powerpc64__) || defined(__riscv) || defined(__s390__)
   const unsigned struct___old_kernel_stat_sz = 0;
 #elif !defined(__sparc__)
   const unsigned struct___old_kernel_stat_sz = 32;
@@ -540,7 +543,7 @@ namespace __sanitizer {
   typedef long __sanitizer___kernel_off_t;
 #endif
 
-#if defined(__powerpc__) || defined(__mips__)
+#if defined(__powerpc__) || defined(__mips__) || defined(__riscv)
   typedef unsigned int __sanitizer___kernel_old_uid_t;
   typedef unsigned int __sanitizer___kernel_old_gid_t;
 #else
-- 
2.10.2

[PATCH 1/6] RISC-V Port: gcc/config/riscv/riscv.c

[Palmer Dabbelt]

This is split from the rest of the gcc submission so I can fit this
patch on the mailing list's 200KiB limit.
---
 gcc/config/riscv/riscv.c | 4157 ++
 1 file changed, 4157 insertions(+)
 create mode 100644 gcc/config/riscv/riscv.c

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
new file mode 100644
index 000..f4911d3
--- /dev/null
+++ b/gcc/config/riscv/riscv.c
@@ -0,0 +1,4157 @@
+/* Subroutines used for code generation for RISC-V.
+   Copyright (C) 2011-2017 Free Software Foundation, Inc.
+   Contributed by Andrew Waterman (and...@sifive.com).
+   Based on MIPS target for GNU compiler.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-attr.h"
+#include "recog.h"
+#include "output.h"
+#include "hash-set.h"
+#include "machmode.h"
+#include "vec.h"
+#include "double-int.h"
+#include "input.h"
+#include "alias.h"
+#include "symtab.h"
+#include "wide-int.h"
+#include "inchash.h"
+#include "tree.h"
+#include "fold-const.h"
+#include "varasm.h"
+#include "stringpool.h"
+#include "stor-layout.h"
+#include "calls.h"
+#include "function.h"
+#include "hashtab.h"
+#include "flags.h"
+#include "statistics.h"
+#include "real.h"
+#include "fixed-value.h"
+#include "expmed.h"
+#include "dojump.h"
+#include "explow.h"
+#include "memmodel.h"
+#include "emit-rtl.h"
+#include "stmt.h"
+#include "expr.h"
+#include "insn-codes.h"
+#include "optabs.h"
+#include "libfuncs.h"
+#include "reload.h"
+#include "tm_p.h"
+#include "ggc.h"
+#include "gstab.h"
+#include "hash-table.h"
+#include "debug.h"
+#include "target.h"
+#include "target-def.h"
+#include "common/common-target.h"
+#include "langhooks.h"
+#include "dominance.h"
+#include "cfg.h"
+#include "cfgrtl.h"
+#include "cfganal.h"
+#include "lcm.h"
+#include "cfgbuild.h"
+#include "cfgcleanup.h"
+#include "predict.h"
+#include "basic-block.h"
+#include "bitmap.h"
+#include "regset.h"
+#include "df.h"
+#include "sched-int.h"
+#include "tree-ssa-alias.h"
+#include "internal-fn.h"
+#include "gimple-fold.h"
+#include "tree-eh.h"
+#include "gimple-expr.h"
+#include "is-a.h"
+#include "gimple.h"
+#include "gimplify.h"
+#include "diagnostic.h"
+#include "target-globals.h"
+#include "opts.h"
+#include "tree-pass.h"
+#include "context.h"
+#include "hash-map.h"
+#include "plugin-api.h"
+#include "ipa-ref.h"
+#include "cgraph.h"
+#include "builtins.h"
+#include "rtl-iter.h"
+#include 
+
+/* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF.  */
+#define UNSPEC_ADDRESS_P(X)\
+  (GET_CODE (X) == UNSPEC  \
+   && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST  \
+   && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
+
+/* Extract the symbol or label from UNSPEC wrapper X.  */
+#define UNSPEC_ADDRESS(X) \
+  XVECEXP (X, 0, 0)
+
+/* Extract the symbol type from UNSPEC wrapper X.  */
+#define UNSPEC_ADDRESS_TYPE(X) \
+  ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
+
+/* True if bit BIT is set in VALUE.  */
+#define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0)
+
+/* Classifies an address.
+
+   ADDRESS_REG
+   A natural register + offset address.  The register satisfies
+   riscv_valid_base_register_p and the offset is a const_arith_operand.
+
+   ADDRESS_LO_SUM
+   A LO_SUM rtx.  The first operand is a valid base register and
+   the second operand is a symbolic address.
+
+   ADDRESS_CONST_INT
+   A signed 16-bit constant address.
+
+   ADDRESS_SYMBOLIC:
+   A constant symbolic address.  */
+enum riscv_address_type {
+  ADDRESS_REG,
+  ADDRESS_LO_SUM,
+  ADDRESS_CONST_INT,
+  ADDRESS_SYMBOLIC
+};
+
+/* Information about a function's frame layout.  */
+struct GTY(())  riscv_frame_info {
+  /* The size of the frame in bytes.  */
+  HOST_WIDE_INT total_size;
+
+  /* Bit X is set if the function saves or restores GPR X.  */
+  unsigned int mask;
+
+  /* Likewise FPR X.  */
+  unsigned int fmask;
+
+  /* How much the GPR save/restore routines adjust sp (or 0 if unused).  */
+  unsigned save_libcall_adjustment;
+
+  /* Offsets of fixed-point and floating-point save areas from frame bottom */

[PATCH/AARCH64] Add scheduler for Thunderx2t99

[Hurugalawadi, Naveen]

Hi James,

The scheduling patch for vulcan was posted at the following link:-
https://gcc.gnu.org/ml/gcc-patches/2016-07/msg01205.html

We are working on the patch and addressed the comments for thunderx2t99.

>> I tried lowering the repeat expressions as so:
Done.

>>split off the AdvSIMD/FP model from the main pipeline
Done.

>> A change like wiring the vulcan_f0 and vulcan_f1 reservations
>> to be cpu_units of a new define_automaton "vulcan_advsimd"
Done.

>> simplifying some of the remaining large expressions
>> (vulcan_asimd_load*_mult, vulcan_asimd_load*_elts) can bring the size down
Did not understand much about this comment.
Can you please let me know about the simplification?

Please find attached the modified patch as per your suggestions and comments.
Please review the patch and let us know if its okay?

Thanks,
Naveendiff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index a7a4b33..4d39673 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -75,7 +75,7 @@ AARCH64_CORE("xgene1",  xgene1,xgene1,8A,  AARCH64_FL_FOR_ARCH8, xge
 
 /* Broadcom ('B') cores. */
 AARCH64_CORE("thunderx2t99",  thunderx2t99, cortexa57, 8_1A,  AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x42, 0x516, -1)
-AARCH64_CORE("vulcan",  vulcan, cortexa57, 8_1A,  AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x42, 0x516, -1)
+AARCH64_CORE("vulcan",  vulcan, vulcan, 8_1A,  AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x42, 0x516, -1)
 
 /* V8 big.LITTLE implementations.  */
 
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index bde4231..063559c 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -220,6 +220,7 @@
 (include "../arm/exynos-m1.md")
 (include "thunderx.md")
 (include "../arm/xgene1.md")
+(include "thunderx2t99.md")
 
 ;; ---
 ;; Jumps and other miscellaneous insns
diff --git a/gcc/config/aarch64/thunderx2t99.md b/gcc/config/aarch64/thunderx2t99.md
new file mode 100644
index 000..00d40f8
--- /dev/null
+++ b/gcc/config/aarch64/thunderx2t99.md
@@ -0,0 +1,513 @@
+;; Cavium ThunderX 2 CN99xx pipeline description
+;; Copyright (C) 2016-2017 Free Software Foundation, Inc.
+;;
+;; Contributed by Cavium, Broadcom and Mentor Embedded.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+(define_automaton "thunderx2t99, thunderx2t99_advsimd, thunderx2t99_ldst")
+(define_automaton "thunderx2t99_mult")
+
+(define_cpu_unit "thunderx2t99_i0" "thunderx2t99")
+(define_cpu_unit "thunderx2t99_i1" "thunderx2t99")
+(define_cpu_unit "thunderx2t99_i2" "thunderx2t99")
+
+(define_cpu_unit "thunderx2t99_ls0" "thunderx2t99_ldst")
+(define_cpu_unit "thunderx2t99_ls1" "thunderx2t99_ldst")
+(define_cpu_unit "thunderx2t99_sd" "thunderx2t99_ldst")
+
+; Pseudo-units for multiply pipeline.
+
+(define_cpu_unit "thunderx2t99_i1m1" "thunderx2t99_mult")
+(define_cpu_unit "thunderx2t99_i1m2" "thunderx2t99_mult")
+(define_cpu_unit "thunderx2t99_i1m3" "thunderx2t99_mult")
+
+; Pseudo-units for load delay (assuming dcache hit).
+
+(define_cpu_unit "thunderx2t99_ls0d1" "thunderx2t99_ldst")
+(define_cpu_unit "thunderx2t99_ls0d2" "thunderx2t99_ldst")
+(define_cpu_unit "thunderx2t99_ls0d3" "thunderx2t99_ldst")
+
+(define_cpu_unit "thunderx2t99_ls1d1" "thunderx2t99_ldst")
+(define_cpu_unit "thunderx2t99_ls1d2" "thunderx2t99_ldst")
+(define_cpu_unit "thunderx2t99_ls1d3" "thunderx2t99_ldst")
+
+; Make some aliases for f0/f1.
+(define_cpu_unit "thunderx2t99_f0" "thunderx2t99_advsimd")
+(define_cpu_unit "thunderx2t99_f1" "thunderx2t99_advsimd")
+
+(define_reservation "thunderx2t99_i012" "thunderx2t99_i0|thunderx2t99_i1|thunderx2t99_i2")
+(define_reservation "thunderx2t99_ls01" "thunderx2t99_ls0|thunderx2t99_ls1")
+(define_reservation "thunderx2t99_f01" "thunderx2t99_f0|thunderx2t99_f1")
+
+(define_reservation "thunderx2t99_ls_both" "thunderx2t99_ls0+thunderx2t99_ls1")
+
+; A load with delay in the ls0/ls1 pipes.
+(define_reservation "thunderx2t99_l0delay" "thunderx2t99_ls0,\
+  thunderx2t99_ls0d1,thunderx2t99_ls0d2,\
+  thunderx2t99_ls0d3")
+(define_reservation "thunderx2t99_l1delay" "thunderx2t99_ls1,\
+  thunderx2t99_ls1d1,thunderx2t99_ls1d2,\
+  thunderx2t99_ls1d3")
+(defin

Re: [RFA] [PR tree-optimization/33562] [PATCH 1/4] Byte tracking in DSE - v3

[Jeff Law]

On 01/04/2017 06:22 AM, Richard Biener wrote:



Bootstrapped and regression tested on x86_64-linux-gnu.  OK for the trunk?


New functions in sbitmap.c lack function comments.

Bah.  Sophomoric on my part.  Fixed.



bitmap_count_bits fails to guard against GCC_VERSION >= 3400 (the version
is not important, but non-GCC host compilers are).  See bitmap.c for a
fallback.
Mistake on my part.  I keep thinking we support starting the bootstrap 
process with the most recently released GCC, but we support 3.4 as well 
as other C++98/C++03 compilers.  Fixed in the next update (and tested by 
forcing the fallback method).




Both bitmap_clear_range and bitmap_set_range look rather inefficient...
(it's not likely anybody will clean this up after you)
They were, but not anymore.  Now they build a mask to deal with any 
partial clearing/setting in the first word, then a single memset for any 
whole words in the middle, then another masking operation on residuals 
in the last word.  Verified behavior by by keeping two bitmaps, one with 
the old slow approach and one with the faster implementation and 
checking for equality.  Obviously those verification bits won't be in 
the final patch.



I'd say split out the sbitmap.[ch] changes.

Sure.  That's easy enough.



+DEFPARAM(PARAM_DSE_MAX_OBJECT_SIZE,
+"dse-max-object-size",
+"Maximum size (in bytes) of objects tracked by dead store
elimination.",
+256, 0, 0)

the docs suggest that DSE doesn't handle larger stores but it does (just in
the original limited way).  Maybe "tracked bytewise" is better.

Agreed and fixed.




+static bool
+valid_ao_ref_for_dse (ao_ref *ref)
+{
+  return (ao_ref_base (ref)
+ && ref->max_size != -1
+ && (ref->offset % BITS_PER_UNIT) == 0
+ && (ref->size % BITS_PER_UNIT) == 0
+ && (ref->size / BITS_PER_UNIT) > 0);

I think the last test is better written as ref->size != -1.

Seems reasonable.  Fixed.




Btw, seeing you discount non-byte size/offset stores this somehow asks
for store-merging being done before the last DSE (it currently runs after).
Sth to keep in mind for GCC 8.
Yea, probably.  Of course it may also be the case that DSE enables store 
merging.  Worth some experimentation.





+/* Delete a dead store STMT, which is mem* call of some kind.  */

call STMT

Fixed.



+static void
+delete_dead_call (gimple *stmt)
+{
+
excess vertical space

Likewise.


..
+  if (lhs)
+{
+  tree ptr = gimple_call_arg (stmt, 0);
+  gimple *new_stmt = gimple_build_assign (lhs, ptr);
+  unlink_stmt_vdef (stmt);
+  if (gsi_replace (&gsi, new_stmt, true))
+bitmap_set_bit (need_eh_cleanup, gimple_bb (stmt)->index);

  release_ssa_name (gimple_vdef (stmt));


+  { m_live_bytes = sbitmap_alloc (PARAM_VALUE
(PARAM_DSE_MAX_OBJECT_SIZE));m_byte_tracking_enabled = false; }

formatting.

Yea. Fixed.



The DSE parts look good to me with the nits above fixed.  Just re-spin
the sbitmap.[ch] part please.

Will repost the sbitmap.c bits after retesting the series.

jeff

Re: [RFA] [PR tree-optimization/33562] [PATCH 1/4] Byte tracking in DSE - v3

[Jeff Law]

On 01/04/2017 06:23 AM, Richard Biener wrote:

On Wed, Jan 4, 2017 at 2:22 PM, Richard Biener
 wrote:

On Thu, Dec 22, 2016 at 7:26 AM, Jeff Law  wrote:

This is the first of the 4 part patchkit to address deficiencies in our DSE
implementation.

This patch addresses the P2 regression 33562 which has been a low priority
regression since gcc-4.3.  To summarize, DSE no longer has the ability to
detect an aggregate store as dead if subsequent stores are done in a
piecemeal fashion.

I originally tackled this by changing how we lower complex objects. That was
sufficient to address 33562, but was reasonably rejected.

This version attacks the problem by improving DSE to track stores to memory
at a byte level.  That allows us to determine if a series of stores
completely covers an earlier store (thus making the earlier store dead).

A useful side effect of this is we can detect when parts of a store are dead
and potentially rewrite the store.  This patch implements that for complex
object initializations.  While not strictly part of 33562, it's so closely
related that I felt it belongs as part of this patch.

This originally limited the size of the tracked memory space to 64 bytes.  I
bumped the limit after working through the CONSTRUCTOR and mem* trimming
patches.  The 256 byte limit is still fairly arbitrary and I wouldn't lose
sleep if we throttled back to 64 or 128 bytes.

Later patches in the kit will build upon this patch.  So if pieces look like
skeleton code, that's because it is.

The changes since the V2 patch are:

1. Using sbitmaps rather than bitmaps.
2. Returning a tri-state from dse_classify_store (renamed from
dse_possible_dead_store_p)
3. More efficient trim computation
4. Moving trimming code out of dse_classify_store
5. Refactoring code to delete dead calls/assignments
6. dse_optimize_stmt moves into the dse_dom_walker class

Not surprisingly, this patch has most of the changes based on prior feedback
as it includes the raw infrastructure.

Bootstrapped and regression tested on x86_64-linux-gnu.  OK for the trunk?


New functions in sbitmap.c lack function comments.

bitmap_count_bits fails to guard against GCC_VERSION >= 3400 (the version
is not important, but non-GCC host compilers are).  See bitmap.c for a
fallback.

Both bitmap_clear_range and bitmap_set_range look rather inefficient...
(it's not likely anybody will clean this up after you)

I'd say split out the sbitmap.[ch] changes.

+DEFPARAM(PARAM_DSE_MAX_OBJECT_SIZE,
+"dse-max-object-size",
+"Maximum size (in bytes) of objects tracked by dead store
elimination.",
+256, 0, 0)

the docs suggest that DSE doesn't handle larger stores but it does (just in
the original limited way).  Maybe "tracked bytewise" is better.


Oh, and new --params need documeting in invoke.texi.

Fixed.

jeff

Re: [RFA][PATCH 3/4] Trim mem* calls in DSE

[Jeff Law]

On 01/04/2017 07:04 AM, Richard Biener wrote:


Didn't see a re-post of this one so reviewing the old.
Didn't figure mem* trimming was suitable for gcc-7 as I couldn't justify 
it as a bugfix, so I didn't ping it.


I don't think it changed materially.  All your comments are still 
applicable to the version in my tree.






* tree-ssa-dse.c (need_ssa_update): New file scoped boolean.
(decrement_count): New function.
(increment_start_addr, trim_memstar_call): Likewise.
(trim_partially_dead_store): Call trim_memstar_call.
(pass_dse::execute): Initialize need_ssa_update.  If set, then
return TODO_ssa_update.

* gcc.dg/tree-ssa/ssa-dse-25.c: New test.

diff --git a/gcc/tree-ssa-dse.c b/gcc/tree-ssa-dse.c
index 1482c7f..b21b9b5 100644
--- a/gcc/tree-ssa-dse.c
+++ b/gcc/tree-ssa-dse.c
@@ -79,6 +80,10 @@ static bitmap need_eh_cleanup;
It is always safe to return FALSE.  But typically better optimziation
can be achieved by analyzing more statements.  */

+/* If trimming stores requires insertion of new statements, then we
+   will need an SSA update.  */
+static bool need_ssa_update;
+


huh?  You set this to true after inserting a POINTER_PLUS_EXPR, I don't see
how you need an SSA update for this.
I'll go back and re-investigate.  I could easily have goof'd the 
in-place update and be papering over that with the ssa update.







 static bool
 initialize_ao_ref_for_dse (gimple *stmt, ao_ref *write)
 {
@@ -309,6 +314,113 @@ trim_constructor_store (bitmap orig, bitmap live,
gimple *stmt)
 }
 }

+/* STMT is a memcpy, memmove or memset.  Decrement the number of bytes
+   copied/set by DECREMENT.  */
+static void
+decrement_count (gimple *stmt, int decrement)
+{
+  tree *countp = gimple_call_arg_ptr (stmt, 2);
+  gcc_assert (TREE_CODE (*countp) == INTEGER_CST);
+  tree x = fold_build2 (MINUS_EXPR, TREE_TYPE (*countp), *countp,
+   build_int_cst (TREE_TYPE (*countp), decrement));
+  *countp = x;


thanks to wide-int the following should work

   *countp = wide_int_to_tree (TREE_TYPE (*countp), *countp - decrement);

Sweet.  I like that much better.



(if not please use int_const_binop rather than fold_build2 here and
below as well)


+}
+
+static void
+increment_start_addr (gimple *stmt ATTRIBUTE_UNUSED, tree *where, int
increment)
+{
+  /* If the address wasn't initially a MEM_REF, make it a MEM_REF.  */
+  if (TREE_CODE (*where) == ADDR_EXPR
+  && TREE_CODE (TREE_OPERAND (*where, 0)) != MEM_REF)
+{
+  tree t = TREE_OPERAND (*where, 0);
+  t = build_ref_for_offset (EXPR_LOCATION (t), t,
+   increment * BITS_PER_UNIT, false,
+   ptr_type_node, NULL, false);


please don't use build_ref_for_offset for this.  Simply only handle the SSA_NAME
case here and below ...
I think build_ref_for_offset was what spurred the tree-sra.h inclusion. 
IIRC I was seeing a goodly number of cases where the argument wasn't a 
MEM_REF or SSA_NAME at this point.  But I'll double-check.


If we don't need build_ref_for_offset, do you still want me to pull its 
prototype into the new tree-sra.h, or just leave it as-is?







+  *where = build_fold_addr_expr (t);
+  return;
+}
+  else if (TREE_CODE (*where) == SSA_NAME)
+{
+  tree tem = make_ssa_name (TREE_TYPE (*where));
+  gassign *newop
+= gimple_build_assign (tem, POINTER_PLUS_EXPR, *where,
+  build_int_cst (sizetype, increment));
+  gimple_stmt_iterator gsi = gsi_for_stmt (stmt);
+  gsi_insert_before (&gsi, newop, GSI_SAME_STMT);
+  need_ssa_update = true;
+  *where = tem;
+  update_stmt (gsi_stmt (gsi));
+  return;
+}
+
+  /* We can just adjust the offset in the MEM_REF expression.  */
+  tree x1 = TREE_OPERAND (TREE_OPERAND (*where, 0), 1);
+  tree x = fold_build2 (PLUS_EXPR, TREE_TYPE (x1), x1,
+   build_int_cst (TREE_TYPE (x1), increment));
+  TREE_OPERAND (TREE_OPERAND (*where, 0), 1) = x;

...

re-fold the thing as MEM_REF which will do all the magic for you:

  *where = build_fold_addr_expr (fold_build2 (MEM_REF, char_type_node,
*where, build_int_cst (ptr_type_node, increment)));

that handles &MEM[] and &foo.bar just fine and avoids adding magic here.
And that (&foo.bar) is likely what I was looking to handle with the 
first if clause above where I called build_ref_for_offset.




Otherwise looks ok.  I think I'd like to see this in GCC 7 given it's
so much similar to the constructor pruning.
OK.  I'll sort through the issues noted above and get this one reposted 
as well.


jeff

Re: [PATCH C++] Fix PR77489 -- mangling of discriminator >= 10

[Markus Trippelsdorf]

On 2017.01.11 at 13:03 +0100, Jakub Jelinek wrote:
> On Wed, Jan 11, 2017 at 12:48:29PM +0100, Markus Trippelsdorf wrote:
> > @@ -1965,7 +1966,11 @@ write_discriminator (const int discriminator)
> >if (discriminator > 0)
> >  {
> >write_char ('_');
> > +  if (abi_version_at_least(11) && discriminator - 1 >= 10)
> > +   write_char ('_');
> >write_unsigned_number (discriminator - 1);
> > +  if (abi_version_at_least(11) && discriminator - 1 >= 10)
> > +   write_char ('_');
> 
> Formatting nits, there should be space before (11).
> 
> > +// { dg-final { scan-assembler "_ZZ3foovE8localVar__10_" } }
> > +// { dg-final { scan-assembler "_ZZ3foovE8localVar__11_" } }
> 
> Would be nice to also
> // { dg-final { scan-assembler "_ZZ3foovE8localVar_9" } }
> 
> Otherwise, I defer to Jason (primarily whether this doesn't need
> ABI version 12).

Thanks for review. I will fix these issues. 
Jason said on IRC that he is fine with ABI version 11.

Ok for trunk?

-- 
Markus

[PATCH v2 C++] Fix PR70182 -- missing "on" in mangling of unresolved operators

[Markus Trippelsdorf]

On 2017.01.11 at 08:21 -0500, Nathan Sidwell wrote:
> On 01/11/2017 08:16 AM, Markus Trippelsdorf wrote:
> 
> > --- a/gcc/cp/mangle.c
> > +++ b/gcc/cp/mangle.c
> > @@ -2813,6 +2813,8 @@ write_template_args (tree args)
> >  static void
> >  write_member_name (tree member)
> >  {
> > +  if (abi_version_at_least (11) && IDENTIFIER_OPNAME_P (member))
> > +write_string ("on");
> 
> It looks like you need to:
> 1) add documentation to doc/invoke.texi (-fabi-version)
> 2) add something like:
>   if (abi_warn_or_compat_version_crosses (11))
>   G.need_abi_warning = 1;
> into that if clause.

Thanks for the review. Here is a new patch:

OK for trunk?


libiberty:

PR c++/70182
* cp-demangle.c (d_unqualified_name): Handle "on" for
operator names.
* testsuite/demangle-expected: Add tests.

gcc/cp:

PR c++/70182
* mangle.c (write_template_args): Add "on" for operator names.

gcc:

PR c++/70182
* doc/invoke.texi (fabi-version): Mention mangling fix for
operator names.


diff --git a/gcc/cp/mangle.c b/gcc/cp/mangle.c
index e831deb31405..ef9e8fa71221 100644
--- a/gcc/cp/mangle.c
+++ b/gcc/cp/mangle.c
@@ -2813,6 +2813,12 @@ write_template_args (tree args)
 static void
 write_member_name (tree member)
 {
+  if (abi_version_at_least (11) && IDENTIFIER_OPNAME_P (member))
+{
+  write_string ("on");
+  if (abi_warn_or_compat_version_crosses (11))
+   G.need_abi_warning = 1;
+}
   if (identifier_p (member))
 write_unqualified_id (member);
   else if (DECL_P (member))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 9c77db25e776..75ef5875c0cb 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -2250,7 +2250,7 @@ attributes that affect type identity, such as ia32 
calling convention
 attributes (e.g. @samp{stdcall}).
 
 Version 11, which first appeared in G++ 7, corrects the mangling of
-sizeof... expressions.  It also implies
+sizeof... expressions and operator names.  It also implies
 @option{-fnew-inheriting-ctors}.
 
 See also @option{-Wabi}.
diff --git a/gcc/testsuite/g++.dg/abi/mangle13.C 
b/gcc/testsuite/g++.dg/abi/mangle13.C
index 716c4c36f410..c8822a34039c 100644
--- a/gcc/testsuite/g++.dg/abi/mangle13.C
+++ b/gcc/testsuite/g++.dg/abi/mangle13.C
@@ -1,4 +1,4 @@
-// { dg-options "-fabi-version=0" }
+// { dg-options "-fabi-version=10" }
 
 struct A {
   template  int f ();
diff --git a/gcc/testsuite/g++.dg/abi/mangle37.C 
b/gcc/testsuite/g++.dg/abi/mangle37.C
index 691566b384ba..4dd87e84c108 100644
--- a/gcc/testsuite/g++.dg/abi/mangle37.C
+++ b/gcc/testsuite/g++.dg/abi/mangle37.C
@@ -1,5 +1,6 @@
 // Testcase for mangling of expressions involving operator names.
 // { dg-do compile { target c++11 } }
+// { dg-options "-fabi-version=10" }
 // { dg-final { scan-assembler "_Z1fI1AEDTclonplfp_fp_EET_" } }
 // { dg-final { scan-assembler "_Z1gI1AEDTclonplIT_Efp_fp_EES1_" } }
 // { dg-final { scan-assembler "_Z1hI1AEDTcldtfp_miEET_" } }
diff --git a/gcc/testsuite/g++.dg/abi/pr70182.C 
b/gcc/testsuite/g++.dg/abi/pr70182.C
new file mode 100644
index ..d299362910c1
--- /dev/null
+++ b/gcc/testsuite/g++.dg/abi/pr70182.C
@@ -0,0 +1,28 @@
+// { dg-options "-fabi-version=0" }
+
+struct A {
+  template  int f ();
+  int operator+();
+  operator int ();
+  template  
+  int operator-();
+};
+
+typedef int (A::*P)();
+
+template  struct S {};
+
+template  void g (S<&T::template f >) {}
+template  void g (S<&T::operator+ >) {}
+template  void g (S<&T::operator int>) {}
+template  void g (S<&T::template operator-  >) {}
+
+template void g (S<&A::f >);
+template void g (S<&A::operator+>);
+template void g (S<&A::operator int>);
+template void g (S<&A::operator- >);
+
+// { dg-final { scan-assembler _Z1gI1AEv1SIXadsrT_1fIiEEE } }
+// { dg-final { scan-assembler _Z1gI1AEv1SIXadsrT_onplEE } }
+// { dg-final { scan-assembler _Z1gI1AEv1SIXadsrT_oncviEE } }
+// { dg-final { scan-assembler _Z1gI1AEv1SIXadsrT_onmiIdEEE } }
diff --git a/gcc/testsuite/g++.dg/dfp/mangle-1.C 
b/gcc/testsuite/g++.dg/dfp/mangle-1.C
index 455d3e4c0ef6..ee9644b27a53 100644
--- a/gcc/testsuite/g++.dg/dfp/mangle-1.C
+++ b/gcc/testsuite/g++.dg/dfp/mangle-1.C
@@ -1,4 +1,5 @@
 // { dg-do compile }
+// { dg-options "-fabi-version=10" }
 
 // Mangling of classes from std::decimal are special-cased.
 // Derived from g++.dg/abi/mangle13.C.
diff --git a/libiberty/cp-demangle.c b/libiberty/cp-demangle.c
index d84929eca20d..f0dbf9381c6b 100644
--- a/libiberty/cp-demangle.c
+++ b/libiberty/cp-demangle.c
@@ -1594,6 +1594,8 @@ d_unqualified_name (struct d_info *di)
 ret = d_source_name (di);
   else if (IS_LOWER (peek))
 {
+  if (peek == 'o' && d_peek_next_char (di) == 'n')
+   d_advance (di, 2);
   ret = d_operator_name (di);
   if (ret != NULL && ret->type == DEMANGLE_COMPONENT_OPERATOR)
{
diff --git a/libiberty/testsuite/demangle-expected 
b/libiberty/testsuite/demangle-expected
index 07e258fe58b3..c1cfa1545eca 100