Re: [PATCH] Add debug_bb_details and debug_bb_n_details

2020-10-25 Thread Xionghu Luo via Gcc-patches 


On 2020/10/23 18:18, Richard Biener wrote:
> On Fri, 23 Oct 2020, Xiong Hu Luo wrote:
> 
>> Sometimes debug_bb_slim&debug_bb_n_slim is not enough, how about adding
>> this debug_bb_details&debug_bb_n_details? Or any other similar call
>> existed?
> There's already debug_bb and debug_bb_n in cfg.c which works on both
> RTL and GIMPLE.  How about instead adding overloads that accept
> a flags argument so you can do
> 
> debug_bb_n (5, TDF_DETAILS)
> 
> ?  The debug_bb_slim variant would then just a forwarder.
> 

Thanks.  Updated the patch as below:


[PATCH v2] Add overloaded debug_bb and debug_bb_n with dump flags


Add overloads that accept a flags argument so we can print
debug_bb_n (5, TDF_DETAILS) in gdb, also the debug_bb_slim
variant would then be just a forwarder.

gcc/ChangeLog:

2020-10-26  Xionghu Luo  

* cfg.c (debug_bb): New overloaded function.
(debug_bb_n): New overloaded function.
* cfg.h (debug_bb_n): New declaration.
(debug_bb_n): New declaration.
* print-rtl.c (debug_bb_slim): Call debug_bb with flags.
---
 gcc/cfg.c   | 20 +++-
 gcc/cfg.h   |  2 ++
 gcc/print-rtl.c |  2 +-
 3 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/gcc/cfg.c b/gcc/cfg.c
index 270a48f729a..05f922f5470 100644
--- a/gcc/cfg.c
+++ b/gcc/cfg.c
@@ -720,7 +720,7 @@ free_aux_for_edges (void)
 DEBUG_FUNCTION void
 debug_bb (basic_block bb)
 {
-  dump_bb (stderr, bb, 0, dump_flags);
+  debug_bb (bb, dump_flags);
 }
 
 DEBUG_FUNCTION basic_block
@@ -731,6 +731,24 @@ debug_bb_n (int n)
   return bb;
 }
 
+/* Print bb with specified flags.  */
+
+DEBUG_FUNCTION void
+debug_bb (basic_block bb, dump_flags_t flags)
+{
+  dump_bb (stderr, bb, 0, flags);
+}
+
+/* Print bb numbered n with specified flags.  */
+
+DEBUG_FUNCTION basic_block
+debug_bb_n (int n, dump_flags_t flags)
+{
+  basic_block bb = BASIC_BLOCK_FOR_FN (cfun, n);
+  debug_bb (bb, flags);
+  return bb;
+}
+
 /* Dumps cfg related information about basic block BB to OUTF.
If HEADER is true, dump things that appear before the instructions
contained in BB.  If FOOTER is true, dump things that appear after.
diff --git a/gcc/cfg.h b/gcc/cfg.h
index 1eb7866bac9..93fde6df2bf 100644
--- a/gcc/cfg.h
+++ b/gcc/cfg.h
@@ -108,6 +108,8 @@ extern void clear_aux_for_edges (void);
 extern void free_aux_for_edges (void);
 extern void debug_bb (basic_block);
 extern basic_block debug_bb_n (int);
+extern void debug_bb (basic_block, dump_flags_t);
+extern basic_block debug_bb_n (int, dump_flags_t);
 extern void dump_bb_info (FILE *, basic_block, int, dump_flags_t, bool, bool);
 extern void brief_dump_cfg (FILE *, dump_flags_t);
 extern void update_bb_profile_for_threading (basic_block, profile_count, edge);
diff --git a/gcc/print-rtl.c b/gcc/print-rtl.c
index 25265efc71b..d514b1c5373 100644
--- a/gcc/print-rtl.c
+++ b/gcc/print-rtl.c
@@ -2139,7 +2139,7 @@ extern void debug_bb_slim (basic_block);
 DEBUG_FUNCTION void
 debug_bb_slim (basic_block bb)
 {
-  dump_bb (stderr, bb, 0, TDF_SLIM | TDF_BLOCKS);
+  debug_bb (bb, TDF_SLIM | TDF_BLOCKS);
 }
 
 extern void debug_bb_n_slim (int);
-- 
2.27.0.90.geebb51ba8c

Re: error: ‘EVRP_MODE_DEBUG’ was not declared – was: [PUSHED] Ranger classes.

2020-10-25 Thread Maciej W. Rozycki 
On Tue, 6 Oct 2020, Andrew MacLeod via Gcc-patches wrote:

> >> Build fails here now with: gimple-range.h:168:59: error:
> >> ‘EVRP_MODE_DEBUG’ was not declared in this scope
> >>
> > And now builds – as the "Hybrid EVRP and testcases" was pushed as well,
> > a bit more than a quarter of an hour later. (At least it finished
> > building the compiler itself, I do not expect surprises in the library
> > parts.)
> >
> > Tobias
> Guess I should have just pushed it all as one commit. I thought the first part
> was pretty separate from the second... and it was except for one line :-P  of
> course I had problems getting the second one out or it would have followed
> quicker.

 It is still broken at `-O0', does not build with `--enable-werror-always' 
(which IMO should be on by default except for releases, just as we do with 
binutils AFAIK, so as to make sure people do not introduce build problems 
too easily):

.../gcc/gimple-range.cc: In function 'bool range_of_builtin_call(range_query&, 
irange&, gcall*)':
.../gcc/gimple-range.cc:677:15: error: 'zerov' may be used uninitialized 
[-Werror=maybe-uninitialized]
  677 |   if (zerov == prec)
  |   ^~
cc1plus: all warnings being treated as errors
make[2]: *** [Makefile:1122: gimple-range.o] Error 1

  Maciej

Re: [PATCH 2/2] combine: Don't turn (mult (extend x) 2^n) into extract

2020-10-25 Thread Segher Boessenkool 
Hi!

On Thu, Oct 15, 2020 at 09:59:24AM +0100, Alex Coplan wrote:
> This patch remedies this situation: after the patch, make_extraction()
> now also identifies RTXs such as:
> 
> (mult:DI (subreg:DI (reg:SI r)) (const_int 2^n))
> 
> and rewrites this as:
> 
> (mult:DI (sign_extend:DI (reg:SI r)) (const_int 2^n))
> 
> instead of using a sign_extract.

Do we do that in simplify-rtx already (w/ the proper SUBREG_PROMOTED_*
stuff set)?  If not, we should; if so, why does that not work here?

(Just the subreg->{sign,zero}_extend that is, nothing with the mult.)


Segher

Re: [patch, fortran] Partial fix for PR97454, declarations of some library functions

2020-10-25 Thread Thomas Koenig via Gcc-patches 

Hi Paul,


OK for master.


Committed, thanks.


Thanks for working on this one!


There is still a lto to do (I left in this typo by
design :-), especially with cshift and friends.  Let's see
how far I can progress until gcc 11 with this one, if helping
out Nicolas with coarray stuff leaves me time for that.

Best regards

Thomas

Re: [RS6000] Tests that use int128_t and -m32

2020-10-25 Thread David Edelsohn via Gcc-patches 
On Sun, Oct 25, 2020 at 7:20 AM Alan Modra  wrote:
>
> All these tests fail with -m32 due to lack of int128 support, in some
> cases with what I thought was not the best error message.  For example
> vsx_mask-move-runnable.c:34:3: error: unknown type name 'vector'
> is misleading.  The problem isn't "vector" but "vector __uint128_t".
>
> * gcc.target/powerpc/vsx-load-element-extend-char.c: Require int128.
> * gcc.target/powerpc/vsx-load-element-extend-int.c: Likewise.
> * gcc.target/powerpc/vsx-load-element-extend-longlong.c: Likewise.
> * gcc.target/powerpc/vsx-load-element-extend-short.c: Likewise.
> * gcc.target/powerpc/vsx-store-element-truncate-char.c: Likewise.
> * gcc.target/powerpc/vsx-store-element-truncate-int.c: Likewise.
> * gcc.target/powerpc/vsx-store-element-truncate-longlong.c: Likewise.
> * gcc.target/powerpc/vsx-store-element-truncate-short.c: Likewise.
> * gcc.target/powerpc/vsx_mask-count-runnable.c: Likewise.
> * gcc.target/powerpc/vsx_mask-expand-runnable.c: Likewise.
> * gcc.target/powerpc/vsx_mask-extract-runnable.c: Likewise.
> * gcc.target/powerpc/vsx_mask-move-runnable.c: Likewise.

Good catch.

Another problem with all of the vsx_mask test cases is that they use
-mcpu=power10 instead of  -mdejagnu-cpu=power10.  Can you follow up
with that fix or do you want me to?

Thanks, David

>
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c 
> b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
> index 0b8cfd610f8..7a7cb77c3a0 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
> @@ -4,6 +4,7 @@
>
>  /* { dg-do compile {target power10_ok} } */
>  /* { dg-do run {target power10_hw} } */
> +/* { dg-require-effective-target { int128 } } */
>  /* { dg-options "-mdejagnu-cpu=power10 -O3" } */
>
>  /* At the time of writing, the number of lxvrbx instructions is
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c 
> b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
> index b10d3cb43d2..414678c9461 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
> @@ -4,6 +4,7 @@
>
>  /* { dg-do compile {target power10_ok} } */
>  /* { dg-do run {target power10_hw} } */
> +/* { dg-require-effective-target { int128 } } */
>
>  /* Deliberately set optization to zero for this test to confirm
> the lxvr*x instruction is generated. At higher optimization levels
> diff --git 
> a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c 
> b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
> index 52fcf2e572f..c1e3ebc25ca 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
> @@ -4,6 +4,7 @@
>
>  /* { dg-do compile {target power10_ok} } */
>  /* { dg-do run {target power10_hw} } */
> +/* { dg-require-effective-target { int128 } } */
>  /* { dg-options "-mdejagnu-cpu=power10 -O3" } */
>
>  /* At time of writing, we also geenerate a .constrprop copy
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c 
> b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
> index 8fc0cc66eb7..698ba30c6f8 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
> @@ -4,6 +4,7 @@
>
>  /* { dg-do compile {target power10_ok} } */
>  /* { dg-do run {target power10_hw} } */
> +/* { dg-require-effective-target { int128 } } */
>
>  /* Deliberately set optization to zero for this test to confirm
> the lxvr*x instruction is generated. At higher optimization levels
> diff --git 
> a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c 
> b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
> index 99f3904983b..53fc2cc9bae 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
> @@ -3,6 +3,7 @@
>
>  /* { dg-do compile {target power10_ok} } */
>  /* { dg-do run {target power10_hw} } */
> +/* { dg-require-effective-target { int128 } } */
>  /* Deliberately set optization to zero for this test to confirm
> the stxvr*x instruction is generated. At higher optimization levels
> the instruction we are looking for is sometimes replaced by other
> diff --git 
> a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c 
> b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
> index 6e2acf83c38..4c64b413e16 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-trunc

Make default duplicate and insert methods of summaries abort; fix fallout

2020-10-25 Thread Jan Hubicka 
Hi,
the default duplicate and insert methods of sumaries produce empty
summary that is not useful for anything and makes it easy to introduce
bugs.

This patch makes the default hooks to abort and summaries that do not
need dupicaito/insertion disable the corresponding hooks. I also
implemented missing insertion hook for ipa-sra which forced me to move
analysis out of anounmous namespace.

Wi aready have disable_insertion_hook, I also added
disable_duplication_hook.  Martin (Liska), it would be nice to simply
unregiter the hooks instead of having bool controlling htem so we save
some indirect calls.

Bootstrapped/regtested x86_64-linux, plan to commit it tomorrow if there
are no comments.

Honza

2020-10-23  Jan Hubicka  

* cgraph.h (struct cgraph_node): Make ipa_transforms_to_apply vl_ptr.
* ipa-inline-analysis.c (initialize_growth_caches): Disable insertion
and duplication hooks.
* ipa-inline-transform.c (clone_inlined_nodes): Clear
ipa_transforms_to_apply.
(save_inline_function_body): Disable insertion hoook for
ipa_saved_clone_sources.
* ipa-prop.c (ipcp_transformation_initialize): Disable insertion hook.
* ipa-prop.h (ipa_node_params_t): Disable insertion hook.
* ipa-reference.c (propagate): Disable insertion hoook.
* ipa-sra.c (ipa_sra_summarize_function): Move out of anonymous
namespace.
(ipa_sra_function_summaries::insert): New virtual function.
* passes.c (execute_one_pass): Do not add transforms to inline clones.
* symbol-summary.h (function_summary_base): Make insert and duplicate
hooks fail instead of silently producing empty summaries; add way to
disable duplication hooks
(call_summary_base): Likewise.
* tree-nested.c (nested_function_info::get_create): Disable insertion
hooks
(maybe_record_nested_function): Likewise.


diff --git a/gcc/cgraph.h b/gcc/cgraph.h
index 9eb48d5b62f..65e4646efcd 100644
--- a/gcc/cgraph.h
+++ b/gcc/cgraph.h
@@ -1402,7 +1402,7 @@ struct GTY((tag ("SYMTAB_FUNCTION"))) cgraph_node : 
public symtab_node
   /* Interprocedural passes scheduled to have their transform functions
  applied next time we execute local pass on them.  We maintain it
  per-function in order to allow IPA passes to introduce new functions.  */
-  vec GTY((skip)) ipa_transforms_to_apply;
+  vec GTY((skip)) ipa_transforms_to_apply;
 
   /* For inline clones this points to the function they will be
  inlined into.  */
diff --git a/gcc/ipa-inline-analysis.c b/gcc/ipa-inline-analysis.c
index acbf82e84d9..bd0e322605f 100644
--- a/gcc/ipa-inline-analysis.c
+++ b/gcc/ipa-inline-analysis.c
@@ -127,6 +127,9 @@ initialize_growth_caches ()
 = new fast_call_summary (symtab);
   node_context_cache
 = new fast_function_summary (symtab);
+  edge_growth_cache->disable_duplication_hook ();
+  node_context_cache->disable_insertion_hook ();
+  node_context_cache->disable_duplication_hook ();
 }
 
 /* Free growth caches.  */
diff --git a/gcc/ipa-inline-transform.c b/gcc/ipa-inline-transform.c
index 3782cce12e3..279ba2f7cb0 100644
--- a/gcc/ipa-inline-transform.c
+++ b/gcc/ipa-inline-transform.c
@@ -231,6 +231,11 @@ clone_inlined_nodes (struct cgraph_edge *e, bool duplicate,
 e->callee->remove_from_same_comdat_group ();
 
   e->callee->inlined_to = inlining_into;
+  if (e->callee->ipa_transforms_to_apply.length ())
+{
+  e->callee->ipa_transforms_to_apply.release ();
+  e->callee->ipa_transforms_to_apply = vNULL;
+}
 
   /* Recursively clone all bodies.  */
   for (e = e->callee->callees; e; e = next)
@@ -606,7 +611,10 @@ save_inline_function_body (struct cgraph_node *node)
 
   tree prev_body_holder = node->decl;
   if (!ipa_saved_clone_sources)
-ipa_saved_clone_sources = new function_summary  (symtab);
+{
+  ipa_saved_clone_sources = new function_summary  (symtab);
+  ipa_saved_clone_sources->disable_insertion_hook ();
+}
   else
 {
   tree *p = ipa_saved_clone_sources->get (node);
diff --git a/gcc/ipa-prop.c b/gcc/ipa-prop.c
index a848f1db95e..6014766b418 100644
--- a/gcc/ipa-prop.c
+++ b/gcc/ipa-prop.c
@@ -4211,7 +4211,10 @@ ipcp_transformation_initialize (void)
   if (!ipa_vr_hash_table)
 ipa_vr_hash_table = hash_table::create_ggc (37);
   if (ipcp_transformation_sum == NULL)
-ipcp_transformation_sum = ipcp_transformation_t::create_ggc (symtab);
+{
+  ipcp_transformation_sum = ipcp_transformation_t::create_ggc (symtab);
+  ipcp_transformation_sum->disable_insertion_hook ();
+}
 }
 
 /* Release the IPA CP transformation summary.  */
diff --git a/gcc/ipa-prop.h b/gcc/ipa-prop.h
index 0f9bd9f..77e92b04bba 100644
--- a/gcc/ipa-prop.h
+++ b/gcc/ipa-prop.h
@@ -941,7 +941,10 @@ class GTY((user)) ipa_node_params_t: public 
function_summary 
 {
 public:
   ipa_node_params_t (symbol_table *table, bool ggc):
-function_summary (table, ggc) { }
+function_summa

Re: [PATCH] avr: Add atmega324pb MCU

2020-10-25 Thread Matwey V. Kornilov via Gcc-patches 
Ping?

чт, 4 июн. 2020 г. в 18:30, Matwey V. Kornilov :

> Reference: https://www.microchip.com/wwwproducts/en/ATMEGA324PB
> ---
>  gcc/config/avr/avr-mcus.def | 1 +
>  gcc/doc/avr-mmcu.texi   | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/avr/avr-mcus.def b/gcc/config/avr/avr-mcus.def
> index 24046c367a7..ac80f9e63ff 100644
> --- a/gcc/config/avr/avr-mcus.def
> +++ b/gcc/config/avr/avr-mcus.def
> @@ -207,6 +207,7 @@ AVR_MCU ("atmega323",ARCH_AVR5, AVR_ISA_NONE,
> "__AVR_ATmega323__",
>  AVR_MCU ("atmega324a",   ARCH_AVR5, AVR_ISA_NONE,
> "__AVR_ATmega324A__",0x0100, 0x0, 0x8000, 0)
>  AVR_MCU ("atmega324p",   ARCH_AVR5, AVR_ISA_NONE,
> "__AVR_ATmega324P__",0x0100, 0x0, 0x8000, 0)
>  AVR_MCU ("atmega324pa",  ARCH_AVR5, AVR_ISA_NONE,
> "__AVR_ATmega324PA__",   0x0100, 0x0, 0x8000, 0)
> +AVR_MCU ("atmega324pb",  ARCH_AVR5, AVR_ISA_NONE,
> "__AVR_ATmega324PB__",   0x0100, 0x0, 0x8000, 0)
>  AVR_MCU ("atmega325",ARCH_AVR5, AVR_ISA_NONE,
> "__AVR_ATmega325__", 0x0100, 0x0, 0x8000, 0)
>  AVR_MCU ("atmega325a",   ARCH_AVR5, AVR_ISA_NONE,
> "__AVR_ATmega325A__",0x0100, 0x0, 0x8000, 0)
>  AVR_MCU ("atmega325p",   ARCH_AVR5, AVR_ISA_NONE,
> "__AVR_ATmega325P__",0x0100, 0x0, 0x8000, 0)
> diff --git a/gcc/doc/avr-mmcu.texi b/gcc/doc/avr-mmcu.texi
> index 5cd7b50afa2..87ed4476b1a 100644
> --- a/gcc/doc/avr-mmcu.texi
> +++ b/gcc/doc/avr-mmcu.texi
> @@ -38,7 +38,7 @@
>
>  @item avr5
>  ``Enhanced'' devices with 16@tie{}KiB up to 64@tie{}KiB of program
> memory.
> -@*@var{mcu}@tie{}= @code{atmega16}, @code{atmega16a},
> @code{atmega16hva}, @code{atmega16hva2}, @code{atmega16hvb},
> @code{atmega16hvbrevb}, @code{atmega16m1}, @code{atmega16u4},
> @code{atmega161}, @code{atmega162}, @code{atmega163}, @code{atmega164a},
> @code{atmega164p}, @code{atmega164pa}, @code{atmega165}, @code{atmega165a},
> @code{atmega165p}, @code{atmega165pa}, @code{atmega168}, @code{atmega168a},
> @code{atmega168p}, @code{atmega168pa}, @code{atmega168pb},
> @code{atmega169}, @code{atmega169a}, @code{atmega169p}, @code{atmega169pa},
> @code{atmega32}, @code{atmega32a}, @code{atmega32c1}, @code{atmega32hvb},
> @code{atmega32hvbrevb}, @code{atmega32m1}, @code{atmega32u4},
> @code{atmega32u6}, @code{atmega323}, @code{atmega324a}, @code{atmega324p},
> @code{atmega324pa}, @code{atmega325}, @code{atmega325a}, @code{atmega325p},
> @code{atmega325pa}, @code{atmega328}, @code{atmega328p},
> @code{atmega328pb}, @code{atmega329}, @code{atmega329a}, @code{atmega329p},
> @code{atmega329pa}, @code{atmega3250}, @code{atmega3250a},
> @code{atmega3250p}, @code{atmega3250pa}, @code{atmega3290},
> @code{atmega3290a}, @code{atmega3290p}, @code{atmega3290pa},
> @code{atmega406}, @code{atmega64}, @code{atmega64a}, @code{atmega64c1},
> @code{atmega64hve}, @code{atmega64hve2}, @code{atmega64m1},
> @code{atmega64rfr2}, @code{atmega640}, @code{atmega644}, @code{atmega644a},
> @code{atmega644p}, @code{atmega644pa}, @code{atmega644rfr2},
> @code{atmega645}, @code{atmega645a}, @code{atmega645p}, @code{atmega649},
> @code{atmega649a}, @code{atmega649p}, @code{atmega6450},
> @code{atmega6450a}, @code{atmega6450p}, @code{atmega6490},
> @code{atmega6490a}, @code{atmega6490p}, @code{ata5795}, @code{ata5790},
> @code{ata5790n}, @code{ata5791}, @code{ata6613c}, @code{ata6614q},
> @code{ata5782}, @code{ata5831}, @code{ata8210}, @code{ata8510},
> @code{ata5702m322}, @code{at90pwm161}, @code{at90pwm216},
> @code{at90pwm316}, @code{at90can32}, @code{at90can64}, @code{at90scr100},
> @code{at90usb646}, @code{at90usb647}, @code{at94k}, @code{m3000}.
> +@*@var{mcu}@tie{}= @code{atmega16}, @code{atmega16a},
> @code{atmega16hva}, @code{atmega16hva2}, @code{atmega16hvb},
> @code{atmega16hvbrevb}, @code{atmega16m1}, @code{atmega16u4},
> @code{atmega161}, @code{atmega162}, @code{atmega163}, @code{atmega164a},
> @code{atmega164p}, @code{atmega164pa}, @code{atmega165}, @code{atmega165a},
> @code{atmega165p}, @code{atmega165pa}, @code{atmega168}, @code{atmega168a},
> @code{atmega168p}, @code{atmega168pa}, @code{atmega168pb},
> @code{atmega169}, @code{atmega169a}, @code{atmega169p}, @code{atmega169pa},
> @code{atmega32}, @code{atmega32a}, @code{atmega32c1}, @code{atmega32hvb},
> @code{atmega32hvbrevb}, @code{atmega32m1}, @code{atmega32u4},
> @code{atmega32u6}, @code{atmega323}, @code{atmega324a}, @code{atmega324p},
> @code{atmega324pa}, @code{atmega324pb}, @code{atmega325},
> @code{atmega325a}, @code{atmega325p}, @code{atmega325pa}, @code{atmega328},
> @code{atmega328p}, @code{atmega328pb}, @code{atmega329}, @code{atmega329a},
> @code{atmega329p}, @code{atmega329pa}, @code{atmega3250},
> @code{atmega3250a}, @code{atmega3250p}, @code{atmega3250pa},
> @code{atmega3290}, @code{atmega3290a}, @code{atmega3290p},
> @code{atmega3290pa}, @code{atmega406}, @code{atmega64}, @code{atmega64a},
> @code{atmega64c1}, @code{atmega64hve}, @code{atmega64hve2},
> @code{atmega64m1}, @code{atm

[RS6000] biarch test fail

2020-10-25 Thread Alan Modra via Gcc-patches 
I thought this one was worth at least commenting as to why it fails
when biarch testing.  OK?

* gcc.target/powerpc/bswap64-4.c: Comment.

diff --git a/gcc/testsuite/gcc.target/powerpc/bswap64-4.c 
b/gcc/testsuite/gcc.target/powerpc/bswap64-4.c
index a3c05539652..11787000409 100644
--- a/gcc/testsuite/gcc.target/powerpc/bswap64-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/bswap64-4.c
@@ -7,6 +7,12 @@
 /* { dg-final { scan-assembler-times "ldbrx" 1 { target has_arch_pwr7 } } } */
 /* { dg-final { scan-assembler-times "stdbrx" 1 { target has_arch_pwr7 } } } */
 
+/* This test will fail when biarch testing with
+   "RUNTESTFLAGS=--target_board=unix'{-m64,-m32}'" because the -m32 is
+   added on the command line after the dg-options -mpowerpc64, and
+   common/config/rs6000/rs6000-common.c:rs6000_handle_option disables
+   -mpowerpc64 for -m32.  */
+
 long long swap_load (long long *a) { return __builtin_bswap64 (*a); }
 long long swap_reg (long long a) { return __builtin_bswap64 (a); }
 void swap_store (long long *a, long long b) { *a = __builtin_bswap64 (b); }

-- 
Alan Modra
Australia Development Lab, IBM

[RS6000] Remove -mpcrel from tests

2020-10-25 Thread Alan Modra via Gcc-patches 
When running with -m32
FAIL: gcc.target/powerpc/pr94740.c (test for excess errors)
Excess errors:
cc1: error: '-mpcrel' requires '-mcmodel=medium'

The others don't run for -m32, but remove the unnecessary -mpcrel
anyway.

* gcc.target/powerpc/localentry-1.c: Remove -mpcrel from options.
* gcc.target/powerpc/notoc-direct-1.c: Likewise.
* gcc.target/powerpc/pr94740.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/powerpc/localentry-1.c 
b/gcc/testsuite/gcc.target/powerpc/localentry-1.c
index c3c51680cfe..1343df2b8f1 100644
--- a/gcc/testsuite/gcc.target/powerpc/localentry-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/localentry-1.c
@@ -1,11 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mpcrel" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
 /* { dg-require-effective-target powerpc_elfv2 } */
 /* { dg-require-effective-target power10_ok } */
 
-/* Ensure we generate ".localentry fn,1" for both leaf and non-leaf functions.
-   At present, -mcpu=power10 does not enable pc-relative mode, so make sure we
-   enable it to be able to check for .localentry.  */
+/* Ensure we generate ".localentry fn,1" for both leaf and non-leaf
+   functions.  */
 
 extern int y (int);
 
diff --git a/gcc/testsuite/gcc.target/powerpc/notoc-direct-1.c 
b/gcc/testsuite/gcc.target/powerpc/notoc-direct-1.c
index 74187e1d5dc..8fa09b03f4f 100644
--- a/gcc/testsuite/gcc.target/powerpc/notoc-direct-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/notoc-direct-1.c
@@ -1,11 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mpcrel" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
 /* { dg-require-effective-target powerpc_elfv2 } */
 /* { dg-require-effective-target power10_ok } */
 
-/* Test that calls generated from PC-relative code are annotated with @notoc.
-   At present, -mcpu=power10 does not enable pc-relative mode.  Enable it here
-   explicitly until it is turned on by default.  */
+/* Test that calls generated from PC-relative code are annotated with
+   @notoc.  */
 
 extern int yy0 (int);
 extern void yy1 (int);
@@ -40,4 +39,3 @@ int ww (void)
 /* { dg-final { scan-assembler {yy0@notoc} } } */
 /* { dg-final { scan-assembler {zz1@notoc} } } */
 /* { dg-final { scan-assembler {zz0@notoc} } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/pr94740.c 
b/gcc/testsuite/gcc.target/powerpc/pr94740.c
index 9c2b4644701..09decc38c2c 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr94740.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr94740.c
@@ -1,7 +1,7 @@
 /* PR rtl-optimization/94740 */
 /* { dg-do compile } */
 /* { dg-require-effective-target power10_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10 -mpcrel" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
 
 int array[8];
 int

-- 
Alan Modra
Australia Development Lab, IBM

[RS6000] Unsupported test options for -m32

2020-10-25 Thread Alan Modra via Gcc-patches 
FAIL: gcc.target/powerpc/swaps-p8-22.c (test for excess errors)
Excess errors:
cc1: error: '-mcmodel' not supported in this configuration

* gcc.target/powerpc/swaps-p8-22.c: Disable for -m32.

diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-22.c 
b/gcc/testsuite/gcc.target/powerpc/swaps-p8-22.c
index 83f6ab3a1c0..bceada41b75 100644
--- a/gcc/testsuite/gcc.target/powerpc/swaps-p8-22.c
+++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-require-effective-target { lp64 && powerpc_p8vector_ok } } */
 /* { dg-options "-O2 -mdejagnu-cpu=power8 -maltivec -mcmodel=large" } */
 
 /* The expansion for vector character multiply introduces a vperm operation.

-- 
Alan Modra
Australia Development Lab, IBM

[RS6000] Tests that use int128_t and -m32

2020-10-25 Thread Alan Modra via Gcc-patches 
All these tests fail with -m32 due to lack of int128 support, in some
cases with what I thought was not the best error message.  For example
vsx_mask-move-runnable.c:34:3: error: unknown type name 'vector'
is misleading.  The problem isn't "vector" but "vector __uint128_t".

* gcc.target/powerpc/vsx-load-element-extend-char.c: Require int128.
* gcc.target/powerpc/vsx-load-element-extend-int.c: Likewise.
* gcc.target/powerpc/vsx-load-element-extend-longlong.c: Likewise.
* gcc.target/powerpc/vsx-load-element-extend-short.c: Likewise.
* gcc.target/powerpc/vsx-store-element-truncate-char.c: Likewise.
* gcc.target/powerpc/vsx-store-element-truncate-int.c: Likewise.
* gcc.target/powerpc/vsx-store-element-truncate-longlong.c: Likewise.
* gcc.target/powerpc/vsx-store-element-truncate-short.c: Likewise.
* gcc.target/powerpc/vsx_mask-count-runnable.c: Likewise.
* gcc.target/powerpc/vsx_mask-expand-runnable.c: Likewise.
* gcc.target/powerpc/vsx_mask-extract-runnable.c: Likewise.
* gcc.target/powerpc/vsx_mask-move-runnable.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c 
b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
index 0b8cfd610f8..7a7cb77c3a0 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
 /* { dg-options "-mdejagnu-cpu=power10 -O3" } */
 
 /* At the time of writing, the number of lxvrbx instructions is
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c 
b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
index b10d3cb43d2..414678c9461 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
 
 /* Deliberately set optization to zero for this test to confirm
the lxvr*x instruction is generated. At higher optimization levels
diff --git 
a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c 
b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
index 52fcf2e572f..c1e3ebc25ca 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
 /* { dg-options "-mdejagnu-cpu=power10 -O3" } */
 
 /* At time of writing, we also geenerate a .constrprop copy
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c 
b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
index 8fc0cc66eb7..698ba30c6f8 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
 
 /* Deliberately set optization to zero for this test to confirm
the lxvr*x instruction is generated. At higher optimization levels
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c 
b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
index 99f3904983b..53fc2cc9bae 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
@@ -3,6 +3,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
 /* Deliberately set optization to zero for this test to confirm
the stxvr*x instruction is generated. At higher optimization levels
the instruction we are looking for is sometimes replaced by other
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c 
b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
index 6e2acf83c38..4c64b413e16 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
@@ -3,6 +3,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target { int128 } } */
 /* Deliberately set optization to zero for this test to confirm
the stxvr*x instruction is generated. At higher optimization levels
the instruction we are looking for is sometimes replaced by other
diff --git 
a/gcc/testsuite/gcc.target/powerpc/vs

Re: [PATCH] Ada, Darwin, PowerPC : Fix bootstrap after 128 int changes.

2020-10-25 Thread Arnaud Charlet 
> Three bootstrap breaks in one week must be close to a record, even for
> powerpc-darwin ;)

Indeed, sorry about that!

> tested on powerpc-darwin9 (m32/m64),
> OK for master?

OK, thanks.

> P.S. There are some apparent regressions/new GNAT fails for the m64 multilib
> but these will be addressed separately.
> 
> Excess errors:
> validity_check.adb:13:04: run-time configuration error
> validity_check.adb:13:04: entity "System.Scalar_Values.Is_Is16" not defined
> 
> commit message
> 
> The GNATRTL_128BIT_PAIRS/OBJS need to be added for 64bit
> multilibs on powerpc-darwin, and for powerpc64-darwin.
> 
> gcc/ada/ChangeLog:
> 
>   * Makefile.rtl: Add GNATRTL_128BIT_PAIRS/OBJS for 64bit
>   PowerPC Darwin cases.

Re: [patch, fortran] Partial fix for PR97454, declarations of some library functions

2020-10-25 Thread Paul Richard Thomas via Gcc-patches 
Hi Thomas,

OK for master.

Thanks for working on this one!

Paul


On Fri, 16 Oct 2020 at 20:33, Thomas Koenig via Fortran 
wrote:

> Hello world,
>
> here's a patch which corrects some wrong declarations (and fixes
> the segfault for FINDLOC on Darwin ARM).
>
> Regression-tested. OK for trunk?
>
> Best regards
>
> Thomas
>
> Correct decls for functions which do not pass actual arguments.
>
> A wrong decl for findloc caused segfaults at runtime on
> Darwin for ARM; however, this is only a symptom of a larger
> disease: The declarations for our library functions are often
> inconsistent.  This patch solves that problem for the functions
> specifically for the functions for which we do not pass optional
> arguments, i.e. findloc and (min|max)loc.
>
> It works by saving the symbols of the specific functions in
> gfc_intrinsic_namespace and by generating the formal argument
> lists from the actual argument lists.  Because symbols are
> re-used, so are the backend decls.
>
> gcc/fortran/ChangeLog:
>
> PR fortran/97454
> * gfortran.h (gfc_symbol): Add pass_as_value flag.
> (gfc_copy_formal_args_intr): Add optional argument
> copy_type.
> (gfc_get_intrinsic_function_symbol): Add prototype.
> (gfc_find_intrinsic_symbol): Add prototype.
> * intrinsic.c (gfc_get_intrinsic_function_symbol): New function.
> (gfc_find_intrinsic_symbol): New function.
> * symbol.c (gfc_copy_formal_args_intr): Add argument. Handle case
> where the type needs to be copied from the actual argument.
> * trans-intrinsic.c (remove_empty_actual_arguments): New function.
> (specific_intrinsic_symbol): New function.
> (gfc_conv_intrinsic_funcall): Use it.
> (strip_kind_from_actual): Adjust so that the expression pointer
> is set to NULL.
> (gfc_conv_intrinsic_minmaxloc): Likewise.
> (gfc_conv_intrinsic_minmaxval): Adjust removal of dim.
> * trans-types.c (gfc_sym_type): If sym->pass_as_value is set, do
> not pass by reference.
>


-- 
"If you can't explain it simply, you don't understand it well enough" -
Albert Einstein

[PATCH] Ada, Darwin, PowerPC : Fix bootstrap after 128 int changes.

2020-10-25 Thread Iain Sandoe 
Hi.

Three bootstrap breaks in one week must be close to a record, even for
powerpc-darwin ;)

tested on powerpc-darwin9 (m32/m64),
OK for master?
Iain

P.S. There are some apparent regressions/new GNAT fails for the m64 multilib
but these will be addressed separately.

Excess errors:
validity_check.adb:13:04: run-time configuration error
validity_check.adb:13:04: entity "System.Scalar_Values.Is_Is16" not defined

 commit message

The GNATRTL_128BIT_PAIRS/OBJS need to be added for 64bit
multilibs on powerpc-darwin, and for powerpc64-darwin.

gcc/ada/ChangeLog:

* Makefile.rtl: Add GNATRTL_128BIT_PAIRS/OBJS for 64bit
PowerPC Darwin cases.
---
 gcc/ada/Makefile.rtl | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl
index 254db518f3e..2b5d1de17fa 100644
--- a/gcc/ada/Makefile.rtl
+++ b/gcc/ada/Makefile.rtl
@@ -2796,8 +2796,19 @@ ifeq ($(strip $(filter-out darwin%,$(target_os))),)
   $(ATOMICS_BUILTINS_TARGET_PAIRS) \
   system.ads

Re: [RS6000] VSX_MM_SUFFIX

2020-10-25 Thread Segher Boessenkool 
On Sun, Oct 25, 2020 at 11:55:39AM +1030, Alan Modra wrote:
> On Sat, Oct 24, 2020 at 12:31:43PM -0500, Segher Boessenkool wrote:
> > On Sat, Oct 24, 2020 at 02:59:34PM +1030, Alan Modra wrote:
> > > Those instructions aren't generated, we don't see them anywhere on a
> > > power10 all-lang bootstrap except in one testcase designed to exercise
> > > them.
> > 
> > But that is completely not relevant :-)
> > 
> > If you use a macro that doesn't exist, the compiler simply does not
> > build!
> 
> My empirical evidence to the contrary says your theoretical arguments
> are invalid.  :-)
> 
> $ gcc/xgcc -Bgcc/ -S 
> ~/src/gcc/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c -O2 
> -mcpu=power10
> $ grep VSX_MM vsx_mask-count-runnable.s
>   vcntmb 9,0,1
>   vcntmb 9,0,1
>   vcntmb 9,0,1
>   vcntmb 9,0,1

Oh, wow.  How unexpected (to me, anyway).  I'll open a PR.


Segher