[PATCH] RISC-V: allow vx instruction use "zero" as scalar register.

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/ChangeLog:

* config/riscv/vector.md: use "zero" reg.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/binop_vx_constraint-121.c: New test.

  li a5,0
  vdiv.vx v0,v1,a5 ===> vdiv.vx v0,v1,zero
---
 gcc/config/riscv/vector.md| 57 +++
 .../riscv/rvv/base/binop_vx_constraint-121.c  | 55 ++
 2 files changed, 88 insertions(+), 24 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-121.c

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index ec177fa7efb..d526c1fc5f1 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1247,11 +1247,11 @@
 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
  (any_commutative_binop:VI_QHS
(vec_duplicate:VI_QHS
- (match_operand: 4 "register_operand"  "  r,  r"))
+ (match_operand: 4 "reg_or_0_operand"  " rJ, rJ"))
(match_operand:VI_QHS 3 "register_operand"   " vr, vr"))
  (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
   "TARGET_VECTOR"
-  "v.vx\t%0,%3,%4%p1"
+  "v.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "")
(set_attr "mode" "")])
 
@@ -1269,10 +1269,10 @@
  (any_non_commutative_binop:VI_QHS
(match_operand:VI_QHS 3 "register_operand"   " vr, vr")
(vec_duplicate:VI_QHS
- (match_operand: 4 "register_operand"  "  r,  r")))
+ (match_operand: 4 "reg_or_0_operand"  " rJ, rJ")))
  (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
   "TARGET_VECTOR"
-  "v.vx\t%0,%3,%4%p1"
+  "v.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "")
(set_attr "mode" "")])
 
@@ -1324,8 +1324,11 @@
rtx v = gen_reg_rtx (mode);
 
if (riscv_vector::simm32_p (operands[4]))
- operands[4] = gen_rtx_SIGN_EXTEND (mode,
-   force_reg (Pmode, operands[4]));
+ {
+   if (!rtx_equal_p (operands[4], const0_rtx))
+ operands[4] = force_reg (Pmode, operands[4]);
+   operands[4] = gen_rtx_SIGN_EXTEND (mode, operands[4]);
+ }
else
  {
if (CONST_INT_P (operands[4]))
@@ -1356,11 +1359,11 @@
 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
  (any_commutative_binop:VI_D
(vec_duplicate:VI_D
- (match_operand: 4 "register_operand"  "  r,  r"))
+ (match_operand: 4 "reg_or_0_operand"  " rJ, rJ"))
(match_operand:VI_D 3 "register_operand" " vr, vr"))
  (match_operand:VI_D 2 "vector_merge_operand"   "0vu,0vu")))]
   "TARGET_VECTOR"
-  "v.vx\t%0,%3,%4%p1"
+  "v.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "")
(set_attr "mode" "")])
 
@@ -1378,11 +1381,11 @@
  (any_commutative_binop:VI_D
(vec_duplicate:VI_D
  (sign_extend:
-   (match_operand: 4 "register_operand" "  r,  r")))
+   (match_operand: 4 "reg_or_0_operand" " rJ, rJ")))
(match_operand:VI_D 3 "register_operand" " vr, vr"))
  (match_operand:VI_D 2 "vector_merge_operand"   "0vu,0vu")))]
   "TARGET_VECTOR"
-  "v.vx\t%0,%3,%4%p1"
+  "v.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "")
(set_attr "mode" "")])
 
@@ -1411,8 +1414,11 @@
rtx v = gen_reg_rtx (mode);
 
if (riscv_vector::simm32_p (operands[4]))
- operands[4] = gen_rtx_SIGN_EXTEND (mode,
-   force_reg (Pmode, operands[4]));
+ {
+   if (!rtx_equal_p (operands[4], const0_rtx))
+ operands[4] = force_reg (Pmode, operands[4]);
+   operands[4] = gen_rtx_SIGN_EXTEND (mode, operands[4]);
+ }
else
  {
if (CONST_INT_P (operands[4]))
@@ -1444,10 +1450,10 @@
  (any_non_commutative_binop:VI_D
(match_operand:VI_D 3 "register_operand" " vr, vr")
(vec_duplicate:VI_D
- (match_operand: 4 "register_operand"  "  r,  r")))
+ (match_operand: 4 "reg_or_0_operand"  " rJ, rJ")))
  (match_operand:VI_D 2 "vector_merge_operand"   "0vu,0vu")))]
   "TARGET_VECTOR"
-  "v.vx\t%0,%3,%4%p1"
+  "v.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "")
(set_attr "mode" "")])
 
@@ -1466,10 +1472,10 @@
(match_operand:VI_D 3 "register_operand" " vr, vr")
(vec_duplicate:VI_D
  (sign_extend:
-   (match_operand: 4 "register_operand" "  r,  r"
+   (match_operand: 4 "reg_or_0_operand" " rJ, rJ"
  (match_operand:VI_D 2 "vector_merge_operand"   "0vu,0vu")))]
   "TARGET_VECTOR"
-  "v.vx\t%0,%3,%4%p1"
+  "v.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "")
(set_attr "mode" "")])
 
@@ -1836,11 +1842,11 @@
 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
  (unspec:VI_QHS
[(vec_duplicate:VI_QHS
-  (match_operand: 4 "register_operand"  "  r,  r"))
+  (match_operand: 4 "reg_or_0_operand"  " 

Re: [committed] amdgcn: Pass -mstack-size through to runtime

[Tobias Burnus]

On 06.02.23 18:22, Andrew Stubbs wrote:

The -mstack-size option has been marked obsolete in favour of setting
an environment variable at runtime ("GCN_STACK_SIZE"), [...] but my
testing setup uses remote execute which doesn't support that yet, and
means I would skip my own tests (not ideal).


Namely, the problem with remote testing is that DejaGNU's setenv does
not work. This is a reoccurring theme but still unsolved, cf.

https://lists.gnu.org/archive/html/dejagnu/2008-07/msg0.html

https://lists.gnu.org/archive/html/dejagnu/2019-11/msg0.html

Now, only someone needs to find the time to fix DejaGNU ...

Tobias

-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 
München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas 
Heurung, Frank Thürauf; Sitz der Gesellschaft: München; Registergericht 
München, HRB 106955

[PATCH] RISC-V: Add constraint tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: New test.

---
 .../riscv/rvv/base/binop_vx_constraint-120.c | 16 
 1 file changed, 16 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
new file mode 100644
index 000..809b185dd65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwmulsu_vx_i16mf4(vbool64_t mask, vint16mf4_t merge, 
vint8mf8_t op1,int8_t op2,size_t vl)
+{
+  return __riscv_vwmulsu_vx_i16mf4_tumu(mask,merge,op1,0,vl);
+}
+
+vint16mf4_t test___riscv_vwmul_vx_i16mf4(vbool64_t mask, vint16mf4_t merge, 
vint8mf8_t op1,int8_t op2,size_t vl)
+{
+  return __riscv_vwmul_vx_i16mf4_tumu(mask,merge,op1,0,vl);
+}
+
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,zero}
 1 } } */
+/* { dg-final { scan-assembler-times 
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,zero}
 1 } } */
-- 
2.36.1

[PATCH] RISC-V: Add vwsub.vv C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vwsub_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vv_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vwsub_vv-1.c| 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vv-2.c| 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vv-3.c| 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vv_m-1.c  | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vv_m-2.c  | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vv_m-3.c  | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vv_mu-1.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vv_mu-2.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vv_mu-3.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vv_tu-1.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vv_tu-2.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vv_tu-3.c | 111 ++
 .../riscv/rvv/base/vwsub_vv_tum-1.c   | 111 ++
 .../riscv/rvv/base/vwsub_vv_tum-2.c   | 111 ++
 .../riscv/rvv/base/vwsub_vv_tum-3.c   | 111 ++
 .../riscv/rvv/base/vwsub_vv_tumu-1.c  | 111 ++
 .../riscv/rvv/base/vwsub_vv_tumu-2.c  | 111 ++
 .../riscv/rvv/base/vwsub_vv_tumu-3.c  | 111 ++
 18 files changed, 1998 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv-1.c
new file mode 100644
index 000..42e9e46ad1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vv_i16mf4(vint8mf8_t op1,vint8mf8_t op2,size_t 
vl)
+{
+return __riscv_vwsub_vv_i16mf4(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vv_i16mf2(vint8mf4_t op1,vint8mf4_t op2,size_t 
vl)
+{
+return __riscv_vwsub_vv_i16mf2(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_vv_i16m1(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+return __riscv_vwsub_vv_i16m1(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_vv_i16m2(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+return __riscv_vwsub_vv_i16m2(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_vv_i16m4(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+return __riscv_vwsub_vv_i16m4(op1,op2,vl);
+}
+
+

[PATCH] RISC-V: Add vwsub.vx C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vwsub_vx-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_m-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_m-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_m-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_vx_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vwsub_vx-1.c| 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vx-2.c| 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vx-3.c| 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vx_m-1.c  | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vx_m-2.c  | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vx_m-3.c  | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vx_mu-1.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vx_mu-2.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vx_mu-3.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vx_tu-1.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vx_tu-2.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_vx_tu-3.c | 111 ++
 .../riscv/rvv/base/vwsub_vx_tum-1.c   | 111 ++
 .../riscv/rvv/base/vwsub_vx_tum-2.c   | 111 ++
 .../riscv/rvv/base/vwsub_vx_tum-3.c   | 111 ++
 .../riscv/rvv/base/vwsub_vx_tumu-1.c  | 111 ++
 .../riscv/rvv/base/vwsub_vx_tumu-2.c  | 111 ++
 .../riscv/rvv/base/vwsub_vx_tumu-3.c  | 111 ++
 18 files changed, 1998 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx-1.c
new file mode 100644
index 000..fee2b8d2285
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_vx_i16mf4(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+return __riscv_vwsub_vx_i16mf4(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_vx_i16mf2(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+return __riscv_vwsub_vx_i16mf2(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_vx_i16m1(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+return __riscv_vwsub_vx_i16m1(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_vx_i16m2(vint8m1_t op1,int8_t op2,size_t vl)
+{
+return __riscv_vwsub_vx_i16m2(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_vx_i16m4(vint8m2_t op1,int8_t op2,size_t vl)
+{
+return __riscv_vwsub_vx_i16m4(op1,op2,vl);
+}
+
+
+vint16m8_t test___

[PATCH] RISC-V: Add vwsub.wv C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vwsub_wv-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wv_tumu-3.c: New test.


---
 .../gcc.target/riscv/rvv/base/vwsub_wv-1.c| 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wv-2.c| 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wv-3.c| 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wv_m-1.c  | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wv_m-2.c  | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wv_m-3.c  | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wv_mu-1.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wv_mu-2.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wv_mu-3.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wv_tu-1.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wv_tu-2.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wv_tu-3.c | 111 ++
 .../riscv/rvv/base/vwsub_wv_tum-1.c   | 111 ++
 .../riscv/rvv/base/vwsub_wv_tum-2.c   | 111 ++
 .../riscv/rvv/base/vwsub_wv_tum-3.c   | 111 ++
 .../riscv/rvv/base/vwsub_wv_tumu-1.c  | 111 ++
 .../riscv/rvv/base/vwsub_wv_tumu-2.c  | 111 ++
 .../riscv/rvv/base/vwsub_wv_tumu-3.c  | 111 ++
 18 files changed, 1998 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-1.c
new file mode 100644
index 000..31bbaf4bcc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wv_i16mf4(vint16mf4_t op1,vint8mf8_t op2,size_t 
vl)
+{
+return __riscv_vwsub_wv_i16mf4(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wv_i16mf2(vint16mf2_t op1,vint8mf4_t op2,size_t 
vl)
+{
+return __riscv_vwsub_wv_i16mf2(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wv_i16m1(vint16m1_t op1,vint8mf2_t op2,size_t vl)
+{
+return __riscv_vwsub_wv_i16m1(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wv_i16m2(vint16m2_t op1,vint8m1_t op2,size_t vl)
+{
+return __riscv_vwsub_wv_i16m2(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wv_i16m4(vint16m4_t op1,vint8m2_t op2,size_t vl)
+{
+return __riscv_vwsub_wv_i16m4(op1,op2,vl);
+

[PATCH] RISC-V: Add vwsub.wx C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vwsub_wx-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_m-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_m-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_m-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsub_wx_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vwsub_wx-1.c| 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wx-2.c| 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wx-3.c| 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wx_m-1.c  | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wx_m-2.c  | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wx_m-3.c  | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wx_mu-1.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wx_mu-2.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wx_mu-3.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wx_tu-1.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wx_tu-2.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsub_wx_tu-3.c | 111 ++
 .../riscv/rvv/base/vwsub_wx_tum-1.c   | 111 ++
 .../riscv/rvv/base/vwsub_wx_tum-2.c   | 111 ++
 .../riscv/rvv/base/vwsub_wx_tum-3.c   | 111 ++
 .../riscv/rvv/base/vwsub_wx_tumu-1.c  | 111 ++
 .../riscv/rvv/base/vwsub_wx_tumu-2.c  | 111 ++
 .../riscv/rvv/base/vwsub_wx_tumu-3.c  | 111 ++
 18 files changed, 1998 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx-1.c
new file mode 100644
index 000..1cf611427f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwsub_wx_i16mf4(vint16mf4_t op1,int8_t op2,size_t vl)
+{
+return __riscv_vwsub_wx_i16mf4(op1,0xAA,vl);
+}
+
+
+vint16mf2_t test___riscv_vwsub_wx_i16mf2(vint16mf2_t op1,int8_t op2,size_t vl)
+{
+return __riscv_vwsub_wx_i16mf2(op1,0xAA,vl);
+}
+
+
+vint16m1_t test___riscv_vwsub_wx_i16m1(vint16m1_t op1,int8_t op2,size_t vl)
+{
+return __riscv_vwsub_wx_i16m1(op1,0xAA,vl);
+}
+
+
+vint16m2_t test___riscv_vwsub_wx_i16m2(vint16m2_t op1,int8_t op2,size_t vl)
+{
+return __riscv_vwsub_wx_i16m2(op1,0xAA,vl);
+}
+
+
+vint16m4_t test___riscv_vwsub_wx_i16m4(vint16m4_t op1,int8_t op2,size_t vl)
+{
+return __riscv_vwsub_wx_i16m4(op1,0xAA,vl);
+}
+
+
+vint16m8_

Re: [PATCH] RISC-V: Add vwsubu.wx C API tests

[juzhe.zh...@rivai.ai]

Sorry for the wrong title, it should be add vwsubu.wv C API tests



juzhe.zh...@rivai.ai
 
From: juzhe.zhong
Date: 2023-02-07 14:17
To: gcc-patches
CC: kito.cheng; Ju-Zhe Zhong
Subject: [PATCH] RISC-V: Add vwsubu.wx C API tests
From: Ju-Zhe Zhong 
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/vwsubu_wv-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c: New test.
 
---
.../gcc.target/riscv/rvv/base/vwsubu_wv-1.c   | 111 ++
.../gcc.target/riscv/rvv/base/vwsubu_wv-2.c   | 111 ++
.../gcc.target/riscv/rvv/base/vwsubu_wv-3.c   | 111 ++
.../gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c | 111 ++
.../gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c | 111 ++
.../gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c | 111 ++
.../riscv/rvv/base/vwsubu_wv_mu-1.c   | 111 ++
.../riscv/rvv/base/vwsubu_wv_mu-2.c   | 111 ++
.../riscv/rvv/base/vwsubu_wv_mu-3.c   | 111 ++
.../riscv/rvv/base/vwsubu_wv_tu-1.c   | 111 ++
.../riscv/rvv/base/vwsubu_wv_tu-2.c   | 111 ++
.../riscv/rvv/base/vwsubu_wv_tu-3.c   | 111 ++
.../riscv/rvv/base/vwsubu_wv_tum-1.c  | 111 ++
.../riscv/rvv/base/vwsubu_wv_tum-2.c  | 111 ++
.../riscv/rvv/base/vwsubu_wv_tum-3.c  | 111 ++
.../riscv/rvv/base/vwsubu_wv_tumu-1.c | 111 ++
.../riscv/rvv/base/vwsubu_wv_tumu-2.c | 111 ++
.../riscv/rvv/base/vwsubu_wv_tumu-3.c | 111 ++
18 files changed, 1998 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c
new file mode 100644
index 000..73d261cc78b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4(vuint16mf4_t op1,vuint8mf8_t 
op2,size_t vl)
+{
+return __riscv_vwsubu_wv_u16mf4(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2(vuint16mf2_t op1,vuint8mf4_t 
op2,size_t vl)
+{
+return __riscv_vwsubu_wv_u16mf2(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1(vuint16m1_t op1,vuint8mf2_t 
op2,size_t vl)
+{
+return __riscv_vwsubu_wv_u16m1(op1,op2,vl);
+}
+
+
+vuint16m2_t test___

[PATCH] RISC-V: Add vwsubu.vv C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vwsubu_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vv_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vwsubu_vv-1.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_vv-2.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_vv-3.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_vv_m-1.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_vv_m-2.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_vv_m-3.c | 111 ++
 .../riscv/rvv/base/vwsubu_vv_mu-1.c   | 111 ++
 .../riscv/rvv/base/vwsubu_vv_mu-2.c   | 111 ++
 .../riscv/rvv/base/vwsubu_vv_mu-3.c   | 111 ++
 .../riscv/rvv/base/vwsubu_vv_tu-1.c   | 111 ++
 .../riscv/rvv/base/vwsubu_vv_tu-2.c   | 111 ++
 .../riscv/rvv/base/vwsubu_vv_tu-3.c   | 111 ++
 .../riscv/rvv/base/vwsubu_vv_tum-1.c  | 111 ++
 .../riscv/rvv/base/vwsubu_vv_tum-2.c  | 111 ++
 .../riscv/rvv/base/vwsubu_vv_tum-3.c  | 111 ++
 .../riscv/rvv/base/vwsubu_vv_tumu-1.c | 111 ++
 .../riscv/rvv/base/vwsubu_vv_tumu-2.c | 111 ++
 .../riscv/rvv/base/vwsubu_vv_tumu-3.c | 111 ++
 18 files changed, 1998 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv-1.c
new file mode 100644
index 000..76616380a8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_vv_u16mf4(vuint8mf8_t op1,vuint8mf8_t 
op2,size_t vl)
+{
+return __riscv_vwsubu_vv_u16mf4(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_vv_u16mf2(vuint8mf4_t op1,vuint8mf4_t 
op2,size_t vl)
+{
+return __riscv_vwsubu_vv_u16mf2(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_vv_u16m1(vuint8mf2_t op1,vuint8mf2_t 
op2,size_t vl)
+{
+return __riscv_vwsubu_vv_u16m1(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_vv_u16m2(vuint8m1_t op1,vuint8m1_t op2,size_t 
vl)
+{
+return __riscv_vwsubu_vv_u16m2(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_vv_u16m4(vuint8m2_t op1,vuint8m2_t op2,siz

[PATCH] RISC-V: Add vwsubu.vx C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vwsubu_vx-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_m-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_m-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_m-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_vx_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vwsubu_vx-1.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_vx-2.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_vx-3.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_vx_m-1.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_vx_m-2.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_vx_m-3.c | 111 ++
 .../riscv/rvv/base/vwsubu_vx_mu-1.c   | 111 ++
 .../riscv/rvv/base/vwsubu_vx_mu-2.c   | 111 ++
 .../riscv/rvv/base/vwsubu_vx_mu-3.c   | 111 ++
 .../riscv/rvv/base/vwsubu_vx_tu-1.c   | 111 ++
 .../riscv/rvv/base/vwsubu_vx_tu-2.c   | 111 ++
 .../riscv/rvv/base/vwsubu_vx_tu-3.c   | 111 ++
 .../riscv/rvv/base/vwsubu_vx_tum-1.c  | 111 ++
 .../riscv/rvv/base/vwsubu_vx_tum-2.c  | 111 ++
 .../riscv/rvv/base/vwsubu_vx_tum-3.c  | 111 ++
 .../riscv/rvv/base/vwsubu_vx_tumu-1.c | 111 ++
 .../riscv/rvv/base/vwsubu_vx_tumu-2.c | 111 ++
 .../riscv/rvv/base/vwsubu_vx_tumu-3.c | 111 ++
 18 files changed, 1998 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx-1.c
new file mode 100644
index 000..38252ab0058
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_vx_u16mf4(vuint8mf8_t op1,uint8_t op2,size_t 
vl)
+{
+return __riscv_vwsubu_vx_u16mf4(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_vx_u16mf2(vuint8mf4_t op1,uint8_t op2,size_t 
vl)
+{
+return __riscv_vwsubu_vx_u16mf2(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_vx_u16m1(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+return __riscv_vwsubu_vx_u16m1(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_vx_u16m2(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+return __riscv_vwsubu_vx_u16m2(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_vx_u16m4(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+retu

[PATCH] RISC-V: Add vwsubu.wx C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vwsubu_wv-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vwsubu_wv-1.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_wv-2.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_wv-3.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c | 111 ++
 .../riscv/rvv/base/vwsubu_wv_mu-1.c   | 111 ++
 .../riscv/rvv/base/vwsubu_wv_mu-2.c   | 111 ++
 .../riscv/rvv/base/vwsubu_wv_mu-3.c   | 111 ++
 .../riscv/rvv/base/vwsubu_wv_tu-1.c   | 111 ++
 .../riscv/rvv/base/vwsubu_wv_tu-2.c   | 111 ++
 .../riscv/rvv/base/vwsubu_wv_tu-3.c   | 111 ++
 .../riscv/rvv/base/vwsubu_wv_tum-1.c  | 111 ++
 .../riscv/rvv/base/vwsubu_wv_tum-2.c  | 111 ++
 .../riscv/rvv/base/vwsubu_wv_tum-3.c  | 111 ++
 .../riscv/rvv/base/vwsubu_wv_tumu-1.c | 111 ++
 .../riscv/rvv/base/vwsubu_wv_tumu-2.c | 111 ++
 .../riscv/rvv/base/vwsubu_wv_tumu-3.c | 111 ++
 18 files changed, 1998 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c
new file mode 100644
index 000..73d261cc78b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wv_u16mf4(vuint16mf4_t op1,vuint8mf8_t 
op2,size_t vl)
+{
+return __riscv_vwsubu_wv_u16mf4(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wv_u16mf2(vuint16mf2_t op1,vuint8mf4_t 
op2,size_t vl)
+{
+return __riscv_vwsubu_wv_u16mf2(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wv_u16m1(vuint16m1_t op1,vuint8mf2_t 
op2,size_t vl)
+{
+return __riscv_vwsubu_wv_u16m1(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wv_u16m2(vuint16m2_t op1,vuint8m1_t op2,size_t 
vl)
+{
+return __riscv_vwsubu_wv_u16m2(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wv_u16m4(vuint16m4_t op1,vuint8m2_t op2

[PATCH] RISC-V: Add vwsubu.wx C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vwsubu_wx-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vwsubu_wx_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vwsubu_wx-1.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_wx-2.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_wx-3.c   | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c | 111 ++
 .../gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c | 111 ++
 .../riscv/rvv/base/vwsubu_wx_mu-1.c   | 111 ++
 .../riscv/rvv/base/vwsubu_wx_mu-2.c   | 111 ++
 .../riscv/rvv/base/vwsubu_wx_mu-3.c   | 111 ++
 .../riscv/rvv/base/vwsubu_wx_tu-1.c   | 111 ++
 .../riscv/rvv/base/vwsubu_wx_tu-2.c   | 111 ++
 .../riscv/rvv/base/vwsubu_wx_tu-3.c   | 111 ++
 .../riscv/rvv/base/vwsubu_wx_tum-1.c  | 111 ++
 .../riscv/rvv/base/vwsubu_wx_tum-2.c  | 111 ++
 .../riscv/rvv/base/vwsubu_wx_tum-3.c  | 111 ++
 .../riscv/rvv/base/vwsubu_wx_tumu-1.c | 111 ++
 .../riscv/rvv/base/vwsubu_wx_tumu-2.c | 111 ++
 .../riscv/rvv/base/vwsubu_wx_tumu-3.c | 111 ++
 18 files changed, 1998 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-1.c
new file mode 100644
index 000..7c41784b3ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-1.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwsubu_wx_u16mf4(vuint16mf4_t op1,uint8_t op2,size_t 
vl)
+{
+return __riscv_vwsubu_wx_u16mf4(op1,0xAA,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwsubu_wx_u16mf2(vuint16mf2_t op1,uint8_t op2,size_t 
vl)
+{
+return __riscv_vwsubu_wx_u16mf2(op1,0xAA,vl);
+}
+
+
+vuint16m1_t test___riscv_vwsubu_wx_u16m1(vuint16m1_t op1,uint8_t op2,size_t vl)
+{
+return __riscv_vwsubu_wx_u16m1(op1,0xAA,vl);
+}
+
+
+vuint16m2_t test___riscv_vwsubu_wx_u16m2(vuint16m2_t op1,uint8_t op2,size_t vl)
+{
+return __riscv_vwsubu_wx_u16m2(op1,0xAA,vl);
+}
+
+
+vuint16m4_t test___riscv_vwsubu_wx_u16m4(vuint16m4_t op1,uint8_t op2,size_t vl)
+{
+

[PATCH] RISC-V: Add integer widening instructions

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc (class widen_binop): New 
class.
(class vwmulsu): Ditto.
(class vwcvt): Ditto.
(BASE): Add integer widening support.
* config/riscv/riscv-vector-builtins-bases.h: Ditto
* config/riscv/riscv-vector-builtins-functions.def (vwadd): New class.
(vwsub): New class.
(vwmul): New class.
(vwmulu): New class.
(vwmulsu): New class.
(vwaddu): New class.
(vwsubu): New class.
(vwcvt_x): New class.
(vwcvtu_x): New class.
* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): New 
class.
(struct widen_alu_def): New class.
(SHAPE): New class.
* config/riscv/riscv-vector-builtins-shapes.h: New class.
* config/riscv/riscv-vector-builtins.cc 
(rvv_arg_type_info::get_base_vector_type): Add integer widening support.
(rvv_arg_type_info::get_tree_type): Ditto.
* config/riscv/riscv-vector-builtins.def (x_x_v): Change into "x_v"
(x_v): Ditto.
* config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Add 
integer widening support.
* config/riscv/riscv-vsetvl.cc (change_insn): Fix reg_equal use bug.
* config/riscv/riscv.h (X0_REGNUM): New constant.
* config/riscv/vector-iterators.md: New iterators.
* config/riscv/vector.md 
(@pred_dual_widen_): New pattern.
(@pred_dual_widen__scalar): 
Ditto.
(@pred_single_widen_): Ditto.
(@pred_single_widen__scalar): 
Ditto.
(@pred_widen_mulsu): Ditto.
(@pred_widen_mulsu_scalar): Ditto.
(@pred_): Ditto.

---
 .../riscv/riscv-vector-builtins-bases.cc  |  75 +++
 .../riscv/riscv-vector-builtins-bases.h   |  10 +
 .../riscv/riscv-vector-builtins-functions.def |  24 ++
 .../riscv/riscv-vector-builtins-shapes.cc |  30 ++-
 .../riscv/riscv-vector-builtins-shapes.h  |   1 +
 gcc/config/riscv/riscv-vector-builtins.cc | 151 +
 gcc/config/riscv/riscv-vector-builtins.def|   2 +-
 gcc/config/riscv/riscv-vector-builtins.h  |   3 +
 gcc/config/riscv/riscv-vsetvl.cc  |  40 
 gcc/config/riscv/riscv.h  |   3 -
 gcc/config/riscv/vector-iterators.md  |   8 +
 gcc/config/riscv/vector.md| 205 +-
 12 files changed, 539 insertions(+), 13 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 43f815156d8..e14a1854eee 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -239,6 +239,63 @@ public:
   }
 };
 
+/* Implements vwadd/vwsub/vwmul.  */
+template
+class widen_binop : public function_base
+{
+public:
+  rtx expand (function_expander &e) const override
+  {
+switch (e.op_info->op)
+  {
+  case OP_TYPE_vv:
+   return e.use_exact_insn (
+ code_for_pred_dual_widen (CODE1, CODE2, e.vector_mode ()));
+  case OP_TYPE_vx:
+   return e.use_exact_insn (
+ code_for_pred_dual_widen_scalar (CODE1, CODE2, e.vector_mode ()));
+  case OP_TYPE_wv:
+   return e.use_exact_insn (
+ code_for_pred_single_widen (CODE1, CODE2, e.vector_mode ()));
+  case OP_TYPE_wx:
+   return e.use_exact_insn (
+ code_for_pred_single_widen_scalar (CODE1, CODE2, e.vector_mode ()));
+  default:
+   gcc_unreachable ();
+  }
+  }
+};
+
+/* Implements vwmulsu.  */
+class vwmulsu : public function_base
+{
+public:
+  rtx expand (function_expander &e) const override
+  {
+switch (e.op_info->op)
+  {
+  case OP_TYPE_vv:
+   return e.use_exact_insn (code_for_pred_widen_mulsu (e.vector_mode ()));
+  case OP_TYPE_vx:
+   return e.use_exact_insn (
+ code_for_pred_widen_mulsu_scalar (e.vector_mode ()));
+  default:
+   gcc_unreachable ();
+  }
+  }
+};
+
+/* Implements vwcvt.  */
+template
+class vwcvt : public function_base
+{
+public:
+  rtx expand (function_expander &e) const override
+  {
+return e.use_exact_insn (code_for_pred (CODE, e.vector_mode ()));
+  }
+};
+
 static CONSTEXPR const vsetvl vsetvl_obj;
 static CONSTEXPR const vsetvl vsetvlmax_obj;
 static CONSTEXPR const loadstore vle_obj;
@@ -288,6 +345,15 @@ static CONSTEXPR const unop vneg_obj;
 static CONSTEXPR const unop vnot_obj;
 static CONSTEXPR const ext vsext_obj;
 static CONSTEXPR const ext vzext_obj;
+static CONSTEXPR const widen_binopvwadd_obj;
+static CONSTEXPR const widen_binopvwsub_obj;
+static CONSTEXPR const widen_binopvwmul_obj;
+static CONSTEXPR const widen_binopvwaddu_obj;
+static CONSTEXPR const widen_binopvwsubu_obj;
+static CONSTEXPR const widen_binopvwmulu_obj;
+static CONSTEXPR const vwmulsu vwmulsu_obj;
+static CONSTEXPR const vwcvt vwcvt_x_obj;
+static CONSTEXPR const vwcvt vwcvtu_x_obj;
 static CONSTEXPR const binop vsadd_obj;
 static CONS

Re: [PATCH] Fortran: ASSOCIATE variables should not be TREE_STATIC [PR95107]

[Jerry D via Gcc-patches]

On 2/6/23 12:10 PM, Harald Anlauf via Fortran wrote:

Dear all,

as the PR shows, it is likely not a good idea to try to make an
ASSOCIATE variable static when -fno-automatic is specified, so
rather keep it on the stack.

Attached patch regtested on x86_64-pc-linux-gnu.  OK for mainline?

Thanks,
Harald



Yes, OK

Thanks,

Jerry

Re: [PATCH] ipa: silent -Wodr notes with -w

[Jan Hubicka via Gcc-patches]

> On 2/1/23 15:26, Martin Jambor wrote:
> > Hi,
> > 
> > On Fri, Dec 02 2022, Martin Liška wrote:
> > > If -w is used, warn_odr properly sets *warned = false and
> > > so it should be preserved when calling warn_types_mismatch.
> > > 
> > > Noticed that during a LTO reduction where I used -w.
> > > 
> > > Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
> > > 
> > > Ready to be installed?
> > > Thanks,
> > > Martin
> > > 
> > > gcc/ChangeLog:
> > > 
> > >   * ipa-devirt.cc (odr_types_equivalent_p): Respect *warned
> > >   value if set.
> > 
> 
> Hi.
> 
> > Sorry for skipping this for so long, usually ODR stuff is... interesting
> > to the point I gladly leave it to Honza.
> 
> Makes sense, however, he's not much active when it comes to patch review.

Sorry, I was confused by the patch and delayed reply to figure out what
you are trying to fix.  Indeed the dererence is missing here, however
every caller that sets warn to true should also set warned to non-NULL.
So indeed derefernce is missing, but I think the check for
warned == NULL should not be necessary.

Honza
> 
> > 
> > Please go ahead and commit the patch.  The way I read the code, your
> > version must have been the intended behavior and the dereference is
> > missing.
> 
> Yep, the patch seems to me quite straightforward.
> 
> Thanks,
> Martin
> 
> > 
> > Thanks,
> > 
> > Martin
> > 
> 

Re: [pushed] wwwdocs: projects/tree-ssa: Use our own copy of GCC Summit 2007 proceedings

[Joseph Myers]

On Mon, 6 Feb 2023, Gerald Pfeifer wrote:

> gccsummit.org is gone with the wind; luckily we have our own copy of the 
> 2006 proceedings.
> 
> If any of you has copies of 2007 and later, can you please drop  me a 
> copy and I'll put them on gcc.gnu.org as well?

Aren't they all on the wiki?  https://en.wikipedia.org/wiki/GCC_Summit has 
direct links to them.

-- 
Joseph S. Myers
jos...@codesourcery.com

Re: [PATCH 1/2] Handle component_ref to a structre/union field including flexible array member [PR101832]

[Joseph Myers]

On Mon, 6 Feb 2023, Qing Zhao via Gcc-patches wrote:

> In GCC14:
> 
> 1. Include this new warning -Wgnu-varaible-sized-type-not-at-end to -Wall
> 2. Deprecate this extension from GCC. (Or delay this to next release?).

Any deprecation, or inclusion in -Wall, would best come with evidence 
about the prevalance of use (possibly unintentional, probably undesirable) 
of these extensions.  For example, maybe someone could do a distribution 
rebuild with a patch to enable these warnings and report the results?

Various misuses of flexible array members are only pedwarns-if-pedantic 
because of such uses - and while the original motivating case 
 was 
_G_config.h, which has since been fixed (though existing installed headers 
from old glibc would need fixincluding, at least if it becomes an error), 
it's very plausible there are uses of these extensions elsewhere.

-- 
Joseph S. Myers
jos...@codesourcery.com

Re: [PATCH] libstdc++: Document P1642 and extensions

[Jonathan Wakely via Gcc-patches]

On Mon, 23 Jan 2023 at 12:49, Arsen Arsenović via Libstdc++
 wrote:
>
> libstdc++-v3/ChangeLog:
>
> * doc/xml/manual/using.xml: Document newly-freestanding
> headers and the effect of the -ffreestanding flag.
> * doc/xml/manual/status_cxx2023.xml: Document P1642R11 as
> completed.
> * doc/xml/manual/configure.xml: Document that hosted installs
> respect __STDC_HOSTED__.
> * doc/xml/manual/test.xml: Document how to run tests in
> freestanding mode.
> ---
> Afternoon,
>
> This patch documents the freestanding changes that are to be included in
> GCC 13.  This revision assumes the changes submitted earlier about
> building a nearly empty library in freestanding, and simplifies the
> linking section a bit as a result.  Due to -ffreestanding now working on
> hosted builds of libstdc++, however, it still includes the advice of
> ``gcc -lsupc++'' for those that are using hosted builds.

Pushed to trunk, thanks!


>
> Thanks in advance, have a great day.
>
>  libstdc++-v3/doc/xml/manual/configure.xml |  5 +-
>  .../doc/xml/manual/status_cxx2023.xml | 11 
>  libstdc++-v3/doc/xml/manual/test.xml  | 14 
>  libstdc++-v3/doc/xml/manual/using.xml | 66 +--
>  4 files changed, 88 insertions(+), 8 deletions(-)
>
> diff --git a/libstdc++-v3/doc/xml/manual/configure.xml 
> b/libstdc++-v3/doc/xml/manual/configure.xml
> index 8b3b8cab8c7..7ff07aea886 100644
> --- a/libstdc++-v3/doc/xml/manual/configure.xml
> +++ b/libstdc++-v3/doc/xml/manual/configure.xml
> @@ -362,7 +362,10 @@
>   built.  The C++ Standard also describes a
>   freestanding environment, in which only a
>   minimal set of headers are provided.  This option builds such an
> - environment.
> + environment.  Note that a hosted library installs headers that still can
> + be used in non hosted environments, as the library checks for
> + __STDC_HOSTED__, however, a library configured with
> + --disable-hosted-libstdcxx will not install unusable 
> headers.
>   
>   
>
> diff --git a/libstdc++-v3/doc/xml/manual/status_cxx2023.xml 
> b/libstdc++-v3/doc/xml/manual/status_cxx2023.xml
> index 365df505f54..f23c64d6a29 100644
> --- a/libstdc++-v3/doc/xml/manual/status_cxx2023.xml
> +++ b/libstdc++-v3/doc/xml/manual/status_cxx2023.xml
> @@ -566,6 +566,17 @@ or any notes about the implementation.
>
>  
>
> +
> +   Easy [utilities], [ranges], and [iterators] 
> +  
> +http://www.w3.org/1999/xlink"; 
> xlink:href="https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2022/p1642r11.html";>
> +P1642R11
> +
> +  
> +   13.1 
> +  
> +
> +
>
>  
>  
> diff --git a/libstdc++-v3/doc/xml/manual/test.xml 
> b/libstdc++-v3/doc/xml/manual/test.xml
> index 7bc6e339723..964c53d2632 100644
> --- a/libstdc++-v3/doc/xml/manual/test.xml
> +++ b/libstdc++-v3/doc/xml/manual/test.xml
> @@ -350,6 +350,20 @@ cat 27_io/objects/char/3_xin.in | a.out
>  
>  
>
> +
> +  If you wish to run the testsuite in a freestanding configuration, you 
> can
> +  pass the -ffreestanding flag.  Doing so will run the tests
> +  that do not require hosted features, and emit a
> +  UNSUPPORTED for those that do.  To run tests in the
> +  freestanding configuration, you still need to build for a target you 
> can
> +  run programs on, e.g. x86_64-pc-linux-gnu, as a few tests
> +  still execute the code they build.  Here's an example of how to run the
> +  testsuite with libstdc++ in freestanding mode:
> +  
> +make check-target-libstdc++-v3 
> RUNTESTFLAGS='--target_board=unix/-ffreestanding'
> +  
> +
> +
>  
>You can run the tests with a compiler and library that have
>already been installed.  Make sure that the compiler (e.g.,
> diff --git a/libstdc++-v3/doc/xml/manual/using.xml 
> b/libstdc++-v3/doc/xml/manual/using.xml
> index 9c444dd2997..7f011a6d931 100644
> --- a/libstdc++-v3/doc/xml/manual/using.xml
> +++ b/libstdc++-v3/doc/xml/manual/using.xml
> @@ -132,6 +132,17 @@
>
>  
>
> +
> +  -ffreestanding
> +  
> +   Limits the library to its freestanding subset.  Headers that are
> +   not supported in freestanding will emit a "This header is not 
> available
> +   in freestanding mode" error.
> +   Headers that are in the freestanding subset partially will not expose
> +   functionality that is not part of the freestanding subset.
> +  
> +
> +
>
>
>  
> @@ -1523,19 +1534,60 @@ namespace gtk
> 
>
>
> -   There exists a library that offers runtime support for
> -   just these headers, and it is called
> -   libsupc++.a. To use it, 
> compile with gcc instead of g++, like 
> so:
> +  
> +   As of GCC 13, libstdc++ implements P1642, which brings in many more
> +   headers, as well a quite a few ones not covered by the paper.
> +
> + 

[pushed] wwwdocs: readings: Update reference for Blackfin

[Gerald Pfeifer]

For once a vendor link that got shorter. :-)

Pushed.

Gerald

---
 htdocs/readings.html | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/htdocs/readings.html b/htdocs/readings.html
index 4bad7e26..29368a9a 100644
--- a/htdocs/readings.html
+++ b/htdocs/readings.html
@@ -94,7 +94,7 @@ names.
 
  Blackfin
   Manufacturer: Analog Devices
-  https://www.analog.com/en/products/processors-microcontrollers/processors-dsp/blackfin-embedded-processors.html";>Blackfin
 Documentation
+  https://www.analog.com/en/product-category/blackfin-embedded-processors.html";>Blackfin
 Documentation
  
 
  c4x
-- 
2.39.1

[pushed] wwwdocs: projects/tree-ssa: Use our own copy of GCC Summit 2007 proceedings

[Gerald Pfeifer]

gccsummit.org is gone with the wind; luckily we have our own copy of the 
2006 proceedings.

If any of you has copies of 2007 and later, can you please drop  me a 
copy and I'll put them on gcc.gnu.org as well?

Pushed.

Gerald
---
 htdocs/projects/tree-ssa/vectorization.html | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/htdocs/projects/tree-ssa/vectorization.html 
b/htdocs/projects/tree-ssa/vectorization.html
index 93fe7448..8a177322 100644
--- a/htdocs/projects/tree-ssa/vectorization.html
+++ b/htdocs/projects/tree-ssa/vectorization.html
@@ -1566,8 +1566,7 @@ while (*p != NULL) {
 
 "Autovectorization in GCC - two years later", Dorit Nuzman and 
Ayal Zaks, 
 GCC summit, June 2006.
-http://www.gccsummit.org/2006/2006-GCC-Summit-Proceedings.pdf";>
-http://www.gccsummit.org/2006/2006-GCC-Summit-Proceedings.pdf
+   https://gcc.gnu.org/pub/gcc/summit/2006-GCC-Summit-Proceedings.pdf";>GCC 
Summit 2006 Proceedings
 
"Auto-Vectorization of Interleaved Data for SIMD",
Dorit Nuzman, Ira Rosen and Ayal Zaks. 
-- 
2.39.1

[PATCH] Fortran: ASSOCIATE variables should not be TREE_STATIC [PR95107]

[Harald Anlauf via Gcc-patches]

Dear all,

as the PR shows, it is likely not a good idea to try to make an
ASSOCIATE variable static when -fno-automatic is specified, so
rather keep it on the stack.

Attached patch regtested on x86_64-pc-linux-gnu.  OK for mainline?

Thanks,
Harald

From c29eb3dbe8c541ef83d5fdf12cafa015ed9447ee Mon Sep 17 00:00:00 2001
From: Harald Anlauf 
Date: Mon, 6 Feb 2023 20:59:51 +0100
Subject: [PATCH] Fortran: ASSOCIATE variables should not be TREE_STATIC
 [PR95107]

gcc/fortran/ChangeLog:

	PR fortran/95107
	* trans-decl.cc (gfc_finish_var_decl): With -fno-automatic, do not
	make ASSOCIATE variables TREE_STATIC.

gcc/testsuite/ChangeLog:

	PR fortran/95107
	* gfortran.dg/save_7.f90: New test.
---
 gcc/fortran/trans-decl.cc|  1 +
 gcc/testsuite/gfortran.dg/save_7.f90 | 17 +
 2 files changed, 18 insertions(+)
 create mode 100644 gcc/testsuite/gfortran.dg/save_7.f90

diff --git a/gcc/fortran/trans-decl.cc b/gcc/fortran/trans-decl.cc
index 7a077801919..f7a7ff607cd 100644
--- a/gcc/fortran/trans-decl.cc
+++ b/gcc/fortran/trans-decl.cc
@@ -742,6 +742,7 @@ gfc_finish_var_decl (tree decl, gfc_symbol * sym)
   /* Keep variables larger than max-stack-var-size off stack.  */
   if (!(sym->ns->proc_name && sym->ns->proc_name->attr.recursive)
   && !sym->attr.automatic
+  && !sym->attr.associate_var
   && sym->attr.save != SAVE_EXPLICIT
   && sym->attr.save != SAVE_IMPLICIT
   && INTEGER_CST_P (DECL_SIZE_UNIT (decl))
diff --git a/gcc/testsuite/gfortran.dg/save_7.f90 b/gcc/testsuite/gfortran.dg/save_7.f90
new file mode 100644
index 000..dfbef12bec0
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/save_7.f90
@@ -0,0 +1,17 @@
+! { dg-do compile }
+! { dg-options "-O2 -fno-automatic" }
+!
+! PR fortran/95107 - do not make associate variables TREE_STATIC
+! Contributed by G.Steinmetz
+
+program p
+  type t
+ real, pointer :: a => null()
+  end type
+  type t2
+ type(t) :: b(1)
+  end type
+  type(t2), save :: x
+  associate (y => x%b)
+  end associate
+end
--
2.35.3

Re: [PATCH 0/2] Repost of patches for solving the build on Fedora 36 problem

[Peter Bergner via Gcc-patches]

On 2/3/23 1:42 AM, Richard Biener wrote:
> On Fri, Feb 3, 2023 at 6:44 AM Michael Meissner via Gcc-patches
>  wrote:
>>
>> I'm reposting these two patches that allow GCC to build on Fedora 36 just to 
>> be
>> clear which patches I'm talking about.  The issue is that if GCC is 
>> configured
>> with long double using the IEEE 128-bit representation, it currently cannot
>> build _mulkc3 and _divkc3 in libgcc.
> 
> It's interesting that we do not see this with openSUSE where I configure with
> 
> --with-cpu=power8 --with-tune=power9 --with-long-double-format=ieee
> --with-long-double-128
> 
> note this is ppc64le, we leave ppc64 and ppc with their default.

That's strange, Bill just retested on our ppc64le openSUSE Tumbleweed system
using basically the same configure options and sees the ICE:

/home/seurer/gcc/git/gcc-trunk/libgcc/config/rs6000/_mulkc3.c: In function 
'__mulkc3_sw':
/home/seurer/gcc/git/gcc-trunk/libgcc/config/rs6000/_mulkc3.c:97:1: internal 
compiler error: in fold_stmt, at gimple-range-fold.cc:522

He did not specify --with=cpu= or --with-tune=, which means he got
power8 defaults for both of those.  It's hard for me to believe that
--with-tune=power9 could hide the issue, but we'll try that configuration
too.  Do you have any other configure options that might affect things?

Peter

Re: [PATCH 0/8] PowerPC future support for Dense Math

[Peter Bergner via Gcc-patches]

On 2/6/23 1:25 AM, Richard Biener wrote:
> May I ask to consider delaying this to stage1 exactly because of this
> last reason?

That is our plan.  We're just still working through the review so it's
ready when stage1 opens up.

Peter

Re: [PATCH] c++: equivalence of non-dependent calls [PR107461]

[Marek Polacek via Gcc-patches]

On Sat, Feb 04, 2023 at 06:02:46PM -0800, Jason Merrill via Gcc-patches wrote:
> On 2/4/23 20:41, Jason Merrill wrote:
> > On 2/4/23 20:08, Patrick Palka wrote:
> > > On Sat, 4 Feb 2023, Jason Merrill wrote:
> > > > > diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
> > > > > index 255332dc0c1..c9360240cd2 100644
> > > > > --- a/gcc/cp/pt.cc
> > > > > +++ b/gcc/cp/pt.cc
> > > > > @@ -1841,6 +1841,7 @@ iterative_hash_template_arg (tree arg,
> > > > > hashval_t val)
> > > > >    case CALL_EXPR:
> > > > >  {
> > > > >    tree fn = CALL_EXPR_FN (arg);
> > > > > +    if (TREE_TYPE (arg) == NULL_TREE)
> > > > 
> > > > How about changing dependent_name to take the CALL_EXPR rather than the
> > > > CALL_EXPR_FN?  That would mean some changes to write_expression
> > > > to move the
> > > > dependent_name handling into the CALL_EXPR handling, but that
> > > > doesn't seem
> > > > like a bad thing.  Other callers seem like a trivial change.
> > > 
> > > Indeed changing dependent_name seems best, but I'm worried about such a
> > > refactoring to write_expression causing unintended mangling changes at
> > > this stage.  Because it seems the CALL_EXPR case of write_expression
> > > isn't the user of the dependent_name branch of write_expression, at
> > > least according to the following patch which causes us to ICE on
> > > mangle{37,57,58,76}.C:
> > 
> > Yeah, I tried the same thing.  Maybe for GCC 13 better to add a new
> > function rather than change the current one.
> 
> mangle76 seems like a bug where we're producing (and testing for) the wrong
> mangling -- mangling (*this). that doesn't exist in the source. clang gets
> it right.

Yes, this is https://gcc.gnu.org/PR98756.
 
> mangle5{7,8} has the right mangling, we're just using dependent_name to
> mangle function names that aren't dependent names (because they're template
> arguments in both cases, and qualified in the latter).

Marek

[committed] amdgcn: Pass -mstack-size through to runtime

[Andrew Stubbs]

The -mstack-size option has been marked obsolete in favour of setting an 
environment variable at runtime ("GCN_STACK_SIZE"), but some testcases 
still need the option set or they have stack overflow. I could change 
them to use the envvar, but my testing setup uses remote execute which 
doesn't support that yet, and means I would skip my own tests (not ideal).


This patch causes the testcase to automatically set GCN_STACK_SIZE 
itself, in a hidden constructor (only if it's not already set), and 
therefore bypasses the problem. I'm leaving the documentation saying 
-mstack-size is obsolete because this fix only works for offload tests, 
and it's still not the preferred user solution.


Committed to mainline. I'll backport to OG12 shortly.

Andrewamdgcn: Pass -mstack-size through to runtime

But only for the offload case.

gcc/ChangeLog:

* config/gcn/mkoffload.cc (gcn_stack_size): New global variable.
(process_asm): Create a constructor for GCN_STACK_SIZE.
(main): Parse the -mstack-size option.

diff --git a/gcc/config/gcn/mkoffload.cc b/gcc/config/gcn/mkoffload.cc
index 9c262f974be..9493f89fec3 100644
--- a/gcc/config/gcn/mkoffload.cc
+++ b/gcc/config/gcn/mkoffload.cc
@@ -117,6 +117,8 @@ uint32_t elf_arch = EF_AMDGPU_MACH_AMDGCN_GFX803;  // 
Default GPU architecture.
 uint32_t elf_flags =
 (EF_AMDGPU_FEATURE_XNACK_ANY_V4 | EF_AMDGPU_FEATURE_SRAMECC_ANY_V4);
 
+static int gcn_stack_size = 0;  /* Zero means use default.  */
+
 /* Delete tempfiles.  */
 
 void
@@ -662,6 +664,18 @@ process_asm (FILE *in, FILE *out, FILE *cfile)
 }
   fprintf (cfile, "\n};\n\n");
 
+  /* Set the stack size if the user configured a value.  */
+  if (gcn_stack_size)
+fprintf (cfile,
+"static __attribute__((constructor))\n"
+"void configure_stack_size (void)\n"
+"{\n"
+"  const char *val = getenv (\"GCN_STACK_SIZE\");\n"
+"  if (!val || val[0] == '\\0')\n"
+"setenv (\"GCN_STACK_SIZE\", \"%d\", true);\n"
+"}\n\n",
+gcn_stack_size);
+
   obstack_free (&fns_os, NULL);
   for (i = 0; i < dims_count; i++)
 free (dims[i].name);
@@ -920,6 +934,10 @@ main (int argc, char **argv)
elf_arch = EF_AMDGPU_MACH_AMDGCN_GFX908;
   else if (strcmp (argv[i], "-march=gfx90a") == 0)
elf_arch = EF_AMDGPU_MACH_AMDGCN_GFX90a;
+#define STR "-mstack-size="
+  else if (startswith (argv[i], STR))
+   gcn_stack_size = atoi (argv[i] + strlen (STR));
+#undef STR
 }
 
   if (!(fopenacc ^ fopenmp))

[PATCH] lto-wrapper: Pass through -funwind-tables and -fasynchronous-unwind-tables

[Andreas Schwab via Gcc-patches]

The -funwind-tables and -fasynchronous-unwind-tables options are relevant
for the output pass, so they need to be passed through by the LTO wrapper.
Otherwise, dwarf2out_assembly_start may output a ".cfi_sections
.debug_frame" directive when debug info was enabled even if every
translation unit was compiled with -funwind-tables.

gcc/
* lto-wrapper.cc (merge_and_complain): Handle
-funwind-tables and -fasynchronous-unwind-tables.
(append_compiler_options): Likewise.
---
 gcc/lto-wrapper.cc | 4 
 1 file changed, 4 insertions(+)

diff --git a/gcc/lto-wrapper.cc b/gcc/lto-wrapper.cc
index 11c4d1b38a4..fe8c5f6e80d 100644
--- a/gcc/lto-wrapper.cc
+++ b/gcc/lto-wrapper.cc
@@ -335,6 +335,8 @@ merge_and_complain (vec &decoded_options,
 
case OPT_fopenmp:
case OPT_fopenacc:
+   case OPT_fasynchronous_unwind_tables:
+   case OPT_funwind_tables:
  /* For selected options we can merge conservatively.  */
  if (existing_opt == -1)
decoded_options.safe_push (*foption);
@@ -737,6 +739,8 @@ append_compiler_options (obstack *argv_obstack, 
vec opts)
case OPT_fopenacc_dim_:
case OPT_foffload_abi_:
case OPT_fcf_protection_:
+   case OPT_fasynchronous_unwind_tables:
+   case OPT_funwind_tables:
case OPT_g:
case OPT_O:
case OPT_Ofast:
-- 
2.39.1


-- 
Andreas Schwab, SUSE Labs, sch...@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."

Re: [PATCH] aarch64: Fix return_address_sign_ab_exception.C regression

[Richard Sandiford via Gcc-patches]

Andrea Corallo via Gcc-patches  writes:
> Hi all,
>
> this is to fix the regression of
> g++.target/aarch64/return_address_sign_ab_exception.C that I
> introduced with d8dadbc9a5199bf7bac1ab7376b0f84f45e94350.
>
> 'aarch_ra_sign_key' for aarch64 ended up being non defined in the opt
> file and the function attribute "branch-protection=pac-ret+leaf+b-key"
> stopped working as expected.
>
> This patch moves the definition of 'aarch_ra_sign_key' to the opt
> files for both Arm back-ends.
>
> Regards
>
>   Andera Corallo
>
> gcc/ChangeLog:
>
>   * config/aarch64/aarch64-protos.h (aarch_ra_sign_key): Remove
>   declaration.
>   * config/aarch64/aarch64.cc (aarch_ra_sign_key): Remove
>   definition.
>   * config/aarch64/aarch64.opt (aarch64_ra_sign_key): Rename
>   to 'aarch_ra_sign_key'.
>   * config/arm/aarch-common.cc (aarch_ra_sign_key): Remove
>   declaration.
>   * config/arm/arm-protos.h (aarch_ra_sign_key): Likewise.
>   * config/arm/arm.cc (enum aarch_key_type): Remove definition.
>   * config/arm/arm.opt: Define.

OK, thanks.

Richard

> ---
>  gcc/config/aarch64/aarch64-protos.h | 2 --
>  gcc/config/aarch64/aarch64.cc   | 2 --
>  gcc/config/aarch64/aarch64.opt  | 2 +-
>  gcc/config/arm/aarch-common.cc  | 1 -
>  gcc/config/arm/arm-protos.h | 1 -
>  gcc/config/arm/arm.cc   | 3 ---
>  gcc/config/arm/arm.opt  | 3 +++
>  7 files changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64-protos.h 
> b/gcc/config/aarch64/aarch64-protos.h
> index 6ab6d49af37..f75eb892f3d 100644
> --- a/gcc/config/aarch64/aarch64-protos.h
> +++ b/gcc/config/aarch64/aarch64-protos.h
> @@ -662,8 +662,6 @@ enum simd_immediate_check {
>AARCH64_CHECK_MOV  = AARCH64_CHECK_ORR | AARCH64_CHECK_BIC
>  };
>  
> -extern enum aarch_key_type aarch_ra_sign_key;
> -
>  extern struct tune_params aarch64_tune_params;
>  
>  /* The available SVE predicate patterns, known in the ACLE as "svpattern".  
> */
> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
> index acc0cfe5f94..1b498979af1 100644
> --- a/gcc/config/aarch64/aarch64.cc
> +++ b/gcc/config/aarch64/aarch64.cc
> @@ -2759,8 +2759,6 @@ static const struct processor all_cores[] =
>{NULL, aarch64_none, aarch64_none, aarch64_no_arch, 0, NULL}
>  };
>  
> -enum aarch_key_type aarch_ra_sign_key = AARCH_KEY_A;
> -
>  /* The current tuning set.  */
>  struct tune_params aarch64_tune_params = generic_tunings;
>  
> diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
> index 137e506fe19..1d7967db9c0 100644
> --- a/gcc/config/aarch64/aarch64.opt
> +++ b/gcc/config/aarch64/aarch64.opt
> @@ -40,7 +40,7 @@ TargetVariable
>  unsigned aarch_enable_bti = 2
>  
>  TargetVariable
> -enum aarch64_key_type aarch64_ra_sign_key = AARCH64_KEY_A
> +enum aarch_key_type aarch_ra_sign_key = AARCH_KEY_A
>  
>  ; The TLS dialect names to use with -mtls-dialect.
>  
> diff --git a/gcc/config/arm/aarch-common.cc b/gcc/config/arm/aarch-common.cc
> index 27e6c8f39b4..5b96ff4c2e8 100644
> --- a/gcc/config/arm/aarch-common.cc
> +++ b/gcc/config/arm/aarch-common.cc
> @@ -661,7 +661,6 @@ arm_md_asm_adjust (vec &outputs, vec & 
> /*inputs*/,
>  
>  #define BRANCH_PROTECT_STR_MAX 255
>  extern char *accepted_branch_protection_string;
> -extern enum aarch_key_type aarch_ra_sign_key;
>  
>  static enum aarch_parse_opt_result
>  aarch_handle_no_branch_protection (char* str, char* rest)
> diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
> index aea472bfbb9..c8ae5e1e9c1 100644
> --- a/gcc/config/arm/arm-protos.h
> +++ b/gcc/config/arm/arm-protos.h
> @@ -585,7 +585,6 @@ struct cpu_option
>  extern const arch_option all_architectures[];
>  extern const cpu_option all_cores[];
>  
> -extern enum aarch_key_type aarch_ra_sign_key;
>  
>  const cpu_option *arm_parse_cpu_option_name (const cpu_option *, const char 
> *,
>const char *, bool = true);
> diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
> index efc48349dd3..3d778b2982e 100644
> --- a/gcc/config/arm/arm.cc
> +++ b/gcc/config/arm/arm.cc
> @@ -2420,9 +2420,6 @@ const struct tune_params arm_fa726te_tune =
>tune_params::SCHED_AUTOPREF_OFF
>  };
>  
> -/* Key type for Pointer Authentication extension.  */
> -enum aarch_key_type aarch_ra_sign_key = AARCH_KEY_A;
> -
>  char *accepted_branch_protection_string = NULL;
>  
>  /* Auto-generated CPU, FPU and architecture tables.  */
> diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
> index 260700f16bc..3a49b51ece0 100644
> --- a/gcc/config/arm/arm.opt
> +++ b/gcc/config/arm/arm.opt
> @@ -30,6 +30,9 @@ enum aarch_function_type aarch_ra_sign_scope = 
> AARCH_FUNCTION_NONE
>  TargetVariable
>  unsigned aarch_enable_bti = 0
>  
> +TargetVariable
> +enum aarch_key_type aarch_ra_sign_key = AARCH_KEY_A
> +
>  Enum
>  Name(tls_type) Type(enum arm_tls_type)
>  TLS dialect to use:

[PATCH] aarch64: Fix return_address_sign_ab_exception.C regression

[Andrea Corallo via Gcc-patches]

Hi all,

this is to fix the regression of
g++.target/aarch64/return_address_sign_ab_exception.C that I
introduced with d8dadbc9a5199bf7bac1ab7376b0f84f45e94350.

'aarch_ra_sign_key' for aarch64 ended up being non defined in the opt
file and the function attribute "branch-protection=pac-ret+leaf+b-key"
stopped working as expected.

This patch moves the definition of 'aarch_ra_sign_key' to the opt
files for both Arm back-ends.

Regards

  Andera Corallo

gcc/ChangeLog:

* config/aarch64/aarch64-protos.h (aarch_ra_sign_key): Remove
declaration.
* config/aarch64/aarch64.cc (aarch_ra_sign_key): Remove
definition.
* config/aarch64/aarch64.opt (aarch64_ra_sign_key): Rename
to 'aarch_ra_sign_key'.
* config/arm/aarch-common.cc (aarch_ra_sign_key): Remove
declaration.
* config/arm/arm-protos.h (aarch_ra_sign_key): Likewise.
* config/arm/arm.cc (enum aarch_key_type): Remove definition.
* config/arm/arm.opt: Define.
---
 gcc/config/aarch64/aarch64-protos.h | 2 --
 gcc/config/aarch64/aarch64.cc   | 2 --
 gcc/config/aarch64/aarch64.opt  | 2 +-
 gcc/config/arm/aarch-common.cc  | 1 -
 gcc/config/arm/arm-protos.h | 1 -
 gcc/config/arm/arm.cc   | 3 ---
 gcc/config/arm/arm.opt  | 3 +++
 7 files changed, 4 insertions(+), 10 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-protos.h 
b/gcc/config/aarch64/aarch64-protos.h
index 6ab6d49af37..f75eb892f3d 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -662,8 +662,6 @@ enum simd_immediate_check {
   AARCH64_CHECK_MOV  = AARCH64_CHECK_ORR | AARCH64_CHECK_BIC
 };
 
-extern enum aarch_key_type aarch_ra_sign_key;
-
 extern struct tune_params aarch64_tune_params;
 
 /* The available SVE predicate patterns, known in the ACLE as "svpattern".  */
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index acc0cfe5f94..1b498979af1 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -2759,8 +2759,6 @@ static const struct processor all_cores[] =
   {NULL, aarch64_none, aarch64_none, aarch64_no_arch, 0, NULL}
 };
 
-enum aarch_key_type aarch_ra_sign_key = AARCH_KEY_A;
-
 /* The current tuning set.  */
 struct tune_params aarch64_tune_params = generic_tunings;
 
diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
index 137e506fe19..1d7967db9c0 100644
--- a/gcc/config/aarch64/aarch64.opt
+++ b/gcc/config/aarch64/aarch64.opt
@@ -40,7 +40,7 @@ TargetVariable
 unsigned aarch_enable_bti = 2
 
 TargetVariable
-enum aarch64_key_type aarch64_ra_sign_key = AARCH64_KEY_A
+enum aarch_key_type aarch_ra_sign_key = AARCH_KEY_A
 
 ; The TLS dialect names to use with -mtls-dialect.
 
diff --git a/gcc/config/arm/aarch-common.cc b/gcc/config/arm/aarch-common.cc
index 27e6c8f39b4..5b96ff4c2e8 100644
--- a/gcc/config/arm/aarch-common.cc
+++ b/gcc/config/arm/aarch-common.cc
@@ -661,7 +661,6 @@ arm_md_asm_adjust (vec &outputs, vec & /*inputs*/,
 
 #define BRANCH_PROTECT_STR_MAX 255
 extern char *accepted_branch_protection_string;
-extern enum aarch_key_type aarch_ra_sign_key;
 
 static enum aarch_parse_opt_result
 aarch_handle_no_branch_protection (char* str, char* rest)
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index aea472bfbb9..c8ae5e1e9c1 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -585,7 +585,6 @@ struct cpu_option
 extern const arch_option all_architectures[];
 extern const cpu_option all_cores[];
 
-extern enum aarch_key_type aarch_ra_sign_key;
 
 const cpu_option *arm_parse_cpu_option_name (const cpu_option *, const char *,
 const char *, bool = true);
diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index efc48349dd3..3d778b2982e 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -2420,9 +2420,6 @@ const struct tune_params arm_fa726te_tune =
   tune_params::SCHED_AUTOPREF_OFF
 };
 
-/* Key type for Pointer Authentication extension.  */
-enum aarch_key_type aarch_ra_sign_key = AARCH_KEY_A;
-
 char *accepted_branch_protection_string = NULL;
 
 /* Auto-generated CPU, FPU and architecture tables.  */
diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
index 260700f16bc..3a49b51ece0 100644
--- a/gcc/config/arm/arm.opt
+++ b/gcc/config/arm/arm.opt
@@ -30,6 +30,9 @@ enum aarch_function_type aarch_ra_sign_scope = 
AARCH_FUNCTION_NONE
 TargetVariable
 unsigned aarch_enable_bti = 0
 
+TargetVariable
+enum aarch_key_type aarch_ra_sign_key = AARCH_KEY_A
+
 Enum
 Name(tls_type) Type(enum arm_tls_type)
 TLS dialect to use:
-- 
2.25.1

RE: [DOC PATCH] Document the VEC_PERM_EXPR tree code (and minor clean-ups).

[Roger Sayle]

Perhaps I'm missing something (I'm not too familiar with SVE semantics), but
is there
a reason that the solution for PR96473 uses a VEC_PERM_EXPR and not just a 
VEC_DUPLICATE_EXPR?  The folding of sv1d1rq (svptrue_..., ...) doesn't seem
to
require either the blending or the permutation functionality of a
VEC_PERM_EXPR.
Instead, it seems to be misusing (the modified) VEC_PERM_EXPR as a form of
VIEW_CONVERT_EXPR that allows us to convert/mismatch the type of the
operands
to the type of the result.

Conceptually, (as in Richard's original motivation for the PR),
svint32_t foo (int32x4_t x) { return svld1rq (svptrue_b8 (), &x[0]); }
can be optimized to (something like)
svint32_t foo (int32x4_t x) { return svdup_32 (x[0]); }  // or dup z0.q,
z0.q[0] equivalent
hence it makes sense for fold to transform the gimple form of the first,
into the
gimple form of the second(?)

Just curious.
Roger
--

> -Original Message-
> From: Richard Sandiford 
> Sent: 06 February 2023 12:22
> To: Richard Biener 
> Cc: Roger Sayle ; GCC Patches  patc...@gcc.gnu.org>
> Subject: Re: [DOC PATCH] Document the VEC_PERM_EXPR tree code (and minor
> clean-ups).
> 
> Richard Biener  writes:
> > On Sat, Feb 4, 2023 at 9:35 PM Roger Sayle 
> wrote:
> >>
> >>
> >> This patch (primarily) documents the VEC_PERM_EXPR tree code in
> >> generic.texi.  For ease of review, it is provided below as a pair of
> >> diffs.  The first contains just the new text added to describe
> >> VEC_PERM_EXPR, the second tidies up this part of the documentation by
> >> sorting the tree codes into alphabetical order, and providing
> >> consistent section naming/capitalization, so changing this section
> >> from "Vectors" to "Vector Expressions" (matching the nearby "Unary
> >> and Binary Expressions").
> >>
> >> Tested with make pdf and make html on x86_64-pc-linux-gnu.
> >> The reviewer(s) can decide whether to approve just the new content,
> >> or the content+clean-up.  Ok for mainline?
> >
> > +@item VEC_PERM_EXPR
> > +This node represents a vector permute/blend operation.  The three
> > +operands must be vectors of the same number of elements.  The first
> > +and second operands must be vectors of the same type as the entire
> > +expression,
> >
> > this was recently relaxed for the case of constant permutes in which
> > case the first and second operands only have to have the same element
> > type as the result.  See tree-cfg.cc:verify_gimple_assign_ternary.
> >
> > The following description will become a bit more awkward here and for
> > rhs1/rhs2 with different number of elements the modulo interpretation
> > doesn't hold - I believe we require in-bounds elements for constant
> > permutes.  Richard can probably clarify things here.
> 
> I thought that the modulo behaviour still applies when the node has a
constant
> selector, it's just that the in-range form is the canonical one.
> 
> With variable-length vectors, I think it's in principle possible to have a
stepped
> constant selector whose start elements are in-range but whose final
elements
> aren't (and instead wrap around when applied).
> E.g. the selector could zip the last quarter of the inputs followed by the
first
> quarter.
> 
> Thanks,
> Richard

Re: [PATCH 1/2] Handle component_ref to a structre/union field including flexible array member [PR101832]

[Qing Zhao via Gcc-patches]

> On Feb 6, 2023, at 4:31 AM, Richard Biener  wrote:
> 
> On Fri, 3 Feb 2023, Qing Zhao wrote:
> 
>> 
>> 
>>> On Feb 3, 2023, at 2:49 AM, Richard Biener  wrote:
>>> 
>>> On Thu, 2 Feb 2023, Qing Zhao wrote:
>>> 
 
 
> On Feb 2, 2023, at 8:54 AM, Richard Biener  wrote:
> 
> On Thu, 2 Feb 2023, Qing Zhao wrote:
> 
>> 
>> 
>>> 
>>> [...]
>>> 
>> +return flexible_size_type_p (TREE_TYPE (last));
> 
> For types with many members this can become quite slow (IIRC we had
> bugs about similar walks of all fields in types), and this function
> looks like it's invoked multiple times on the same type per TU.
> 
> In principle the property is fixed at the time we lay out a record
> type, so we might want to compute it at that time and record the
> result.
 
 You mean in FE? 
>>> 
>>> Yes, either in the frontend or in the middle-ends layout_type.
>>> 
 Yes, that?s better and cleaner.
 
 I will add one more field in the TYPE structure to record this 
 information and check this field during middle end.
 
 I had the same thought in the beginning, but not sure whether adding a 
 new field in IR is necessary or not, other places in middle end might 
 not use this new field.
>>> 
>>> It might be interesting to search for other code walking all fields of
>>> a type to determine this or similar info.
>> 
>> There is one which is defined in tree.cc but only is referenced in 
>> c/c-decl.cc:
>> 
>> /* Determine whether TYPE is a structure with a flexible array member,
>> or a union containing such a structure (possibly recursively).  */
>> flexible_array_type_p
>> 
>> However, this routine is a little different than the one I tried to add:
>> 
>> In the current routine ?flexible_array_type_p?,  only one level nesting 
>> in the structure is accepted, multiple nesting in structure is not 
>> permitted.
>> 
>> So, my question is:  shall we accept multiple nesting in structure? i.e.
> 
> If we don't reject the testcase with an error, then yes.
 
 Gcc currently accepts the multiple nesting in structure without error.  
 So, we will continue to accept such extension as long as the flex array 
 is at the end of the structure. At the same time, for the case the flex 
 array is in the middle of the structure, issue additional warnings now 
 to discourage such usage, and deprecate this case in a future release.
 
 Does this sound reasonable? 
>>> 
>>> Please don't mix several issues - I think the flex array in the
>>> middle of a structure is separate and we shouldn't report that
>>> as flexible_array_type_p or flexible_size_type_p since the size
>>> of the containing structure is not variable.
>> Agreed on this.
>> 
>> My major question here is (for documentation change, sorry for mixing 
>> this thread with the documentation change): do we need to document this 
>> case together with the case in which struct with flex array is embedded 
>> into another structure? (As a GCC extension?)
> 
> I think this should be Josephs call - documenting this might
> encourage people to use such an extension, even if it's a bad
> one we want to get rid of.
That’s true...
> 
> Maybe the easiest thing is to come up with a patch documenting it
> which we can then turn into a deprecation note depending on this
> outcome.

In the other thread for the documentation change, I have listed a plan based on 
the discussion.
 Could you please take a look at it and provide me some comments in that 
thread? (I just copied my 
plan below for your convenience)

Thanks.

Qing

==

In GCC13:

1. Add documentation in extend.texi to include all the following 3 cases as GCC 
extension:

Case 1: The structure with a flexible array member is the last field of another
structure, for example:

struct flex  { int length; char data[]; }
struct out_flex { int m; struct flex flex_data; }

In the above, flex_data.data[] is considered as a flexible array too.

Case 2: The structure with a flexible array member is the field of another 
union, for example:

struct flex1  { int length1; char data1[]; }
struct flex2  { int length2; char data2[]; }
union out_flex { struct flex1 flex_data1; struct flex2 flex_data2; }

In the above, flex_data1.data1[] or flex_data2.data2[] is considered as 
flexible arrays too.

Case 3: The structure with a flexible array member is the middle field of 
another
structure, for example:

struct flex  { int length; char data[]; }
struct out_flex { int m; struct flex flex_data; int n; }

In the above, flex_data.data[] is allowed to be extended flexibly to
the padding. E.g, up to 4 elements.

However, relying on space in struct padding is a bad programming practice,  
compilers do not 
handle such extension consistently, and any code rely

[committed] libstdc++: Fix testsuite warnings about new C++23 deprecations

[Jonathan Wakely via Gcc-patches]

Tested powerpc64le-linux. Pushed to trunk.

-- >8 --

With the recent change to deprecate std::aligned_storage and
std::aligned_union we need to adjust some tests that now fail with
-std=c++23.

libstdc++-v3/ChangeLog:

* include/std/type_traits: Add diagnostic pragmas around
references to deprecated std::aligned_storage and
std::aligned_union traits.
* testsuite/20_util/aligned_storage/requirements/alias_decl.cc:
Add dg-warning for et c++23.
* 
testsuite/20_util/aligned_storage/requirements/explicit_instantiation.cc:
Likewise.
* testsuite/20_util/aligned_storage/value.cc: Likewise.
* testsuite/20_util/aligned_union/1.cc: Likewise.
* testsuite/20_util/aligned_union/requirements/alias_decl.cc:
Likewise.
---
 libstdc++-v3/include/std/type_traits   | 7 +++
 .../20_util/aligned_storage/requirements/alias_decl.cc | 3 +++
 .../aligned_storage/requirements/explicit_instantiation.cc | 3 +++
 libstdc++-v3/testsuite/20_util/aligned_storage/value.cc| 2 ++
 libstdc++-v3/testsuite/20_util/aligned_union/1.cc  | 2 ++
 .../20_util/aligned_union/requirements/alias_decl.cc   | 3 +++
 6 files changed, 20 insertions(+)

diff --git a/libstdc++-v3/include/std/type_traits 
b/libstdc++-v3/include/std/type_traits
index d13af433a17..2bd607a8b8f 100644
--- a/libstdc++-v3/include/std/type_traits
+++ b/libstdc++-v3/include/std/type_traits
@@ -2123,6 +2123,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
? sizeof(_Tp) : __strictest_alignment<_Types...>::_S_size;
 };
 
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
+
   /**
*  @brief Provide aligned storage for types.
*
@@ -2155,6 +2158,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 
   template 
 const size_t aligned_union<_Len, _Types...>::alignment_value;
+#pragma GCC diagnostic pop
 
   /// @cond undocumented
 
@@ -2586,6 +2590,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 { } _GLIBCXX17_DEPRECATED_SUGGEST("std::invoke_result");
 
 #if __cplusplus >= 201402L
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
   /// Alias template for aligned_storage
   template::__type)>
@@ -2593,6 +2599,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 
   template 
 using aligned_union_t _GLIBCXX23_DEPRECATED = typename aligned_union<_Len, 
_Types...>::type;
+#pragma GCC diagnostic pop
 
   /// Alias template for decay
   template
diff --git 
a/libstdc++-v3/testsuite/20_util/aligned_storage/requirements/alias_decl.cc 
b/libstdc++-v3/testsuite/20_util/aligned_storage/requirements/alias_decl.cc
index fc230b66a9d..2e8e90efcd7 100644
--- a/libstdc++-v3/testsuite/20_util/aligned_storage/requirements/alias_decl.cc
+++ b/libstdc++-v3/testsuite/20_util/aligned_storage/requirements/alias_decl.cc
@@ -26,3 +26,6 @@ using namespace std;
 static_assert (is_same::type,
   aligned_storage_t<4>>(),
"aligned_storage_t" );
+
+// { dg-warning "deprecated" "" { target c++23 } 26 }
+// { dg-warning "deprecated" "" { target c++23 } 27 }
diff --git 
a/libstdc++-v3/testsuite/20_util/aligned_storage/requirements/explicit_instantiation.cc
 
b/libstdc++-v3/testsuite/20_util/aligned_storage/requirements/explicit_instantiation.cc
index 36dfe04b083..baec6667f30 100644
--- 
a/libstdc++-v3/testsuite/20_util/aligned_storage/requirements/explicit_instantiation.cc
+++ 
b/libstdc++-v3/testsuite/20_util/aligned_storage/requirements/explicit_instantiation.cc
@@ -29,3 +29,6 @@ namespace std
   template struct aligned_storage<1, alignment_of::value>;
   template struct aligned_storage<2>;
 }
+
+// { dg-warning "deprecated" "" { target c++23 } 29 }
+// { dg-warning "deprecated" "" { target c++23 } 30 }
diff --git a/libstdc++-v3/testsuite/20_util/aligned_storage/value.cc 
b/libstdc++-v3/testsuite/20_util/aligned_storage/value.cc
index 16a5580a6b7..6e9df7ffc5d 100644
--- a/libstdc++-v3/testsuite/20_util/aligned_storage/value.cc
+++ b/libstdc++-v3/testsuite/20_util/aligned_storage/value.cc
@@ -59,3 +59,5 @@ void test01()
   static_assert(sizeof(aligned_storage<5>::type) >= 5, "");
   static_assert(__alignof__(aligned_storage<5>::type) == align_msa, "");
 }
+
+// { dg-warning "deprecated" "" { target c++23 } 0 }
diff --git a/libstdc++-v3/testsuite/20_util/aligned_union/1.cc 
b/libstdc++-v3/testsuite/20_util/aligned_union/1.cc
index b779884dcc2..7501529cbf4 100644
--- a/libstdc++-v3/testsuite/20_util/aligned_union/1.cc
+++ b/libstdc++-v3/testsuite/20_util/aligned_union/1.cc
@@ -64,6 +64,8 @@ void test01()
   static_assert(sizeof(au_type2::type) >= max_s+100,
 "Storage size (at least len)");
 }
+// { dg-warning "deprecated" "" { target c++23 } 57 }
+// { dg-warning "deprecated" "" { target c++23 } 62 }
 
 int main()
 {
diff --git 
a/libstdc++-v3/testsuite/20_util/aligned_union/requirements/alias_decl.cc 
b/libstdc++-v3/testsuite/20_util/aligned_union/requirements/alias_decl.cc
index 6790d2

[committed] libstdc++: Fix non-reserved name for template parameter

[Jonathan Wakely via Gcc-patches]

Tested powerpc64le-linux. Pushed to trunk.

-- >8 --

libstdc++-v3/ChangeLog:

* include/bits/ranges_algo.h (__find_last_fn): Rename T to _Tp.
(__find_last_if_fn): Likewise.
---
 libstdc++-v3/include/bits/ranges_algo.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/libstdc++-v3/include/bits/ranges_algo.h 
b/libstdc++-v3/include/bits/ranges_algo.h
index 5577d862cb5..1685e1d85bb 100644
--- a/libstdc++-v3/include/bits/ranges_algo.h
+++ b/libstdc++-v3/include/bits/ranges_algo.h
@@ -3568,10 +3568,10 @@ namespace ranges
 
   struct __find_last_fn
   {
-template _Sent, typename T, 
typename _Proj = identity>
-  requires indirect_binary_predicate, const T*>
+template _Sent, typename _Tp, 
typename _Proj = identity>
+  requires indirect_binary_predicate, const _Tp*>
   constexpr subrange<_Iter>
-  operator()(_Iter __first, _Sent __last, const T& __value, _Proj __proj = 
{}) const
+  operator()(_Iter __first, _Sent __last, const _Tp& __value, _Proj __proj 
= {}) const
   {
if constexpr (same_as<_Iter, _Sent> && bidirectional_iterator<_Iter>)
  {
@@ -3599,10 +3599,10 @@ namespace ranges
  }
   }
 
-template
-  requires indirect_binary_predicate, _Proj>, const T*>
+template
+  requires indirect_binary_predicate, _Proj>, const _Tp*>
   constexpr borrowed_subrange_t<_Range>
-  operator()(_Range&& __r, const T& __value, _Proj __proj = {}) const
+  operator()(_Range&& __r, const _Tp& __value, _Proj __proj = {}) const
   { return (*this)(ranges::begin(__r), ranges::end(__r), __value, 
std::move(__proj)); }
   };
 
-- 
2.39.1

Re: [PATCH] libstdc++: Enable building libstdc++.{a,so} when !HOSTED

[Jonathan Wakely via Gcc-patches]

This is pushed to trunk now.

On Thu, 20 Oct 2022 at 16:53, Arsen Arsenović via Libstdc++
 wrote:
>
> This enables us to provide symbols for placeholders and numeric limits,
> and allows users to mess about with linker flags less.
>
> libstdc++-v3/ChangeLog:
>
> * Makefile.am [!_GLIBCXX_HOSTED]: Enable src/ subdirectory.
> * Makefile.in: Regenerate.
> * src/Makefile.am [!_GLIBCXX_HOSTED]: Omit compatibility files.
> There's no history to be compatible with.
> * src/c++11/Makefile.am [!_GLIBCXX_HOSTED]: Omit hosted-only
> source files from the build.
> * src/c++17/Makefile.am [!_GLIBCXX_HOSTED]: Likewise.
> * src/c++20/Makefile.am [!_GLIBCXX_HOSTED]: Likewise.
> * src/c++98/Makefile.am [!_GLIBCXX_HOSTED]: Likewise.
> * src/Makefile.in: Regenerate.
> * src/c++11/Makefile.in: Regenerate.
> * src/c++17/Makefile.in: Regenerate.
> * src/c++20/Makefile.in: Regenerate.
> * src/c++98/Makefile.in: Regenerate.
> ---
> Afternoon,
>
> With these changes, when we aren't hosted, we get a libstdc++ library that
> contains only library facilities available in freestanding (i.e. placeholders
> and limits.cc).  This is, AFAICT, the only code in libstdc++.{a,so} that can
> (and should) be available in freestanding.
>
> As an implementation note, this could be a little bit faster (at
> build/configure time), though not necessarily nicer, by having
> src/Makefile.am not try to build convenience libraries for versions of
> C++ that provide nothing.  I opted not to do this since it'd make
> src/Makefile.am even more complex, and make future changes harder to 
> implement.
> libstdc++ also isn't that slow to build, anyway.
>
> Tested on i686-elf.
>
> Have a good day!
>
>  libstdc++-v3/Makefile.am   |  4 ++--
>  libstdc++-v3/Makefile.in   |  4 ++--
>  libstdc++-v3/src/Makefile.am   |  6 +
>  libstdc++-v3/src/Makefile.in   |  8 +--
>  libstdc++-v3/src/c++11/Makefile.am | 16 ++---
>  libstdc++-v3/src/c++11/Makefile.in | 37 +++---
>  libstdc++-v3/src/c++17/Makefile.am |  4 
>  libstdc++-v3/src/c++17/Makefile.in |  6 +++--
>  libstdc++-v3/src/c++20/Makefile.am |  4 
>  libstdc++-v3/src/c++20/Makefile.in |  6 +++--
>  libstdc++-v3/src/c++98/Makefile.am |  4 
>  libstdc++-v3/src/c++98/Makefile.in |  6 +++--
>  12 files changed, 77 insertions(+), 28 deletions(-)
>
> diff --git a/libstdc++-v3/Makefile.am b/libstdc++-v3/Makefile.am
> index 0d147ad3ffe..d7f2b6e76a5 100644
> --- a/libstdc++-v3/Makefile.am
> +++ b/libstdc++-v3/Makefile.am
> @@ -24,11 +24,11 @@ include $(top_srcdir)/fragment.am
>
>  if GLIBCXX_HOSTED
>  ## Note that python must come after src.
> -  hosted_source = src doc po testsuite python
> +  hosted_source = doc po testsuite python
>  endif
>
>  ## Keep this list sync'd with acinclude.m4:GLIBCXX_CONFIGURE.
> -SUBDIRS = include libsupc++ $(hosted_source)
> +SUBDIRS = include libsupc++ src $(hosted_source)
>
>  ACLOCAL_AMFLAGS = -I . -I .. -I ../config
>
> diff --git a/libstdc++-v3/src/Makefile.am b/libstdc++-v3/src/Makefile.am
> index b83c222d51d..4eb78e76297 100644
> --- a/libstdc++-v3/src/Makefile.am
> +++ b/libstdc++-v3/src/Makefile.am
> @@ -121,7 +121,13 @@ cxx11_sources = \
> ${cxx0x_compat_sources} \
> ${ldbl_alt128_compat_sources}
>
> +if GLIBCXX_HOSTED
>  libstdc___la_SOURCES = $(cxx98_sources) $(cxx11_sources)
> +else
> +# When freestanding, there's currently no compatibility to preserve.  Should
> +# that change, any compatibility sources can be added here.
> +libstdc___la_SOURCES =
> +endif
>
>  libstdc___la_LIBADD = \
> $(GLIBCXX_LIBS) \
> diff --git a/libstdc++-v3/src/c++11/Makefile.am 
> b/libstdc++-v3/src/c++11/Makefile.am
> index ecd46aafc01..72f05100c98 100644
> --- a/libstdc++-v3/src/c++11/Makefile.am
> +++ b/libstdc++-v3/src/c++11/Makefile.am
> @@ -51,6 +51,10 @@ else
>  cxx11_abi_sources =
>  endif
>
> +sources_freestanding = \
> +   limits.cc \
> +   placeholders.cc
> +
>  sources = \
> chrono.cc \
> codecvt.cc \
> @@ -66,9 +70,7 @@ sources = \
> hashtable_c++0x.cc \
> ios.cc \
> ios_errcat.cc \
> -   limits.cc \
> mutex.cc \
> -   placeholders.cc \
> random.cc \
> regex.cc  \
> shared_ptr.cc \
> @@ -118,7 +120,15 @@ endif
>
>  vpath % $(top_srcdir)/src/c++11
>
> -libc__11convenience_la_SOURCES = $(sources)  $(inst_sources)
> +if !GLIBCXX_HOSTED
> +libc__11convenience_la_SOURCES = $(sources_freestanding)
> +else
> +libc__11convenience_la_SOURCES = \
> +   $(sources_freestanding) \
> +   $(sources) \
> +   $(inst_sources)
> +endif
> +
>
>  # Use special rules for the hashtable.cc file so that all
>  # the generated template functions are also instantiated.
> diff --git a/libstdc++-v3/src/c++17/Makefile.am 
> b/libstdc++-v3/src/c++17/Makefile.am
> index 3d53f652fac..72095f5b087 100644
> --- a/libstdc

[committed] libstdc++: Disable building additional archives for freestanding

[Jonathan Wakely via Gcc-patches]

Tested powerpc64le-linux. Pushed to trunk.

-- >8 --

This doesn't have any effect yet as we never build anything under
libstdc++-v3/src for freestanding, but that will change in the next
commit.

libstdc++-v3/ChangeLog:

* src/Makefile.am [GLIBCXX_HOSTED] (SUBDIRS): Do not add
filesystem, libbacktrace and experimental.
* src/Makefile.in: Regenerate.
---
 libstdc++-v3/src/Makefile.am | 10 +-
 libstdc++-v3/src/Makefile.in | 14 +-
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/libstdc++-v3/src/Makefile.am b/libstdc++-v3/src/Makefile.am
index 53fc3d0a987..97a5363b40a 100644
--- a/libstdc++-v3/src/Makefile.am
+++ b/libstdc++-v3/src/Makefile.am
@@ -22,6 +22,7 @@
 
 include $(top_srcdir)/fragment.am
 
+if GLIBCXX_HOSTED
 if ENABLE_FILESYSTEM_TS
 filesystem_dir = filesystem
 else
@@ -34,8 +35,15 @@ else
 backtrace_dir =
 endif
 
+experimental_dir = experimental
+else
+filesystem_dir =
+backtrace_dir =
+experimental_dir =
+endif
+
 ## Keep this list sync'd with acinclude.m4:GLIBCXX_CONFIGURE.
-SUBDIRS = c++98 c++11 c++17 c++20 $(filesystem_dir) $(backtrace_dir) 
experimental
+SUBDIRS = c++98 c++11 c++17 c++20 $(filesystem_dir) $(backtrace_dir) 
$(experimental_dir)
 
 # Cross compiler support.
 if VTV_CYGMIN
diff --git a/libstdc++-v3/src/Makefile.in b/libstdc++-v3/src/Makefile.in
index c556d0dee1b..e38b70df9fb 100644
--- a/libstdc++-v3/src/Makefile.in
+++ b/libstdc++-v3/src/Makefile.in
@@ -482,11 +482,15 @@ WARN_CXXFLAGS = \
 
 # -I/-D flags to pass when compiling.
 AM_CPPFLAGS = $(GLIBCXX_INCLUDES) $(CPPFLAGS)
-@ENABLE_FILESYSTEM_TS_FALSE@filesystem_dir = 
-@ENABLE_FILESYSTEM_TS_TRUE@filesystem_dir = filesystem
-@ENABLE_BACKTRACE_FALSE@backtrace_dir = 
-@ENABLE_BACKTRACE_TRUE@backtrace_dir = libbacktrace
-SUBDIRS = c++98 c++11 c++17 c++20 $(filesystem_dir) $(backtrace_dir) 
experimental
+@ENABLE_FILESYSTEM_TS_FALSE@@GLIBCXX_HOSTED_TRUE@filesystem_dir = 
+@ENABLE_FILESYSTEM_TS_TRUE@@GLIBCXX_HOSTED_TRUE@filesystem_dir = filesystem
+@GLIBCXX_HOSTED_FALSE@filesystem_dir = 
+@ENABLE_BACKTRACE_FALSE@@GLIBCXX_HOSTED_TRUE@backtrace_dir = 
+@ENABLE_BACKTRACE_TRUE@@GLIBCXX_HOSTED_TRUE@backtrace_dir = libbacktrace
+@GLIBCXX_HOSTED_FALSE@backtrace_dir = 
+@GLIBCXX_HOSTED_FALSE@experimental_dir = 
+@GLIBCXX_HOSTED_TRUE@experimental_dir = experimental
+SUBDIRS = c++98 c++11 c++17 c++20 $(filesystem_dir) $(backtrace_dir) 
$(experimental_dir)
 @VTV_CYGMIN_FALSE@toolexeclib_LTLIBRARIES = libstdc++.la
 
 # Cross compiler support.
-- 
2.39.1

Re: [PATCH] ipa: Avoid invalid gimple when IPA-CP and IPA-SRA disagree on types (108384)

[Martin Jambor]

Hi,

On Fri, Feb 03 2023, Bernhard Reutner-Fischer wrote:
> On 3 February 2023 12:35:32 CET, Richard Biener via Gcc-patches
>>
>>I think it's OK as-is given this explanation.
>>
>
> s/derefernce/dereference/
>

Thanks for noticing.  I am about to commit the following as an obvious
fix.

Martin


A fix to a typo spotted by Bernhard Reutner-Fischer.  Tested by
building the compiler with the fix.

gcc/ChangeLog:

2023-02-06  Martin Jambor  

* ipa-sra.cc (adjust_parameter_descriptions): Fix a typo in a dump.
---
 gcc/ipa-sra.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/ipa-sra.cc b/gcc/ipa-sra.cc
index 7a2b4dc8608..0495f446bf4 100644
--- a/gcc/ipa-sra.cc
+++ b/gcc/ipa-sra.cc
@@ -4249,8 +4249,8 @@ adjust_parameter_descriptions (cgraph_node *node, 
isra_func_summary *ifs)
 
   dump_list_of_param_indices (node, "are dead on arrival or have a type "
  "mismatch with IPA-CP", dump_dead_indices);
-  dump_list_of_param_indices (node, "are not safe to derefernce in all 
callers",
- dump_bad_cond_indices);
+  dump_list_of_param_indices (node, "are not safe to dereference in all "
+ "callers", dump_bad_cond_indices);
 
   return ret;
 }
-- 
2.39.0

Pushed: [PATCH] LoongArch: Generate bytepick.[wd] for suitable bit operation pattern

[Xi Ruoyao via Gcc-patches]

On Mon, 2023-02-06 at 21:07 +0800, Lulu Cheng wrote:
> 
> 在 2023/2/4 上午1:50, Xi Ruoyao 写道:
> > We can use bytepick.[wd] for
> > 
> >   a << (8 * x) | b >> (8 * (sizeof(a) - x))
> > 
> > while a and b are uint32_t or uint64_t.  This is useful for some cases,
> > for example:
> > https://sourceware.org/pipermail/libc-alpha/2023-February/145203.html
> > 
> > Bootstrapped and regtested on loongarch64-linux-gnu.
> > Ok for trunk (now or GCC 14 stage 1)?
> 
> LGTM!
> 
> I think this change is not big and can be merged into the trunk branch.

Pushed r13-5710.

-- 
Xi Ruoyao 
School of Aerospace Science and Technology, Xidian University

Re: [PATCH] aarch64: Fix up bfmlal lane pattern [PR104921]

[Richard Sandiford via Gcc-patches]

Alex Coplan  writes:
> Hi,
>
> As the testcase shows, this pattern had an incorrect constraint leading
> to GCC's output getting rejected by the assembler.
>
> This patch fixes the constraint accordingly.
>
> The test is split into two: one that can run without bf16 support from
> the assembler and another that checks that the output actually assembles
> when such support is available.
>
> Bootstrapped/regtested on aarch64-linux-gnu.
>
> OK for GCC 13? Or better to wait for next stage 1? What about backports?

OK for GCC 13 & backports, thanks.

Richard
>
> Thanks,
> Alex
>
> gcc/ChangeLog:
>
>   PR target/104921
>   * config/aarch64/aarch64-simd.md (aarch64_bfmlal_lanev4sf):
>   Use correct constraint for operand 3.
>
> gcc/testsuite/ChangeLog:
>
>   PR target/104921
>   * gcc.target/aarch64/pr104921-1.c: New test.
>   * gcc.target/aarch64/pr104921-2.c: New test.
>   * gcc.target/aarch64/pr104921.x: Include file for new tests.
>
> diff --git a/gcc/config/aarch64/aarch64-simd.md 
> b/gcc/config/aarch64/aarch64-simd.md
> index 7f212bf37cd..dd5eed387f2 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -9153,7 +9153,7 @@ (define_insn "aarch64_bfmlal_lanev4sf"
>[(set (match_operand:V4SF 0 "register_operand" "=w")
>  (plus: V4SF (match_operand:V4SF 1 "register_operand" "0")
>  (unspec:V4SF [(match_operand:V8BF 2 "register_operand" 
> "w")
> -  (match_operand:VBF 3 "register_operand" 
> "w")
> +  (match_operand:VBF 3 "register_operand" 
> "x")
>(match_operand:SI 4 "const_int_operand" 
> "n")]
>   BF_MLA)))]
>"TARGET_BF16_SIMD"
> diff --git a/gcc/testsuite/gcc.target/aarch64/pr104921-1.c 
> b/gcc/testsuite/gcc.target/aarch64/pr104921-1.c
> new file mode 100644
> index 000..dcf6fe7d90d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/pr104921-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-additional-options "-O2 -march=armv8.2-a+bf16 -std=gnu99 
> -save-temps" }  */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "pr104921.x"
> +
> +/*
> +**foo:
> +**   mov v([0-9]|1[0-5])\.8b, v16\.8b
> +**   bfmlalb v0\.4s, v1\.8h, v([0-9]|1[0-5])\.h\[0\]
> +**   ret
> +*/
> diff --git a/gcc/testsuite/gcc.target/aarch64/pr104921-2.c 
> b/gcc/testsuite/gcc.target/aarch64/pr104921-2.c
> new file mode 100644
> index 000..211fcd0aca9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/pr104921-2.c
> @@ -0,0 +1,6 @@
> +/* { dg-do assemble } */
> +/* { dg-add-options arm_v8_2a_bf16_neon }  */
> +/* { dg-additional-options "-O2 -std=gnu99" }  */
> +/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
> +
> +#include "pr104921.x"
> diff --git a/gcc/testsuite/gcc.target/aarch64/pr104921.x 
> b/gcc/testsuite/gcc.target/aarch64/pr104921.x
> new file mode 100644
> index 000..1e1a6f24e22
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/pr104921.x
> @@ -0,0 +1,9 @@
> +#include 
> +
> +float32x4_t
> +foo(float32x4_t x, bfloat16x8_t a)
> +{
> +  register bfloat16x4_t b asm ("v16");
> +  asm volatile ("" : "=w"(b));
> +  return vbfmlalbq_lane_f32 (x, a, b, 0);
> +}

[V2][PATCH] Handle component_ref to a structre/union field including flexible array member [PR101832]

[Qing Zhao via Gcc-patches]

This is the 2nd version of the patch, compare to the first version, the major
changes are:

  1. Add a new IR bit in tree_type_common: type_include_flexarray, set this bit
 in FE for struct/union types that include a flexible array member (per
 -fstrict-flex-arrays) at the end.
  2. Check this new bit in tree-objec-size.cc to decide whether a component_ref
 to a struct/union has flexible size or not.
  3. Update the testing case per Seddhish's previous change.

Bootstrapped and regression tested on both X86 and aarch64, no issue.

Okay for commit?

thanks.

Qing.


GCC extension accepts the case when a struct with a flexible array member
is embedded into another struct or union (possibly recursively).
__builtin_object_size should treat such struct as flexible size per
-fstrict-flex-arrays.

gcc/c/ChangeLog:

PR tree-optimization/101832
* c-decl.cc (finish_struct): Set TYPE_INCLUDE_FLEXARRAY for
struct/union type.

gcc/ChangeLog:

PR tree-optimization/101832
* tree-core.h (struct tree_type_common): New bit
type_include_flexarray.
* tree-object-size.cc (addr_object_size): Handle structure/union type
when it has flexible size.
* tree.h (TYPE_INCLUDE_FLEXARRAY): New macro
TYPE_INCLUDE_FLEXARRAY.

gcc/testsuite/ChangeLog:

PR tree-optimization/101832
* gcc.dg/builtin-object-size-pr101832-2.c: New test.
* gcc.dg/builtin-object-size-pr101832-3.c: New test.
* gcc.dg/builtin-object-size-pr101832-4.c: New test.
* gcc.dg/builtin-object-size-pr101832-5.c: New test.
* gcc.dg/builtin-object-size-pr101832.c: New test.
---
 gcc/c/c-decl.cc   |  11 ++
 .../gcc.dg/builtin-object-size-pr101832-2.c   | 132 ++
 .../gcc.dg/builtin-object-size-pr101832-3.c   | 132 ++
 .../gcc.dg/builtin-object-size-pr101832-4.c   | 132 ++
 .../gcc.dg/builtin-object-size-pr101832-5.c   | 120 
 .../gcc.dg/builtin-object-size-pr101832.c | 115 +++
 gcc/tree-core.h   |   4 +-
 gcc/tree-object-size.cc   |  79 +++
 gcc/tree.h|   6 +
 9 files changed, 702 insertions(+), 29 deletions(-)
 create mode 100644 gcc/testsuite/gcc.dg/builtin-object-size-pr101832-2.c
 create mode 100644 gcc/testsuite/gcc.dg/builtin-object-size-pr101832-3.c
 create mode 100644 gcc/testsuite/gcc.dg/builtin-object-size-pr101832-4.c
 create mode 100644 gcc/testsuite/gcc.dg/builtin-object-size-pr101832-5.c
 create mode 100644 gcc/testsuite/gcc.dg/builtin-object-size-pr101832.c

diff --git a/gcc/c/c-decl.cc b/gcc/c/c-decl.cc
index 20e7d1855bf..52fef7d84fa 100644
--- a/gcc/c/c-decl.cc
+++ b/gcc/c/c-decl.cc
@@ -9277,6 +9277,17 @@ finish_struct (location_t loc, tree t, tree fieldlist, 
tree attributes,
   /* Set DECL_NOT_FLEXARRAY flag for FIELD_DECL x.  */
   DECL_NOT_FLEXARRAY (x) = !is_flexible_array_member_p (is_last_field, x);
 
+  /* Set TYPE_INCLUDE_FLEXARRAY for the context of x,
+i.e., the RECORD_TYPE of UNION_TYPE, t.  */
+  TYPE_INCLUDE_FLEXARRAY (t) = !DECL_NOT_FLEXARRAY (x);
+
+  /* Recursively set TYPE_INCLUDE_FLEXARRAY for the context of x, t
+when x is the last field.  */
+  if ((TREE_TYPE (x) != error_mark_node)
+  && TYPE_INCLUDE_FLEXARRAY (TREE_TYPE (x))
+  && is_last_field)
+   TYPE_INCLUDE_FLEXARRAY (t) = true;
+
   if (DECL_NAME (x)
  || RECORD_OR_UNION_TYPE_P (TREE_TYPE (x)))
saw_named_field = true;
diff --git a/gcc/testsuite/gcc.dg/builtin-object-size-pr101832-2.c 
b/gcc/testsuite/gcc.dg/builtin-object-size-pr101832-2.c
new file mode 100644
index 000..af9769d73e0
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/builtin-object-size-pr101832-2.c
@@ -0,0 +1,132 @@
+/* PR 101832: 
+   GCC extension accepts the case when a struct with a flexible array member
+   is embedded into another struct (possibly recursively).
+   __builtin_object_size will treat such struct as flexible size per
+   -fstrict-flex-arrays.  */ 
+/* { dg-do run } */
+/* { dg-options "-O2 -fstrict-flex-arrays=1" } */
+
+#include "builtin-object-size-common.h"
+
+#define expect(p, _v) do { \
+  size_t v = _v; \
+  if (p == v) \
+__builtin_printf ("ok:  %s == %zd\n", #p, p); \
+  else {\
+__builtin_printf ("WAT: %s == %zd (expected %zd)\n", #p, p, v); \
+FAIL (); \
+  } \
+} while (0);
+
+
+struct A {
+  int n;
+  char data[];
+};
+
+struct B {
+  int m;
+  struct A a;
+};
+
+struct C {
+  int q;
+  struct B b;
+};
+
+struct A0 {
+  int n;
+  char data[0];
+};
+
+struct B0 {
+  int m;
+  struct A0 a;
+};
+
+struct C0 {
+  int q;
+  struct B0 b;
+};
+
+struct A1 {
+  int n;
+  char data[1];
+};
+
+struct B1 {
+  int m;
+  struct A1 a;
+};
+
+struct C1 {
+  int q;
+  struct B1 b;
+};
+
+struct An {
+  int n;
+  char data[8];
+};
+
+struct Bn {
+  int m

[PATCH] aarch64: Fix up bfmlal lane pattern [PR104921]

[Alex Coplan via Gcc-patches]

Hi,

As the testcase shows, this pattern had an incorrect constraint leading
to GCC's output getting rejected by the assembler.

This patch fixes the constraint accordingly.

The test is split into two: one that can run without bf16 support from
the assembler and another that checks that the output actually assembles
when such support is available.

Bootstrapped/regtested on aarch64-linux-gnu.

OK for GCC 13? Or better to wait for next stage 1? What about backports?

Thanks,
Alex

gcc/ChangeLog:

PR target/104921
* config/aarch64/aarch64-simd.md (aarch64_bfmlal_lanev4sf):
Use correct constraint for operand 3.

gcc/testsuite/ChangeLog:

PR target/104921
* gcc.target/aarch64/pr104921-1.c: New test.
* gcc.target/aarch64/pr104921-2.c: New test.
* gcc.target/aarch64/pr104921.x: Include file for new tests.
diff --git a/gcc/config/aarch64/aarch64-simd.md 
b/gcc/config/aarch64/aarch64-simd.md
index 7f212bf37cd..dd5eed387f2 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -9153,7 +9153,7 @@ (define_insn "aarch64_bfmlal_lanev4sf"
   [(set (match_operand:V4SF 0 "register_operand" "=w")
 (plus: V4SF (match_operand:V4SF 1 "register_operand" "0")
 (unspec:V4SF [(match_operand:V8BF 2 "register_operand" "w")
-  (match_operand:VBF 3 "register_operand" "w")
+  (match_operand:VBF 3 "register_operand" "x")
   (match_operand:SI 4 "const_int_operand" "n")]
  BF_MLA)))]
   "TARGET_BF16_SIMD"
diff --git a/gcc/testsuite/gcc.target/aarch64/pr104921-1.c 
b/gcc/testsuite/gcc.target/aarch64/pr104921-1.c
new file mode 100644
index 000..dcf6fe7d90d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr104921-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -march=armv8.2-a+bf16 -std=gnu99 -save-temps" 
}  */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "pr104921.x"
+
+/*
+**foo:
+** mov v([0-9]|1[0-5])\.8b, v16\.8b
+** bfmlalb v0\.4s, v1\.8h, v([0-9]|1[0-5])\.h\[0\]
+** ret
+*/
diff --git a/gcc/testsuite/gcc.target/aarch64/pr104921-2.c 
b/gcc/testsuite/gcc.target/aarch64/pr104921-2.c
new file mode 100644
index 000..211fcd0aca9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr104921-2.c
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-add-options arm_v8_2a_bf16_neon }  */
+/* { dg-additional-options "-O2 -std=gnu99" }  */
+/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+
+#include "pr104921.x"
diff --git a/gcc/testsuite/gcc.target/aarch64/pr104921.x 
b/gcc/testsuite/gcc.target/aarch64/pr104921.x
new file mode 100644
index 000..1e1a6f24e22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr104921.x
@@ -0,0 +1,9 @@
+#include 
+
+float32x4_t
+foo(float32x4_t x, bfloat16x8_t a)
+{
+  register bfloat16x4_t b asm ("v16");
+  asm volatile ("" : "=w"(b));
+  return vbfmlalbq_lane_f32 (x, a, b, 0);
+}

Re: [PATCH] LoongArch: Generate bytepick.[wd] for suitable bit operation pattern

[Lulu Cheng]

在 2023/2/4 上午1:50, Xi Ruoyao 写道:

We can use bytepick.[wd] for

 a << (8 * x) | b >> (8 * (sizeof(a) - x))

while a and b are uint32_t or uint64_t.  This is useful for some cases,
for example:
https://sourceware.org/pipermail/libc-alpha/2023-February/145203.html

Bootstrapped and regtested on loongarch64-linux-gnu.
Ok for trunk (now or GCC 14 stage 1)?


LGTM!

I think this change is not big and can be merged into the trunk branch.


Thanks!



gcc/ChangeLog:

* config/loongarch/loongarch.md (bytepick_w_ashift_amount):
New define_int_iterator.
(bytepick_d_ashift_amount): Likewise.
(bytepick_imm): New define_int_attr.
(bytepick_w_lshiftrt_amount): Likewise.
(bytepick_d_lshiftrt_amount): Likewise.
(bytepick_w_): New define_insn template.
(bytepick_w__extend): Likewise.
(bytepick_d_): Likewise.
(bytepick_w): Remove unused define_insn.
(bytepick_d): Likewise.
(UNSPEC_BYTEPICK_W): Remove unused unspec.
(UNSPEC_BYTEPICK_D): Likewise.
* config/loongarch/predicates.md (const_0_to_3_operand):
Remove unused define_predicate.
(const_0_to_7_operand): Likewise.

gcc/testsuite/ChangeLog:

* g++.target/loongarch/bytepick.C: New test.
---
  gcc/config/loongarch/loongarch.md | 60 ++-
  gcc/config/loongarch/predicates.md|  8 ---
  gcc/testsuite/g++.target/loongarch/bytepick.C | 32 ++
  3 files changed, 77 insertions(+), 23 deletions(-)
  create mode 100644 gcc/testsuite/g++.target/loongarch/bytepick.C

diff --git a/gcc/config/loongarch/loongarch.md 
b/gcc/config/loongarch/loongarch.md
index 0884ec09dfb..3509c3c21c1 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -48,8 +48,6 @@ (define_c_enum "unspec" [
UNSPEC_EH_RETURN
  
;; Bit operation

-  UNSPEC_BYTEPICK_W
-  UNSPEC_BYTEPICK_D
UNSPEC_BITREV_4B
UNSPEC_BITREV_8B
  
@@ -544,6 +542,27 @@ (define_int_attr lrint_allow_inexact [(UNSPEC_FTINT "1")

  (UNSPEC_FTINTRM "0")
  (UNSPEC_FTINTRP "0")])
  
+;; Iterator and attributes for bytepick.d

+(define_int_iterator bytepick_w_ashift_amount [8 16 24])
+(define_int_attr bytepick_w_lshiftrt_amount [(8 "24")
+(16 "16")
+(24 "8")])
+(define_int_iterator bytepick_d_ashift_amount [8 16 24 32 40 48 56])
+(define_int_attr bytepick_d_lshiftrt_amount [(8 "56")
+(16 "48")
+(24 "40")
+(32 "32")
+(40 "24")
+(48 "16")
+(56 "8")])
+(define_int_attr bytepick_imm [(8 "1")
+(16 "2")
+(24 "3")
+(32 "4")
+(40 "5")
+(48 "6")
+(56 "7")])
+
  ;;
  ;;  
  ;;
@@ -3364,24 +3383,35 @@ (define_insn "fclass_"
[(set_attr "type" "unknown")
 (set_attr "mode" "")])
  
-(define_insn "bytepick_w"

+(define_insn "bytepick_w_"
[(set (match_operand:SI 0 "register_operand" "=r")
-   (unspec:SI [(match_operand:SI 1 "register_operand" "r")
-   (match_operand:SI 2 "register_operand" "r")
-   (match_operand:SI 3 "const_0_to_3_operand" "n")]
-   UNSPEC_BYTEPICK_W))]
+   (ior:SI (lshiftrt (match_operand:SI 1 "register_operand" "r")
+ (const_int ))
+   (ashift (match_operand:SI 2 "register_operand" "r")
+   (const_int bytepick_w_ashift_amount]
""
-  "bytepick.w\t%0,%1,%2,%z3"
+  "bytepick.w\t%0,%1,%2,"
[(set_attr "mode" "SI")])
  
-(define_insn "bytepick_d"

+(define_insn "bytepick_w__extend"
[(set (match_operand:DI 0 "register_operand" "=r")
-   (unspec:DI [(match_operand:DI 1 "register_operand" "r")
-   (match_operand:DI 2 "register_operand" "r")
-   (match_operand:DI 3 "const_0_to_7_operand" "n")]
-   UNSPEC_BYTEPICK_D))]
-  ""
-  "bytepick.d\t%0,%1,%2,%z3"
+   (sign_extend:DI
+ (ior:SI (lshiftrt (match_operand:SI 1 "register_operand" "r")
+   (const_int ))
+ (ashift (match_operand:SI 2 "register_operand" "r")
+ (const_int bytepick_w_ashift_amount)]
+  "TARGET_64BIT"
+  "bytepick.w\t%0,%1,%2,"
+  [(set_attr "mode" "SI")])
+
+(define_insn "bytepick_d_"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+   (ior:DI (lshiftrt (match_operand:DI 1 "register_operand" "r")
+ (const_int ))
+   (ashift (m

[PATCH] RISC-V: Add vmulh.vv C++ API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vmulh_vv-1.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv-2.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv-3.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vmulh_vv_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vmulh_vv-1.C| 314 ++
 .../g++.target/riscv/rvv/base/vmulh_vv-2.C| 314 ++
 .../g++.target/riscv/rvv/base/vmulh_vv-3.C| 314 ++
 .../g++.target/riscv/rvv/base/vmulh_vv_mu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vmulh_vv_mu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vmulh_vv_mu-3.C | 160 +
 .../g++.target/riscv/rvv/base/vmulh_vv_tu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vmulh_vv_tu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vmulh_vv_tu-3.C | 160 +
 .../riscv/rvv/base/vmulh_vv_tum-1.C   | 160 +
 .../riscv/rvv/base/vmulh_vv_tum-2.C   | 160 +
 .../riscv/rvv/base/vmulh_vv_tum-3.C   | 160 +
 .../riscv/rvv/base/vmulh_vv_tumu-1.C  | 160 +
 .../riscv/rvv/base/vmulh_vv_tumu-2.C  | 160 +
 .../riscv/rvv/base/vmulh_vv_tumu-3.C  | 160 +
 15 files changed, 2862 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv-1.C
new file mode 100644
index 000..98fece060e4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulh(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+return __riscv_vmulh(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulh(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+return __riscv_vmulh(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulh(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+return __riscv_vmulh(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulh(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+return __riscv_vmulh(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulh(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+return __riscv_vmulh(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmulh(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+return __riscv_vmulh(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmulh(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+return __riscv_vmulh(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmulh(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+return __riscv_vmulh(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmulh(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+return __riscv_vmulh(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmulh(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+return __riscv_vmulh(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmulh(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+return __riscv_vmulh(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmulh(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+return __riscv_vmulh(op1,op2

[PATCH] RISC-V: Add vmulhsu.vv C++ API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vmulhsu_vv-1.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv-2.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv-3.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vmulhsu_vv_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vmulhsu_vv-1.C  | 314 ++
 .../g++.target/riscv/rvv/base/vmulhsu_vv-2.C  | 314 ++
 .../g++.target/riscv/rvv/base/vmulhsu_vv-3.C  | 314 ++
 .../riscv/rvv/base/vmulhsu_vv_mu-1.C  | 160 +
 .../riscv/rvv/base/vmulhsu_vv_mu-2.C  | 160 +
 .../riscv/rvv/base/vmulhsu_vv_mu-3.C  | 160 +
 .../riscv/rvv/base/vmulhsu_vv_tu-1.C  | 160 +
 .../riscv/rvv/base/vmulhsu_vv_tu-2.C  | 160 +
 .../riscv/rvv/base/vmulhsu_vv_tu-3.C  | 160 +
 .../riscv/rvv/base/vmulhsu_vv_tum-1.C | 160 +
 .../riscv/rvv/base/vmulhsu_vv_tum-2.C | 160 +
 .../riscv/rvv/base/vmulhsu_vv_tum-3.C | 160 +
 .../riscv/rvv/base/vmulhsu_vv_tumu-1.C| 160 +
 .../riscv/rvv/base/vmulhsu_vv_tumu-2.C| 160 +
 .../riscv/rvv/base/vmulhsu_vv_tumu-3.C| 160 +
 15 files changed, 2862 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv-1.C
new file mode 100644
index 000..7ba9ab0642a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+return __riscv_vmulhsu(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+return __riscv_vmulhsu(op1,op2

[PATCH] RISC-V: Add vmulh.vv C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vmulh_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vmulh_vv_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vmulh_vv-1.c| 160 ++
 .../gcc.target/riscv/rvv/base/vmulh_vv-2.c| 160 ++
 .../gcc.target/riscv/rvv/base/vmulh_vv-3.c| 160 ++
 .../gcc.target/riscv/rvv/base/vmulh_vv_m-1.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vmulh_vv_m-2.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vmulh_vv_m-3.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vmulh_vv_mu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vmulh_vv_mu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vmulh_vv_mu-3.c | 160 ++
 .../gcc.target/riscv/rvv/base/vmulh_vv_tu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vmulh_vv_tu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vmulh_vv_tu-3.c | 160 ++
 .../riscv/rvv/base/vmulh_vv_tum-1.c   | 160 ++
 .../riscv/rvv/base/vmulh_vv_tum-2.c   | 160 ++
 .../riscv/rvv/base/vmulh_vv_tum-3.c   | 160 ++
 .../riscv/rvv/base/vmulh_vv_tumu-1.c  | 160 ++
 .../riscv/rvv/base/vmulh_vv_tumu-2.c  | 160 ++
 .../riscv/rvv/base/vmulh_vv_tumu-3.c  | 160 ++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv-1.c
new file mode 100644
index 000..5d74c915ffc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulh_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+return __riscv_vmulh_vv_i8mf8(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulh_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+return __riscv_vmulh_vv_i8mf4(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulh_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+return __riscv_vmulh_vv_i8mf2(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulh_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+return __riscv_vmulh_vv_i8m1(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulh_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+return __riscv_vmulh_vv_i8m2(op1,op2,vl);
+}
+
+
+vint8m4_t te

Re: [DOC PATCH] Document the VEC_PERM_EXPR tree code (and minor clean-ups).

[Richard Sandiford via Gcc-patches]

Richard Biener  writes:
> On Sat, Feb 4, 2023 at 9:35 PM Roger Sayle  wrote:
>>
>>
>> This patch (primarily) documents the VEC_PERM_EXPR tree code in
>> generic.texi.  For ease of review, it is provided below as a pair
>> of diffs.  The first contains just the new text added to describe
>> VEC_PERM_EXPR, the second tidies up this part of the documentation
>> by sorting the tree codes into alphabetical order, and providing
>> consistent section naming/capitalization, so changing this section
>> from "Vectors" to "Vector Expressions" (matching the nearby
>> "Unary and Binary Expressions").
>>
>> Tested with make pdf and make html on x86_64-pc-linux-gnu.
>> The reviewer(s) can decide whether to approve just the new content,
>> or the content+clean-up.  Ok for mainline?
>
> +@item VEC_PERM_EXPR
> +This node represents a vector permute/blend operation.  The three operands
> +must be vectors of the same number of elements.  The first and second
> +operands must be vectors of the same type as the entire expression,
>
> this was recently relaxed for the case of constant permutes in which case
> the first and second operands only have to have the same element type
> as the result.  See tree-cfg.cc:verify_gimple_assign_ternary.
>
> The following description will become a bit more awkward here and
> for rhs1/rhs2 with different number of elements the modulo interpretation
> doesn't hold - I believe we require in-bounds elements for constant
> permutes.  Richard can probably clarify things here.

I thought that the modulo behaviour still applies when the node has a
constant selector, it's just that the in-range form is the canonical one.

With variable-length vectors, I think it's in principle possible to have
a stepped constant selector whose start elements are in-range but whose
final elements aren't (and instead wrap around when applied).
E.g. the selector could zip the last quarter of the inputs followed
by the first quarter.

Thanks,
Richard

Re: [aarch64] Use dup and zip1 for interleaving elements in initializing vector

[Richard Sandiford via Gcc-patches]

Prathamesh Kulkarni  writes:
> On Fri, 3 Feb 2023 at 20:47, Richard Sandiford
>  wrote:
>>
>> Prathamesh Kulkarni  writes:
>> > On Fri, 3 Feb 2023 at 07:10, Prathamesh Kulkarni
>> >  wrote:
>> >>
>> >> On Thu, 2 Feb 2023 at 20:50, Richard Sandiford
>> >>  wrote:
>> >> >
>> >> > Prathamesh Kulkarni  writes:
>> >> > >> >> > I have attached a patch that extends the transform if one half 
>> >> > >> >> > is dup
>> >> > >> >> > and other is set of constants.
>> >> > >> >> > For eg:
>> >> > >> >> > int8x16_t f(int8_t x)
>> >> > >> >> > {
>> >> > >> >> >   return (int8x16_t) { x, 1, x, 2, x, 3, x, 4, x, 5, x, 6, x, 
>> >> > >> >> > 7, x, 8 };
>> >> > >> >> > }
>> >> > >> >> >
>> >> > >> >> > code-gen trunk:
>> >> > >> >> > f:
>> >> > >> >> > adrpx1, .LC0
>> >> > >> >> > ldr q0, [x1, #:lo12:.LC0]
>> >> > >> >> > ins v0.b[0], w0
>> >> > >> >> > ins v0.b[2], w0
>> >> > >> >> > ins v0.b[4], w0
>> >> > >> >> > ins v0.b[6], w0
>> >> > >> >> > ins v0.b[8], w0
>> >> > >> >> > ins v0.b[10], w0
>> >> > >> >> > ins v0.b[12], w0
>> >> > >> >> > ins v0.b[14], w0
>> >> > >> >> > ret
>> >> > >> >> >
>> >> > >> >> > code-gen with patch:
>> >> > >> >> > f:
>> >> > >> >> > dup v0.16b, w0
>> >> > >> >> > adrpx0, .LC0
>> >> > >> >> > ldr q1, [x0, #:lo12:.LC0]
>> >> > >> >> > zip1v0.16b, v0.16b, v1.16b
>> >> > >> >> > ret
>> >> > >> >> >
>> >> > >> >> > Bootstrapped+tested on aarch64-linux-gnu.
>> >> > >> >> > Does it look OK ?
>> >> > >> >>
>> >> > >> >> Looks like a nice improvement.  It'll need to wait for GCC 14 now 
>> >> > >> >> though.
>> >> > >> >>
>> >> > >> >> However, rather than handle this case specially, I think we 
>> >> > >> >> should instead
>> >> > >> >> take a divide-and-conquer approach: split the initialiser into 
>> >> > >> >> even and
>> >> > >> >> odd elements, find the best way of loading each part, then 
>> >> > >> >> compare the
>> >> > >> >> cost of these sequences + ZIP with the cost of the fallback code 
>> >> > >> >> (the code
>> >> > >> >> later in aarch64_expand_vector_init).
>> >> > >> >>
>> >> > >> >> For example, doing that would allow:
>> >> > >> >>
>> >> > >> >>   { x, y, 0, y, 0, y, 0, y, 0, y }
>> >> > >> >>
>> >> > >> >> to be loaded more easily, even though the even elements aren't 
>> >> > >> >> wholly
>> >> > >> >> constant.
>> >> > >> > Hi Richard,
>> >> > >> > I have attached a prototype patch based on the above approach.
>> >> > >> > It subsumes specializing for above {x, y, x, y, x, y, x, y} case 
>> >> > >> > by generating
>> >> > >> > same sequence, thus I removed that hunk, and improves the 
>> >> > >> > following cases:
>> >> > >> >
>> >> > >> > (a)
>> >> > >> > int8x16_t f_s16(int8_t x)
>> >> > >> > {
>> >> > >> >   return (int8x16_t) { x, 1, x, 2, x, 3, x, 4,
>> >> > >> >  x, 5, x, 6, x, 7, x, 8 };
>> >> > >> > }
>> >> > >> >
>> >> > >> > code-gen trunk:
>> >> > >> > f_s16:
>> >> > >> > adrpx1, .LC0
>> >> > >> > ldr q0, [x1, #:lo12:.LC0]
>> >> > >> > ins v0.b[0], w0
>> >> > >> > ins v0.b[2], w0
>> >> > >> > ins v0.b[4], w0
>> >> > >> > ins v0.b[6], w0
>> >> > >> > ins v0.b[8], w0
>> >> > >> > ins v0.b[10], w0
>> >> > >> > ins v0.b[12], w0
>> >> > >> > ins v0.b[14], w0
>> >> > >> > ret
>> >> > >> >
>> >> > >> > code-gen with patch:
>> >> > >> > f_s16:
>> >> > >> > dup v0.16b, w0
>> >> > >> > adrpx0, .LC0
>> >> > >> > ldr q1, [x0, #:lo12:.LC0]
>> >> > >> > zip1v0.16b, v0.16b, v1.16b
>> >> > >> > ret
>> >> > >> >
>> >> > >> > (b)
>> >> > >> > int8x16_t f_s16(int8_t x, int8_t y)
>> >> > >> > {
>> >> > >> >   return (int8x16_t) { x, y, 1, y, 2, y, 3, y,
>> >> > >> > 4, y, 5, y, 6, y, 7, y };
>> >> > >> > }
>> >> > >> >
>> >> > >> > code-gen trunk:
>> >> > >> > f_s16:
>> >> > >> > adrpx2, .LC0
>> >> > >> > ldr q0, [x2, #:lo12:.LC0]
>> >> > >> > ins v0.b[0], w0
>> >> > >> > ins v0.b[1], w1
>> >> > >> > ins v0.b[3], w1
>> >> > >> > ins v0.b[5], w1
>> >> > >> > ins v0.b[7], w1
>> >> > >> > ins v0.b[9], w1
>> >> > >> > ins v0.b[11], w1
>> >> > >> > ins v0.b[13], w1
>> >> > >> > ins v0.b[15], w1
>> >> > >> > ret
>> >> > >> >
>> >> > >> > code-gen patch:
>> >> > >> > f_s16:
>> >> > >> > adrpx2, .LC0
>> >> > >> > dup v1.16b, w1
>> >> > >> > ldr q0, [x2, #:lo12:.LC0]
>> >> > >> > ins v0.b[0], w0
>> >> > >> > zip1v0.16b, v0.16b, v1.16b
>> >> > >> > ret
>> >> > >>
>> >> > >> Nice.
>> >> > >>
>> >> > >> > There are a couple of issues I have come across:
>> >> > >> > (1)

[PATCH] RISC-V: Add vmulhsu.vv C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vmulhsu_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vmulhsu_vv-1.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vmulhsu_vv-2.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vmulhsu_vv-3.c  | 160 ++
 .../riscv/rvv/base/vmulhsu_vv_m-1.c   | 160 ++
 .../riscv/rvv/base/vmulhsu_vv_m-2.c   | 160 ++
 .../riscv/rvv/base/vmulhsu_vv_m-3.c   | 160 ++
 .../riscv/rvv/base/vmulhsu_vv_mu-1.c  | 160 ++
 .../riscv/rvv/base/vmulhsu_vv_mu-2.c  | 160 ++
 .../riscv/rvv/base/vmulhsu_vv_mu-3.c  | 160 ++
 .../riscv/rvv/base/vmulhsu_vv_tu-1.c  | 160 ++
 .../riscv/rvv/base/vmulhsu_vv_tu-2.c  | 160 ++
 .../riscv/rvv/base/vmulhsu_vv_tu-3.c  | 160 ++
 .../riscv/rvv/base/vmulhsu_vv_tum-1.c | 160 ++
 .../riscv/rvv/base/vmulhsu_vv_tum-2.c | 160 ++
 .../riscv/rvv/base/vmulhsu_vv_tum-3.c | 160 ++
 .../riscv/rvv/base/vmulhsu_vv_tumu-1.c| 160 ++
 .../riscv/rvv/base/vmulhsu_vv_tumu-2.c| 160 ++
 .../riscv/rvv/base/vmulhsu_vv_tumu-3.c| 160 ++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv-1.c
new file mode 100644
index 000..7a92b844349
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmulhsu_vv_i8mf8(vint8mf8_t op1,vuint8mf8_t op2,size_t 
vl)
+{
+return __riscv_vmulhsu_vv_i8mf8(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmulhsu_vv_i8mf4(vint8mf4_t op1,vuint8mf4_t op2,size_t 
vl)
+{
+return __riscv_vmulhsu_vv_i8mf4(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmulhsu_vv_i8mf2(vint8mf2_t op1,vuint8mf2_t op2,size_t 
vl)
+{
+return __riscv_vmulhsu_vv_i8mf2(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmulhsu_vv_i8m1(vint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+return __riscv_vmulhsu_vv_i8m1(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmulhsu_vv_i8m2(vint8m

[PATCH] RISC-V: Add vmulhu.vv C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vmulhu_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vmulhu_vv_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vmulhu_vv-1.c   | 160 ++
 .../gcc.target/riscv/rvv/base/vmulhu_vv-2.c   | 160 ++
 .../gcc.target/riscv/rvv/base/vmulhu_vv-3.c   | 160 ++
 .../gcc.target/riscv/rvv/base/vmulhu_vv_m-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vmulhu_vv_m-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vmulhu_vv_m-3.c | 160 ++
 .../riscv/rvv/base/vmulhu_vv_mu-1.c   | 160 ++
 .../riscv/rvv/base/vmulhu_vv_mu-2.c   | 160 ++
 .../riscv/rvv/base/vmulhu_vv_mu-3.c   | 160 ++
 .../riscv/rvv/base/vmulhu_vv_tu-1.c   | 160 ++
 .../riscv/rvv/base/vmulhu_vv_tu-2.c   | 160 ++
 .../riscv/rvv/base/vmulhu_vv_tu-3.c   | 160 ++
 .../riscv/rvv/base/vmulhu_vv_tum-1.c  | 160 ++
 .../riscv/rvv/base/vmulhu_vv_tum-2.c  | 160 ++
 .../riscv/rvv/base/vmulhu_vv_tum-3.c  | 160 ++
 .../riscv/rvv/base/vmulhu_vv_tumu-1.c | 160 ++
 .../riscv/rvv/base/vmulhu_vv_tumu-2.c | 160 ++
 .../riscv/rvv/base/vmulhu_vv_tumu-3.c | 160 ++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv-1.c
new file mode 100644
index 000..eebb763c8f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vmulhu_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t 
op2,size_t vl)
+{
+return __riscv_vmulhu_vv_u8mf8(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmulhu_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t 
op2,size_t vl)
+{
+return __riscv_vmulhu_vv_u8mf4(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmulhu_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t 
op2,size_t vl)
+{
+return __riscv_vmulhu_vv_u8mf2(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vmulhu_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+return __riscv_vmulhu_vv_u8m1(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vmulhu_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+

[Patch] libgomp: Fix reverse-offload for GOMP_MAP_TO_PSET

[Tobias Burnus]

Seems as if I missed a GOMP_MAP_TO_PSET issue before. As nvptx is
XFAILed before, I only found it when testing on AMDGCN.

For an array-descriptor 'ai' variable, omplower has:
  map(tofrom:MEM  [(integer(kind=4)[0:] *)D.4346] [len: 
D.4345])
  map(to:ai [pointer set, len: 64])
  map(alloc:ai.data [pointer assign, bias: 0])

The latter reaches GCC with the same address as 'ai' – i.e. the
one of the array descriptor. This then needs to be dereferenced
to get the address of the actual pointer.
The patch assumes (and asserts) that 'ai.data' is part of the 'ai'
such that I can use the host address of 'ai' to access the data.
If that's not guaranteed, we have to find another way (e.g. another
lookup). But so far it seems to hold and I have not seen a bias
other than 0.

With that patch, libgomp.fortran/reverse-offload-5.f90 now works
with AMDGCN.

OK? Any comments to the attached patch?

Tobias
-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 
München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas 
Heurung, Frank Thürauf; Sitz der Gesellschaft: München; Registergericht 
München, HRB 106955
libgomp: Fix reverse-offload for GOMP_MAP_TO_PSET

libgomp/
	* target.c (gomp_target_rev): Dereference ptr
	to get device address.
	* libgomp.fortran/reverse-offload-5.f90: Add test
	for unallocated allocatable.

 libgomp/target.c| 7 ++-
 libgomp/testsuite/libgomp.fortran/reverse-offload-5.f90 | 6 --
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/libgomp/target.c b/libgomp/target.c
index c1682caea13..5cdd845291a 100644
--- a/libgomp/target.c
+++ b/libgomp/target.c
@@ -3579,8 +3579,13 @@ gomp_target_rev (uint64_t fn_ptr, uint64_t mapnum, uint64_t devaddrs_ptr,
 		  }
 		int k;
 		n2 = NULL;
-		cdata[i].present = true;
+		/* Dereference devaddrs[j] to get the device addr.  */
+		assert (devaddrs[j]-sizes[j] == cdata[i].devaddr);
+		devaddrs[j] = *(uint64_t *) (devaddrs[i] + sizes[j]);
+		cdata[j].present = true;
 		cdata[j].devaddr = devaddrs[j];
+		if (devaddrs[j] == 0)
+		  continue;
 		k = gomp_map_cdata_lookup (cdata, devaddrs, kinds, sizes, j,
 	   devaddrs[j],
 	   devaddrs[j] + sizeof (void*),
diff --git a/libgomp/testsuite/libgomp.fortran/reverse-offload-5.f90 b/libgomp/testsuite/libgomp.fortran/reverse-offload-5.f90
index ef7eb7bdd52..16810eb47de 100644
--- a/libgomp/testsuite/libgomp.fortran/reverse-offload-5.f90
+++ b/libgomp/testsuite/libgomp.fortran/reverse-offload-5.f90
@@ -24,7 +24,7 @@ s2 = 55
 
 !$omp target map(to: A, A2, s1, s2)
 block
-  integer, allocatable :: ai(:), ai2(:), si1, si2
+  integer, allocatable :: ai(:), ai2(:), ai3(:), si1, si2, si3
 
   a = a * 2
   a2 = a2 * 3
@@ -38,7 +38,7 @@ block
 
   !$omp target device (ancestor:1)  &
   !$omp&   map(to: A, s1, ai, si1) map(always, to: a2, s2)  &
-  !$omp&   map(tofrom: ai2, si2)
+  !$omp&   map(tofrom: ai2, si2, ai3, si3)
 if (shared_mem) then
   if (any (a  /= 2 * [1,2,3,4])) stop 1
   if (s1 /= 4 * 532) stop 2
@@ -52,6 +52,7 @@ block
 if (any (ai2 /= [8,4,7,1])) stop 8
 if (si1 /= 64) stop 9
 if (si2 /= 765) stop 10
+if (allocated (ai3) .or. allocated(si3)) stop 26
 
 a = a*3
 a2 = a2*7
@@ -80,6 +81,7 @@ block
   endif
   if (any (ai2 /= 21 * [8,4,7,1])) stop 24
   if (si2 /= 31 * 765) stop 25
+  if (allocated (ai3) .or. allocated(si3)) stop 27
 
   deallocate (ai, ai2, si1, si2)
 end block

[PATCH] RISC-V: Add vmulh C/C++ support

[juzhe . zhong]

From: Ju-Zhe Zhong 

Co-authored-by: kito-cheng 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add flag for 'V' extension.
* config/riscv/riscv-vector-builtins-bases.cc (class vmulh): New class.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vmulh): Add vmulh 
API support.
(vmulhu): Ditto.
(vmulhsu): Ditto.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_FULL_V_I_OPS): 
New macro.
(DEF_RVV_FULL_V_U_OPS): Ditto.
(vint8mf8_t): Ditto.
(vint8mf4_t): Ditto.
(vint8mf2_t): Ditto.
(vint8m1_t): Ditto.
(vint8m2_t): Ditto.
(vint8m4_t): Ditto.
(vint8m8_t): Ditto.
(vint16mf4_t): Ditto.
(vint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vint32mf2_t): Ditto.
(vint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vint64m1_t): Ditto.
(vint64m2_t): Ditto.
(vint64m4_t): Ditto.
(vint64m8_t): Ditto.
(vuint8mf8_t): Ditto.
(vuint8mf4_t): Ditto.
(vuint8mf2_t): Ditto.
(vuint8m1_t): Ditto.
(vuint8m2_t): Ditto.
(vuint8m4_t): Ditto.
(vuint8m8_t): Ditto.
(vuint16mf4_t): Ditto.
(vuint16mf2_t): Ditto.
(vuint16m1_t): Ditto.
(vuint16m2_t): Ditto.
(vuint16m4_t): Ditto.
(vuint16m8_t): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FULL_V_I_OPS): Ditto.
(DEF_RVV_FULL_V_U_OPS): Ditto.
(check_required_extensions): Add vmulh support.
(rvv_arg_type_info::get_tree_type): Ditto.
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_FULL_V): Ditto.
(enum rvv_base_type): Ditto.
* config/riscv/riscv.opt: Add 'V' extension flag.
* config/riscv/vector-iterators.md (su): New iterator.
* config/riscv/vector.md (@pred_mulh): New pattern.
(@pred_mulh_scalar): Ditto.
(*pred_mulh_scalar): Ditto.
(*pred_mulh_extended_scalar): Ditto.

---
 gcc/common/config/riscv/riscv-common.cc   |   1 +
 .../riscv/riscv-vector-builtins-bases.cc  |  27 
 .../riscv/riscv-vector-builtins-bases.h   |   3 +
 .../riscv/riscv-vector-builtins-functions.def |   6 +
 .../riscv/riscv-vector-builtins-types.def |  62 +
 gcc/config/riscv/riscv-vector-builtins.cc |  93 +
 gcc/config/riscv/riscv-vector-builtins.h  |   3 +
 gcc/config/riscv/riscv.opt|   2 +
 gcc/config/riscv/vector-iterators.md  |  22 +++
 gcc/config/riscv/vector.md| 128 ++
 10 files changed, 347 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 616e2f897b9..1a6c8dbd97d 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1177,6 +1177,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"f", &gcc_options::x_target_flags, MASK_HARD_FLOAT},
   {"d", &gcc_options::x_target_flags, MASK_DOUBLE_FLOAT},
   {"c", &gcc_options::x_target_flags, MASK_RVC},
+  {"v", &gcc_options::x_target_flags, MASK_FULL_V},
   {"v", &gcc_options::x_target_flags, MASK_VECTOR},
 
   {"zicsr",&gcc_options::x_riscv_zi_subext, MASK_ZICSR},
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 1a9469a370a..43f815156d8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -218,6 +218,27 @@ public:
   }
 };
 
+/* Implements vmulh/vmulhu/vmulhsu.  */
+template
+class vmulh : public function_base
+{
+public:
+  rtx expand (function_expander &e) const override
+  {
+switch (e.op_info->op)
+  {
+  case OP_TYPE_vx:
+   return e.use_exact_insn (
+ code_for_pred_mulh_scalar (UNSPEC, e.vector_mode ()));
+  case OP_TYPE_vv:
+   return e.use_exact_insn (
+ code_for_pred_mulh (UNSPEC, e.vector_mode ()));
+  default:
+   gcc_unreachable ();
+  }
+  }
+};
+
 static CONSTEXPR const vsetvl vsetvl_obj;
 static CONSTEXPR const vsetvl vsetvlmax_obj;
 static CONSTEXPR const loadstore vle_obj;
@@ -256,6 +277,9 @@ static CONSTEXPR const binop vmax_obj;
 static CONSTEXPR const binop vminu_obj;
 static CONSTEXPR const binop vmaxu_obj;
 static CONSTEXPR const binop vmul_obj;
+static CONSTEXPR const vmulh vmulh_obj;
+static CONSTEXPR const vmulh vmulhu_obj;
+static CONSTEXPR 

[PATCH]AArch64[committed] testsuite: remove broken test

[Tamar Christina via Gcc-patches]

Hi All,

This test is somewhat broken, on systems with the profiling extension it fails
because the +profile is required.

The functionality tested here is already tested in nativecpu tests, so deleting
this test. 

Committed under the obvious rule.

Regtested on aarch64-none-linux-gnu and no issues.

Ok for master?

Thanks,
Tamar

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/options_set_10.c: Removed.

--- inline copy of patch -- 
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_10.c 
b/gcc/testsuite/gcc.target/aarch64/options_set_10.c
deleted file mode 100644
index 
1fc8aa86fd6ef7a7a8f502be149f07514091eccd..
--- a/gcc/testsuite/gcc.target/aarch64/options_set_10.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
-/* { dg-additional-options "-mcpu=native" } */
-
-int main ()
-{
-  return 0;
-}
-
-/* { dg-final { scan-assembler-not {\.arch .+\+profile.*} } } */
-
- /* Check that an empty feature string is not detected during mcpu=native.  */




-- 
diff --git a/gcc/testsuite/gcc.target/aarch64/options_set_10.c 
b/gcc/testsuite/gcc.target/aarch64/options_set_10.c
deleted file mode 100644
index 
1fc8aa86fd6ef7a7a8f502be149f07514091eccd..
--- a/gcc/testsuite/gcc.target/aarch64/options_set_10.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
-/* { dg-additional-options "-mcpu=native" } */
-
-int main ()
-{
-  return 0;
-}
-
-/* { dg-final { scan-assembler-not {\.arch .+\+profile.*} } } */
-
- /* Check that an empty feature string is not detected during mcpu=native.  */

Re: [wwwdocs] document modula-2 in gcc-13/changes.html (and index.html)

[Gaius Mulley via Gcc-patches]

Gerald Pfeifer  writes:

> On Fri, 3 Feb 2023, Gaius Mulley wrote:
>> The following patch provides a summary of the modula-2 front end
>> and also contains links to the online modula-2 documentation in
>> index.html.
>
>> +Modula-2
>> +
>> +  Support for the language Modula-2 has been added.  The dialects
>> +  supported are PIM2, PIM3, PIM4 and ISO/IEC 10514-1.  Also included
>> +  are a complete set of ISO/IEC 10514-1 libraries and PIM
>> +libraries.
>
> I wonder whether we can this a bit more active. 
>
> Maybe something like "This includes support for the ... dialects, a 
> complete set of ...and ..."?
>
>> +  https://gcc.gnu.org/onlinedocs/m2/Compiler-options.html";>
>> +  Compiler options.
>
> Maybe put this in parenthesis since it's not an update as such and more 
> relatives to the previous item?
>
>> +  Linking has been redesigned.
>
> What are we saying here? I.e., what is the change we are announcing? As a 
> user, what might I notice? Why do I care?
>

Thanks for spotting this - agreed.

> The above are questions to possibly improve this for our users. Please 
> adjust as you see fit, or push as is, if you prefer.
>
>
> On a somewhat related note: This is definitely big enough to warrant an 
> entry in the News section on our main page. :-)  Do you want to propose
> something?
>
> Gerald

Ah yes thank you for the advice - here is an improved proposed patch
containing:

* htdocs/frontends.html: An update to say the front end is now in
the development trunk.
* htdocs/gcc-13/changes.html: A description of which dialects are
supported and the user level front end changes so far.
* htdocs/index.html: Proposed news entry.
* htdocs/onlinedocs/index.html: PDF, PS and HTML documentation
links.

regards,
Gaius


diff --git a/htdocs/frontends.html b/htdocs/frontends.html
index 12af359b..75be4658 100644
--- a/htdocs/frontends.html
+++ b/htdocs/frontends.html
@@ -41,10 +41,10 @@ has a back end that generates assembler directly, using the 
GCC back end.
 (at an early stage of development).
 
 http://www.nongnu.org/gm2/";>GNU Modula-2 implements
-the PIM2, PIM3, PIM4 and ISO dialects of the language.  The compiler
-is fully operational with GCC 10 and GCC 11 (on
-GNU/Linux x86 systems).  Work is in progress to move the front end to
-the GCC trunk.  The front end is mostly written in Modula-2 and it
+the ISO/IEC 10514-1, PIM2, PIM3 and PIM4 dialects of the language.
+The compiler is operational with GCC 10, GCC 11 GCC 12 (on
+GNU/Linux x86 systems).  The front end is now in the GCC development
+trunk (GCC 13).  The front end is mostly written in Modula-2 and it
 includes a bootstrap tool which translates Modula-2 into C/C++.
 
 Modula-3 (for links see 
 
 
 
+Modula-2
+
+  Support for the language Modula-2 has been added.  This includes
+support for the ISO/IEC 10514-1, PIM2, PIM3, PIM4 dialects
+together with a complete set of ISO/IEC 10514-1 and PIM
+libraries.
+  The <* noreturn *> attribute is supported
+with the -Wreturn-type
+https://gcc.gnu.org/onlinedocs/m2/Compiler-options.html";>
+  option.
+
+
 
 
 
diff --git a/htdocs/index.html b/htdocs/index.html
index 80730c06..3d03ef46 100644
--- a/htdocs/index.html
+++ b/htdocs/index.html
@@ -61,6 +61,11 @@ mission statement.
   has been contributed to Compiler Explorer (aka godbolt.org) by Marc
   Poulhiès
 
+Modula-2 front end 
added
+  [2022-12-14]
+The Modula-2 programming language front end has been added to GCC.
+  This front end was contributed by Gaius Mulley.
+
 https://gcc.gnu.org/wiki/cauldron2022";>GNU Tools Cauldron 
2022
 [2022-09-02]
 Prague, Czech Republic and online, September 16-18 2022
diff --git a/htdocs/onlinedocs/index.html b/htdocs/onlinedocs/index.html
index 343ff9f5..27a8a505 100644
--- a/htdocs/onlinedocs/index.html
+++ b/htdocs/onlinedocs/index.html
@@ -1647,6 +1647,12 @@ existing release.
href="https://gcc.gnu.org/onlinedocs/gdc.ps.gz";>PostScript or https://gcc.gnu.org/onlinedocs/gdc-html.tar.gz";>an
HTML tarball)
+https://gcc.gnu.org/onlinedocs/m2/";>GNU M2 Manual (https://gcc.gnu.org/onlinedocs/m2.pdf";>also in
+   PDF or https://gcc.gnu.org/onlinedocs/m2.ps.gz";>PostScript or https://gcc.gnu.org/onlinedocs/m2-html.tar.gz";>an
+   HTML tarball)
 https://gcc.gnu.org/onlinedocs/libgomp/";>GNU Offloading and
Multi Processing Runtime Library Manual (https://gcc.gnu.org/onlinedocs/libgomp.pdf";>also in

Re: [PATCH 1/2] Handle component_ref to a structre/union field including flexible array member [PR101832]

[Richard Biener via Gcc-patches]

On Fri, 3 Feb 2023, Qing Zhao wrote:

> 
> 
> > On Feb 3, 2023, at 2:49 AM, Richard Biener  wrote:
> > 
> > On Thu, 2 Feb 2023, Qing Zhao wrote:
> > 
> >> 
> >> 
> >>> On Feb 2, 2023, at 8:54 AM, Richard Biener  wrote:
> >>> 
> >>> On Thu, 2 Feb 2023, Qing Zhao wrote:
> >>> 
>  
>  
> > 
> > [...]
> > 
>  +return flexible_size_type_p (TREE_TYPE (last));
> >>> 
> >>> For types with many members this can become quite slow (IIRC we had
> >>> bugs about similar walks of all fields in types), and this function
> >>> looks like it's invoked multiple times on the same type per TU.
> >>> 
> >>> In principle the property is fixed at the time we lay out a record
> >>> type, so we might want to compute it at that time and record the
> >>> result.
> >> 
> >> You mean in FE? 
> > 
> > Yes, either in the frontend or in the middle-ends layout_type.
> > 
> >> Yes, that?s better and cleaner.
> >> 
> >> I will add one more field in the TYPE structure to record this 
> >> information and check this field during middle end.
> >> 
> >> I had the same thought in the beginning, but not sure whether adding a 
> >> new field in IR is necessary or not, other places in middle end might 
> >> not use this new field.
> > 
> > It might be interesting to search for other code walking all fields of
> > a type to determine this or similar info.
>  
>  There is one which is defined in tree.cc but only is referenced in 
>  c/c-decl.cc:
>  
>  /* Determine whether TYPE is a structure with a flexible array member,
>   or a union containing such a structure (possibly recursively).  */
>  flexible_array_type_p
>  
>  However, this routine is a little different than the one I tried to add:
>  
>  In the current routine ?flexible_array_type_p?,  only one level nesting 
>  in the structure is accepted, multiple nesting in structure is not 
>  permitted.
>  
>  So, my question is:  shall we accept multiple nesting in structure? i.e.
> >>> 
> >>> If we don't reject the testcase with an error, then yes.
> >> 
> >> Gcc currently accepts the multiple nesting in structure without error.  
> >> So, we will continue to accept such extension as long as the flex array 
> >> is at the end of the structure. At the same time, for the case the flex 
> >> array is in the middle of the structure, issue additional warnings now 
> >> to discourage such usage, and deprecate this case in a future release.
> >> 
> >> Does this sound reasonable? 
> > 
> > Please don't mix several issues - I think the flex array in the
> > middle of a structure is separate and we shouldn't report that
> > as flexible_array_type_p or flexible_size_type_p since the size
> > of the containing structure is not variable.
> Agreed on this.
> 
> My major question here is (for documentation change, sorry for mixing 
> this thread with the documentation change): do we need to document this 
> case together with the case in which struct with flex array is embedded 
> into another structure? (As a GCC extension?)

I think this should be Josephs call - documenting this might
encourage people to use such an extension, even if it's a bad
one we want to get rid of.

Maybe the easiest thing is to come up with a patch documenting it
which we can then turn into a deprecation note depending on this
outcome.

Richard.