Re: [PATCH] tree-optimization: [PR108684] ICE in verify_ssa due to simple_dce_from_worklist

[Richard Biener via Gcc-patches]

On Wed, Feb 8, 2023 at 8:14 PM Andrew Pinski via Gcc-patches
 wrote:
>
> In simple_dce_from_worklist, we were removing an inline-asm which had a vdef
> (due to clobbering memory) but not unlinking the statement's vdef.
> This fixes that oversight. This was a latent bug exposed recently
> by both VRP and removal of stores to static starting to use
> simple_dce_from_worklist.
>
> OK for trunk (and for GCC 12 after a week)?
> Bootstrapped and tested on x86_64-linux-gnu with no regressions.

I think this is actually wrong-code - we cannot remove memory side-effects
of a stmt and the

  /* The defining statement needs to be defining only this name.
 ASM is the only statement that can define more than one
 (non-virtual) name. */
  if (is_a(t)
  && !single_ssa_def_operand (t, SSA_OP_DEF))
continue;

should use SSA_OP_ALL_DEFS instead.

OK with that change.

Richard.

> PR tree-optimization/108684
>
> gcc/ChangeLog:
>
> * tree-ssa-dce.cc (simple_dce_from_worklist):
> Call unlink_stmt_vdef on the statement before
> removing it.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.c-torture/compile/dce-inline-asm-1.c: New test.
> * gcc.c-torture/compile/dce-inline-asm-2.c: New test.
>
> co-authored-by: Andrew Macleod  
> ---
>  .../gcc.c-torture/compile/dce-inline-asm-1.c | 15 +++
>  .../gcc.c-torture/compile/dce-inline-asm-2.c | 16 
>  gcc/tree-ssa-dce.cc  |  1 +
>  3 files changed, 32 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c
>  create mode 100644 gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c
>
> diff --git a/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c 
> b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c
> new file mode 100644
> index 000..a9f02e44bd7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c
> @@ -0,0 +1,15 @@
> +/* PR tree-optimization/108684 */
> +/* This used to ICE as when we remove the store to
> +   `t`, we also would remove the inline-asm which
> +   had a VDEF on it but we didn't update the
> +   VUSE that was later on.  */
> +static int t;
> +
> +int f (int *a)
> +{
> +  int t1;
> +  asm (" " : "=X" (t1) : : "memory");
> +  t = t1;
> +  return *a;
> +}
> +
> diff --git a/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c 
> b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c
> new file mode 100644
> index 000..a41b16e4bd0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c
> @@ -0,0 +1,16 @@
> +/* PR tree-optimization/108684 */
> +/* This used to ICE as when we removed the
> +   __builtin_unreachable in VRP, as we
> +   would also remove the branch and the
> +   inline-asm. The inline-asm had a VDEF on it,
> +   which we didn't update further along and
> +   not have the VDEF on the return statement
> +   updated.  */
> +
> +int f (int a)
> +{
> +  asm (" " : "=X" (a) : : "memory");
> +  if (a)
> +return 0;
> +  __builtin_unreachable();
> +}
> diff --git a/gcc/tree-ssa-dce.cc b/gcc/tree-ssa-dce.cc
> index b2fe9f4f55e..752785541e4 100644
> --- a/gcc/tree-ssa-dce.cc
> +++ b/gcc/tree-ssa-dce.cc
> @@ -2140,6 +2140,7 @@ simple_dce_from_worklist (bitmap worklist)
> remove_phi_node (&gsi, true);
>else
> {
> + unlink_stmt_vdef (t);
>   gsi_remove (&gsi, true);
>   release_defs (t);
> }
> --
> 2.31.1
>

Re: [PATCH] When simplifing BFR of an insert, require a mode precision integral type (PR108688)

[Richard Biener via Gcc-patches]

On Wed, Feb 8, 2023 at 10:15 PM Andrew Pinski via Gcc-patches
 wrote:
>
> The same problem as PR 88739 has crept in but
> this time in match.pd when simplifying bit_field_ref of
> an bit_insert. That is we are generating a BIT_FIELD_REF
> of a non-mode-precision integral type.
>
> OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.

Hmm.  Can we handle the case of the extraction exactly covering the
insertion separately then and simplify to plain @1?

Thanks,
Richard.

> PR tree-optimization/108688
>
> gcc/ChangeLog:
>
> * match.pd (bit_field_ref [bit_insert]):
> Avoid generating BIT_FIELD_REFs of non-mode-precision
> integral operands
>
> gcc/testsuite/ChangeLog:
>
> * gcc.c-torture/compile/pr108688-1.c: New test.
> ---
>  gcc/match.pd |  4 +++-
>  gcc/testsuite/gcc.c-torture/compile/pr108688-1.c | 15 +++
>  2 files changed, 18 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr108688-1.c
>
> diff --git a/gcc/match.pd b/gcc/match.pd
> index c9e8bebede2..d8353072822 100644
> --- a/gcc/match.pd
> +++ b/gcc/match.pd
> @@ -7487,7 +7487,9 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
>isize = tree_to_uhwi (TYPE_SIZE (TREE_TYPE (@1)));
>}
>(switch
> -   (if (wi::leu_p (wi::to_wide (@ipos), wi::to_wide (@rpos))
> +   (if ((!INTEGRAL_TYPE_P (TREE_TYPE (@1))
> + || type_has_mode_precision_p (TREE_TYPE (@1)))
> +&& wi::leu_p (wi::to_wide (@ipos), wi::to_wide (@rpos))
> && wi::leu_p (wi::to_wide (@rpos) + wi::to_wide (@rsize),
>   wi::to_wide (@ipos) + isize))
>  (BIT_FIELD_REF @1 @rsize { wide_int_to_tree (bitsizetype,
> diff --git a/gcc/testsuite/gcc.c-torture/compile/pr108688-1.c 
> b/gcc/testsuite/gcc.c-torture/compile/pr108688-1.c
> new file mode 100644
> index 000..43d782d62bd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.c-torture/compile/pr108688-1.c
> @@ -0,0 +1,15 @@
> +
> +
> +union U { signed int d : 7; signed int e : 2; } u;
> +int a, b;
> +
> +void
> +foo (void)
> +{
> +  for (int i = 0; i < 64; i++)
> +{
> +  u.d = a;
> +  u.e ^= b;
> +}
> +}
> +
> --
> 2.17.1
>

Re: [PATCH] lto-wrapper: Pass through -funwind-tables and -fasynchronous-unwind-tables

[Richard Biener via Gcc-patches]

On Mon, Feb 6, 2023 at 4:27 PM Andreas Schwab via Gcc-patches
 wrote:
>
> The -funwind-tables and -fasynchronous-unwind-tables options are relevant
> for the output pass, so they need to be passed through by the LTO wrapper.
> Otherwise, dwarf2out_assembly_start may output a ".cfi_sections
> .debug_frame" directive when debug info was enabled even if every
> translation unit was compiled with -funwind-tables.

OK.

> gcc/
> * lto-wrapper.cc (merge_and_complain): Handle
> -funwind-tables and -fasynchronous-unwind-tables.
> (append_compiler_options): Likewise.
> ---
>  gcc/lto-wrapper.cc | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/gcc/lto-wrapper.cc b/gcc/lto-wrapper.cc
> index 11c4d1b38a4..fe8c5f6e80d 100644
> --- a/gcc/lto-wrapper.cc
> +++ b/gcc/lto-wrapper.cc
> @@ -335,6 +335,8 @@ merge_and_complain (vec 
> &decoded_options,
>
> case OPT_fopenmp:
> case OPT_fopenacc:
> +   case OPT_fasynchronous_unwind_tables:
> +   case OPT_funwind_tables:
>   /* For selected options we can merge conservatively.  */
>   if (existing_opt == -1)
> decoded_options.safe_push (*foption);
> @@ -737,6 +739,8 @@ append_compiler_options (obstack *argv_obstack, 
> vec opts)
> case OPT_fopenacc_dim_:
> case OPT_foffload_abi_:
> case OPT_fcf_protection_:
> +   case OPT_fasynchronous_unwind_tables:
> +   case OPT_funwind_tables:
> case OPT_g:
> case OPT_O:
> case OPT_Ofast:
> --
> 2.39.1
>
>
> --
> Andreas Schwab, SUSE Labs, sch...@suse.de
> GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
> "And now for something completely different."

[PATCH] c++, debug: Fix up locus of DW_TAG_imported_module [PR108716]

[Jakub Jelinek via Gcc-patches]

Hi!

Before IMPORTED_DECL has been introduced in PR37410, we used to emit correct
DW_AT_decl_line on DW_TAG_imported_module on the testcase below, after that
change we haven't emitted it at all for a while and after some time
started emitting incorrect locus, in particular the location of } closing
the function.

The problem is that while we have correct EXPR_LOCATION on the USING_STMT,
when genericizing that USING_STMT into IMPORTED_DECL we don't copy the
location to DECL_SOURCE_LOCATION, so it gets whatever input_location happens
to be when it is created.

The following patch fixes that, bootstrapped/regtested on x86_64-linux and
i686-linux, ok for trunk?

2023-02-09  Jakub Jelinek  

PR debug/108716
* cp-gimplify.cc (cp_genericize_r) : Set
DECL_SOURCE_LOCATION on IMPORTED_DECL to expression location
of USING_STMT or input_location.

* g++.dg/debug/dwarf2/pr108716.C: New test.

--- gcc/cp/cp-gimplify.cc.jj2023-02-01 10:19:43.038140336 +0100
+++ gcc/cp/cp-gimplify.cc   2023-02-08 10:36:00.301501540 +0100
@@ -1514,6 +1514,8 @@ cp_genericize_r (tree *stmt_p, int *walk
tree using_directive = make_node (IMPORTED_DECL);
TREE_TYPE (using_directive) = void_type_node;
DECL_CONTEXT (using_directive) = current_function_decl;
+   DECL_SOURCE_LOCATION (using_directive)
+ = cp_expr_loc_or_input_loc (stmt);
 
IMPORTED_DECL_ASSOCIATED_DECL (using_directive) = decl;
DECL_CHAIN (using_directive) = BLOCK_VARS (block);
--- gcc/testsuite/g++.dg/debug/dwarf2/pr108716.C.jj 2023-02-08 
11:48:39.667385750 +0100
+++ gcc/testsuite/g++.dg/debug/dwarf2/pr108716.C2023-02-08 
11:48:57.998115610 +0100
@@ -0,0 +1,14 @@
+// PR debug/108716
+// { dg-options "-O0 -gdwarf-5 -dA -fno-merge-debug-strings" }
+// { dg-final { scan-assembler "DIE \\(\[^\n\r\]*\\) 
DW_TAG_imported_module\[^\n\r\]*\[\n\r]*\[^\n\r\]* 
DW_AT_decl_file\[^\n\r\]*\[\n\r]*\[^\n\r\]*0xc\[^\n\r\]* 
DW_AT_decl_line\[^\n\r\]*\[\n\r]*(\[^\n\r\]*0x13\[^\n\r\]* 
DW_AT_decl_column\[^\n\r\]*\[\n\r]*)?" } }
+
+namespace M {
+  int x = 1;
+}
+
+int
+main ()
+{
+  using namespace M;
+  return 0;
+}

Jakub

[Patch] Fortran/OpenMP: Fix -fopenmp-simd for 'omp assume(s)'

[Tobias Burnus]

Found by chance recently; I thought about a couple of ways to handle it
but then settled to the proposed solution.

OK for mainline?

Tobias
-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 
München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas 
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München, HRB 106955
Fortran/OpenMP: Fix -fopenmp-simd for 'omp assume(s)'

While 'omp assume' is enabled by -fopenmp-simd, 'omp assumes' is not;
however, due to the way parsing works in Fortran (esp. for fixed-form
source code), 'assumes' was parsed by 'assume' which then stumbled over
the tailing 's'.

gcc/fortran/

* parse.cc (decode_omp_directive): Really ignore 'assumes' with
	-fopenmp-simd.

gcc/testsuite/

* gfortran.dg/gomp/openmp-simd-8.f90: New test.

 gcc/fortran/parse.cc |  3 +++
 gcc/testsuite/gfortran.dg/gomp/openmp-simd-8.f90 | 25 
 2 files changed, 28 insertions(+)

diff --git a/gcc/fortran/parse.cc b/gcc/fortran/parse.cc
index 039e7e7da53..f5154d97ae8 100644
--- a/gcc/fortran/parse.cc
+++ b/gcc/fortran/parse.cc
@@ -885,6 +885,9 @@ decode_omp_directive (void)
   switch (c)
 {
 case 'a':
+  /* For -fopenmp-simd, ignore 'assumes'; note no clause starts with 's'. */
+  if (!flag_openmp && gfc_match ("assumes") == MATCH_YES)
+	break;
   matcho ("assumes", gfc_match_omp_assumes, ST_OMP_ASSUMES);
   matchs ("assume", gfc_match_omp_assume, ST_OMP_ASSUME);
   matcho ("atomic", gfc_match_omp_atomic, ST_OMP_ATOMIC);
diff --git a/gcc/testsuite/gfortran.dg/gomp/openmp-simd-8.f90 b/gcc/testsuite/gfortran.dg/gomp/openmp-simd-8.f90
new file mode 100644
index 000..cf92abf2f9e
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/gomp/openmp-simd-8.f90
@@ -0,0 +1,25 @@
+! { dg-options "-fno-openmp -fopenmp-simd -fdump-tree-original" }
+
+! While 'omp assumes' is ignored with -fopenmp-simd,
+! 'omp assume' is processed - check that this works.
+
+module m
+  !$omp assumes no_openmp invalid_clause  ! Should get ignored
+contains
+  integer function foo()
+foo = 5
+  end function
+end
+
+program main
+  use m
+  implicit none
+  !$omp assumes no_openmp  ! likewise ignored
+  integer :: n
+  !$omp assume holds (foo() > 0) ! should be honoured
+n = foo()
+if (n == 0) stop
+  !$omp end assume
+end
+
+! { dg-final { scan-tree-dump "\\.ASSUME \\(foo \\(\\) > 0\\);" "original" } }

Re: [Patch] libgomp: Fix reverse-offload for GOMP_MAP_TO_PSET

[Tobias Burnus]

(Updated to fix -m32 build, otherwise unchanged.)

Any other comments?

On 07.02.23 23:51, Thomas Schwinge wrote:


On 2023-02-06T12:52:11+0100, Tobias Burnus  wrote:

Seems as if I missed a GOMP_MAP_TO_PSET issue before. As nvptx is
XFAILed before, I only found it when testing on AMDGCN.

For an array-descriptor 'ai' variable, omplower has:
map(tofrom:MEM  [(integer(kind=4)[0:] *)D.4346] [len: 
D.4345])
map(to:ai [pointer set, len: 64])
map(alloc:ai.data [pointer assign, bias: 0])

The latter reaches GCC with the same address as 'ai' – i.e. the
one of the array descriptor. This then needs to be dereferenced
to get the address of the actual pointer.
The patch assumes (and asserts) that 'ai.data' is part of the 'ai'
such that I can use the host address of 'ai' to access the data.
If that's not guaranteed, we have to find another way (e.g. another
lookup). But so far it seems to hold and I have not seen a bias
other than 0.

With that patch, libgomp.fortran/reverse-offload-5.f90 now works
with AMDGCN.

...

OK? Any comments to the attached patch?

...

For x86_64-pc-linux-gnu '-m32' multilib:

...

I suppose you'd do similar to what you already have a few lines above;
that is, cast through 'uintptr_t':

 devaddrs[j] = *(uint64_t *) (uintptr_t) (devaddrs[i] + sizes[j]);

Tobias
-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 
München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas 
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München, HRB 106955
libgomp: Fix reverse-offload for GOMP_MAP_TO_PSET

libgomp/
	* target.c (gomp_target_rev): Dereference ptr
	to get device address.
	* libgomp.fortran/reverse-offload-5.f90: Add test
	for unallocated allocatable.

 libgomp/target.c| 8 +++-
 libgomp/testsuite/libgomp.fortran/reverse-offload-5.f90 | 6 --
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/libgomp/target.c b/libgomp/target.c
index c1682caea13..88f29908a08 100644
--- a/libgomp/target.c
+++ b/libgomp/target.c
@@ -3579,8 +3579,14 @@ gomp_target_rev (uint64_t fn_ptr, uint64_t mapnum, uint64_t devaddrs_ptr,
 		  }
 		int k;
 		n2 = NULL;
-		cdata[i].present = true;
+		/* Dereference devaddrs[j] to get the device addr.  */
+		assert (devaddrs[j]-sizes[j] == cdata[i].devaddr);
+		devaddrs[j] = *(uint64_t *) (uintptr_t) (devaddrs[i]
+			 + sizes[j]);
+		cdata[j].present = true;
 		cdata[j].devaddr = devaddrs[j];
+		if (devaddrs[j] == 0)
+		  continue;
 		k = gomp_map_cdata_lookup (cdata, devaddrs, kinds, sizes, j,
 	   devaddrs[j],
 	   devaddrs[j] + sizeof (void*),
diff --git a/libgomp/testsuite/libgomp.fortran/reverse-offload-5.f90 b/libgomp/testsuite/libgomp.fortran/reverse-offload-5.f90
index ef7eb7bdd52..16810eb47de 100644
--- a/libgomp/testsuite/libgomp.fortran/reverse-offload-5.f90
+++ b/libgomp/testsuite/libgomp.fortran/reverse-offload-5.f90
@@ -24,7 +24,7 @@ s2 = 55
 
 !$omp target map(to: A, A2, s1, s2)
 block
-  integer, allocatable :: ai(:), ai2(:), si1, si2
+  integer, allocatable :: ai(:), ai2(:), ai3(:), si1, si2, si3
 
   a = a * 2
   a2 = a2 * 3
@@ -38,7 +38,7 @@ block
 
   !$omp target device (ancestor:1)  &
   !$omp&   map(to: A, s1, ai, si1) map(always, to: a2, s2)  &
-  !$omp&   map(tofrom: ai2, si2)
+  !$omp&   map(tofrom: ai2, si2, ai3, si3)
 if (shared_mem) then
   if (any (a  /= 2 * [1,2,3,4])) stop 1
   if (s1 /= 4 * 532) stop 2
@@ -52,6 +52,7 @@ block
 if (any (ai2 /= [8,4,7,1])) stop 8
 if (si1 /= 64) stop 9
 if (si2 /= 765) stop 10
+if (allocated (ai3) .or. allocated(si3)) stop 26
 
 a = a*3
 a2 = a2*7
@@ -80,6 +81,7 @@ block
   endif
   if (any (ai2 /= 21 * [8,4,7,1])) stop 24
   if (si2 /= 31 * 765) stop 25
+  if (allocated (ai3) .or. allocated(si3)) stop 27
 
   deallocate (ai, ai2, si1, si2)
 end block

Re: [Patch] Fortran/OpenMP: Fix -fopenmp-simd for 'omp assume(s)'

[Jakub Jelinek via Gcc-patches]

On Thu, Feb 09, 2023 at 09:56:09AM +0100, Tobias Burnus wrote:
> Found by chance recently; I thought about a couple of ways to handle it
> but then settled to the proposed solution.
> 
> OK for mainline?
> 
> Tobias
> -
> Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 
> München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas 
> Heurung, Frank Thürauf; Sitz der Gesellschaft: München; Registergericht 
> München, HRB 106955

> Fortran/OpenMP: Fix -fopenmp-simd for 'omp assume(s)'
> 
> While 'omp assume' is enabled by -fopenmp-simd, 'omp assumes' is not;
> however, due to the way parsing works in Fortran (esp. for fixed-form
> source code), 'assumes' was parsed by 'assume' which then stumbled over
> the tailing 's'.
> 
> gcc/fortran/
> 
> * parse.cc (decode_omp_directive): Really ignore 'assumes' with
>   -fopenmp-simd.
> 
> gcc/testsuite/
> 
> * gfortran.dg/gomp/openmp-simd-8.f90: New test.

Ok.

Jakub

[PATCH] testsuite: adjust patterns in RISC-V tests to skip unwind table directives

[Andreas Schwab via Gcc-patches]

PR target/108723
* gcc.target/riscv/shorten-memrefs-1.c: Adjust patterns to skip
over cfi directives.
* gcc.target/riscv/shorten-memrefs-2.c: Likewise.
* gcc.target/riscv/shorten-memrefs-3.c: Likewise.
* gcc.target/riscv/shorten-memrefs-4.c: Likewise.
* gcc.target/riscv/shorten-memrefs-5.c: Likewise.
* gcc.target/riscv/shorten-memrefs-6.c: Likewise.
* gcc.target/riscv/shorten-memrefs-8.c: Likewise.
---
 gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c | 4 ++--
 gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c | 8 
 gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c | 2 +-
 gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c | 4 ++--
 gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c | 8 
 gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c | 2 +-
 gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c | 4 ++--
 7 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c 
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
index f0222f46eff..cce7c80f6c1 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
@@ -23,5 +23,5 @@ store2z (long long *array)
   array[203] = 0;
 }
 
-/* { dg-final { scan-assembler-not "store1z:\n\taddi" } } */
-/* { dg-final { scan-assembler-not "store2z:\n\taddi" } } */
+/* { dg-final { scan-assembler-not "store1z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */
+/* { dg-final { scan-assembler-not "store2z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c 
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
index ec39104fd88..a9ddb797d06 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
@@ -44,9 +44,9 @@ load2r (long long *array)
   return a;
 }
 
-/* { dg-final { scan-assembler "store1a:\n\taddi" } } */
+/* { dg-final { scan-assembler "store1a:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
 /* The sd insns in store2a are not rewritten because shorten_memrefs currently
only optimizes lw and sw.
-/* { dg-final { scan-assembler "store2a:\n\taddi" { xfail riscv*-*-*  } } } */
-/* { dg-final { scan-assembler "load1r:\n\taddi" } } */
-/* { dg-final { scan-assembler "load2r:\n\taddi" } } */
+/* { dg-final { scan-assembler "store2a:\n(\t?\\.\[^\n\]*\n)*\taddi" { xfail 
riscv*-*-*  } } } */
+/* { dg-final { scan-assembler "load1r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
+/* { dg-final { scan-assembler "load2r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c 
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
index 50316284832..3d561124b81 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
@@ -36,5 +36,5 @@ load2a (long long a0, long long a1, long long a2, long long 
a3, long long a4,
   return sub2 (a0, a1, a2, a3, a4, 0, a);
 }
 
-/* { dg-final { scan-assembler-not "load1a:\n\taddi" { xfail riscv*-*-* } } } 
*/
+/* { dg-final { scan-assembler-not "load1a:\n(\t?\\.\[^\n\]*\n)*\taddi" { 
xfail riscv*-*-* } } } */
 /* { dg-final { scan-assembler-not "load2a:\n.*addi\[ 
\t\]*\[at\]\[0-9\],\[at\]\[0-9\],\[0-9\]*" { xfail riscv*-*-*  } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c 
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
index d985512e2b3..26decf085fb 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
@@ -23,5 +23,5 @@ store2z (long long *array)
   array[203] = 0;
 }
 
-/* { dg-final { scan-assembler-not "store1z:\n\taddi" } } */
-/* { dg-final { scan-assembler-not "store2z:\n\taddi" } } */
+/* { dg-final { scan-assembler-not "store1z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */
+/* { dg-final { scan-assembler-not "store2z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c 
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
index 9217922c10d..11e858ed6da 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
@@ -44,11 +44,11 @@ load2r (long long *array)
   return a;
 }
 
-/* { dg-final { scan-assembler "store1a:\n\taddi" } } */
+/* { dg-final { scan-assembler "store1a:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
 /* The sd insns in store2a are not rewritten because shorten_memrefs currently
only optimizes lw and sw.
-/* { dg-final { scan-assembler "store2a:\n\taddi" { xfail riscv*-*-* } } } */
-/* { dg-final { scan-assembler "load1r:\n\taddi" } } */
+/* { dg-final { scan-assembler "store2a:\n(\t?\\.\[^\n\]*\n)*\taddi" { xfail 
riscv*-*-* } } } */
+/* { dg-final { scan-assembler "load1r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
 /* The ld insns in load2r are not rewritten because shorten_memrefs currently
only optimizes lw and sw.
-/* { dg-final { scan-assembler "load2r:\n\taddi" { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler "lo

Re: [PATCH] When simplifing BFR of an insert, require a mode precision integral type (PR108688)

[Jakub Jelinek via Gcc-patches]

On Thu, Feb 09, 2023 at 09:16:17AM +0100, Richard Biener via Gcc-patches wrote:
> On Wed, Feb 8, 2023 at 10:15 PM Andrew Pinski via Gcc-patches
>  wrote:
> >
> > The same problem as PR 88739 has crept in but
> > this time in match.pd when simplifying bit_field_ref of
> > an bit_insert. That is we are generating a BIT_FIELD_REF
> > of a non-mode-precision integral type.
> >
> > OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.
> 
> Hmm.  Can we handle the case of the extraction exactly covering the
> insertion separately then and simplify to plain @1?

I was suggesting that in the PR.  Here it is as an incremental patch
on top of Andrew's patch.  Ok for trunk if it passes bootstrap/regtest?

On the newly added testcase the ifcvt-folding difference without/with the
incremental patch is:
--- pr108688.c.171t.ifcvt_  2023-02-09 10:47:30.169916845 +0100
+++ pr108688.c.171t.ifcvt   2023-02-09 10:48:44.942793453 +0100
@@ -25,6 +25,8 @@ Number of blocks in CFG: 11
 Number of blocks to update: 5 ( 45%)
 
 
+Applying pattern match.pd:7487, gimple-match.cc:243200
+Applying pattern match.pd:3987, gimple-match.cc:75423
 Matching expression match.pd:1677, gimple-match.cc:209
 Applying pattern match.pd:1733, gimple-match.cc:109481
 Matching expression match.pd:2393, gimple-match.cc:852
@@ -70,7 +72,6 @@ void foo ()
   signed char _29;
_30;
   unsigned int ivtmp_33;
-   _ifc__35;
   unsigned char _ifc__37;
   unsigned char _ifc__38;
   unsigned char _ifc__39;
@@ -91,8 +92,7 @@ void foo ()
   _2 = () a.0_1;
   _ifc__38 = u.D.2741;
   _ifc__39 = BIT_INSERT_EXPR <_ifc__38, _2, 0 (7 bits)>;
-  _ifc__35 = BIT_FIELD_REF <_ifc__39, 7, 0>;
-  _4 = (signed char) _ifc__35;
+  _4 = (signed char) _2;
   b.1_5 = b;
   _6 = (signed char) b.1_5;
   _7 = _4 ^ _6;

2023-02-09  Jakub Jelinek  

PR tree-optimization/108688
* match.pd (bit_field_ref [bit_insert]): Simplify BIT_FIELD_REF
of BIT_INSERT_EXPR extracting exactly all inserted bits even
when without mode precision.  Formatting fixes.

* gcc.c-torture/compile/pr108688-1.c: Add PR number as comment.
* gcc.dg/pr108688.c: New test.

--- gcc/match.pd.jj 2023-02-09 09:42:53.782418805 +0100
+++ gcc/match.pd2023-02-09 10:48:06.859365613 +0100
@@ -7475,13 +7475,16 @@ (define_operator_list SYNC_FETCH_AND_AND
   }
   (switch
(if ((!INTEGRAL_TYPE_P (TREE_TYPE (@1))
- || type_has_mode_precision_p (TREE_TYPE (@1)))
-&& wi::leu_p (wi::to_wide (@ipos), wi::to_wide (@rpos))
+|| type_has_mode_precision_p (TREE_TYPE (@1)))
+   && wi::leu_p (wi::to_wide (@ipos), wi::to_wide (@rpos))
&& wi::leu_p (wi::to_wide (@rpos) + wi::to_wide (@rsize),
  wi::to_wide (@ipos) + isize))
 (BIT_FIELD_REF @1 @rsize { wide_int_to_tree (bitsizetype,
- wi::to_wide (@rpos)
+wi::to_wide (@rpos)
 - wi::to_wide (@ipos)); }))
+   (if (wi::eq_p (wi::to_wide (@ipos), wi::to_wide (@rpos))
+&& compare_tree_int (@rsize, isize) == 0)
+(convert @1))
(if (wi::geu_p (wi::to_wide (@ipos),
   wi::to_wide (@rpos) + wi::to_wide (@rsize))
|| wi::geu_p (wi::to_wide (@rpos),
--- gcc/testsuite/gcc.c-torture/compile/pr108688-1.c.jj 2023-02-09 
09:42:53.782418805 +0100
+++ gcc/testsuite/gcc.c-torture/compile/pr108688-1.c2023-02-09 
10:34:18.339817796 +0100
@@ -1,4 +1,4 @@
-
+/* PR tree-optimization/108688 */
 
 union U { signed int d : 7; signed int e : 2; } u;
 int a, b;
@@ -12,4 +12,3 @@ foo (void)
   u.e ^= b;
 }
 }
-
--- gcc/testsuite/gcc.dg/pr108688.c.jj  2023-02-09 10:50:27.468253110 +0100
+++ gcc/testsuite/gcc.dg/pr108688.c 2023-02-09 10:50:16.383419646 +0100
@@ -0,0 +1,16 @@
+/* PR tree-optimization/108688 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-tree-pre -fno-tree-fre -fno-tree-dominator-opts 
-fno-tree-loop-im -fno-code-hoisting" } */
+
+union U { signed int d : 7; signed int e : 2; } u;
+int a, b;
+
+void
+foo (void)
+{
+  for (int i = 0; i < 64; i++)
+{
+  u.d = a;
+  u.d ^= b;
+}
+}


Jakub

Re: [Patch] OpenMP: Parse align clause in allocate directive in C/C++

[Tobias Burnus]

Updated patch included. Changes:

* Removed xfail for C++

* For C, I updated the comment as suggested.

* For C++: I updated/extended the FIXME comment and added the 'align'
check (the simple version as first suggested; I did not went for the one
which supports some templates.)

Any further comments before I commit it?

Tobias

On 31.01.23 13:09, Jakub Jelinek wrote:

On Tue, Dec 13, 2022 at 06:44:27PM +0100, Tobias Burnus wrote:

OpenMP: Parse align clause in allocate directive in C/C++

gcc/c/ChangeLog:

 * c-parser.cc (c_parser_omp_allocate): Parse align
 clause and check for restrictions.

gcc/cp/ChangeLog:

 * parser.cc (cp_parser_omp_allocate): Parse align
 clause.

gcc/testsuite/ChangeLog:

 * c-c++-common/gomp/allocate-5.c: Extend for align clause.

  gcc/c/c-parser.cc| 88 
  gcc/cp/parser.cc | 58 +-
  gcc/testsuite/c-c++-common/gomp/allocate-5.c | 36 
  3 files changed, 144 insertions(+), 38 deletions(-)

diff --git a/gcc/c/c-parser.cc b/gcc/c/c-parser.cc
index 1bbb39f9b08..62c302748dd 100644
--- a/gcc/c/c-parser.cc
+++ b/gcc/c/c-parser.cc
@@ -18819,32 +18819,71 @@ c_parser_oacc_wait (location_t loc, c_parser *parser, 
char *p_name)
return stmt;
  }

-/* OpenMP 5.0:
-   # pragma omp allocate (list)  [allocator(allocator)]  */
+/* OpenMP 5.x:
+   # pragma omp allocate (list)  clauses
+
+   OpenMP 5.0 clause:
+   allocator (omp_allocator_handle_t expression)
+
+   OpenMP 5.1 additional clause:
+   align (int expression)] */

integer-expression or constant-expression or just expression.
Also, 2 spaces before */ rather than just one.


+  else if (p[2] == 'i')
+{
+  alignment = c_fully_fold (expr.value, false, NULL);
+  if (TREE_CODE (alignment) != INTEGER_CST
+  || !INTEGRAL_TYPE_P (TREE_TYPE (alignment))
+  || tree_int_cst_sgn (alignment) != 1
+  || !integer_pow2p (alignment))

Note, the reason why we diagnose this in c-parser.cc and for C++
in semantics.cc rather than in parser.cc are templates, it would be
wasteful to handle it in two spots (parser.cc and during instantiation).


-  if (allocator)
+  if (allocator || alignment)
  for (tree c = nl; c != NULL_TREE; c = OMP_CLAUSE_CHAIN (c))
-  OMP_CLAUSE_ALLOCATE_ALLOCATOR (c) = allocator;
+  {
+OMP_CLAUSE_ALLOCATE_ALLOCATOR (c) = allocator;
+OMP_CLAUSE_ALLOCATE_ALIGN (c) = alignment;
+  }

So, if you want for now until we actually support the directive
properly diagnose it here in the parser (otherwise there is nothing
to stick it on for later), then it would need either what semantics.cc
currently uses:
   if (!type_dependent_expression_p (align)
   && !INTEGRAL_TYPE_P (TREE_TYPE (align)))
 {
   error_at (OMP_CLAUSE_LOCATION (c),
 "% clause % modifier "
 "argument needs to be positive constant "
 "power of two integer expression");
   remove = true;
 }
   else
 {
   align = mark_rvalue_use (align);
   if (!processing_template_decl)
 {
   align = maybe_constant_value (align);
   if (TREE_CODE (align) != INTEGER_CST
   || !tree_fits_uhwi_p (align)
   || !integer_pow2p (align))
 {
   error_at (OMP_CLAUSE_LOCATION (c),
 "% clause % modifier "
 "argument needs to be positive constant "
 "power of two integer expression");
   remove = true;
 }
 }
 }
with adjusted diagnostics, or perhaps instead of the
!processing_template_decl guarding do
fold_non_dependent_expr (align, !tf_none)
instead of maybe_constant_value and just for
processing_template_decl && TREE_CODE (align) != INTEGER_CST
do nothing instead of the other tests and diagnostics.
With the !processing_template_decl guarding it wouldn't diagnose
ever non-power of two or non-constant operand in templates,
with fold_non_dependent_expr etc. it would as long as they are
not dependent.

Otherwise LGTM, with or without the above changes.

-
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München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas 
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OpenMP: Parse align clause in allocate directive in C/C++

gcc/c/ChangeLog:

	* c-parser.cc (c_parser_omp_allocate): Parse align
	clause and check for restrictions.

gcc/cp/ChangeLog:

	* parser.cc (cp_parser_omp_allocate): Parse align
	cla

Re: [Patch] OpenMP: Parse align clause in allocate directive in C/C++

[Jakub Jelinek via Gcc-patches]

On Thu, Feb 09, 2023 at 11:16:39AM +0100, Tobias Burnus wrote:
> Any further comments before I commit it?
> OpenMP: Parse align clause in allocate directive in C/C++
> 
> gcc/c/ChangeLog:
> 
>   * c-parser.cc (c_parser_omp_allocate): Parse align
>   clause and check for restrictions.
> 
> gcc/cp/ChangeLog:
> 
>   * parser.cc (cp_parser_omp_allocate): Parse align
>   clause.

The " and check for restrictions" part now applies also to C++...

> +   if (expr != error_mark_node)
> + alignment = expr;
> +   /* FIXME: Remove when adding check to semantic.cc; cf FIXME below.  */

s/semantic.cc/semantics.cc/

Ok with those nits fixed.

Jakub

Re: [PATCH 1/2] Handle component_ref to a structre/union field including flexible array member [PR101832]

[Richard Biener via Gcc-patches]

On Wed, 8 Feb 2023, Qing Zhao wrote:

> 
> 
> > On Feb 7, 2023, at 6:37 PM, Joseph Myers  wrote:
> > 
> > On Tue, 7 Feb 2023, Qing Zhao via Gcc-patches wrote:
> > 
> >> Then, this routine (flexible_array_type_p) is mainly for diagnostic 
> >> purpose.
> >> It cannot be used to determine whether the structure/union type recursively
> >> include a flexible array member at the end.
> >> 
> >> Is my understanding correct?
> > 
> > My comments were about basic principles of what gets diagnosed, and the 
> > need for different predicates in different contexts; I wasn't trying to 
> > assert anything about how that maps onto what functions should be used in 
> > what contexts.
> Okay. 
> 
> But I noticed that “flexible_array_type_p” later was moved from FE to
>  middle-end and put into tree.cc, tree.h as a general utility routine, and to 
> 
> /* Determine whether TYPE is a structure with a flexible array member,
>or a union containing such a structure (possibly recursively).  */
> 
> However, since this routine does not cover the cases when the structure 
> with flexible array member was recursively embedded into structures, (which 
> we 
> agreed that it should be considered as a flexible sized type). 
> 
> Therefore, I feel that It might not be proper to include this routine in 
> middle end 
> (and actually no other places In middle end use this routine so far).
> 
> That’s the reason I asked the previous question. 
> 
> It might be better to move the routine “flexible_array_type_p” back from 
> middle-end to
> FE for the diagnosis purpose only. 

It's always dangerous to move functions with such a descriptive name to
a place where it suggests wider use is applicable.  Also since
objc/objc-act.cc has a function with the same name (if that had same
content before r10-5097-g4569f8b3652ae1 then the function should
have been moved to c-family/ instead).

The only "middle-end" use, btw., is in ./config/nios2/nios2.cc,
intoduced by said revision and your points probably mean this change
was misguided and flexible_array_type_p isn't the thing to fix here.
flexible-size _objects_ are clearly denoted by DECL_SIZE being
non-constant - though the case of .sdata is quite odd and the issue
fixed is probably running into a bug elsewhere ...

Sandra?

Thanks,
Richard.

[PATCH] docs: add cavear for __builtin_cpu_supports

[Martin Liška]

Document that the function does not work correctly for old
VIA processors.

Ready to be installed?
Thanks,
Martin

PR target/100758

gcc/ChangeLog:

* doc/extend.texi: Document that the function
does not work correctly for old VIA processors.
---
 gcc/doc/extend.texi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 5a026c4b48c..2aedf6dfe69 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -22071,6 +22071,9 @@ else
  count = generic_countbits (n); //generic implementation.
   @}
 @end smallexample
+
+Caveat: The built-in function does not work correctly on old VIA
+processors (Centaur family).
 @end deftypefn
 
 The following built-in functions are made available by @option{-mmmx}.
-- 
2.39.1

Re: [PATCH] docs: add cavear for __builtin_cpu_supports

[Gerald Pfeifer]

On Thu, 9 Feb 2023, Martin Liška wrote:
> Document that the function does not work correctly for old VIA 
> processors.

Thanks for doing this, Martin!

> +Caveat: The built-in function does not work correctly on old VIA
> +processors (Centaur family).

Maybe say "This built-in function...", though that's a nuance. The patch 
is okay either way.

Gerald

Re: [PATCH] docs: add cavear for __builtin_cpu_supports

[Martin Liška]

On 2/9/23 11:43, Gerald Pfeifer wrote:
> On Thu, 9 Feb 2023, Martin Liška wrote:
>> Document that the function does not work correctly for old VIA 
>> processors.
> 
> Thanks for doing this, Martin!
> 
>> +Caveat: The built-in function does not work correctly on old VIA
>> +processors (Centaur family).
> 
> Maybe say "This built-in function...", though that's a nuance. The patch 
> is okay either way.

Thanks for review, I've just pushed it with the suggestion.

Martin

> 
> Gerald

[PATCH V1 0/1] UNRATIFIED RISC-V:Add 'ZiCond' extension

[shiyulong]

From: yulong 

*** WAIT FOR SPECIFICATION FREEZE ***
This is an implementation for unratified and not frozen RISC-V extension
and not intended to be merged for now.
The intent to submit this patchset is to synchronize with the implementation
of binutils about the ZiCond extension.

This patchset adds following unratified extension to GNU gcc:

- 'ZiCond'(Integer Conditional Operations) version 1.0 development which
adds 2 instructions ('czero.eqz' and 'czero.nez').

This extension makes conditional arithmetic feature much simpler (fewer
instructions when no branches are allowed).  Note that constant timing
guarantee (data-independence / certain side-channel resistance) for this
extension is being discussed and may not be guaranteed.


This is based on the commit 394e24376939 of the specification document:


*** BLURB HERE ***

yulong (1):
  UNRATIFIED RISC-V: Add 'ZiCond' extension

 gcc/common/config/riscv/riscv-common.cc   |  4 
 gcc/config/riscv/riscv-builtins.cc|  8 
 gcc/config/riscv/riscv-ftypes.def |  2 ++
 gcc/config/riscv/riscv-opts.h |  3 +++
 gcc/config/riscv/riscv-zicond.def |  5 +
 gcc/config/riscv/riscv.md | 22 ++
 gcc/config/riscv/riscv.opt|  3 +++
 gcc/testsuite/gcc.target/riscv/zicond-1.c | 15 +++
 gcc/testsuite/gcc.target/riscv/zicond-2.c | 15 +++
 9 files changed, 77 insertions(+)
 create mode 100644 gcc/config/riscv/riscv-zicond.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-2.c

-- 
2.25.1

[PATCH V1 1/1] UNRATIFIED RISC-V: Add 'ZiCond' extension

[shiyulong]

From: yulong 

[DO NOT MERGE]
Until 'ZiCond' extension is frozen/ratified and final version number is
determined, this patch should not be merged upstream.  This commit uses
version 1.0 as in the documentation.

This commit adds support for the latest draft of RISC-V Integer Conditional
(ZiCond) extension consisting of 2 new instructions.

This is based on the early draft of ZiCond on GitHub:


gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add zicond ext.
* config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): New.
(AVAIL): New.
(RISCV_FTYPE_ATYPES2): New.
* config/riscv/riscv-ftypes.def (2): New.
* config/riscv/riscv-opts.h (MASK_ZICOND): New.
(TARGET_ZICOND): New.
* config/riscv/riscv.md (riscv_eqz_): Add new mode.
(riscv_nez_): Add new mode.
* config/riscv/riscv.opt: New.
* config/riscv/riscv-zicond.def: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zicond-1.c: New test.
* gcc.target/riscv/zicond-2.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   |  4 
 gcc/config/riscv/riscv-builtins.cc|  8 
 gcc/config/riscv/riscv-ftypes.def |  2 ++
 gcc/config/riscv/riscv-opts.h |  3 +++
 gcc/config/riscv/riscv-zicond.def |  5 +
 gcc/config/riscv/riscv.md | 22 ++
 gcc/config/riscv/riscv.opt|  3 +++
 gcc/testsuite/gcc.target/riscv/zicond-1.c | 15 +++
 gcc/testsuite/gcc.target/riscv/zicond-2.c | 15 +++
 9 files changed, 77 insertions(+)
 create mode 100644 gcc/config/riscv/riscv-zicond.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-2.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 787674003cb..5a8b1278ac8 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -190,6 +190,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zicond",ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zk",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zkn",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zks",   ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1209,6 +1211,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM},
   {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP},
 
+  {"zicond", &gcc_options::x_riscv_zicond_subext, MASK_ZICOND},
+
   {"zve32x",   &gcc_options::x_target_flags, MASK_VECTOR},
   {"zve32f",   &gcc_options::x_target_flags, MASK_VECTOR},
   {"zve64x",   &gcc_options::x_target_flags, MASK_VECTOR},
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 25ca407f9a9..66a8126b2b4 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -42,6 +42,7 @@ along with GCC; see the file COPYING3.  If not see
 /* Macros to create an enumeration identifier for a function prototype.  */
 #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
 #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
+#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
 
 /* Classifies the prototype of a built-in function.  */
 enum riscv_function_type {
@@ -99,6 +100,10 @@ AVAIL (zero64,  TARGET_ZICBOZ && TARGET_64BIT)
 AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
 AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
 AVAIL (always, (!0))
+AVAIL (nez32, TARGET_ZICOND && !TARGET_64BIT)
+AVAIL (nez64, TARGET_ZICOND && TARGET_64BIT)
+AVAIL (eqz32, TARGET_ZICOND && !TARGET_64BIT)
+AVAIL (eqz64, TARGET_ZICOND && TARGET_64BIT)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -142,9 +147,12 @@ AVAIL (always, (!0))
   RISCV_ATYPE_##A
 #define RISCV_FTYPE_ATYPES1(A, B) \
   RISCV_ATYPE_##A, RISCV_ATYPE_##B
+#define RISCV_FTYPE_ATYPES2(A, B, C) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
 
 static const struct riscv_builtin_description riscv_builtins[] = {
   #include "riscv-cmo.def"
+  #include "riscv-zicond.def"
 
   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
   DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float),
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index 3a40c33e7c2..d305282d811 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -32,3 +32,5 @@ DEF_RISCV_FTYPE (1, (VOID, USI))
 DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
 DEF_RISCV_FTYPE (1, (SI, SI))
 DEF_RISCV_FTYPE (1, (DI, DI))
+DEF_RISCV_FTYPE (2, (SI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, DI))
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index ff398c0a2ae..0baf6553913 100644
--- a/gc

[og12] 'c-c++-common/gomp/alloc-pinned-1.c' -> 'libgomp.c-c++-common/alloc-pinned-1.c' (was: [PATCH 5/5] openmp: -foffload-memory=pinned)

[Thomas Schwinge]

Hi!

On 2022-03-08T11:30:59+, Hafiz Abid Qadeer  wrote:
> From: Andrew Stubbs 
>
> [...]

> --- /dev/null
> +++ b/gcc/testsuite/c-c++-common/gomp/alloc-pinned-1.c
> @@ -0,0 +1,28 @@
> +/* { dg-do run } */

Pushed to devel/omp/gcc-12 branch
commit 9c0ffa3776a135a69697253a0bd75ebf9b9d0150
"'c-c++-common/gomp/alloc-pinned-1.c' -> 
'libgomp.c-c++-common/alloc-pinned-1.c'",
see attached.

Note that this likewise applies to the current upstream submission:

"openmp: -foffload-memory=pinned".


Grüße
 Thomas


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>From 9c0ffa3776a135a69697253a0bd75ebf9b9d0150 Mon Sep 17 00:00:00 2001
From: Thomas Schwinge 
Date: Mon, 30 Jan 2023 17:46:29 +0100
Subject: [PATCH] 'c-c++-common/gomp/alloc-pinned-1.c' ->
 'libgomp.c-c++-common/alloc-pinned-1.c'

Otherwise, for build-tree testing:

xgcc: fatal error: cannot read spec file 'libgomp.spec': No such file or directory

..., and thus corresponding FAILs, UNRESOLVEDs.

Fix-up for og12 commit 842df187487f5b16ae29bbe7e9acd79661a9df48
"openmp: -foffload-memory=pinned".

	gcc/testsuite/
	* c-c++-common/gomp/alloc-pinned-1.c: Cut.
	libgomp/
	* testsuite/libgomp.c-c++-common/alloc-pinned-1.c: Paste.
---
 gcc/testsuite/ChangeLog.omp   | 2 ++
 libgomp/ChangeLog.omp | 4 
 .../testsuite/libgomp.c-c++-common}/alloc-pinned-1.c  | 0
 3 files changed, 6 insertions(+)
 rename {gcc/testsuite/c-c++-common/gomp => libgomp/testsuite/libgomp.c-c++-common}/alloc-pinned-1.c (100%)

diff --git a/gcc/testsuite/ChangeLog.omp b/gcc/testsuite/ChangeLog.omp
index 42769c7dae5..9f9d5a10ac3 100644
--- a/gcc/testsuite/ChangeLog.omp
+++ b/gcc/testsuite/ChangeLog.omp
@@ -1,5 +1,7 @@
 2023-02-09  Thomas Schwinge  
 
+	* c-c++-common/gomp/alloc-pinned-1.c: Cut.
+
 	* gfortran.dg/gomp/allocate-4.f90: Fix 'omp_allocator_handle_kind'
 	example.
 
diff --git a/libgomp/ChangeLog.omp b/libgomp/ChangeLog.omp
index d319d43ceb0..39165173884 100644
--- a/libgomp/ChangeLog.omp
+++ b/libgomp/ChangeLog.omp
@@ -1,3 +1,7 @@
+2023-02-09  Thomas Schwinge  
+
+	* testsuite/libgomp.c-c++-common/alloc-pinned-1.c: Paste.
+
 2023-02-08  Tobias Burnus  
 
 	Backported from master:
diff --git a/gcc/testsuite/c-c++-common/gomp/alloc-pinned-1.c b/libgomp/testsuite/libgomp.c-c++-common/alloc-pinned-1.c
similarity index 100%
rename from gcc/testsuite/c-c++-common/gomp/alloc-pinned-1.c
rename to libgomp/testsuite/libgomp.c-c++-common/alloc-pinned-1.c
-- 
2.25.1

[og12] '{c-c++-common,gfortran.dg}/gomp/uses_allocators-*' -> 'libgomp.{c-c++-common,fortran}/uses_allocators-*' (was: [PATCH, OpenMP] Implement uses_allocators clause for target regions)

[Thomas Schwinge]

Hi!

On 2022-05-06T21:20:48+0800, Chung-Lin Tang  wrote:
> [...]

> --- /dev/null
> +++ b/gcc/testsuite/c-c++-common/gomp/uses_allocators-1.c

> +#include 

Etc.

> --- /dev/null
> +++ b/gcc/testsuite/gfortran.dg/gomp/uses_allocators-1.f90

> +  use omp_lib

Etc.

Pushed to devel/omp/gcc-12 branch
commit 6e0ba07ff1859bc822c7220bfff18e7e9a147206
"'{c-c++-common,gfortran.dg}/gomp/uses_allocators-*' -> 
'libgomp.{c-c++-common,fortran}/uses_allocators-*'",
see attached.


Grüße
 Thomas


-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 
München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas 
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>From 6e0ba07ff1859bc822c7220bfff18e7e9a147206 Mon Sep 17 00:00:00 2001
From: Thomas Schwinge 
Date: Mon, 30 Jan 2023 17:55:13 +0100
Subject: [PATCH] '{c-c++-common,gfortran.dg}/gomp/uses_allocators-*' ->
 'libgomp.{c-c++-common,fortran}/uses_allocators-*'

Otherwise, for build-tree testing:

[...]/gcc/testsuite/c-c++-common/gomp/uses_allocators-1.c:4:10: fatal error: omp.h: No such file or directory

[...]/gcc/testsuite/c-c++-common/gomp/uses_allocators-2.c:3:10: fatal error: omp.h: No such file or directory

[...]/gcc/testsuite/c-c++-common/gomp/uses_allocators-3.c:4:10: fatal error: omp.h: No such file or directory

[...]/gcc/testsuite/gfortran.dg/gomp/uses_allocators-1.f90:5:7: Fatal Error: Cannot open module file 'omp_lib.mod' for reading at (1): No such file or directory

[...]/gcc/testsuite/gfortran.dg/gomp/uses_allocators-2.f90:4:7: Fatal Error: Cannot open module file 'omp_lib.mod' for reading at (1): No such file or directory

[...]/gcc/testsuite/gfortran.dg/gomp/uses_allocators-3.f90:4:7: Fatal Error: Cannot open module file 'omp_lib.mod' for reading at (1): No such file or directory

..., and thus corresponding FAILs, UNRESOLVEDs.

Fix-up for og12 commit dbc770c4351c8824e8083f8aff6117a6b4ba3c0d
"openmp: Implement uses_allocators clause".

	gcc/testsuite/
	* c-c++-common/gomp/uses_allocators-1.c: Cut.
	* c-c++-common/gomp/uses_allocators-2.c: Likewise.
	* c-c++-common/gomp/uses_allocators-3.c: Likewise.
	* gfortran.dg/gomp/uses_allocators-1.f90: Likewise.
	* gfortran.dg/gomp/uses_allocators-2.f90: Likewise.
	* gfortran.dg/gomp/uses_allocators-3.f90: Likewise.
	libgomp/
	* testsuite/libgomp.c++/c++.exp (check_effective_target_c)
	(check_effective_target_c++): New.
	* testsuite/libgomp.c/c.exp (check_effective_target_c)
	(check_effective_target_c++): Likewise.
	* testsuite/libgomp.c-c++-common/uses_allocators-1.c: Paste.
	* testsuite/libgomp.c-c++-common/uses_allocators-2.c: Likewise.
	* testsuite/libgomp.c-c++-common/uses_allocators-3.c: Likewise.
	* testsuite/libgomp.fortran/uses_allocators-1.f90: Likewise.
	* testsuite/libgomp.fortran/uses_allocators-2.f90: Likewise.
	* testsuite/libgomp.fortran/uses_allocators-3.f90: Likewise.
---
 gcc/testsuite/ChangeLog.omp   |  7 +++
 libgomp/ChangeLog.omp | 11 +++
 libgomp/testsuite/libgomp.c++/c++.exp |  7 +++
 .../libgomp.c-c++-common}/uses_allocators-1.c |  0
 .../libgomp.c-c++-common}/uses_allocators-2.c |  0
 .../libgomp.c-c++-common}/uses_allocators-3.c |  0
 libgomp/testsuite/libgomp.c/c.exp |  7 +++
 .../testsuite/libgomp.fortran}/uses_allocators-1.f90  |  0
 .../testsuite/libgomp.fortran}/uses_allocators-2.f90  |  0
 .../testsuite/libgomp.fortran}/uses_allocators-3.f90  |  0
 10 files changed, 32 insertions(+)
 rename {gcc/testsuite/c-c++-common/gomp => libgomp/testsuite/libgomp.c-c++-common}/uses_allocators-1.c (100%)
 rename {gcc/testsuite/c-c++-common/gomp => libgomp/testsuite/libgomp.c-c++-common}/uses_allocators-2.c (100%)
 rename {gcc/testsuite/c-c++-common/gomp => libgomp/testsuite/libgomp.c-c++-common}/uses_allocators-3.c (100%)
 rename {gcc/testsuite/gfortran.dg/gomp => libgomp/testsuite/libgomp.fortran}/uses_allocators-1.f90 (100%)
 rename {gcc/testsuite/gfortran.dg/gomp => libgomp/testsuite/libgomp.fortran}/uses_allocators-2.f90 (100%)
 rename {gcc/testsuite/gfortran.dg/gomp => libgomp/testsuite/libgomp.fortran}/uses_allocators-3.f90 (100%)

diff --git a/gcc/testsuite/ChangeLog.omp b/gcc/testsuite/ChangeLog.omp
index 9f9d5a10ac3..936e7af0945 100644
--- a/gcc/testsuite/ChangeLog.omp
+++ b/gcc/testsuite/ChangeLog.omp
@@ -1,5 +1,12 @@
 2023-02-09  Thomas Schwinge  
 
+	* c-c++-common/gomp/uses_allocators-1.c: Cut.
+	* c-c++-common/gomp/uses_allocators-2.c: Likewise.
+	* c-c++-common/gomp/uses_allocators-3.c: Likewise.
+	* gfortran.dg/gomp/uses_allocators-1.f90: Likewise.
+	* gfortran.dg/gomp/uses_allocators-2.f90: Likewise.
+	* gfortran.dg/gomp/uses_allocators-3.f90: Likewise.
+
 	* c-c++-common/gomp/alloc-pinned-1.c: Cut.
 
 	* gfortran.dg/gomp/allocate-4.f90: Fix 'omp_allocator_handle_kind'
diff --git a/libgomp/ChangeLog.omp b/libgomp/ChangeLo

[og12] 'gfortran.dg/gomp/allocate-4.f90' -> 'libgomp.fortran/allocate-5.f90' (was: [PATCH 1/5] [gfortran] Add parsing support for allocate directive (OpenMP 5.0))

[Thomas Schwinge]

Hi!

On 2022-01-13T14:53:16+, Hafiz Abid Qadeer  wrote:
> [...]

> --- /dev/null
> +++ b/gcc/testsuite/gfortran.dg/gomp/allocate-4.f90

> +  use omp_lib

Pushed to devel/omp/gcc-12 branch
commit 7e1963a4e6ac97b6629c1e9e858ae28487f518cf
"'gfortran.dg/gomp/allocate-4.f90' -> 'libgomp.fortran/allocate-5.f90'",
see attached.

Note that this likewise applies to the current upstream submission:

"Add parsing support for allocate directive (OpenMP 5.0)".


Grüße
 Thomas


-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 
München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas 
Heurung, Frank Thürauf; Sitz der Gesellschaft: München; Registergericht 
München, HRB 106955
>From 7e1963a4e6ac97b6629c1e9e858ae28487f518cf Mon Sep 17 00:00:00 2001
From: Thomas Schwinge 
Date: Mon, 30 Jan 2023 18:04:16 +0100
Subject: [PATCH] 'gfortran.dg/gomp/allocate-4.f90' ->
 'libgomp.fortran/allocate-5.f90'

Otherwise, for build-tree testing:

[...]/gcc/testsuite/gfortran.dg/gomp/allocate-4.f90:10:7: Fatal Error: Cannot open module file 'omp_lib.mod' for reading at (1): No such file or directory

..., and thus corresponding FAILs.

(Not renamed to 'libgomp.fortran/allocate-4.f90', as that one already exists.)

Fix-up for og12 commit 491478d12b83e102f72858e8a871a25c951df293
"Add parsing support for allocate directive (OpenMP 5.0)".

	gcc/testsuite/
	* gfortran.dg/gomp/allocate-4.f90: Cut.
	libgomp/
	* testsuite/libgomp.fortran/allocate-5.f90: Paste.
---
 gcc/testsuite/ChangeLog.omp | 2 ++
 libgomp/ChangeLog.omp   | 2 ++
 .../testsuite/libgomp.fortran/allocate-5.f90| 0
 3 files changed, 4 insertions(+)
 rename gcc/testsuite/gfortran.dg/gomp/allocate-4.f90 => libgomp/testsuite/libgomp.fortran/allocate-5.f90 (100%)

diff --git a/gcc/testsuite/ChangeLog.omp b/gcc/testsuite/ChangeLog.omp
index 936e7af0945..f0c58e4d26a 100644
--- a/gcc/testsuite/ChangeLog.omp
+++ b/gcc/testsuite/ChangeLog.omp
@@ -1,5 +1,7 @@
 2023-02-09  Thomas Schwinge  
 
+	* gfortran.dg/gomp/allocate-4.f90: Cut.
+
 	* c-c++-common/gomp/uses_allocators-1.c: Cut.
 	* c-c++-common/gomp/uses_allocators-2.c: Likewise.
 	* c-c++-common/gomp/uses_allocators-3.c: Likewise.
diff --git a/libgomp/ChangeLog.omp b/libgomp/ChangeLog.omp
index 0a3d53602da..603a17e4c8d 100644
--- a/libgomp/ChangeLog.omp
+++ b/libgomp/ChangeLog.omp
@@ -1,5 +1,7 @@
 2023-02-09  Thomas Schwinge  
 
+	* testsuite/libgomp.fortran/allocate-5.f90: Paste.
+
 	* testsuite/libgomp.c++/c++.exp (check_effective_target_c)
 	(check_effective_target_c++): New.
 	* testsuite/libgomp.c/c.exp (check_effective_target_c)
diff --git a/gcc/testsuite/gfortran.dg/gomp/allocate-4.f90 b/libgomp/testsuite/libgomp.fortran/allocate-5.f90
similarity index 100%
rename from gcc/testsuite/gfortran.dg/gomp/allocate-4.f90
rename to libgomp/testsuite/libgomp.fortran/allocate-5.f90
-- 
2.25.1

[PATCH] i386: Call get_available_features for all CPUs with max_level >= 1 [PR100758]

[Jakub Jelinek via Gcc-patches]

Hi!

get_available_features doesn't depend on cpu_model2->__cpu_{family,model}
and just sets stuff up based on CPUID leaf 1, or some extended ones,
so I wonder why are we calling it separately for Intel, AMD and Zhaoxin
and not for all other CPUs too?  I think various programs in the wild
which aren't using __builtin_cpu_{is,supports} just check the various CPUID
leafs and query bits in there, without blacklisting unknown CPU vendors,
so I think even __builtin_cpu_supports ("sse2") etc. should be reliable
if those VENDOR_{CENTAUR,CYRIX,NSC,OTHER} CPUs set those bits in CPUID leaf
1 or some extended ones.  Calling it for all CPUs also means it can be
inlined because there will be just a single caller.

I will test on Intel but can't test it on non-Intel (or with some extra
effort on AMD; for both of those arches it should be really no change in
behavior).

Thoughts on this?

2023-02-09  Jakub Jelinek  

PR target/100758
* common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Formatting fixes.
(cpu_indicator_init): Call get_available_features for all CPUs with
max_level >= 1, rather than just Intel, AMD or Zhaoxin.  Formatting
fixes.

--- gcc/common/config/i386/cpuinfo.h.jj 2023-01-16 11:52:15.910736614 +0100
+++ gcc/common/config/i386/cpuinfo.h2023-02-09 12:51:23.539470140 +0100
@@ -601,8 +601,8 @@ get_intel_cpu (struct __processor_model
 
 static inline const char *
 get_zhaoxin_cpu (struct __processor_model *cpu_model,
-   struct __processor_model2 *cpu_model2,
-   unsigned int *cpu_features2)
+struct __processor_model2 *cpu_model2,
+unsigned int *cpu_features2)
 {
   const char *cpu = NULL;
   unsigned int family = cpu_model2->__cpu_family;
@@ -1016,6 +1016,10 @@ cpu_indicator_init (struct __processor_m
   extended_model = (eax >> 12) & 0xf0;
   extended_family = (eax >> 20) & 0xff;
 
+  /* Find available features. */
+  get_available_features (cpu_model, cpu_model2, cpu_features2,
+ ecx, edx);
+
   if (vendor == signature_INTEL_ebx)
 {
   /* Adjust model and family for Intel CPUS. */
@@ -1030,9 +1034,6 @@ cpu_indicator_init (struct __processor_m
   cpu_model2->__cpu_family = family;
   cpu_model2->__cpu_model = model;
 
-  /* Find available features. */
-  get_available_features (cpu_model, cpu_model2, cpu_features2,
- ecx, edx);
   /* Get CPU type.  */
   get_intel_cpu (cpu_model, cpu_model2, cpu_features2);
   cpu_model->__cpu_vendor = VENDOR_INTEL;
@@ -1049,9 +1050,6 @@ cpu_indicator_init (struct __processor_m
   cpu_model2->__cpu_family = family;
   cpu_model2->__cpu_model = model;
 
-  /* Find available features. */
-  get_available_features (cpu_model, cpu_model2, cpu_features2,
- ecx, edx);
   /* Get CPU type.  */
   get_amd_cpu (cpu_model, cpu_model2, cpu_features2);
   cpu_model->__cpu_vendor = VENDOR_AMD;
@@ -1059,22 +1057,17 @@ cpu_indicator_init (struct __processor_m
   else if (vendor == signature_CENTAUR_ebx && family < 0x07)
 cpu_model->__cpu_vendor = VENDOR_CENTAUR;
   else if (vendor == signature_SHANGHAI_ebx
-   || vendor == signature_CENTAUR_ebx)
+  || vendor == signature_CENTAUR_ebx)
 {
   /* Adjust model and family for ZHAOXIN CPUS.  */
   if (family == 0x07)
-   {
- model += extended_model;
-   }
+   model += extended_model;
 
   cpu_model2->__cpu_family = family;
   cpu_model2->__cpu_model = model;
 
-  /* Find available features.  */
-  get_available_features (cpu_model, cpu_model2, cpu_features2,
- ecx, edx);
   /* Get CPU type.  */
-  get_zhaoxin_cpu (cpu_model, cpu_model2,cpu_features2);
+  get_zhaoxin_cpu (cpu_model, cpu_model2, cpu_features2);
   cpu_model->__cpu_vendor = VENDOR_ZHAOXIN;
 }
   else if (vendor == signature_CYRIX_ebx)

Jakub

Re: [PATCH V1 1/1] UNRATIFIED RISC-V: Add 'ZiCond' extension

[Philipp Tomsich]

Just a quick heads-up to avoid duplication of work: we have a series
queued up for later this week (right now, SPEC2017 is still running
for QA purposes) that adds if-conversion support and converts that
into Zicond operations.
It doesn't have much overlap (except handling the "zicond" flag), as
we don't use builtins but a new canonical pattern.

Philipp.


On Thu, 9 Feb 2023 at 12:06,  wrote:
>
> From: yulong 
>
> [DO NOT MERGE]
> Until 'ZiCond' extension is frozen/ratified and final version number is
> determined, this patch should not be merged upstream.  This commit uses
> version 1.0 as in the documentation.
>
> This commit adds support for the latest draft of RISC-V Integer Conditional
> (ZiCond) extension consisting of 2 new instructions.
>
> This is based on the early draft of ZiCond on GitHub:
> 
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc: Add zicond ext.
> * config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): New.
> (AVAIL): New.
> (RISCV_FTYPE_ATYPES2): New.
> * config/riscv/riscv-ftypes.def (2): New.
> * config/riscv/riscv-opts.h (MASK_ZICOND): New.
> (TARGET_ZICOND): New.
> * config/riscv/riscv.md (riscv_eqz_): Add new mode.
> (riscv_nez_): Add new mode.
> * config/riscv/riscv.opt: New.
> * config/riscv/riscv-zicond.def: New file.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zicond-1.c: New test.
> * gcc.target/riscv/zicond-2.c: New test.
> ---
>  gcc/common/config/riscv/riscv-common.cc   |  4 
>  gcc/config/riscv/riscv-builtins.cc|  8 
>  gcc/config/riscv/riscv-ftypes.def |  2 ++
>  gcc/config/riscv/riscv-opts.h |  3 +++
>  gcc/config/riscv/riscv-zicond.def |  5 +
>  gcc/config/riscv/riscv.md | 22 ++
>  gcc/config/riscv/riscv.opt|  3 +++
>  gcc/testsuite/gcc.target/riscv/zicond-1.c | 15 +++
>  gcc/testsuite/gcc.target/riscv/zicond-2.c | 15 +++
>  9 files changed, 77 insertions(+)
>  create mode 100644 gcc/config/riscv/riscv-zicond.def
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-2.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 787674003cb..5a8b1278ac8 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -190,6 +190,8 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>{"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
>{"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
>
> +  {"zicond",ISA_SPEC_CLASS_NONE, 1, 0},
> +
>{"zk",ISA_SPEC_CLASS_NONE, 1, 0},
>{"zkn",   ISA_SPEC_CLASS_NONE, 1, 0},
>{"zks",   ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1209,6 +1211,8 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM},
>{"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP},
>
> +  {"zicond", &gcc_options::x_riscv_zicond_subext, MASK_ZICOND},
> +
>{"zve32x",   &gcc_options::x_target_flags, MASK_VECTOR},
>{"zve32f",   &gcc_options::x_target_flags, MASK_VECTOR},
>{"zve64x",   &gcc_options::x_target_flags, MASK_VECTOR},
> diff --git a/gcc/config/riscv/riscv-builtins.cc 
> b/gcc/config/riscv/riscv-builtins.cc
> index 25ca407f9a9..66a8126b2b4 100644
> --- a/gcc/config/riscv/riscv-builtins.cc
> +++ b/gcc/config/riscv/riscv-builtins.cc
> @@ -42,6 +42,7 @@ along with GCC; see the file COPYING3.  If not see
>  /* Macros to create an enumeration identifier for a function prototype.  */
>  #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
>  #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
> +#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
>
>  /* Classifies the prototype of a built-in function.  */
>  enum riscv_function_type {
> @@ -99,6 +100,10 @@ AVAIL (zero64,  TARGET_ZICBOZ && TARGET_64BIT)
>  AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
>  AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
>  AVAIL (always, (!0))
> +AVAIL (nez32, TARGET_ZICOND && !TARGET_64BIT)
> +AVAIL (nez64, TARGET_ZICOND && TARGET_64BIT)
> +AVAIL (eqz32, TARGET_ZICOND && !TARGET_64BIT)
> +AVAIL (eqz64, TARGET_ZICOND && TARGET_64BIT)
>
>  /* Construct a riscv_builtin_description from the given arguments.
>
> @@ -142,9 +147,12 @@ AVAIL (always, (!0))
>RISCV_ATYPE_##A
>  #define RISCV_FTYPE_ATYPES1(A, B) \
>RISCV_ATYPE_##A, RISCV_ATYPE_##B
> +#define RISCV_FTYPE_ATYPES2(A, B, C) \
> +  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
>
>  static const struct riscv_builtin_description riscv_builtins[] = {
>#include "riscv-cmo.def"
> +  #include "riscv-zicond.def"
>
>DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
>DIRECT_NO_TARGET_BUILT

Re: [PATCH 1/2] Handle component_ref to a structre/union field including flexible array member [PR101832]

[Qing Zhao via Gcc-patches]

> On Feb 9, 2023, at 5:35 AM, Richard Biener  wrote:
> 
> On Wed, 8 Feb 2023, Qing Zhao wrote:
> 
>> 
>> 
>>> On Feb 7, 2023, at 6:37 PM, Joseph Myers  wrote:
>>> 
>>> On Tue, 7 Feb 2023, Qing Zhao via Gcc-patches wrote:
>>> 
 Then, this routine (flexible_array_type_p) is mainly for diagnostic 
 purpose.
 It cannot be used to determine whether the structure/union type recursively
 include a flexible array member at the end.
 
 Is my understanding correct?
>>> 
>>> My comments were about basic principles of what gets diagnosed, and the 
>>> need for different predicates in different contexts; I wasn't trying to 
>>> assert anything about how that maps onto what functions should be used in 
>>> what contexts.
>> Okay. 
>> 
>> But I noticed that “flexible_array_type_p” later was moved from FE to
>> middle-end and put into tree.cc, tree.h as a general utility routine, and to 
>> 
>> /* Determine whether TYPE is a structure with a flexible array member,
>>   or a union containing such a structure (possibly recursively).  */
>> 
>> However, since this routine does not cover the cases when the structure 
>> with flexible array member was recursively embedded into structures, (which 
>> we 
>> agreed that it should be considered as a flexible sized type). 
>> 
>> Therefore, I feel that It might not be proper to include this routine in 
>> middle end 
>> (and actually no other places In middle end use this routine so far).
>> 
>> That’s the reason I asked the previous question. 
>> 
>> It might be better to move the routine “flexible_array_type_p” back from 
>> middle-end to
>> FE for the diagnosis purpose only. 
> 
> It's always dangerous to move functions with such a descriptive name to
> a place where it suggests wider use is applicable.  Also since
> objc/objc-act.cc has a function with the same name (if that had same
> content before r10-5097-g4569f8b3652ae1 then the function should
> have been moved to c-family/ instead).
The routine “flexible_array_type_p” in objc/objc-act.cc is a little different 
from the one in middle-end:

It includes the ARRAY_TYPE in addition to RECORD_TYPE and UNION_TYPE.
> 
> The only "middle-end" use, btw., is in ./config/nios2/nios2.cc,
> intoduced by said revision and your points probably mean this change
> was misguided and flexible_array_type_p isn't the thing to fix here.

Yes, I guess so. 

Qing
> flexible-size _objects_ are clearly denoted by DECL_SIZE being
> non-constant - though the case of .sdata is quite odd and the issue
> fixed is probably running into a bug elsewhere ...
> 
> Sandra?
> 
> Thanks,
> Richard.

Re: [PATCH] When simplifing BFR of an insert, require a mode precision integral type (PR108688)

[Richard Biener via Gcc-patches]

On Thu, Feb 9, 2023 at 10:57 AM Jakub Jelinek  wrote:
>
> On Thu, Feb 09, 2023 at 09:16:17AM +0100, Richard Biener via Gcc-patches 
> wrote:
> > On Wed, Feb 8, 2023 at 10:15 PM Andrew Pinski via Gcc-patches
> >  wrote:
> > >
> > > The same problem as PR 88739 has crept in but
> > > this time in match.pd when simplifying bit_field_ref of
> > > an bit_insert. That is we are generating a BIT_FIELD_REF
> > > of a non-mode-precision integral type.
> > >
> > > OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.
> >
> > Hmm.  Can we handle the case of the extraction exactly covering the
> > insertion separately then and simplify to plain @1?
>
> I was suggesting that in the PR.  Here it is as an incremental patch
> on top of Andrew's patch.  Ok for trunk if it passes bootstrap/regtest?

Yes.

Thanks,
Richard.

> On the newly added testcase the ifcvt-folding difference without/with the
> incremental patch is:
> --- pr108688.c.171t.ifcvt_  2023-02-09 10:47:30.169916845 +0100
> +++ pr108688.c.171t.ifcvt   2023-02-09 10:48:44.942793453 +0100
> @@ -25,6 +25,8 @@ Number of blocks in CFG: 11
>  Number of blocks to update: 5 ( 45%)
>
>
> +Applying pattern match.pd:7487, gimple-match.cc:243200
> +Applying pattern match.pd:3987, gimple-match.cc:75423
>  Matching expression match.pd:1677, gimple-match.cc:209
>  Applying pattern match.pd:1733, gimple-match.cc:109481
>  Matching expression match.pd:2393, gimple-match.cc:852
> @@ -70,7 +72,6 @@ void foo ()
>signed char _29;
> _30;
>unsigned int ivtmp_33;
> -   _ifc__35;
>unsigned char _ifc__37;
>unsigned char _ifc__38;
>unsigned char _ifc__39;
> @@ -91,8 +92,7 @@ void foo ()
>_2 = () a.0_1;
>_ifc__38 = u.D.2741;
>_ifc__39 = BIT_INSERT_EXPR <_ifc__38, _2, 0 (7 bits)>;
> -  _ifc__35 = BIT_FIELD_REF <_ifc__39, 7, 0>;
> -  _4 = (signed char) _ifc__35;
> +  _4 = (signed char) _2;
>b.1_5 = b;
>_6 = (signed char) b.1_5;
>_7 = _4 ^ _6;
>
> 2023-02-09  Jakub Jelinek  
>
> PR tree-optimization/108688
> * match.pd (bit_field_ref [bit_insert]): Simplify BIT_FIELD_REF
> of BIT_INSERT_EXPR extracting exactly all inserted bits even
> when without mode precision.  Formatting fixes.
>
> * gcc.c-torture/compile/pr108688-1.c: Add PR number as comment.
> * gcc.dg/pr108688.c: New test.
>
> --- gcc/match.pd.jj 2023-02-09 09:42:53.782418805 +0100
> +++ gcc/match.pd2023-02-09 10:48:06.859365613 +0100
> @@ -7475,13 +7475,16 @@ (define_operator_list SYNC_FETCH_AND_AND
>}
>(switch
> (if ((!INTEGRAL_TYPE_P (TREE_TYPE (@1))
> - || type_has_mode_precision_p (TREE_TYPE (@1)))
> -&& wi::leu_p (wi::to_wide (@ipos), wi::to_wide (@rpos))
> +|| type_has_mode_precision_p (TREE_TYPE (@1)))
> +   && wi::leu_p (wi::to_wide (@ipos), wi::to_wide (@rpos))
> && wi::leu_p (wi::to_wide (@rpos) + wi::to_wide (@rsize),
>   wi::to_wide (@ipos) + isize))
>  (BIT_FIELD_REF @1 @rsize { wide_int_to_tree (bitsizetype,
> - wi::to_wide (@rpos)
> +wi::to_wide (@rpos)
>  - wi::to_wide (@ipos)); }))
> +   (if (wi::eq_p (wi::to_wide (@ipos), wi::to_wide (@rpos))
> +&& compare_tree_int (@rsize, isize) == 0)
> +(convert @1))
> (if (wi::geu_p (wi::to_wide (@ipos),
>wi::to_wide (@rpos) + wi::to_wide (@rsize))
> || wi::geu_p (wi::to_wide (@rpos),
> --- gcc/testsuite/gcc.c-torture/compile/pr108688-1.c.jj 2023-02-09 
> 09:42:53.782418805 +0100
> +++ gcc/testsuite/gcc.c-torture/compile/pr108688-1.c2023-02-09 
> 10:34:18.339817796 +0100
> @@ -1,4 +1,4 @@
> -
> +/* PR tree-optimization/108688 */
>
>  union U { signed int d : 7; signed int e : 2; } u;
>  int a, b;
> @@ -12,4 +12,3 @@ foo (void)
>u.e ^= b;
>  }
>  }
> -
> --- gcc/testsuite/gcc.dg/pr108688.c.jj  2023-02-09 10:50:27.468253110 +0100
> +++ gcc/testsuite/gcc.dg/pr108688.c 2023-02-09 10:50:16.383419646 +0100
> @@ -0,0 +1,16 @@
> +/* PR tree-optimization/108688 */
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -fno-tree-pre -fno-tree-fre -fno-tree-dominator-opts 
> -fno-tree-loop-im -fno-code-hoisting" } */
> +
> +union U { signed int d : 7; signed int e : 2; } u;
> +int a, b;
> +
> +void
> +foo (void)
> +{
> +  for (int i = 0; i < 64; i++)
> +{
> +  u.d = a;
> +  u.d ^= b;
> +}
> +}
>
>
> Jakub
>

[PATCH] target/108738 - optimize bit operations in STV

[Richard Biener via Gcc-patches]

The following does low-hanging optimizations, combining bitmap
test and set and removing redundant operations.

This shaves off half of the testcase compile time.

Bootstrapped and tested on x86_64-unknown-linux-gnu, OK?

Thanks,
Richard.

PR target/108738
* config/i386/i386-features.cc (scalar_chain::add_to_queue):
Combine bitmap test and set.
(scalar_chain::add_insn): Likewise.
(scalar_chain::analyze_register_chain): Remove redundant
attempt to add to queue and instead strengthen assert.
Sink common attempts to mark the def dual-mode.
(scalar_chain::add_to_queue): Remove redundant insn bitmap
check.
---
 gcc/config/i386/i386-features.cc | 18 --
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc
index 9bd6d8677bb..eff91301009 100644
--- a/gcc/config/i386/i386-features.cc
+++ b/gcc/config/i386/i386-features.cc
@@ -314,14 +314,12 @@ scalar_chain::~scalar_chain ()
 void
 scalar_chain::add_to_queue (unsigned insn_uid)
 {
-  if (bitmap_bit_p (insns, insn_uid)
-  || bitmap_bit_p (queue, insn_uid))
+  if (!bitmap_set_bit (queue, insn_uid))
 return;
 
   if (dump_file)
 fprintf (dump_file, "  Adding insn %d into chain's #%d queue\n",
 insn_uid, chain_id);
-  bitmap_set_bit (queue, insn_uid);
 }
 
 /* For DImode conversion, mark register defined by DEF as requiring
@@ -362,10 +360,9 @@ void
 scalar_chain::analyze_register_chain (bitmap candidates, df_ref ref)
 {
   df_link *chain;
+  bool mark_def = false;
 
-  gcc_assert (bitmap_bit_p (insns, DF_REF_INSN_UID (ref))
- || bitmap_bit_p (candidates, DF_REF_INSN_UID (ref)));
-  add_to_queue (DF_REF_INSN_UID (ref));
+  gcc_checking_assert (bitmap_bit_p (insns, DF_REF_INSN_UID (ref)));
 
   for (chain = DF_REF_CHAIN (ref); chain; chain = chain->next)
 {
@@ -398,9 +395,12 @@ scalar_chain::analyze_register_chain (bitmap candidates, 
df_ref ref)
  if (dump_file)
fprintf (dump_file, "  r%d use in insn %d isn't convertible\n",
 DF_REF_REGNO (chain->ref), uid);
- mark_dual_mode_def (ref);
+ mark_def = true;
}
 }
+
+  if (mark_def)
+mark_dual_mode_def (ref);
 }
 
 /* Add instruction into a chain.  */
@@ -408,14 +408,12 @@ scalar_chain::analyze_register_chain (bitmap candidates, 
df_ref ref)
 void
 scalar_chain::add_insn (bitmap candidates, unsigned int insn_uid)
 {
-  if (bitmap_bit_p (insns, insn_uid))
+  if (!bitmap_set_bit (insns, insn_uid))
 return;
 
   if (dump_file)
 fprintf (dump_file, "  Adding insn %d to chain #%d\n", insn_uid, chain_id);
 
-  bitmap_set_bit (insns, insn_uid);
-
   rtx_insn *insn = DF_INSN_UID_GET (insn_uid)->insn;
   rtx def_set = single_set (insn);
   if (def_set && REG_P (SET_DEST (def_set))
-- 
2.35.3

[PATCH] target/108738 - STV bitmap operations compile-time hog

[Richard Biener via Gcc-patches]

When the set of candidates becomes very large then repeated
bit checks on it during the build of an actual chain can become
slow because of the O(n) nature of bitmap tests.  The following
switches the candidates bitmaps to the tree representation before
building the chains to get O(log n) amortized behavior.

For the testcase at hand this improves STV time by 50%.

Bootstrapped and tested on x86_64-unknown-linux-gnu, OK?

Thanks,
Richard.

PR target/108738
* config/i386/i386-features.cc (convert_scalars_to_vector):
Switch candidates bitmaps to tree view before building the chains.
---
 gcc/config/i386/i386-features.cc | 49 +---
 1 file changed, 26 insertions(+), 23 deletions(-)

diff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc
index ec13d4e7489..9bd6d8677bb 100644
--- a/gcc/config/i386/i386-features.cc
+++ b/gcc/config/i386/i386-features.cc
@@ -2283,30 +2283,33 @@ convert_scalars_to_vector (bool timode_p)
   fprintf (dump_file, "There are no candidates for optimization.\n");
 
   for (unsigned i = 0; i <= 2; ++i)
-while (!bitmap_empty_p (&candidates[i]))
-  {
-   unsigned uid = bitmap_first_set_bit (&candidates[i]);
-   scalar_chain *chain;
-
-   if (cand_mode[i] == TImode)
- chain = new timode_scalar_chain;
-   else
- chain = new general_scalar_chain (cand_mode[i], cand_vmode[i]);
-
-   /* Find instructions chain we want to convert to vector mode.
-  Check all uses and definitions to estimate all required
-  conversions.  */
-   chain->build (&candidates[i], uid);
-
-   if (chain->compute_convert_gain () > 0)
- converted_insns += chain->convert ();
-   else
- if (dump_file)
-   fprintf (dump_file, "Chain #%d conversion is not profitable\n",
-chain->chain_id);
+{
+  bitmap_tree_view (&candidates[i]);
+  while (!bitmap_empty_p (&candidates[i]))
+   {
+ unsigned uid = bitmap_first_set_bit (&candidates[i]);
+ scalar_chain *chain;
 
-   delete chain;
-  }
+ if (cand_mode[i] == TImode)
+   chain = new timode_scalar_chain;
+ else
+   chain = new general_scalar_chain (cand_mode[i], cand_vmode[i]);
+
+ /* Find instructions chain we want to convert to vector mode.
+Check all uses and definitions to estimate all required
+conversions.  */
+ chain->build (&candidates[i], uid);
+
+ if (chain->compute_convert_gain () > 0)
+   converted_insns += chain->convert ();
+ else
+   if (dump_file)
+ fprintf (dump_file, "Chain #%d conversion is not profitable\n",
+  chain->chain_id);
+
+ delete chain;
+   }
+}
 
   if (dump_file)
 fprintf (dump_file, "Total insns converted: %d\n", converted_insns);
-- 
2.35.3

Re: [PATCH 1/2] Handle component_ref to a structre/union field including flexible array member [PR101832]

[Qing Zhao via Gcc-patches]

> On Feb 8, 2023, at 6:18 PM, Qing Zhao via Gcc-patches 
>  wrote:
> 
> 
> 
>> On Feb 8, 2023, at 2:09 PM, Joseph Myers  wrote:
>> 
>> On Wed, 8 Feb 2023, Qing Zhao via Gcc-patches wrote:
>> 
>>> But I noticed that “flexible_array_type_p” later was moved from FE to
>>> middle-end and put into tree.cc, tree.h as a general utility routine, and 
>>> to 
>>> 
>>> /* Determine whether TYPE is a structure with a flexible array member,
>>>  or a union containing such a structure (possibly recursively).  */
>>> 
>>> However, since this routine does not cover the cases when the structure 
>>> with flexible array member was recursively embedded into structures, (which 
>>> we 
>>> agreed that it should be considered as a flexible sized type). 
>>> 
>>> Therefore, I feel that It might not be proper to include this routine in 
>>> middle end 
>>> (and actually no other places In middle end use this routine so far).
>> 
>> I think we've established that diagnostics and at least some middle-end 
>> purposes need different conditions.
> 
> Yes, agreed.
> 
>> Diagnostics for nesting a structure 
>> with a flexible array member inside another structure should only count [] 
>> as a flexible array member,
> 
> Diagnostics should be consistent with the documentation. 
> The use cases that violate what is defined in documentation should be 
> diagnostics. 
> 
> This include both C standard and GCC extension. 
> For C standard violation, -pedantic will report them.
> For GCC extension, the corresponding warning message should report them.
> 
> And both such warning can be issued either in FE or in Middle end. 
> 
> Is the above understand correct?
> 
>> whereas permitting flexible array uses in the 
>> middle end should allow [0] and [1] under some circumstances (depending on 
>> command-line options).
> 
>> 
>>> But:
>>> 
>>> struct flex0 { int n; int data[0]; };
>>> struct out_flex_end0 { int m; struct flex0 flex_data; }; 
>>> struct outer_flex_end0 { int p; struct out_flex_end0 out_flex_data; }; 
>>> 
>>> In the above, only “flex0” is flexible sized type by default. 
>>> But “out_flex_end0” and “out_flex_end0” are Not considered as flexible 
>>> sized type by default? 
>> 
>> It would be OK (and I'm not saying here that this is necessarily 
>> desirable), since that's at the end of another structure rather than in 
>> the middle, to consider them flexible for the purposes of code generation.
> 
> This is the part I am still not very clear and not feel very comfortable:
> 
> In the documentation on GCC extension of embedding structure with flexible 
> array member into another structure/union, 
> 
> Should we include [0], [1] and [n] cases as GCC extension by default? Or we 
> only include [] for nested struct as an extension?
> 
> For example:
> 
> struct flex0  { int length; char data[0]; };
> 
> struct out_flex0 { int m; struct flex0 flex_data; };
> struct out_flex0_mid  {  struct flex0 flex_data; int m};
> 
> Should we treat the above out_flex0->flex_data as flexible array by default?
> Should we issue warning for the above out_flex9_mid with a new warning option 
> -Wgnu-variable-sized-type-at-end?
> 
> How about the following:
> struct flex1  { int length; char data[1]; };
> 
> struct out_flex1 { int m; struct flex1 flex_data; };
> struct out_flex1_mid  {  struct flex1 flex_data; int m};
> 
> And:
> struct flexn { int length; char data[4]; };
> 
> struct out_flexn { int m; struct flexn flex_data; };
> struct out_flexn_mid  {  struct flexn flex_data; int m};
> 
> 
> 

More thought on the above:

I think that we need to be more careful with the documentation of the GCC 
extension on embedding structure with flexible array member into the end of 
another structure/union. 
As Richard mentioned before, documentation might encourage people to use it…

So, the major question here is:

 in addition to the C99 standard flexible array member [ ], shall we include 
[0], [1] or even [4] into this extension, and treat the structure with a 
trailing [0], [1], or [4] embedded into another structure/union still as 
flexible-sized?

I think that we might need to limit this extension ONLY to C99 standard FAM [ 
].  All other [0], [1], or [4] should be excluded from this extension. The 
reasons are:

1. The real usages of such GCC extension (embedding structure with FAM into 
another structure/union), as my understanding, the old glibc’s <_G_config.h> 
(https://gcc.gnu.org/legacy-ml/gcc-patches/2002-08/msg01149.html), and the bug 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101832, ONLY involved C99 standard 
FAM;

2. Embedding a structure with C99 FAM [] into the end of another structure, and 
still treat it flexible sized might have more usages, and as discussed with 
Kees, it might be reasonable to promote this into a  C standard later if needed.

So, based on this consideration, I think I should only document the following 
as GCC extension:

struct flex  { int length; char data[ ]; };
struct out_flex { int m; struct flex flex

Re: [Patch][v2] OpenMP/Fortran: Partially fix non-rect loop nests [PR107424]

[Tobias Burnus]

Updated patch. Changes: the canonic(al) and the if/else(if) cosmetic
formatting changes.

Testcases: Additionally, I checked for the value of a zero-loop trip in
libgomp.fortran/non-rectangular-loop-1.f90 and added lastprivate to all
of .../non-rectangular-loop-{3,4}.f90 (unless the loop-iteration
variable is a pointer).

At least those three files pass with and without -fopenmp, implying that
there the lastprivate check is correct. ('1a' and '5' also use
lastprivate, but those fail with a 'sorry' before a value test can be
done.) In '1' there are also several tests with 'parallel do', but only
SIMD has been tested more extensively (in general and for lastprivate).

I think the test coverage should be sufficient. Any further test idea?
Otherwise, I would commit it now.

Tobias

PS: Next planned by me: revising the 'omp loop' patch and a longer
pending 'map(alloc:' patch. And at some point supporting at least some
non-±1 increments with non-rect loop nests.

On 31.01.23 12:37, Jakub Jelinek wrote:

On Wed, Jan 25, 2023 at 03:47:18PM +0100, Tobias Burnus wrote:

updated patch included, i.e. avoiding 'count' for 'j' when a 'j.0' would
do (i.e. only local var without the different step calculation). I also
now reject if there is a non-unit step on the loop using an outer var.

Eventually still to be done: replace the 'sorry' by working code, i.e.
implement the suggestions to handle some/all non-unit iteration steps as
proposed in this thread.

On 20.01.23 18:39, Jakub Jelinek wrote:

I think instead of non-unity etc. it is better to talk about constant
step 1 or -1.

I concur.



The actual problem with non-simple loops for non-rectangular loops is
both in case it is an inner loop which uses some outer loop's iterator,
or if it is outer loop whose iterator is used, both of those cases
will not be handled properly.

I have now added a check for the other case as well.

Just to confirm, the following is fine, isn't it?

!$omp simd collapse(4)
do i = 1, 10, 2
   do outer_var = 1, 10  ! step = + 1
 do j = 1, 10, 2
   do inner_var = 1, outer_var  ! step = 1

i.e. both the inner_var and outer_var have 'step = 1',
even if other loops in the 'collapse' have step != 1.
I think it should be fine.

Yes, the loops which don't define outer_var for other loops nor
use outer_var from other loops can be in any form, we can compute
their number of iterations before the whole loop nest for them,
so for the non-rectangular iterations computations we can ignore
those except for multiplication by the pre-computed count.


OpenMP/Fortran: Partially fix non-rect loop nests [PR107424]

This patch ensures that loop bounds depending on outer loop vars use the
proper TREE_VEC format. It additionally gives a sorry if such an outer
var has a non-one/non-minus-one increment as currently a count variable
is used in this case (see PR).

Finally, it avoids 'count' and just uses a local loop variable if the
step increment is +/-1.

 PR fortran/107424

gcc/fortran/ChangeLog:

 * trans-openmp.cc (struct dovar_init_d): Add 'sym' and
 'non_unit_incr' members.
 (gfc_nonrect_loop_expr): New.
 (gfc_trans_omp_do): Call it; use normal loop bounds
 for unit stride - and only create local loop var.

libgomp/ChangeLog:

 * testsuite/libgomp.fortran/non-rectangular-loop-1.f90: New test.
 * testsuite/libgomp.fortran/non-rectangular-loop-1a.f90: New test.
 * testsuite/libgomp.fortran/non-rectangular-loop-2.f90: New test.
 * testsuite/libgomp.fortran/non-rectangular-loop-3.f90: New test.
 * testsuite/libgomp.fortran/non-rectangular-loop-4.f90: New test.
 * testsuite/libgomp.fortran/non-rectangular-loop-5.f90: New test.

gcc/testsuite/ChangeLog:

 * gfortran.dg/goacc/privatization-1-compute-loop.f90: Update dg-note.
 * gfortran.dg/goacc/privatization-1-routine_gang-loop.f90: Likewise.

+static bool
+gfc_nonrect_loop_expr (stmtblock_t *pblock, gfc_se *sep, int loop_n,
+   gfc_code *code, gfc_expr *expr, vec *inits,
+   int simple, gfc_expr *curr_loop_var)
+{
+  int i;
+  for (i = 0; i < loop_n; i++)
+{
+  gcc_assert (code->ext.iterator->var->expr_type == EXPR_VARIABLE);
+  if (gfc_find_sym_in_expr (code->ext.iterator->var->symtree->n.sym, expr))
+break;
+  code = code->block->next;
+}
+  if (i >= loop_n)
+return false;
+
+  /* Canonic format: TREE_VEC with [var, multiplier, offset].  */

I think we use everywhere Canonical rather than Canonic


+  gfc_symbol *var = code->ext.iterator->var->symtree->n.sym;
+
+  tree tree_var = NULL_TREE;
+  tree a1 = integer_one_node;
+  tree a2 = integer_zero_node;
+
+  if (!simple)
+{
+  /* FIXME: Handle non-unit iter steps, cf. PR fortran/107424.  */
+  sorry_at (gfc_get_location (&curr_loop_var->where),
+"non-rectangular loop nest with step other than constant 1 "
+"or -1 for %qs", curr_loop_var->symtree->n.sym->name);
+  return false;
+}
+
+  dovar_init *di;

Re: [Patch][v2] OpenMP/Fortran: Partially fix non-rect loop nests [PR107424]

[Jakub Jelinek via Gcc-patches]

On Thu, Feb 09, 2023 at 03:46:35PM +0100, Tobias Burnus wrote:
> I think the test coverage should be sufficient. Any further test idea?
> Otherwise, I would commit it now.

LGTM, thanks.

Jakub

Re: [PATCH] tree-optimization: [PR108684] ICE in verify_ssa due to simple_dce_from_worklist

[Andrew Pinski via Gcc-patches]

On Thu, Feb 9, 2023 at 12:07 AM Richard Biener via Gcc-patches
 wrote:
>
> On Wed, Feb 8, 2023 at 8:14 PM Andrew Pinski via Gcc-patches
>  wrote:
> >
> > In simple_dce_from_worklist, we were removing an inline-asm which had a vdef
> > (due to clobbering memory) but not unlinking the statement's vdef.
> > This fixes that oversight. This was a latent bug exposed recently
> > by both VRP and removal of stores to static starting to use
> > simple_dce_from_worklist.
> >
> > OK for trunk (and for GCC 12 after a week)?
> > Bootstrapped and tested on x86_64-linux-gnu with no regressions.
>
> I think this is actually wrong-code - we cannot remove memory side-effects
> of a stmt and the
>
>   /* The defining statement needs to be defining only this name.
>  ASM is the only statement that can define more than one
>  (non-virtual) name. */
>   if (is_a(t)
>   && !single_ssa_def_operand (t, SSA_OP_DEF))
> continue;
>
> should use SSA_OP_ALL_DEFS instead.

Yes there is definitely wrong code. Will implement this change and add
a testcase which was being definitely being miscompiled (I put the
testcase in the bug report already).

Thanks,
Andrew Pinski

>
> OK with that change.
>
> Richard.
>
> > PR tree-optimization/108684
> >
> > gcc/ChangeLog:
> >
> > * tree-ssa-dce.cc (simple_dce_from_worklist):
> > Call unlink_stmt_vdef on the statement before
> > removing it.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.c-torture/compile/dce-inline-asm-1.c: New test.
> > * gcc.c-torture/compile/dce-inline-asm-2.c: New test.
> >
> > co-authored-by: Andrew Macleod  
> > ---
> >  .../gcc.c-torture/compile/dce-inline-asm-1.c | 15 +++
> >  .../gcc.c-torture/compile/dce-inline-asm-2.c | 16 
> >  gcc/tree-ssa-dce.cc  |  1 +
> >  3 files changed, 32 insertions(+)
> >  create mode 100644 gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c
> >  create mode 100644 gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c
> >
> > diff --git a/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c 
> > b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c
> > new file mode 100644
> > index 000..a9f02e44bd7
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c
> > @@ -0,0 +1,15 @@
> > +/* PR tree-optimization/108684 */
> > +/* This used to ICE as when we remove the store to
> > +   `t`, we also would remove the inline-asm which
> > +   had a VDEF on it but we didn't update the
> > +   VUSE that was later on.  */
> > +static int t;
> > +
> > +int f (int *a)
> > +{
> > +  int t1;
> > +  asm (" " : "=X" (t1) : : "memory");
> > +  t = t1;
> > +  return *a;
> > +}
> > +
> > diff --git a/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c 
> > b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c
> > new file mode 100644
> > index 000..a41b16e4bd0
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c
> > @@ -0,0 +1,16 @@
> > +/* PR tree-optimization/108684 */
> > +/* This used to ICE as when we removed the
> > +   __builtin_unreachable in VRP, as we
> > +   would also remove the branch and the
> > +   inline-asm. The inline-asm had a VDEF on it,
> > +   which we didn't update further along and
> > +   not have the VDEF on the return statement
> > +   updated.  */
> > +
> > +int f (int a)
> > +{
> > +  asm (" " : "=X" (a) : : "memory");
> > +  if (a)
> > +return 0;
> > +  __builtin_unreachable();
> > +}
> > diff --git a/gcc/tree-ssa-dce.cc b/gcc/tree-ssa-dce.cc
> > index b2fe9f4f55e..752785541e4 100644
> > --- a/gcc/tree-ssa-dce.cc
> > +++ b/gcc/tree-ssa-dce.cc
> > @@ -2140,6 +2140,7 @@ simple_dce_from_worklist (bitmap worklist)
> > remove_phi_node (&gsi, true);
> >else
> > {
> > + unlink_stmt_vdef (t);
> >   gsi_remove (&gsi, true);
> >   release_defs (t);
> > }
> > --
> > 2.31.1
> >

Re: [PATCH] i386: Call get_available_features for all CPUs with max_level >= 1 [PR100758]

[H.J. Lu via Gcc-patches]

On Thu, Feb 9, 2023 at 4:12 AM Jakub Jelinek  wrote:
>
> Hi!
>
> get_available_features doesn't depend on cpu_model2->__cpu_{family,model}
> and just sets stuff up based on CPUID leaf 1, or some extended ones,
> so I wonder why are we calling it separately for Intel, AMD and Zhaoxin
> and not for all other CPUs too?  I think various programs in the wild
> which aren't using __builtin_cpu_{is,supports} just check the various CPUID
> leafs and query bits in there, without blacklisting unknown CPU vendors,
> so I think even __builtin_cpu_supports ("sse2") etc. should be reliable
> if those VENDOR_{CENTAUR,CYRIX,NSC,OTHER} CPUs set those bits in CPUID leaf
> 1 or some extended ones.  Calling it for all CPUs also means it can be
> inlined because there will be just a single caller.
>
> I will test on Intel but can't test it on non-Intel (or with some extra
> effort on AMD; for both of those arches it should be really no change in
> behavior).
>
> Thoughts on this?

No objection here.   It just isn't easy to verify CPUID behavior on
other processors.

Thanks.

> 2023-02-09  Jakub Jelinek  
>
> PR target/100758
> * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Formatting fixes.
> (cpu_indicator_init): Call get_available_features for all CPUs with
> max_level >= 1, rather than just Intel, AMD or Zhaoxin.  Formatting
> fixes.
>
> --- gcc/common/config/i386/cpuinfo.h.jj 2023-01-16 11:52:15.910736614 +0100
> +++ gcc/common/config/i386/cpuinfo.h2023-02-09 12:51:23.539470140 +0100
> @@ -601,8 +601,8 @@ get_intel_cpu (struct __processor_model
>
>  static inline const char *
>  get_zhaoxin_cpu (struct __processor_model *cpu_model,
> -   struct __processor_model2 *cpu_model2,
> -   unsigned int *cpu_features2)
> +struct __processor_model2 *cpu_model2,
> +unsigned int *cpu_features2)
>  {
>const char *cpu = NULL;
>unsigned int family = cpu_model2->__cpu_family;
> @@ -1016,6 +1016,10 @@ cpu_indicator_init (struct __processor_m
>extended_model = (eax >> 12) & 0xf0;
>extended_family = (eax >> 20) & 0xff;
>
> +  /* Find available features. */
> +  get_available_features (cpu_model, cpu_model2, cpu_features2,
> + ecx, edx);
> +
>if (vendor == signature_INTEL_ebx)
>  {
>/* Adjust model and family for Intel CPUS. */
> @@ -1030,9 +1034,6 @@ cpu_indicator_init (struct __processor_m
>cpu_model2->__cpu_family = family;
>cpu_model2->__cpu_model = model;
>
> -  /* Find available features. */
> -  get_available_features (cpu_model, cpu_model2, cpu_features2,
> - ecx, edx);
>/* Get CPU type.  */
>get_intel_cpu (cpu_model, cpu_model2, cpu_features2);
>cpu_model->__cpu_vendor = VENDOR_INTEL;
> @@ -1049,9 +1050,6 @@ cpu_indicator_init (struct __processor_m
>cpu_model2->__cpu_family = family;
>cpu_model2->__cpu_model = model;
>
> -  /* Find available features. */
> -  get_available_features (cpu_model, cpu_model2, cpu_features2,
> - ecx, edx);
>/* Get CPU type.  */
>get_amd_cpu (cpu_model, cpu_model2, cpu_features2);
>cpu_model->__cpu_vendor = VENDOR_AMD;
> @@ -1059,22 +1057,17 @@ cpu_indicator_init (struct __processor_m
>else if (vendor == signature_CENTAUR_ebx && family < 0x07)
>  cpu_model->__cpu_vendor = VENDOR_CENTAUR;
>else if (vendor == signature_SHANGHAI_ebx
> -   || vendor == signature_CENTAUR_ebx)
> +  || vendor == signature_CENTAUR_ebx)
>  {
>/* Adjust model and family for ZHAOXIN CPUS.  */
>if (family == 0x07)
> -   {
> - model += extended_model;
> -   }
> +   model += extended_model;
>
>cpu_model2->__cpu_family = family;
>cpu_model2->__cpu_model = model;
>
> -  /* Find available features.  */
> -  get_available_features (cpu_model, cpu_model2, cpu_features2,
> - ecx, edx);
>/* Get CPU type.  */
> -  get_zhaoxin_cpu (cpu_model, cpu_model2,cpu_features2);
> +  get_zhaoxin_cpu (cpu_model, cpu_model2, cpu_features2);
>cpu_model->__cpu_vendor = VENDOR_ZHAOXIN;
>  }
>else if (vendor == signature_CYRIX_ebx)
>
> Jakub
>


-- 
H.J.

Re: [PATCH] i386: Call get_available_features for all CPUs with max_level >= 1 [PR100758]

[Jakub Jelinek via Gcc-patches]

On Thu, Feb 09, 2023 at 07:30:52AM -0800, H.J. Lu wrote:
> On Thu, Feb 9, 2023 at 4:12 AM Jakub Jelinek  wrote:
> > get_available_features doesn't depend on cpu_model2->__cpu_{family,model}
> > and just sets stuff up based on CPUID leaf 1, or some extended ones,
> > so I wonder why are we calling it separately for Intel, AMD and Zhaoxin
> > and not for all other CPUs too?  I think various programs in the wild
> > which aren't using __builtin_cpu_{is,supports} just check the various CPUID
> > leafs and query bits in there, without blacklisting unknown CPU vendors,
> > so I think even __builtin_cpu_supports ("sse2") etc. should be reliable
> > if those VENDOR_{CENTAUR,CYRIX,NSC,OTHER} CPUs set those bits in CPUID leaf
> > 1 or some extended ones.  Calling it for all CPUs also means it can be
> > inlined because there will be just a single caller.
> >
> > I will test on Intel but can't test it on non-Intel (or with some extra
> > effort on AMD; for both of those arches it should be really no change in
> > behavior).
> >
> > Thoughts on this?
> 
> No objection here.   It just isn't easy to verify CPUID behavior on
> other processors.

Sure, worst case it can be reverted or exceptions could be added if some
CPUs misbehave but then we'd hopefully have detailed into on how exactly it
behaves.

FYI, I've successfully bootstrapped/regtested this on Intel i9-7960X
and Martin Liska has regtested it with just i386.exp tests on AMD.

Uros, is this ok now?

> > 2023-02-09  Jakub Jelinek  
> >
> > PR target/100758
> > * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Formatting fixes.
> > (cpu_indicator_init): Call get_available_features for all CPUs with
> > max_level >= 1, rather than just Intel, AMD or Zhaoxin.  Formatting
> > fixes.

Jakub

Re: Ping: [PATCH v4] rs6000: Fix incorrect RTL for Power LE when removing the UNSPECS [PR106069]

[Segher Boessenkool]

On Thu, Feb 09, 2023 at 10:15:22AM +0800, Xionghu Luo wrote:
> Thanks Kewen!
> Ping this again @Segher.
> Maybe we could also merge this patch if no objections from Segher as 
> several reviews and tests taken on this already...

Please send the patch as the head of its own thread, not as a reply deep
in a thread of an older version?


Segher

[PATCH] c++: Don't defer local statics initialized with constant expressions [PR108702]

[Jakub Jelinek via Gcc-patches]

Hi!

The stmtexpr19.C testcase used to be rejected as it has a static
variable in statement expression in constexpr context, but as that
static variable is initialized by constant expression, when P2647R1
was implemented we agreed to make it valid.

Now, as reported, the testcase compiles fine, but doesn't actually link
because the static variable isn't defined anywhere, and with -flto ICEs
because of this problem.  This is because we never
varpool_node::finalize_decl those vars, the constant expression in which
the DECL_EXPR is present for the static VAR_DECL is folded (constant
evaluated) into just the address of the VAR_DECL.
Now, similar testcase included below (do we want to include it in the
testsuite too?) works fine, because in
cp_finish_decl -> make_rtl_for_nonlocal_decl
we have since PR70353 fix:
  /* We defer emission of local statics until the corresponding
 DECL_EXPR is expanded.  But with constexpr its function might never
 be expanded, so go ahead and tell cgraph about the variable now.  */
  defer_p = ((DECL_FUNCTION_SCOPE_P (decl)
  && !var_in_maybe_constexpr_fn (decl))
 || DECL_VIRTUAL_P (decl));
and so don't defer them in constexpr/consteval functions.  The following
patch extends that and doesn't defer vars initialized by constant
expressions either, because otherwise there is nothing to finalize those.
It is true that e.g. with -O0
int foo (int x) {
  if (x) { static int y = 1; ++y; }
  if (0) { static int z = 1; ++z; }
  return sizeof (({ static int w = 1; w; }));
}
we used to emit just y and z and with the patch emit also w, but with
optimizations that is optimized away properly.

Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?

The testcase I was talking above that works because of the
&& !var_in_maybe_constexpr_fn (decl) case is:

extern "C" void abort ();

constexpr const int *
foo ()
{
  static constexpr int a = 1;
  return &a;
}

consteval const int *
bar ()
{
  static constexpr int a = 1;
  return &a;
}

[[gnu::noipa]] void
baz (const int *x)
{
  if (*x != 1)
abort ();
}

int
main ()
{
  constexpr const int *p = foo ();
  constexpr const int *q = bar ();
  baz (p);
  baz (q);
  if (p == q)
abort ();
}

2023-02-09  Jakub Jelinek  

PR c++/108702
* decl.cc (make_rtl_for_nonlocal_decl): Don't defer local statics
initialized by constant expressions.

* g++.dg/ext/stmtexpr19.C: Use dg-do link rather than dg-do compile.

--- gcc/cp/decl.cc.jj   2023-01-24 11:10:13.151076134 +0100
+++ gcc/cp/decl.cc  2023-02-09 13:29:50.527083618 +0100
@@ -7731,9 +7731,12 @@ make_rtl_for_nonlocal_decl (tree decl, t
 
   /* We defer emission of local statics until the corresponding
  DECL_EXPR is expanded.  But with constexpr its function might never
- be expanded, so go ahead and tell cgraph about the variable now.  */
+ be expanded, so go ahead and tell cgraph about the variable now.
+ Also don't defer local statics initialized by constant expressions,
+ see PR108702.  */
   defer_p = ((DECL_FUNCTION_SCOPE_P (decl)
- && !var_in_maybe_constexpr_fn (decl))
+ && !var_in_maybe_constexpr_fn (decl)
+ && !DECL_INITIALIZED_BY_CONSTANT_EXPRESSION_P (decl))
 || DECL_VIRTUAL_P (decl));
 
   /* Defer template instantiations.  */
--- gcc/testsuite/g++.dg/ext/stmtexpr19.C.jj2022-11-19 09:26:30.168061316 
+0100
+++ gcc/testsuite/g++.dg/ext/stmtexpr19.C   2023-02-09 13:32:48.887453520 
+0100
@@ -1,6 +1,6 @@
 // PR c++/81073
 // { dg-options "" }
-// { dg-do compile { target c++11 } }
+// { dg-do link { target c++11 } }
 
 struct test { const int *addr; };
 

Jakub

[wwwdocs] gcc-13/changes.html: Document C++ -fexcess-precision=standard

[Jakub Jelinek via Gcc-patches]

Hi!

Martin Liska mentioned that porting_to.html doesn't mention
the C++ excess precision changes.  Not really sure if porting_to
should document those, but I think changes.html certainly should.
And perhaps porting_to could have some examples and link to this
spot in changes.

Ok for wwwdocs?

--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -230,6 +230,21 @@ a work-in-progress.
 
 C++
 
+  Excess precision support (which has been available in C since GCC 4.5)
+  has been implemented for C++ as well.  It is enabled by default
+  in strict standard modes like -std=c++17, where it
+  defaults to -fexcess-precision=standard, while in GNU
+  standard modes like -std=gnu++20 it defaults to
+  -fexcess-precision=fast.  The option affects mainly
+  IA-32/x86-64 where when defaulting to x87 math and in some cases on
+  Motorola 68000 float and double expressions
+  are evaluated in long double precision and S/390, System z,
+  IBM z Systems where float expressions are evaluated in
+  double precision.  Also, on several architectures where
+  std::float16_t or std::bfloat16_t types
+  are supported those are evaluated in float precision.
+  -fexcess-precision=fast restores previous behavior.
+  
   Several C++23 features have been implemented:
 
   https://wg21.link/p2324";>P2324R1, Labels at the end of

Jakub

Re: [PATCH] i386: Call get_available_features for all CPUs with max_level >= 1 [PR100758]

[Uros Bizjak via Gcc-patches]

On Thu, Feb 9, 2023 at 4:43 PM Jakub Jelinek  wrote:
>
> On Thu, Feb 09, 2023 at 07:30:52AM -0800, H.J. Lu wrote:
> > On Thu, Feb 9, 2023 at 4:12 AM Jakub Jelinek  wrote:
> > > get_available_features doesn't depend on cpu_model2->__cpu_{family,model}
> > > and just sets stuff up based on CPUID leaf 1, or some extended ones,
> > > so I wonder why are we calling it separately for Intel, AMD and Zhaoxin
> > > and not for all other CPUs too?  I think various programs in the wild
> > > which aren't using __builtin_cpu_{is,supports} just check the various 
> > > CPUID
> > > leafs and query bits in there, without blacklisting unknown CPU vendors,
> > > so I think even __builtin_cpu_supports ("sse2") etc. should be reliable
> > > if those VENDOR_{CENTAUR,CYRIX,NSC,OTHER} CPUs set those bits in CPUID 
> > > leaf
> > > 1 or some extended ones.  Calling it for all CPUs also means it can be
> > > inlined because there will be just a single caller.
> > >
> > > I will test on Intel but can't test it on non-Intel (or with some extra
> > > effort on AMD; for both of those arches it should be really no change in
> > > behavior).
> > >
> > > Thoughts on this?
> >
> > No objection here.   It just isn't easy to verify CPUID behavior on
> > other processors.
>
> Sure, worst case it can be reverted or exceptions could be added if some
> CPUs misbehave but then we'd hopefully have detailed into on how exactly it
> behaves.
>
> FYI, I've successfully bootstrapped/regtested this on Intel i9-7960X
> and Martin Liska has regtested it with just i386.exp tests on AMD.
>
> Uros, is this ok now?

OK. Let's go forward with the patch.

Thanks,
Uros.

>
> > > 2023-02-09  Jakub Jelinek  
> > >
> > > PR target/100758
> > > * common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Formatting 
> > > fixes.
> > > (cpu_indicator_init): Call get_available_features for all CPUs 
> > > with
> > > max_level >= 1, rather than just Intel, AMD or Zhaoxin.  
> > > Formatting
> > > fixes.
>
> Jakub
>

Re: [PATCH 1/2] Handle component_ref to a structre/union field including flexible array member [PR101832]

[Kees Cook via Gcc-patches]

On Thu, Feb 09, 2023 at 02:40:57PM +, Qing Zhao wrote:
> So, the major question here is:
> 
>  in addition to the C99 standard flexible array member [ ], shall we include 
> [0], [1] or even [4] into this extension, and treat the structure with a 
> trailing [0], [1], or [4] embedded into another structure/union still as 
> flexible-sized?
> 
> I think that we might need to limit this extension ONLY to C99 standard FAM [ 
> ].  All other [0], [1], or [4] should be excluded from this extension. The 
> reasons are:
> 
> 1. The real usages of such GCC extension (embedding structure with FAM into 
> another structure/union), as my understanding, the old glibc’s <_G_config.h> 
> (https://gcc.gnu.org/legacy-ml/gcc-patches/2002-08/msg01149.html), and the 
> bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101832, ONLY involved C99 
> standard FAM;
> 
> 2. Embedding a structure with C99 FAM [] into the end of another structure, 
> and still treat it flexible sized might have more usages, and as discussed 
> with Kees, it might be reasonable to promote this into a  C standard later if 
> needed.
> 
> So, based on this consideration, I think I should only document the following 
> as GCC extension:
> 
> struct flex  { int length; char data[ ]; };
> struct out_flex { int m; struct flex flex_data; };
> 
> Issue warnings for the following: (when the structure is not at the end)
> 
> struct out_flex_mid  {  struct flex flex_data; int m};
> 
> 
> However, for the trailing [0], [1], or [4], when such structure embedded into 
> the end of another structure, We should NOT treat the outer structure as 
> flexible sized. 
> Logically, we will NOT issue warnings when such structure is not at the end. 
> 
> Let me know if you have any comment or suggestions.

FWIW this all sounds correct to me.

-- 
Kees Cook

[PATCH 1/2]middle-end: Fix wrong overmatching of div-bitmask by using new optabs [PR108583]

[Tamar Christina via Gcc-patches]

Hi All,

As discussed in the ticket, this replaces the approach for optimizing the
div by bitmask operation from a hook into optabs implemented through
add_highpart.

In order to be able to use this we need to check whether the current precision
has enough bits to do the operation without any of the additions overflowing.

We use range information to determine this and only do the operation if we're
sure am overflow won't occur.

Bootstrapped Regtested on aarch64-none-linux-gnu and  issues.

Ok for master?

Thanks,
Tamar

gcc/ChangeLog:

PR target/108583
* doc/tm.texi (TARGET_VECTORIZE_CAN_SPECIAL_DIV_BY_CONST): Remove.
* doc/tm.texi.in: Likewise.
* explow.cc (round_push, align_dynamic_address): Revert previous patch.
* expmed.cc (expand_divmod): Likewise.
* expmed.h (expand_divmod): Likewise.
* expr.cc (force_operand, expand_expr_divmod): Likewise.
* optabs.cc (expand_doubleword_mod, expand_doubleword_divmod): Likewise.
* internal-fn.def (ADDH): New.
* optabs.def (sadd_highpart_optab, uadd_highpart_optab): New.
* doc/md.texi: Document them.
* doc/rtl.texi: Likewise.
* target.def (can_special_div_by_const): Remove.
* target.h: Remove tree-core.h include
* targhooks.cc (default_can_special_div_by_const): Remove.
* targhooks.h (default_can_special_div_by_const): Remove.
* tree-vect-generic.cc (expand_vector_operation): Remove hook.
* tree-vect-patterns.cc (vect_recog_divmod_pattern): Remove hook and
implement new obtab recognition based on range.
* tree-vect-stmts.cc (vectorizable_operation): Remove hook.

gcc/testsuite/ChangeLog:

PR target/108583
* gcc.dg/vect/vect-div-bitmask-4.c: New test.
* gcc.dg/vect/vect-div-bitmask-5.c: New test.

--- inline copy of patch -- 
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 
7235d34c4b30949febfa10d5a626ac9358281cfa..02004c4b0f4d88dffe980f7408038595e21af35d
 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -5668,6 +5668,18 @@ represented in RTL using a @code{smul_highpart} RTX 
expression.
 Similar, but the multiplication is unsigned.  This may be represented
 in RTL using an @code{umul_highpart} RTX expression.
 
+@cindex @code{sadd@var{m}3_highpart} instruction pattern
+@item @samp{smul@var{m}3_highpart}
+Perform a signed addition of operands 1 and 2, which have mode
+@var{m}, and store the most significant half of the product in operand 0.
+The least significant half of the product is discarded.  This may be
+represented in RTL using a @code{sadd_highpart} RTX expression.
+
+@cindex @code{uadd@var{m}3_highpart} instruction pattern
+@item @samp{uadd@var{m}3_highpart}
+Similar, but the addition is unsigned.  This may be represented
+in RTL using an @code{uadd_highpart} RTX expression.
+
 @cindex @code{madd@var{m}@var{n}4} instruction pattern
 @item @samp{madd@var{m}@var{n}4}
 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi
index 
d1380e1eb3ba6b2853686f41f2bf937bfcbed1fe..63a7ef6e566eeea4f14c00343d171940ec4222f3
 100644
--- a/gcc/doc/rtl.texi
+++ b/gcc/doc/rtl.texi
@@ -2535,6 +2535,17 @@ out in machine mode @var{m}.  @code{smul_highpart} 
returns the high part
 of a signed multiplication, @code{umul_highpart} returns the high part
 of an unsigned multiplication.
 
+@findex sadd_highpart
+@findex uadd_highpart
+@cindex high-part addition
+@cindex addition high part
+@item (sadd_highpart:@var{m} @var{x} @var{y})
+@itemx (uadd_highpart:@var{m} @var{x} @var{y})
+Represents the high-part addition of @var{x} and @var{y} carried
+out in machine mode @var{m}.  @code{sadd_highpart} returns the high part
+of a signed addition, @code{uadd_highpart} returns the high part
+of an unsigned addition.
+
 @findex fma
 @cindex fused multiply-add
 @item (fma:@var{m} @var{x} @var{y} @var{z})
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 
c6c891972d1e58cd163b259ba96a599d62326865..3ab2031a336b8758d5791484017e6b0d62ab077e
 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -6137,22 +6137,6 @@ instruction pattern.  There is no need for the hook to 
handle these two
 implementation approaches itself.
 @end deftypefn
 
-@deftypefn {Target Hook} bool TARGET_VECTORIZE_CAN_SPECIAL_DIV_BY_CONST (enum 
@var{tree_code}, tree @var{vectype}, wide_int @var{constant}, rtx 
*@var{output}, rtx @var{in0}, rtx @var{in1})
-This hook is used to test whether the target has a special method of
-division of vectors of type @var{vectype} using the value @var{constant},
-and producing a vector of type @var{vectype}.  The division
-will then not be decomposed by the vectorizer and kept as a div.
-
-When the hook is being used to test whether the target supports a special
-divide, @var{in0}, @var{in1}, and @var{output} are all null.  When the hook
-is being used to emit a division, @var{in0} and @var{in1} are the source
-vectors of type @var{vecttype} 

[PATCH 2/2]AArch64 Update div-bitmask to implement new optab instead of target hook [PR108583]

[Tamar Christina via Gcc-patches]

Hi All,

This replaces the custom division hook with just an implementation through
add_highpart.  For NEON we implement the add highpart (Addition + extraction of
the upper highpart of the register in the same precision) as ADD + LSR.

This representation allows us to easily optimize the sequence using existing
sequences. This gets us a pretty decent sequence using SRA:

umull   v1.8h, v0.8b, v3.8b
umull2  v0.8h, v0.16b, v3.16b
add v5.8h, v1.8h, v2.8h
add v4.8h, v0.8h, v2.8h
usrav1.8h, v5.8h, 8
usrav0.8h, v4.8h, 8
uzp2v1.16b, v1.16b, v0.16b

To get the most optimal sequence however we match (a + ((b + c) >> n)) where n
is half the precision of the mode of the operation into addhn + uaddw which is
a general good optimization on its own and gets us back to:

.L4:
ldr q0, [x3]
umull   v1.8h, v0.8b, v5.8b
umull2  v0.8h, v0.16b, v5.16b
addhn   v3.8b, v1.8h, v4.8h
addhn   v2.8b, v0.8h, v4.8h
uaddw   v1.8h, v1.8h, v3.8b
uaddw   v0.8h, v0.8h, v2.8b
uzp2v1.16b, v1.16b, v0.16b
str q1, [x3], 16
cmp x3, x4
bne .L4

For SVE2 we optimize the initial sequence to the same ADD + LSR which gets us:

.L3:
ld1bz0.h, p0/z, [x0, x3]
mul z0.h, p1/m, z0.h, z2.h
add z1.h, z0.h, z3.h
usraz0.h, z1.h, #8
lsr z0.h, z0.h, #8
st1bz0.h, p0, [x0, x3]
inchx3
whilelo p0.h, w3, w2
b.any   .L3
.L1:
ret

and to get the most optimal sequence I match (a + b) >> n (same constraint on n)
to addhnb which gets us to:

.L3:
ld1bz0.h, p0/z, [x0, x3]
mul z0.h, p1/m, z0.h, z2.h
addhnb  z1.b, z0.h, z3.h
addhnb  z0.b, z0.h, z1.h
st1bz0.h, p0, [x0, x3]
inchx3
whilelo p0.h, w3, w2
b.any   .L3

There are multiple RTL representations possible for these optimizations, I did
not represent them using a zero_extend because we seem very inconsistent in this
in the backend.  Since they are unspecs we won't match them from vector ops
anyway. I figured maintainers would prefer this, but my maintainer ouija board
is still out for repairs :)

There are no new test as new correctness tests were added to the mid-end and
the existing codegen tests for this already exist.

Bootstrapped Regtested on aarch64-none-linux-gnu and  issues.

Ok for master?

Thanks,
Tamar

gcc/ChangeLog:

PR target/108583
* config/aarch64/aarch64-simd.md (@aarch64_bitmask_udiv3): Remove.
(add3_highpart, *bitmask_shift_plus): New.
* config/aarch64/aarch64-sve2.md (add3_highpart,
*bitmask_shift_plus): New.
(@aarch64_bitmask_udiv3): Remove.
* config/aarch64/aarch64.cc
(aarch64_vectorize_can_special_div_by_constant): Removed.
* config/aarch64/iterators.md (UNSPEC_SADD_HIGHPART,
UNSPEC_UADD_HIGHPART, ADD_HIGHPART): New.

--- inline copy of patch -- 
diff --git a/gcc/config/aarch64/aarch64-simd.md 
b/gcc/config/aarch64/aarch64-simd.md
index 
7f212bf37cd2c120dceb7efa733c9fa76226f029..26871a56d1fdb134f0ad9d828ce68a8df0272c53
 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4867,62 +4867,48 @@ (define_expand "aarch64_hn2"
   }
 )
 
-;; div optimizations using narrowings
-;; we can do the division e.g. shorts by 255 faster by calculating it as
-;; (x + ((x + 257) >> 8)) >> 8 assuming the operation is done in
-;; double the precision of x.
-;;
-;; If we imagine a short as being composed of two blocks of bytes then
-;; adding 257 or 0b_0001__0001 to the number is equivalent to
-;; adding 1 to each sub component:
-;;
-;;  short value of 16-bits
-;; ┌──┬┐
-;; │  ││
-;; └──┴┘
-;;   8-bit part1 ▲  8-bit part2   ▲
-;;   ││
-;;   ││
-;;  +1   +1
-;;
-;; after the first addition, we have to shift right by 8, and narrow the
-;; results back to a byte.  Remember that the addition must be done in
-;; double the precision of the input.  Since 8 is half the size of a short
-;; we can use a narrowing halfing instruction in AArch64, addhn which also
-;; does the addition in a wider precision and narrows back to a byte.  The
-;; shift itself is implicit in the operation as it writes back only the top
-;; half of the result. i.e. bits 2*esize-1:esize.
-;;
-;; Since we have narrowed the result of the first part back to a byte, for
-;; the second addition we can use a widening addition, uaddw.
-;;
-;; For the final shift, since it's unsigned arithmetic we emit an ushr by 8.
-;;
-;; The shift is later optimized by combine to a uzp2 with movi #0.
-(define_expand "@aarch64_bitmask_udiv3"
-  [(match_operand:VQN 0 "register_operand")
-   (match_operand:VQN 1 "register_op

Re: [PATCH 2/2] c++: speculative constexpr and is_constant_evaluated [PR108243]

[Patrick Palka via Gcc-patches]

On Sun, 5 Feb 2023, Jason Merrill wrote:

> On 2/3/23 15:51, Patrick Palka wrote:
> > On Mon, 30 Jan 2023, Jason Merrill wrote:
> > 
> > > On 1/27/23 17:02, Patrick Palka wrote:
> > > > This PR illustrates that __builtin_is_constant_evaluated currently acts
> > > > as an optimization barrier for our speculative constexpr evaluation,
> > > > since we don't want to prematurely fold the builtin to false if the
> > > > expression in question would be later manifestly constant evaluated (in
> > > > which case it must be folded to true).
> > > > 
> > > > This patch fixes this by permitting __builtin_is_constant_evaluated
> > > > to get folded as false during cp_fold_function, since at that point
> > > > we're sure we're doing manifestly constant evaluation.  To that end
> > > > we add a flags parameter to cp_fold that controls what mce_value the
> > > > CALL_EXPR case passes to maybe_constant_value.
> > > > 
> > > > bootstrapped and rgetsted no x86_64-pc-linux-gnu, does this look OK for
> > > > trunk?
> > > > 
> > > > PR c++/108243
> > > > 
> > > > gcc/cp/ChangeLog:
> > > > 
> > > > * cp-gimplify.cc (enum fold_flags): Define.
> > > > (cp_fold_data::genericize): Replace this data member with ...
> > > > (cp_fold_data::fold_flags): ... this.
> > > > (cp_fold_r): Adjust cp_fold_data use and cp_fold_calls.
> > > > (cp_fold_function): Likewise.
> > > > (cp_fold_maybe_rvalue): Likewise.
> > > > (cp_fully_fold_init): Likewise.
> > > > (cp_fold): Add fold_flags parameter.  Don't cache if flags
> > > > isn't empty.
> > > > : Pass mce_false to maybe_constant_value
> > > > if if ff_genericize is set.
> > > > 
> > > > gcc/testsuite/ChangeLog:
> > > > 
> > > > * g++.dg/opt/pr108243.C: New test.
> > > > ---
> > > >gcc/cp/cp-gimplify.cc   | 76
> > > > ++---
> > > >gcc/testsuite/g++.dg/opt/pr108243.C | 29 +++
> > > >2 files changed, 76 insertions(+), 29 deletions(-)
> > > >create mode 100644 gcc/testsuite/g++.dg/opt/pr108243.C
> > > > 
> > > > diff --git a/gcc/cp/cp-gimplify.cc b/gcc/cp/cp-gimplify.cc
> > > > index a35cedd05cc..d023a63768f 100644
> > > > --- a/gcc/cp/cp-gimplify.cc
> > > > +++ b/gcc/cp/cp-gimplify.cc
> > > > @@ -43,12 +43,20 @@ along with GCC; see the file COPYING3.  If not see
> > > >#include "omp-general.h"
> > > >#include "opts.h"
> > > >+/* Flags for cp_fold and cp_fold_r.  */
> > > > +
> > > > +enum fold_flags {
> > > > +  ff_none = 0,
> > > > +  /* Whether we're being called from cp_fold_function.  */
> > > > +  ff_genericize = 1 << 0,
> > > > +};
> > > > +
> > > >/* Forward declarations.  */
> > > >  static tree cp_genericize_r (tree *, int *, void *);
> > > >static tree cp_fold_r (tree *, int *, void *);
> > > >static void cp_genericize_tree (tree*, bool);
> > > > -static tree cp_fold (tree);
> > > > +static tree cp_fold (tree, fold_flags);
> > > >  /* Genericize a TRY_BLOCK.  */
> > > >@@ -996,9 +1004,8 @@ struct cp_genericize_data
> > > >struct cp_fold_data
> > > >{
> > > >  hash_set pset;
> > > > -  bool genericize; // called from cp_fold_function?
> > > > -
> > > > -  cp_fold_data (bool g): genericize (g) {}
> > > > +  fold_flags flags;
> > > > +  cp_fold_data (fold_flags flags): flags (flags) {}
> > > >};
> > > >  static tree
> > > > @@ -1039,7 +1046,7 @@ cp_fold_r (tree *stmt_p, int *walk_subtrees, void
> > > > *data_)
> > > >  break;
> > > >}
> > > >-  *stmt_p = stmt = cp_fold (*stmt_p);
> > > > +  *stmt_p = stmt = cp_fold (*stmt_p, data->flags);
> > > >if (data->pset.add (stmt))
> > > >{
> > > > @@ -1119,12 +1126,12 @@ cp_fold_r (tree *stmt_p, int *walk_subtrees,
> > > > void
> > > > *data_)
> > > >  here rather than in cp_genericize to avoid problems with the
> > > > invisible
> > > >  reference transition.  */
> > > >case INIT_EXPR:
> > > > -  if (data->genericize)
> > > > +  if (data->flags & ff_genericize)
> > > > cp_genericize_init_expr (stmt_p);
> > > >  break;
> > > >  case TARGET_EXPR:
> > > > -  if (data->genericize)
> > > > +  if (data->flags & ff_genericize)
> > > > cp_genericize_target_expr (stmt_p);
> > > >/* Folding might replace e.g. a COND_EXPR with a TARGET_EXPR;
> > > > in
> > > > @@ -1157,7 +1164,7 @@ cp_fold_r (tree *stmt_p, int *walk_subtrees, void
> > > > *data_)
> > > >void
> > > >cp_fold_function (tree fndecl)
> > > >{
> > > > -  cp_fold_data data (/*genericize*/true);
> > > > +  cp_fold_data data (ff_genericize);
> > > >  cp_walk_tree (&DECL_SAVED_TREE (fndecl), cp_fold_r, &data, NULL);
> > > >}
> > > >@@ -2375,7 +2382,7 @@ cp_fold_maybe_rvalue (tree x, bool rval)
> > > >{
> > > >  while (true)
> > > >{
> > > > -  x = cp_fold (x);
> > > > +  x = cp_fold (x, ff_none);
> > > >  if (rv

[PATCH] c++: ICE with -fno-elide-constructors and trivial fn [PR101073]

[Marek Polacek via Gcc-patches]

In constexpr-nsdmi3.C, with -fno-elide-constructors, we don't elide
the Y::Y(const Y&) call used to initialize o.c.  So store_init_value
-> cxx_constant_init must constexpr-evaluate the call to Y::Y(const Y&)
in cxx_eval_call_expression.  It's a trivial function, so we do the
"Shortcut trivial constructor/op=" code and rather than evaluating
the function, we just create an assignment

  o.c = *(const struct Y &) (const struct Y *) &(&)->b

which is a MODIFY_EXPR, so the preeval code in cxx_eval_store_expression
clears .ctor and .object, therefore we can't replace the PLACEHOLDER_EXPR
whereupon we crash at

  /* A placeholder without a referent.  We can get here when
 checking whether NSDMIs are noexcept, or in massage_init_elt;
 just say it's non-constant for now.  */
  gcc_assert (ctx->quiet);

The PLACEHOLDER_EXPR can also be on the LHS as in constexpr-nsdmi10.C.
I don't think we can do much here, but I noticed that the whole
trivial_fn_p (fun) block is only entered when -fno-elide-constructors.
This is true since GCC 9; it wasn't easy to bisect what changes made it
so, but r240845 is probably one of them.  -fno-elide-constructors is an
option for experiments only so it's not clear to me why we'd still want
to shortcut trivial constructor/op=.  I propose to remove the code and
add a checking assert to make sure we're not getting a trivial_fn_p
unless -fno-elide-constructors.

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk?  I don't
think I want to backport this.

PR c++/101073

gcc/cp/ChangeLog:

* constexpr.cc (cxx_eval_call_expression): Replace shortcutting trivial
constructor/op= with a checking assert.

gcc/testsuite/ChangeLog:

* g++.dg/cpp0x/constexpr-nsdmi3.C: New test.
* g++.dg/cpp1y/constexpr-nsdmi10.C: New test.
---
 gcc/cp/constexpr.cc   | 25 +++
 gcc/testsuite/g++.dg/cpp0x/constexpr-nsdmi3.C | 17 +
 .../g++.dg/cpp1y/constexpr-nsdmi10.C  | 18 +
 3 files changed, 38 insertions(+), 22 deletions(-)
 create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-nsdmi3.C
 create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-nsdmi10.C

diff --git a/gcc/cp/constexpr.cc b/gcc/cp/constexpr.cc
index 564766c8a00..1d53dcf0f20 100644
--- a/gcc/cp/constexpr.cc
+++ b/gcc/cp/constexpr.cc
@@ -2865,28 +2865,9 @@ cxx_eval_call_expression (const constexpr_ctx *ctx, tree 
t,
   ctx = &new_ctx;
 }
 
-  /* Shortcut trivial constructor/op=.  */
-  if (trivial_fn_p (fun))
-{
-  tree init = NULL_TREE;
-  if (call_expr_nargs (t) == 2)
-   init = convert_from_reference (get_nth_callarg (t, 1));
-  else if (TREE_CODE (t) == AGGR_INIT_EXPR
-  && AGGR_INIT_ZERO_FIRST (t))
-   init = build_zero_init (DECL_CONTEXT (fun), NULL_TREE, false);
-  if (init)
-   {
- tree op = get_nth_callarg (t, 0);
- if (is_dummy_object (op))
-   op = ctx->object;
- else
-   op = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (op)), op);
- tree set = build2 (MODIFY_EXPR, TREE_TYPE (op), op, init);
- new_ctx.call = &new_call;
- return cxx_eval_constant_expression (&new_ctx, set, lval,
-  non_constant_p, overflow_p);
-   }
-}
+  /* We used to shortcut trivial constructor/op= here, but nowadays
+ we can only get a trivial function here with -fno-elide-constructors.  */
+  gcc_checking_assert (!trivial_fn_p (fun) || !flag_elide_constructors);
 
   bool non_constant_args = false;
   new_call.bindings
diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-nsdmi3.C 
b/gcc/testsuite/g++.dg/cpp0x/constexpr-nsdmi3.C
new file mode 100644
index 000..ec1c4e53387
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-nsdmi3.C
@@ -0,0 +1,17 @@
+// PR c++/101073
+// { dg-do compile { target c++11 } }
+// { dg-additional-options "-fno-elide-constructors" }
+
+struct Y
+{
+  int a;
+};
+
+struct X
+{
+  Y b = Y{1};
+  Y c = this->b;
+};
+
+constexpr X o = { };
+static_assert(o.b.a == 1 && o.c.a == 1, "");
diff --git a/gcc/testsuite/g++.dg/cpp1y/constexpr-nsdmi10.C 
b/gcc/testsuite/g++.dg/cpp1y/constexpr-nsdmi10.C
new file mode 100644
index 000..35cb8acc15b
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp1y/constexpr-nsdmi10.C
@@ -0,0 +1,18 @@
+// PR c++/101073
+// { dg-do compile { target c++14 } }
+// { dg-additional-options "-fno-elide-constructors" }
+// A copy of constexpr-nsdmi9.C.
+
+struct Y
+{
+  int a;
+};
+
+struct X
+{
+  Y b = (c={5});
+  Y c = (b={1});
+};
+
+constexpr X o = { };
+static_assert(o.b.a == 1 && o.c.a == 1, "");

base-commit: b24e9c083093a9e1b1007933a184c02f7ff058db
-- 
2.39.1

[PATCH] c++: sizeof(expr) in non-templated requires-expr [PR108563]

[Patrick Palka via Gcc-patches]

When substituting into sizeof(expr), tsubst_copy_and_build elides
substitution into the operand if args is NULL_TREE, and instead
considers the TREE_TYPE of the operand.  But here the (templated)
operand is a TEMPLATE_ID_EXPR with empty TREE_TYPE, so we can't elide
substitution in this case.

Contrary to the associated comment (dating back to r69130) substituting
args=NULL_TREE should generally work since we do exactly that in e.g.
fold_non_dependent_expr, and I don't see why the operand of sizeof would
be an exception.  So this patch just removes this special case.

Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
trunk?  Diff generated with -w to ignore noisy whitespace changes.

PR c++/108563

gcc/cp/ChangeLog:

* pt.cc (tsubst_copy_and_build) : Remove
special case for empty args.

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/concepts-requires35.C: New test.
---
 gcc/cp/pt.cc  | 25 ++-
 .../g++.dg/cpp2a/concepts-requires35.C| 14 +++
 2 files changed, 21 insertions(+), 18 deletions(-)
 create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-requires35.C

diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index 9f3fc1fa089..f21d28263d1 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -20652,25 +20652,14 @@ tsubst_copy_and_build (tree t,
  op1 = TREE_TYPE (op1);
bool std_alignof = (TREE_CODE (t) == ALIGNOF_EXPR
&& ALIGNOF_EXPR_STD_P (t));
-if (!args)
- {
-   /* When there are no ARGS, we are trying to evaluate a
-  non-dependent expression from the parser.  Trying to do
-  the substitutions may not work.  */
-   if (!TYPE_P (op1))
- op1 = TREE_TYPE (op1);
- }
+   ++cp_unevaluated_operand;
+   ++c_inhibit_evaluation_warnings;
+   if (TYPE_P (op1))
+ op1 = tsubst (op1, args, complain, in_decl);
else
- {
-   ++cp_unevaluated_operand;
-   ++c_inhibit_evaluation_warnings;
-   if (TYPE_P (op1))
- op1 = tsubst (op1, args, complain, in_decl);
-   else
- op1 = tsubst_copy_and_build (op1, args, complain, in_decl);
-   --cp_unevaluated_operand;
-   --c_inhibit_evaluation_warnings;
- }
+ op1 = tsubst_copy_and_build (op1, args, complain, in_decl);
+   --cp_unevaluated_operand;
+   --c_inhibit_evaluation_warnings;
 if (TYPE_P (op1))
  r = cxx_sizeof_or_alignof_type (input_location,
  op1, TREE_CODE (t), std_alignof,
diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-requires35.C 
b/gcc/testsuite/g++.dg/cpp2a/concepts-requires35.C
new file mode 100644
index 000..2bb4b2b0b5d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/concepts-requires35.C
@@ -0,0 +1,14 @@
+// PR c++/108563
+// { dg-do compile { target c++20 } }
+
+template
+struct foo {
+  static constexpr T value = 0;
+};
+
+template
+inline constexpr T foo_v = foo::value;
+
+static_assert(requires { sizeof(foo_v); });
+static_assert(requires { requires sizeof(foo_v) == sizeof(int*); });
+static_assert(requires { requires sizeof(foo_v) == sizeof(char); });
-- 
2.39.1.418.g7876265d61

Re: [PATCH] c++: sizeof(expr) in non-templated requires-expr [PR108563]

[Patrick Palka via Gcc-patches]

On Thu, 9 Feb 2023, Patrick Palka wrote:

> When substituting into sizeof(expr), tsubst_copy_and_build elides
> substitution into the operand if args is NULL_TREE, and instead
> considers the TREE_TYPE of the operand.  But here the (templated)
> operand is a TEMPLATE_ID_EXPR with empty TREE_TYPE, so we can't elide
> substitution in this case.
> 
> Contrary to the associated comment (dating back to r69130) substituting
> args=NULL_TREE should generally work since we do exactly that in e.g.
> fold_non_dependent_expr, and I don't see why the operand of sizeof would
> be an exception.  So this patch just removes this special case.
> 
> Bootstrapped and regtested on x86_64-pc-linux-gnu, does this look OK for
> trunk?  Diff generated with -w to ignore noisy whitespace changes.

This time with -w actually passed to format-patch:

-- >8 --

PR c++/108563

gcc/cp/ChangeLog:

* pt.cc (tsubst_copy_and_build) : Remove
special case for empty args.

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/concepts-requires35.C: New test.
---
 gcc/cp/pt.cc | 11 ---
 gcc/testsuite/g++.dg/cpp2a/concepts-requires35.C | 14 ++
 2 files changed, 14 insertions(+), 11 deletions(-)
 create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-requires35.C

diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc
index 9f3fc1fa089..f21d28263d1 100644
--- a/gcc/cp/pt.cc
+++ b/gcc/cp/pt.cc
@@ -20652,16 +20652,6 @@ tsubst_copy_and_build (tree t,
  op1 = TREE_TYPE (op1);
bool std_alignof = (TREE_CODE (t) == ALIGNOF_EXPR
&& ALIGNOF_EXPR_STD_P (t));
-if (!args)
- {
-   /* When there are no ARGS, we are trying to evaluate a
-  non-dependent expression from the parser.  Trying to do
-  the substitutions may not work.  */
-   if (!TYPE_P (op1))
- op1 = TREE_TYPE (op1);
- }
-   else
- {
++cp_unevaluated_operand;
++c_inhibit_evaluation_warnings;
if (TYPE_P (op1))
@@ -20670,7 +20660,6 @@ tsubst_copy_and_build (tree t,
  op1 = tsubst_copy_and_build (op1, args, complain, in_decl);
--cp_unevaluated_operand;
--c_inhibit_evaluation_warnings;
- }
 if (TYPE_P (op1))
  r = cxx_sizeof_or_alignof_type (input_location,
  op1, TREE_CODE (t), std_alignof,
diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-requires35.C 
b/gcc/testsuite/g++.dg/cpp2a/concepts-requires35.C
new file mode 100644
index 000..2bb4b2b0b5d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp2a/concepts-requires35.C
@@ -0,0 +1,14 @@
+// PR c++/108563
+// { dg-do compile { target c++20 } }
+
+template
+struct foo {
+  static constexpr T value = 0;
+};
+
+template
+inline constexpr T foo_v = foo::value;
+
+static_assert(requires { sizeof(foo_v); });
+static_assert(requires { requires sizeof(foo_v) == sizeof(int*); });
+static_assert(requires { requires sizeof(foo_v) == sizeof(char); });
-- 
2.39.1.418.g7876265d61

Re: [PATCH] testsuite: adjust patterns in RISC-V tests to skip unwind table directives

[Palmer Dabbelt]

On Thu, 09 Feb 2023 01:48:25 PST (-0800), gcc-patches@gcc.gnu.org wrote:

PR target/108723
* gcc.target/riscv/shorten-memrefs-1.c: Adjust patterns to skip
over cfi directives.
* gcc.target/riscv/shorten-memrefs-2.c: Likewise.
* gcc.target/riscv/shorten-memrefs-3.c: Likewise.
* gcc.target/riscv/shorten-memrefs-4.c: Likewise.
* gcc.target/riscv/shorten-memrefs-5.c: Likewise.
* gcc.target/riscv/shorten-memrefs-6.c: Likewise.
* gcc.target/riscv/shorten-memrefs-8.c: Likewise.
---
 gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c | 4 ++--
 gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c | 8 
 gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c | 2 +-
 gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c | 4 ++--
 gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c | 8 
 gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c | 2 +-
 gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c | 4 ++--
 7 files changed, 16 insertions(+), 16 deletions(-)


It kind of smells like there's some better way to write these test 
cases, but the label->instruction matching was already there.  I'm fine 
just taking the fix for now so


Reviewed-by: Palmer Dabbelt 
Acked-by: Palmer Dabbelt 

but if anyone has ideas on how to make the tests less fragile I'm all 
ears.


I didn't actually run the tests and I'm pretty bad at doing regexes in 
my head, though.  If you ran them and can commit that's good with me, 
but LMK if you want me to.


Thanks!



diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c 
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
index f0222f46eff..cce7c80f6c1 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
@@ -23,5 +23,5 @@ store2z (long long *array)
   array[203] = 0;
 }

-/* { dg-final { scan-assembler-not "store1z:\n\taddi" } } */
-/* { dg-final { scan-assembler-not "store2z:\n\taddi" } } */
+/* { dg-final { scan-assembler-not "store1z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */
+/* { dg-final { scan-assembler-not "store2z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c 
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
index ec39104fd88..a9ddb797d06 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
@@ -44,9 +44,9 @@ load2r (long long *array)
   return a;
 }

-/* { dg-final { scan-assembler "store1a:\n\taddi" } } */
+/* { dg-final { scan-assembler "store1a:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
 /* The sd insns in store2a are not rewritten because shorten_memrefs currently
only optimizes lw and sw.
-/* { dg-final { scan-assembler "store2a:\n\taddi" { xfail riscv*-*-*  } } } */
-/* { dg-final { scan-assembler "load1r:\n\taddi" } } */
-/* { dg-final { scan-assembler "load2r:\n\taddi" } } */
+/* { dg-final { scan-assembler "store2a:\n(\t?\\.\[^\n\]*\n)*\taddi" { xfail 
riscv*-*-*  } } } */
+/* { dg-final { scan-assembler "load1r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
+/* { dg-final { scan-assembler "load2r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c 
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
index 50316284832..3d561124b81 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
@@ -36,5 +36,5 @@ load2a (long long a0, long long a1, long long a2, long long 
a3, long long a4,
   return sub2 (a0, a1, a2, a3, a4, 0, a);
 }

-/* { dg-final { scan-assembler-not "load1a:\n\taddi" { xfail riscv*-*-* } } } 
*/
+/* { dg-final { scan-assembler-not "load1a:\n(\t?\\.\[^\n\]*\n)*\taddi" { 
xfail riscv*-*-* } } } */
 /* { dg-final { scan-assembler-not "load2a:\n.*addi\[ 
\t\]*\[at\]\[0-9\],\[at\]\[0-9\],\[0-9\]*" { xfail riscv*-*-*  } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c 
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
index d985512e2b3..26decf085fb 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
@@ -23,5 +23,5 @@ store2z (long long *array)
   array[203] = 0;
 }

-/* { dg-final { scan-assembler-not "store1z:\n\taddi" } } */
-/* { dg-final { scan-assembler-not "store2z:\n\taddi" } } */
+/* { dg-final { scan-assembler-not "store1z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */
+/* { dg-final { scan-assembler-not "store2z:\n(\t?\\.\[^\n\]*\n)\taddi" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c 
b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
index 9217922c10d..11e858ed6da 100644
--- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
+++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c
@@ -44,11 +44,11 @@ load2r (long long *array)
   return a;
 }

-/* { dg-final { scan-assembler "store1a:\n\taddi" } } */
+/* { dg-final { scan-assembler "store1a:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
 /* The sd insns in store2a are not rewritten because shorten_memrefs currently

Re: [PATCH] testsuite: adjust patterns in RISC-V tests to skip unwind table directives

[Andrew Pinski via Gcc-patches]

On Thu, Feb 9, 2023 at 11:10 AM Palmer Dabbelt  wrote:
>
> On Thu, 09 Feb 2023 01:48:25 PST (-0800), gcc-patches@gcc.gnu.org wrote:
> > PR target/108723
> > * gcc.target/riscv/shorten-memrefs-1.c: Adjust patterns to skip
> > over cfi directives.
> > * gcc.target/riscv/shorten-memrefs-2.c: Likewise.
> > * gcc.target/riscv/shorten-memrefs-3.c: Likewise.
> > * gcc.target/riscv/shorten-memrefs-4.c: Likewise.
> > * gcc.target/riscv/shorten-memrefs-5.c: Likewise.
> > * gcc.target/riscv/shorten-memrefs-6.c: Likewise.
> > * gcc.target/riscv/shorten-memrefs-8.c: Likewise.
> > ---
> >  gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c | 4 ++--
> >  gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c | 8 
> >  gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c | 2 +-
> >  gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c | 4 ++--
> >  gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c | 8 
> >  gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c | 2 +-
> >  gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c | 4 ++--
> >  7 files changed, 16 insertions(+), 16 deletions(-)
>
> It kind of smells like there's some better way to write these test
> cases, but the label->instruction matching was already there.  I'm fine
> just taking the fix for now so
>
> Reviewed-by: Palmer Dabbelt 
> Acked-by: Palmer Dabbelt 
>
> but if anyone has ideas on how to make the tests less fragile I'm all
> ears.
>
> I didn't actually run the tests and I'm pretty bad at doing regexes in
> my head, though.  If you ran them and can commit that's good with me,
> but LMK if you want me to.

Maybe you could use check-function-bodies for these files?
check-function-bodies does remove cfi and other .line directives too
when doing the scanning.

Thanks,
Andrew Pinski

>
> Thanks!
>
> >
> > diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c 
> > b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
> > index f0222f46eff..cce7c80f6c1 100644
> > --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
> > +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c
> > @@ -23,5 +23,5 @@ store2z (long long *array)
> >array[203] = 0;
> >  }
> >
> > -/* { dg-final { scan-assembler-not "store1z:\n\taddi" } } */
> > -/* { dg-final { scan-assembler-not "store2z:\n\taddi" } } */
> > +/* { dg-final { scan-assembler-not "store1z:\n(\t?\\.\[^\n\]*\n)\taddi" } 
> > } */
> > +/* { dg-final { scan-assembler-not "store2z:\n(\t?\\.\[^\n\]*\n)\taddi" } 
> > } */
> > diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c 
> > b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
> > index ec39104fd88..a9ddb797d06 100644
> > --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
> > +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c
> > @@ -44,9 +44,9 @@ load2r (long long *array)
> >return a;
> >  }
> >
> > -/* { dg-final { scan-assembler "store1a:\n\taddi" } } */
> > +/* { dg-final { scan-assembler "store1a:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
> >  /* The sd insns in store2a are not rewritten because shorten_memrefs 
> > currently
> > only optimizes lw and sw.
> > -/* { dg-final { scan-assembler "store2a:\n\taddi" { xfail riscv*-*-*  } } 
> > } */
> > -/* { dg-final { scan-assembler "load1r:\n\taddi" } } */
> > -/* { dg-final { scan-assembler "load2r:\n\taddi" } } */
> > +/* { dg-final { scan-assembler "store2a:\n(\t?\\.\[^\n\]*\n)*\taddi" { 
> > xfail riscv*-*-*  } } } */
> > +/* { dg-final { scan-assembler "load1r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
> > +/* { dg-final { scan-assembler "load2r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
> > diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c 
> > b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
> > index 50316284832..3d561124b81 100644
> > --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
> > +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c
> > @@ -36,5 +36,5 @@ load2a (long long a0, long long a1, long long a2, long 
> > long a3, long long a4,
> >return sub2 (a0, a1, a2, a3, a4, 0, a);
> >  }
> >
> > -/* { dg-final { scan-assembler-not "load1a:\n\taddi" { xfail riscv*-*-* } 
> > } } */
> > +/* { dg-final { scan-assembler-not "load1a:\n(\t?\\.\[^\n\]*\n)*\taddi" { 
> > xfail riscv*-*-* } } } */
> >  /* { dg-final { scan-assembler-not "load2a:\n.*addi\[ 
> > \t\]*\[at\]\[0-9\],\[at\]\[0-9\],\[0-9\]*" { xfail riscv*-*-*  } } } */
> > diff --git a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c 
> > b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
> > index d985512e2b3..26decf085fb 100644
> > --- a/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
> > +++ b/gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c
> > @@ -23,5 +23,5 @@ store2z (long long *array)
> >array[203] = 0;
> >  }
> >
> > -/* { dg-final { scan-assembler-not "store1z:\n\taddi" } } */
> > -/* { dg-final { scan-assembler-not "store2z:\n\taddi" } } */
> > +/* { dg-final { scan-assembler-not "store1z:\n(\t?\\.\[^\n\]*\n)\taddi" } 
> > } */
> > +/* { dg-final { scan-assembler

[PATCH] amdgcn: Add instruction patterns for vector operations on complex numbers

[Andrew Jenner]

This patch introduces instruction patterns for complex number operations 
in the GCN machine description. These patterns are cmul, cmul_conj, 
vec_addsub, vec_fmaddsub, vec_fmsubadd, cadd90, cadd270, cmla and cmls 
(cmla_conj and cmls_conj were not found to be favorable to implement). 
As a side effect of adding cmls, I also added fms patterns corresponding 
to the existing fma patterns. Tested on CDNA2 GFX90a.


OK to commit?


gcc/ChangeLog:

* config/gcn/gcn-protos.h (gcn_expand_dpp_swap_pairs_insn)
(gcn_expand_dpp_distribute_even_insn)
(gcn_expand_dpp_distribute_odd_insn): Declare.
* config/gcn/gcn-valu.md (@dpp_swap_pairs)
(@dpp_distribute_even, @dpp_distribute_odd)
(cmul3, cml4, vec_addsub3)
(cadd3, vec_fmaddsub4, vec_fmsubadd4)
(fms4, fms4_negop2, fms4)
(fms4_negop2): New patterns.
* config/gcn/gcn.cc (gcn_expand_dpp_swap_pairs_insn)
(gcn_expand_dpp_distribute_even_insn)
(gcn_expand_dpp_distribute_odd_insn): New functions.
* config/gcn/gcn.md: Add entries to unspec enum.

gcc/testsuite/ChangeLog:

* gcc.target/gcn/complex.c: New test.diff --git a/gcc/config/gcn/gcn-protos.h b/gcc/config/gcn/gcn-protos.h
index 861044e77f0..d7862b21a2a 100644
--- a/gcc/config/gcn/gcn-protos.h
+++ b/gcc/config/gcn/gcn-protos.h
@@ -27,6 +27,11 @@ extern unsigned int gcn_dwarf_register_number (unsigned int 
regno);
 extern rtx get_exec (int64_t);
 extern rtx get_exec (machine_mode mode);
 extern char * gcn_expand_dpp_shr_insn (machine_mode, const char *, int, int);
+extern char * gcn_expand_dpp_swap_pairs_insn (machine_mode, const char *, int);
+extern char * gcn_expand_dpp_distribute_even_insn (machine_mode, const char *,
+  int unspec);
+extern char * gcn_expand_dpp_distribute_odd_insn (machine_mode, const char *,
+ int unspec);
 extern void gcn_expand_epilogue ();
 extern rtx gcn_expand_scaled_offsets (addr_space_t as, rtx base, rtx offsets,
  rtx scale, bool unsigned_p, rtx exec);
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 47d9d87d58a..cb650bca3ff 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -1224,6 +1224,45 @@
   [(set_attr "type" "vop_dpp")
(set_attr "length" "16")])
 
+(define_insn "@dpp_swap_pairs"
+  [(set (match_operand:V_noHI 0 "register_operand""=v")
+   (unspec:V_noHI
+ [(match_operand:V_noHI 1 "register_operand" " v")]
+ UNSPEC_MOV_DPP_SWAP_PAIRS))]
+  ""
+  {
+return gcn_expand_dpp_swap_pairs_insn (mode, "v_mov_b32",
+  UNSPEC_MOV_DPP_SWAP_PAIRS);
+  }
+  [(set_attr "type" "vop_dpp")
+   (set_attr "length" "16")])
+
+(define_insn "@dpp_distribute_even"
+  [(set (match_operand:V_noHI 0 "register_operand""=v")
+   (unspec:V_noHI
+ [(match_operand:V_noHI 1 "register_operand" " v")]
+ UNSPEC_MOV_DPP_DISTRIBUTE_EVEN))]
+  ""
+  {
+return gcn_expand_dpp_distribute_even_insn (mode, "v_mov_b32",
+   UNSPEC_MOV_DPP_DISTRIBUTE_EVEN);
+  }
+  [(set_attr "type" "vop_dpp")
+   (set_attr "length" "16")])
+
+(define_insn "@dpp_distribute_odd"
+  [(set (match_operand:V_noHI 0 "register_operand""=v")
+   (unspec:V_noHI
+ [(match_operand:V_noHI 1 "register_operand" " v")]
+ UNSPEC_MOV_DPP_DISTRIBUTE_EVEN))]
+  ""
+  {
+return gcn_expand_dpp_distribute_odd_insn (mode, "v_mov_b32",
+  UNSPEC_MOV_DPP_DISTRIBUTE_ODD);
+  }
+  [(set_attr "type" "vop_dpp")
+   (set_attr "length" "16")])
+
 ;; }}}
 ;; {{{ ALU special case: add/sub
 
@@ -2185,6 +2224,194 @@
 DONE;
   })
 
+(define_int_iterator UNSPEC_CMUL_OP [UNSPEC_CMUL UNSPEC_CMUL_CONJ])
+(define_int_attr conj_op [(UNSPEC_CMUL "") (UNSPEC_CMUL_CONJ "_conj")])
+(define_int_attr cmul_subadd [(UNSPEC_CMUL "sub") (UNSPEC_CMUL_CONJ "add")])
+(define_int_attr cmul_addsub [(UNSPEC_CMUL "add") (UNSPEC_CMUL_CONJ "sub")])
+
+(define_expand "cmul3"
+  [(set (match_operand:V_noHI 0 "register_operand" "= &v")
+(unspec:V_noHI
+ [(match_operand:V_noHI 1 "register_operand" "v")
+  (match_operand:V_noHI 2 "register_operand" "v")]
+ UNSPEC_CMUL_OP))]
+  ""
+  {
+// operands[1]  a   b
+// operands[2]  c   d
+rtx t1 = gen_reg_rtx (mode);
+emit_insn (gen_mul3 (t1, operands[1], operands[2]));   // a*c b*d
+
+rtx s2_perm = gen_reg_rtx (mode);
+emit_insn (gen_dpp_swap_pairs (s2_perm, operands[2])); // d   c
+
+rtx t2 = gen_reg_rtx (mode);
+emit_insn (gen_mul3 (t2, operands[1], s2_perm));   // a*d b*c
+
+rtx t1_perm = gen_reg_rtx (mode);
+emit_insn (gen_dpp_swap_pairs (t1_perm, t1));  // b*d a*c
+
+rtx even

[PATCH, committed] Fortran: catch invalid kind in character conversion [PR69636,PR103779]

[Harald Anlauf via Gcc-patches]

Dear all,

the attached trivial and obvious patch replaces an internal error
on encountering an invalid kind in a character conversion by a
regular error recovery.

Pushed after regtesting on x86_64-pc-linux-gnu as
r13-5760-ga618b45ac41cf480f54c4fa4014aed6218931290

Thanks,
Harald

From a618b45ac41cf480f54c4fa4014aed6218931290 Mon Sep 17 00:00:00 2001
From: Harald Anlauf 
Date: Thu, 9 Feb 2023 21:16:14 +0100
Subject: [PATCH] Fortran: catch invalid kind in character conversion
 [PR69636,PR103779]

gcc/fortran/ChangeLog:

	PR fortran/69636
	PR fortran/103779
	* intrinsic.cc (gfc_convert_chartype): Recover on invalid character
	kind in conversion instead of generating an internal error.

gcc/testsuite/ChangeLog:

	PR fortran/69636
	PR fortran/103779
	* gfortran.dg/pr103779.f90: New test.

Co-authored-by: Steven G. Kargl 
---
 gcc/fortran/intrinsic.cc   |  3 ++-
 gcc/testsuite/gfortran.dg/pr103779.f90 | 18 ++
 2 files changed, 20 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gfortran.dg/pr103779.f90

diff --git a/gcc/fortran/intrinsic.cc b/gcc/fortran/intrinsic.cc
index 68f481473b4..17ee999c3b9 100644
--- a/gcc/fortran/intrinsic.cc
+++ b/gcc/fortran/intrinsic.cc
@@ -5419,7 +5419,8 @@ gfc_convert_chartype (gfc_expr *expr, gfc_typespec *ts)
   gcc_assert (expr->ts.type == BT_CHARACTER && ts->type == BT_CHARACTER);

   sym = find_char_conv (&expr->ts, ts);
-  gcc_assert (sym);
+  if (sym == NULL)
+return false;

   /* Insert a pre-resolved function call to the right function.  */
   old_where = expr->where;
diff --git a/gcc/testsuite/gfortran.dg/pr103779.f90 b/gcc/testsuite/gfortran.dg/pr103779.f90
new file mode 100644
index 000..3d76c901e75
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/pr103779.f90
@@ -0,0 +1,18 @@
+! { dg-do compile }
+! PR fortran/69636
+! PR fortran/103779
+! Contributed by G.Steinmetz
+
+character(1,) function f() ! { dg-error "Expected initialization expression" }
+  f = 'a'
+end
+
+character(1,kind=) function g() ! { dg-error "Expected initialization expression" }
+  g = 'a'
+end
+
+character(1,n) function h() ! { dg-error "has not been declared" }
+  h = 'a'
+end
+
+! { dg-prune-output "Bad kind expression" }
--
2.35.3

[OG12][committed] openmp: Add support for the 'present' modifier

[Kwok Cheung Yeung]

Hello

I've ported my patch for supporting the OpenMP 5.1 'present' modifier 
and committed it to the devel/omp/gcc-12 development branch:


229b705862c openmp: Add support for the 'present' modifier

Tested with offloading on amdgcn and nvptx.

Kwok

[PATCH] RISC-V: Add vnsrl/vnsra/vncvt/vmerge/vmv C/C++ support

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/ChangeLog:

* config/riscv/constraints.md (Wbr): Remove unused constraint.
* config/riscv/predicates.md: Fix move operand predicate.
* config/riscv/riscv-vector-builtins-bases.cc (class vnshift): New 
class.
(class vncvt_x): Ditto.
(class vmerge): Ditto.
(class vmv_v): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vsra): Ditto.
(vsrl): Ditto.
(vnsrl): Ditto.
(vnsra): Ditto.
(vncvt_x): Ditto.
(vmerge): Ditto.
(vmv_v): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct narrow_alu_def): 
Ditto.
(struct move_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_WEXTI_OPS): New 
variable.
(DEF_RVV_WEXTU_OPS): Ditto
* config/riscv/riscv-vector-builtins.def (x_x_w): Fix type for suffix.
(v_v): Ditto.
(v_x): Ditto.
(x_w): Ditto.
(x): Ditto.
* config/riscv/riscv.cc (riscv_print_operand): Refine ASM printting 
rule.
* config/riscv/vector-iterators.md (nmsac):New iterator.
(nmsub): New iterator.
* config/riscv/vector.md (@pred_merge): New pattern.
(@pred_merge_scalar): New pattern.
(*pred_merge_scalar): New pattern.
(*pred_merge_extended_scalar): New pattern.
(@pred_narrow_): New pattern.
(@pred_narrow__scalar): New pattern.
(@pred_trunc): New pattern.

---
 gcc/config/riscv/constraints.md   |  13 -
 gcc/config/riscv/predicates.md|   7 +-
 .../riscv/riscv-vector-builtins-bases.cc  |  78 ++
 .../riscv/riscv-vector-builtins-bases.h   |   5 +
 .../riscv/riscv-vector-builtins-functions.def |  17 +-
 .../riscv/riscv-vector-builtins-shapes.cc |  54 
 .../riscv/riscv-vector-builtins-shapes.h  |   2 +
 gcc/config/riscv/riscv-vector-builtins.cc | 115 
 gcc/config/riscv/riscv-vector-builtins.def|   5 +-
 gcc/config/riscv/riscv.cc |  42 ++-
 gcc/config/riscv/vector-iterators.md  |   3 +
 gcc/config/riscv/vector.md| 253 --
 12 files changed, 537 insertions(+), 57 deletions(-)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index b646ad4853c..a051d466ae2 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -166,16 +166,3 @@
   "Vector duplicate memory operand"
   (and (match_code "mem")
(match_code "reg" "0")))
-
-;; (vec_duplicate:V (const_int 2863311530 [0x])) of pred_broadcast
-;; is CSEed into (const_vector:V (const_int 2863311530 [0x])) here
-;; which is not the pattern matching we want since we can't generate
-;; instruction directly for it when SEW = 64 and !TARGET_64BIT. We should
-;; not allow RA (register allocation) allocate a DImode register in
-;; pred_broadcast pattern.
-(define_constraint "Wbr"
-  "@internal
-   Broadcast register operand"
-  (and (match_code "reg")
-   (match_test "REGNO (op) <= GP_REG_LAST
-   && direct_broadcast_operand (op, GET_MODE (op))")))
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 8d2ccb0f7a2..fe2c5ba3c5c 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -288,10 +288,9 @@
(match_test "op == CONSTM1_RTX (GET_MODE (op))")))
 
 (define_predicate "vector_merge_operand"
-  (ior (match_operand 0 "memory_operand")
-   (ior (match_operand 0 "register_operand")
-   (match_test "GET_CODE (op) == UNSPEC
-&& (XINT (op, 1) == UNSPEC_VUNDEF)"
+  (ior (match_operand 0 "register_operand")
+   (match_test "GET_CODE (op) == UNSPEC
+   && (XINT (op, 1) == UNSPEC_VUNDEF)")))
 
 (define_predicate "vector_arith_operand"
   (ior (match_operand 0 "register_operand")
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index bcf2dfe805a..30f9734c36b 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -396,6 +396,74 @@ public:
   }
 };
 
+/* Implements vnsrl/vnsra.  */
+template
+class vnshift : public function_base
+{
+public:
+  rtx expand (function_expander &e) const override
+  {
+switch (e.op_info->op)
+  {
+  case OP_TYPE_wx:
+   return e.use_exact_insn (
+ code_for_pred_narrow_scalar (CODE, e.vector_mode ()));
+  case OP_TYPE_wv:
+   return e.use_exact_insn (code_for_pred_narrow (CODE, e.vector_mode ()));
+  default:
+   gcc_unreachable ();
+  }
+  }
+};
+
+/* Implements vncvt.  */
+class vncvt_x : public function_base
+{
+public:
+  rtx expand (function_expander &e) const override
+  {
+return e.use_e

[pushed] [PR103541] RA: Implement reuse of equivalent memory for caller saves optimization (version 2)

[Vladimir Makarov via Gcc-patches]

This is another try to solve

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103541

The patch was successfully bootstrapped (--enable-languages=all) and 
tested on x86, x86-64, aarch64
commit 1ad898d18904ac68432ba9b8ffa2b083d007cc2d
Author: Vladimir N. Makarov 
Date:   Thu Feb 9 15:18:48 2023 -0500

RA: Implement reuse of equivalent memory for caller saves optimization (2nd version)

The test pr103541.c shows opportunity to reuse memory with constant address for
caller saves optimization for constant or pure function call.  The patch
implements the memory reuse.

PR rtl-optimization/103541
PR rtl-optimization/108711

gcc/ChangeLog:

* ira.h (struct ira_reg_equiv_s): Add new field caller_save_p.
* ira.cc (validate_equiv_mem): Check memref address variance.
(no_equiv): Clear caller_save_p flag.
(update_equiv_regs): Define caller save equivalence for
valid_combine.
(setup_reg_equiv): Clear defined_p flag for caller save equivalence.
* lra-constraints.cc (lra_copy_reg_equiv): Add new arg
call_save_p.  Use caller save equivalence depending on the arg.
(split_reg): Adjust the call.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr103541.c: New.
* g++.target/i386/pr108711.C: New.

diff --git a/gcc/ira.cc b/gcc/ira.cc
index 66df03e8a59..6143db06c52 100644
--- a/gcc/ira.cc
+++ b/gcc/ira.cc
@@ -3070,6 +3070,8 @@ validate_equiv_mem_from_store (rtx dest, const_rtx set ATTRIBUTE_UNUSED,
 info->equiv_mem_modified = true;
 }
 
+static int equiv_init_varies_p (rtx x);
+
 enum valid_equiv { valid_none, valid_combine, valid_reload };
 
 /* Verify that no store between START and the death of REG invalidates
@@ -3113,7 +3115,8 @@ validate_equiv_mem (rtx_insn *start, rtx reg, rtx memref)
 	 been changed and all hell breaks loose.  */
 	  ret = valid_combine;
 	  if (!MEM_READONLY_P (memref)
-	  && !RTL_CONST_OR_PURE_CALL_P (insn))
+	  && (!RTL_CONST_OR_PURE_CALL_P (insn)
+		  || equiv_init_varies_p (XEXP (memref, 0
 	return valid_none;
 	}
 
@@ -3414,6 +3417,7 @@ no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED,
   if (reg_equiv[regno].is_arg_equivalence)
 return;
   ira_reg_equiv[regno].defined_p = false;
+  ira_reg_equiv[regno].caller_save_p = false;
   ira_reg_equiv[regno].init_insns = NULL;
   for (; list; list = list->next ())
 {
@@ -3766,7 +3770,18 @@ update_equiv_regs (void)
 		{
 		  replacement = copy_rtx (SET_SRC (set));
 		  if (validity == valid_reload)
-		note = set_unique_reg_note (insn, REG_EQUIV, replacement);
+		{
+		  note = set_unique_reg_note (insn, REG_EQUIV, replacement);
+		}
+		  else
+		{
+		  /* We still can use this equivalence for caller save
+			 optimization in LRA.  Mark this.  */
+		  ira_reg_equiv[regno].caller_save_p = true;
+		  ira_reg_equiv[regno].init_insns
+			= gen_rtx_INSN_LIST (VOIDmode, insn,
+	 ira_reg_equiv[regno].init_insns);
+		}
 		}
 	}
 
@@ -4156,7 +4171,7 @@ setup_reg_equiv (void)
 		   legitimate, we ignore such REG_EQUIV notes.  */
 		if (memory_operand (x, VOIDmode))
 		  {
-		ira_reg_equiv[i].defined_p = true;
+		ira_reg_equiv[i].defined_p = !ira_reg_equiv[i].caller_save_p;
 		ira_reg_equiv[i].memory = x;
 		continue;
 		  }
diff --git a/gcc/ira.h b/gcc/ira.h
index 58b50dbe8a2..3d35025a46e 100644
--- a/gcc/ira.h
+++ b/gcc/ira.h
@@ -175,8 +175,11 @@ extern struct target_ira *this_target_ira;
 /* Major structure describing equivalence info for a pseudo.  */
 struct ira_reg_equiv_s
 {
-  /* True if we can use this equivalence.  */
+  /* True if we can use this as a general equivalence.  */
   bool defined_p;
+  /* True if we can use this equivalence only for caller save/restore
+ location.  */
+  bool caller_save_p;
   /* True if the usage of the equivalence is profitable.  */
   bool profitable_p;
   /* Equiv. memory, constant, invariant, and initializing insns of
diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index 7bffbc07ee2..dd4f68bbfc0 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -5771,14 +5771,17 @@ choose_split_class (enum reg_class allocno_class,
   return best_cl;
 }
 
-/* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.
-   It only makes sense to call this function if NEW_REGNO is always
-   equal to ORIGINAL_REGNO.  */
+/* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO.  It only
+   makes sense to call this function if NEW_REGNO is always equal to
+   ORIGINAL_REGNO.  Set up defined_p flag when caller_save_p flag is set up and
+   CALL_SAVE_P is true.  */
 
 static void
-lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno)
+lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno,
+		bool call_save_p)
 {
-  if (!ira_reg_equiv[original_regno].defined_p)
+

[PATCH] RISC-V: Add vncvt C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vncvt_x-1.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x-2.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x-3.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_m-1.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_m-2.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_m-3.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vncvt_x-1.c | 201 ++
 .../gcc.target/riscv/rvv/base/vncvt_x-2.c | 201 ++
 .../gcc.target/riscv/rvv/base/vncvt_x-3.c | 201 ++
 .../gcc.target/riscv/rvv/base/vncvt_x_m-1.c   | 201 ++
 .../gcc.target/riscv/rvv/base/vncvt_x_m-2.c   | 201 ++
 .../gcc.target/riscv/rvv/base/vncvt_x_m-3.c   | 201 ++
 .../gcc.target/riscv/rvv/base/vncvt_x_mu-1.c  | 201 ++
 .../gcc.target/riscv/rvv/base/vncvt_x_mu-2.c  | 201 ++
 .../gcc.target/riscv/rvv/base/vncvt_x_mu-3.c  | 201 ++
 .../gcc.target/riscv/rvv/base/vncvt_x_tu-1.c  | 201 ++
 .../gcc.target/riscv/rvv/base/vncvt_x_tu-2.c  | 201 ++
 .../gcc.target/riscv/rvv/base/vncvt_x_tu-3.c  | 201 ++
 .../gcc.target/riscv/rvv/base/vncvt_x_tum-1.c | 201 ++
 .../gcc.target/riscv/rvv/base/vncvt_x_tum-2.c | 201 ++
 .../gcc.target/riscv/rvv/base/vncvt_x_tum-3.c | 201 ++
 .../riscv/rvv/base/vncvt_x_tumu-1.c   | 201 ++
 .../riscv/rvv/base/vncvt_x_tumu-2.c   | 201 ++
 .../riscv/rvv/base/vncvt_x_tumu-3.c   | 201 ++
 18 files changed, 3618 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-1.c
new file mode 100644
index 000..ac570138785
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-1.c
@@ -0,0 +1,201 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vncvt_x_x_w_i8mf8(vint16mf4_t src,size_t vl)
+{
+return __riscv_vncvt_x_x_w_i8mf8(src,vl);
+}
+
+
+vint8mf4_t test___riscv_vncvt_x_x_w_i8mf4(vint16mf2_t src,size_t vl)
+{
+return __riscv_vncvt_x_x_w_i8mf4(src,vl);
+}
+
+
+vint8mf2_t test___riscv_vncvt_x_x_w_i8mf2(vint16m1_t src,size_t vl)
+{
+return __riscv_vncvt_x_x_w_i8mf2(src,vl);
+}
+
+
+vint8m1_t test___riscv_vncvt_x_x_w_i8m1(vint16m2_t src,size_t vl)
+{
+return __riscv_vncvt_x_x_w_i8m1(src,vl);
+}
+
+
+vint8m2_t test___riscv_vncvt_x_x_w_i8m2(vint16m4_t src,size_t vl)
+{
+return __riscv_vncvt_x_x_w_i8m2(src,vl);
+}
+
+
+vint8m4_t test___riscv_vncvt_x_x_w_i8m4(vint16m8_t src,size_t vl)
+{
+return __riscv_vncvt_x_x_w_i8m4(src,

[PATCH] RISC-V: Add vmv C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vmv_v_v-1.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_v-2.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_v-3.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vmv_v_v-1.c | 276 ++
 .../gcc.target/riscv/rvv/base/vmv_v_v-2.c | 276 ++
 .../gcc.target/riscv/rvv/base/vmv_v_v-3.c | 276 ++
 .../gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c  | 276 ++
 .../gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c  | 276 ++
 .../gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c  | 276 ++
 6 files changed, 1656 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-1.c
new file mode 100644
index 000..c485b1df458
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-1.c
@@ -0,0 +1,276 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmv_v_v_i8mf8(vint8mf8_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i8mf8(src,vl);
+}
+
+
+vint8mf4_t test___riscv_vmv_v_v_i8mf4(vint8mf4_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i8mf4(src,vl);
+}
+
+
+vint8mf2_t test___riscv_vmv_v_v_i8mf2(vint8mf2_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i8mf2(src,vl);
+}
+
+
+vint8m1_t test___riscv_vmv_v_v_i8m1(vint8m1_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i8m1(src,vl);
+}
+
+
+vint8m2_t test___riscv_vmv_v_v_i8m2(vint8m2_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i8m2(src,vl);
+}
+
+
+vint8m4_t test___riscv_vmv_v_v_i8m4(vint8m4_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i8m4(src,vl);
+}
+
+
+vint8m8_t test___riscv_vmv_v_v_i8m8(vint8m8_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i8m8(src,vl);
+}
+
+
+vint16mf4_t test___riscv_vmv_v_v_i16mf4(vint16mf4_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i16mf4(src,vl);
+}
+
+
+vint16mf2_t test___riscv_vmv_v_v_i16mf2(vint16mf2_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i16mf2(src,vl);
+}
+
+
+vint16m1_t test___riscv_vmv_v_v_i16m1(vint16m1_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i16m1(src,vl);
+}
+
+
+vint16m2_t test___riscv_vmv_v_v_i16m2(vint16m2_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i16m2(src,vl);
+}
+
+
+vint16m4_t test___riscv_vmv_v_v_i16m4(vint16m4_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i16m4(src,vl);
+}
+
+
+vint16m8_t test___riscv_vmv_v_v_i16m8(vint16m8_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i16m8(src,vl);
+}
+
+
+vint32mf2_t test___riscv_vmv_v_v_i32mf2(vint32mf2_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i32mf2(src,vl);
+}
+
+
+vint32m1_t test___riscv_vmv_v_v_i32m1(vint32m1_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i32m1(src,vl);
+}
+
+
+vint32m2_t test___riscv_vmv_v_v_i32m2(vint32m2_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i32m2(src,vl);
+}
+
+
+vint32m4_t test___riscv_vmv_v_v_i32m4(vint32m4_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i32m4(src,vl);
+}
+
+
+vint32m8_t test___riscv_vmv_v_v_i32m8(vint32m8_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i32m8(src,vl);
+}
+
+
+vint64m1_t test___riscv_vmv_v_v_i64m1(vint64m1_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i64m1(src,vl);
+}
+
+
+vint64m2_t test___riscv_vmv_v_v_i64m2(vint64m2_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i64m2(src,vl);
+}
+
+
+vint64m4_t test___riscv_vmv_v_v_i64m4(vint64m4_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i64m4(src,vl);
+}
+
+
+vint64m8_t test___riscv_vmv_v_v_i64m8(vint64m8_t src,size_t vl)
+{
+return __riscv_vmv_v_v_i64m8(src,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmv_v_v_u8mf8(vuint8mf8_t src,size_t vl)
+{
+return __riscv_vmv_v_v_u8mf8(src,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmv_v_v_u8mf4(vuint8mf4_t src,size_t vl)
+{
+return __riscv_vmv_v_v_u8mf4(src,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmv_v_v_u8mf2(vuint8mf2_t src,size_t vl)
+{
+return __riscv_vmv_v_v_u8mf2(src,vl);
+}
+
+
+vuint8m1_t test___riscv_vmv_v_v_u8m1(vuint8m1_t src,size_t vl)
+{
+return __riscv_vmv_v_v_u8m1(src,vl);
+}
+
+
+vuint8m2_t test___riscv_vmv_v_v_u8m2(vuint8m2_t src,size_t vl)
+{
+return __riscv_vmv_v_v_u8m2(src,vl);
+}
+
+
+vuint8m4_t test___riscv_vmv_v_v_u8m4(vuint8m4_t src,size_t vl)
+{
+re

[PATCH] RISC-V: Add vmv.v.x C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-3.c: New test.

---
 .../riscv/rvv/base/vmv_v_x_rv32-1.c   | 289 +
 .../riscv/rvv/base/vmv_v_x_rv32-2.c   | 289 +
 .../riscv/rvv/base/vmv_v_x_rv32-3.c   | 289 +
 .../riscv/rvv/base/vmv_v_x_rv64-1.c   | 292 ++
 .../riscv/rvv/base/vmv_v_x_rv64-2.c   | 292 ++
 .../riscv/rvv/base/vmv_v_x_rv64-3.c   | 292 ++
 .../riscv/rvv/base/vmv_v_x_tu_rv32-1.c| 289 +
 .../riscv/rvv/base/vmv_v_x_tu_rv32-2.c| 289 +
 .../riscv/rvv/base/vmv_v_x_tu_rv32-3.c| 289 +
 .../riscv/rvv/base/vmv_v_x_tu_rv64-1.c| 292 ++
 .../riscv/rvv/base/vmv_v_x_tu_rv64-2.c| 292 ++
 .../riscv/rvv/base/vmv_v_x_tu_rv64-3.c| 292 ++
 12 files changed, 3486 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c
new file mode 100644
index 000..96f490ee5d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmv_v_x_i8mf8(int8_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i8mf8(src,vl);
+}
+
+
+vint8mf4_t test___riscv_vmv_v_x_i8mf4(int8_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i8mf4(src,vl);
+}
+
+
+vint8mf2_t test___riscv_vmv_v_x_i8mf2(int8_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i8mf2(src,vl);
+}
+
+
+vint8m1_t test___riscv_vmv_v_x_i8m1(int8_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i8m1(src,vl);
+}
+
+
+vint8m2_t test___riscv_vmv_v_x_i8m2(int8_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i8m2(src,vl);
+}
+
+
+vint8m4_t test___riscv_vmv_v_x_i8m4(int8_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i8m4(src,vl);
+}
+
+
+vint8m8_t test___riscv_vmv_v_x_i8m8(int8_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i8m8(src,vl);
+}
+
+
+vint16mf4_t test___riscv_vmv_v_x_i16mf4(int16_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i16mf4(src,vl);
+}
+
+
+vint16mf2_t test___riscv_vmv_v_x_i16mf2(int16_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i16mf2(src,vl);
+}
+
+
+vint16m1_t test___riscv_vmv_v_x_i16m1(int16_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i16m1(src,vl);
+}
+
+
+vint16m2_t test___riscv_vmv_v_x_i16m2(int16_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i16m2(src,vl);
+}
+
+
+vint16m4_t test___riscv_vmv_v_x_i16m4(int16_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i16m4(src,vl);
+}
+
+
+vint16m8_t test___riscv_vmv_v_x_i16m8(int16_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i16m8(src,vl);
+}
+
+
+vint32mf2_t test___riscv_vmv_v_x_i32mf2(int32_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i32mf2(src,vl);
+}
+
+
+vint32m1_t test___riscv_vmv_v_x_i32m1(int32_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i32m1(src,vl);
+}
+
+
+vint32m2_t test___riscv_vmv_v_x_i32m2(int32_t src,size_t vl)
+{
+return __riscv_vmv_v_x_i32m2(src,vl);
+}
+
+
+vint32m4_t test___riscv_vmv_v_x_i32m4(int32_t src,size_t vl)

[pushed] analyzer: fix further overzealous state purging [PR108733]

[David Malcolm via Gcc-patches]

PR analyzer/108733 reports various false positives in qemu from
-Wanalyzer-use-of-uninitialized-value with __attribute__((cleanup))
at -O1 and above.

Root cause is that the state-purging code was failing to treat:
   _25 = MEM[(void * *)&val];
as a usage of "val", leading to it erroneously purging the
initialization of "val" along an execution path that didn't otherwise
use "val", apart from the  __attribute__((cleanup)).

Fixed thusly.

Integration testing on the patch show this change in the number of
diagnostics:
  -Wanalyzer-use-of-uninitialized-value
   coreutils-9.1: 18 -> 16 (-2)
  qemu-7.2.0: 87 -> 80 (-7)
where all that I investigated appear to have been false positives, hence
an improvement.

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu.
Pushed to trunk as r13-5762-g125b57aa674003.

gcc/analyzer/ChangeLog:
PR analyzer/108733
* state-purge.cc (get_candidate_for_purging): Add ADDR_EXPR
and MEM_REF.

gcc/testsuite/ChangeLog:
PR analyzer/108733
* gcc.dg/analyzer/torture/uninit-pr108733.c: New test.

Signed-off-by: David Malcolm 
---
 gcc/analyzer/state-purge.cc   |  2 +
 .../gcc.dg/analyzer/torture/uninit-pr108733.c | 65 +++
 2 files changed, 67 insertions(+)
 create mode 100644 gcc/testsuite/gcc.dg/analyzer/torture/uninit-pr108733.c

diff --git a/gcc/analyzer/state-purge.cc b/gcc/analyzer/state-purge.cc
index 5f2d1f7fefa..3a73146d928 100644
--- a/gcc/analyzer/state-purge.cc
+++ b/gcc/analyzer/state-purge.cc
@@ -63,6 +63,8 @@ get_candidate_for_purging (tree node)
   default:
return NULL_TREE;
 
+  case ADDR_EXPR:
+  case MEM_REF:
   case COMPONENT_REF:
iter = TREE_OPERAND (iter, 0);
continue;
diff --git a/gcc/testsuite/gcc.dg/analyzer/torture/uninit-pr108733.c 
b/gcc/testsuite/gcc.dg/analyzer/torture/uninit-pr108733.c
new file mode 100644
index 000..9e684bf4f09
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/analyzer/torture/uninit-pr108733.c
@@ -0,0 +1,65 @@
+#define NULL ((void*)0)
+
+typedef unsigned char __uint8_t;
+typedef __uint8_t uint8_t;
+typedef char gchar;
+typedef void* gpointer;
+
+extern void g_free(gpointer mem);
+extern gchar* g_strdup(const gchar* str) __attribute__((__malloc__));
+
+static inline void
+g_autoptr_cleanup_generic_gfree(void* p)
+{
+  void** pp = (void**)p;
+  g_free(*pp); /* { dg-bogus "use of uninitialized value" } */
+}
+
+typedef struct Object Object;
+
+void
+error_setg_internal(const char* fmt,
+   ...) __attribute__((__format__(gnu_printf, 1, 2)));
+void
+visit_type_str(const char* name, char** obj);
+typedef struct SpaprMachineState SpaprMachineState;
+
+extern uint8_t
+spapr_get_cap(SpaprMachineState* spapr, int cap);
+
+typedef struct SpaprCapPossible
+{
+  int num;
+  /* [...snip...] */
+  const char* vals[];
+} SpaprCapPossible;
+
+typedef struct SpaprCapabilityInfo
+{
+  const char* name;
+  /* [...snip...] */
+  int index;
+  /* [...snip...] */
+  SpaprCapPossible* possible;
+  /* [...snip...] */
+} SpaprCapabilityInfo;
+
+void
+spapr_cap_get_string(SpaprMachineState* spapr,
+const char* name,
+SpaprCapabilityInfo* cap)
+{
+  __attribute__((cleanup(g_autoptr_cleanup_generic_gfree))) char* val = NULL;
+  uint8_t value = spapr_get_cap(spapr, cap->index);
+
+  if (value >= cap->possible->num) {
+error_setg_internal("Invalid value (%d) for cap-%s",
+   value,
+   cap->name);
+return;
+  }
+
+  val = g_strdup(cap->possible->vals[value]);
+
+  visit_type_str(name, &val);
+}
-- 
2.26.3

Verification Needed

[Cash App via Gcc-patches]

Please verify your identity by visiting Cash Support using your Cash App

Re: [PATCH 2/2] c++: speculative constexpr and is_constant_evaluated [PR108243]

[Jason Merrill via Gcc-patches]

On 2/9/23 09:36, Patrick Palka wrote:

On Sun, 5 Feb 2023, Jason Merrill wrote:


On 2/3/23 15:51, Patrick Palka wrote:

On Mon, 30 Jan 2023, Jason Merrill wrote:


On 1/27/23 17:02, Patrick Palka wrote:

This PR illustrates that __builtin_is_constant_evaluated currently acts
as an optimization barrier for our speculative constexpr evaluation,
since we don't want to prematurely fold the builtin to false if the
expression in question would be later manifestly constant evaluated (in
which case it must be folded to true).

This patch fixes this by permitting __builtin_is_constant_evaluated
to get folded as false during cp_fold_function, since at that point
we're sure we're doing manifestly constant evaluation.  To that end
we add a flags parameter to cp_fold that controls what mce_value the
CALL_EXPR case passes to maybe_constant_value.

bootstrapped and rgetsted no x86_64-pc-linux-gnu, does this look OK for
trunk?

PR c++/108243

gcc/cp/ChangeLog:

* cp-gimplify.cc (enum fold_flags): Define.
(cp_fold_data::genericize): Replace this data member with ...
(cp_fold_data::fold_flags): ... this.
(cp_fold_r): Adjust cp_fold_data use and cp_fold_calls.
(cp_fold_function): Likewise.
(cp_fold_maybe_rvalue): Likewise.
(cp_fully_fold_init): Likewise.
(cp_fold): Add fold_flags parameter.  Don't cache if flags
isn't empty.
: Pass mce_false to maybe_constant_value
if if ff_genericize is set.

gcc/testsuite/ChangeLog:

* g++.dg/opt/pr108243.C: New test.
---
gcc/cp/cp-gimplify.cc   | 76
++---
gcc/testsuite/g++.dg/opt/pr108243.C | 29 +++
2 files changed, 76 insertions(+), 29 deletions(-)
create mode 100644 gcc/testsuite/g++.dg/opt/pr108243.C

diff --git a/gcc/cp/cp-gimplify.cc b/gcc/cp/cp-gimplify.cc
index a35cedd05cc..d023a63768f 100644
--- a/gcc/cp/cp-gimplify.cc
+++ b/gcc/cp/cp-gimplify.cc
@@ -43,12 +43,20 @@ along with GCC; see the file COPYING3.  If not see
#include "omp-general.h"
#include "opts.h"
+/* Flags for cp_fold and cp_fold_r.  */
+
+enum fold_flags {
+  ff_none = 0,
+  /* Whether we're being called from cp_fold_function.  */
+  ff_genericize = 1 << 0,
+};
+
/* Forward declarations.  */
  static tree cp_genericize_r (tree *, int *, void *);
static tree cp_fold_r (tree *, int *, void *);
static void cp_genericize_tree (tree*, bool);
-static tree cp_fold (tree);
+static tree cp_fold (tree, fold_flags);
  /* Genericize a TRY_BLOCK.  */
@@ -996,9 +1004,8 @@ struct cp_genericize_data
struct cp_fold_data
{
  hash_set pset;
-  bool genericize; // called from cp_fold_function?
-
-  cp_fold_data (bool g): genericize (g) {}
+  fold_flags flags;
+  cp_fold_data (fold_flags flags): flags (flags) {}
};
  static tree
@@ -1039,7 +1046,7 @@ cp_fold_r (tree *stmt_p, int *walk_subtrees, void
*data_)
  break;
}
-  *stmt_p = stmt = cp_fold (*stmt_p);
+  *stmt_p = stmt = cp_fold (*stmt_p, data->flags);
if (data->pset.add (stmt))
{
@@ -1119,12 +1126,12 @@ cp_fold_r (tree *stmt_p, int *walk_subtrees,
void
*data_)
 here rather than in cp_genericize to avoid problems with the
invisible
 reference transition.  */
case INIT_EXPR:
-  if (data->genericize)
+  if (data->flags & ff_genericize)
cp_genericize_init_expr (stmt_p);
  break;
  case TARGET_EXPR:
-  if (data->genericize)
+  if (data->flags & ff_genericize)
cp_genericize_target_expr (stmt_p);
/* Folding might replace e.g. a COND_EXPR with a TARGET_EXPR;
in
@@ -1157,7 +1164,7 @@ cp_fold_r (tree *stmt_p, int *walk_subtrees, void
*data_)
void
cp_fold_function (tree fndecl)
{
-  cp_fold_data data (/*genericize*/true);
+  cp_fold_data data (ff_genericize);
  cp_walk_tree (&DECL_SAVED_TREE (fndecl), cp_fold_r, &data, NULL);
}
@@ -2375,7 +2382,7 @@ cp_fold_maybe_rvalue (tree x, bool rval)
{
  while (true)
{
-  x = cp_fold (x);
+  x = cp_fold (x, ff_none);
  if (rval)
x = mark_rvalue_use (x);
  if (rval && DECL_P (x)
@@ -2434,7 +2441,7 @@ cp_fully_fold_init (tree x)
  if (processing_template_decl)
return x;
  x = cp_fully_fold (x);
-  cp_fold_data data (/*genericize*/false);
+  cp_fold_data data (ff_none);
  cp_walk_tree (&x, cp_fold_r, &data, NULL);
  return x;
}
@@ -2469,7 +2476,7 @@ clear_fold_cache (void)
Function returns X or its folded variant.  */
  static tree
-cp_fold (tree x)
+cp_fold (tree x, fold_flags flags)
{
  tree op0, op1, op2, op3;
  tree org_x = x, r = NULL_TREE;
@@ -2490,8 +2497,11 @@ cp_fold (tree x)
  if (fold_cache == NULL)
fold_cache = hash_map::create_ggc (101);
-  if (tree *cached = fold_cache->get (x))
-return *cached;
+  bool cache_p = (flags == ff_none);
+
+  if (cache_p)
+if (tree *c

Re: [PATCH v2] c++: ICE initing lifetime-extended constexpr var [PR107079]

[Jason Merrill via Gcc-patches]

On 2/8/23 18:15, Marek Polacek wrote:

On Wed, Feb 08, 2023 at 04:00:25PM -0800, Jason Merrill wrote:

On 2/8/23 13:01, Marek Polacek wrote:

(This may not be a complete fix but I got stuck so I'm posting what
I have, which at least fixes the ICE.)

We ICE on the simple:

struct X { const X* x = this; };
constexpr const X& x = X{};

where store_init_value initializes 'x' with

&TARGET_EXPR }>

but we must lifetime-extend via extend_ref_init_temps and we get

_ZGR1x_.x = (const struct X *) & >>>;, (const struct X 
&) &_ZGR1x_;

Since 'x' was declared constexpr, we do cxx_constant_init and we hit
the preeval code added in r269003 while evaluating the INIT_EXPR:

_ZGR1x_.x = (const struct X *) & >>>

but we have no ctx.ctor or ctx.object here so lookup_placeholder won't
find anything that could replace X and we ICE on
   7861   /* A placeholder without a referent.  We can get here when
   7862  checking whether NSDMIs are noexcept, or in massage_init_elt;
   7863  just say it's non-constant for now.  */
   7864   gcc_assert (ctx->quiet);
because cxx_constant_init means !ctx->quiet.  It's not correct that
there isn't a referent.  I think the following patch is a pretty
straightforward fix: pass the _ZGR var down to maybe_constant_init so
that it can replace the PLACEHOLDER_EXPR with _ZGR1x_.

What I wasn't able to make work is the commented assert in the test.
It doesn't pass because we complain that _ZGR1x_ isn't a constexpr
variable,


That sounds like we aren't (correctly) implementing

  https://eel.is/c++draft/expr.const#4.7


Ah yes, this is DR2126 = c++/101588.  I wonder if the fix will include
checking startswith (IDENTIFIER_POINTER (DECL_NAME (variable)), "_ZGR")
to see if its lifetime is extended.
  

but making it so would just result in "used in its own
initializer" (which is true).


True, but not in the sense it means; its initializer doesn't depend on its
(uninitialized) value.


...because we're only interested in its address.


diff --git a/gcc/cp/call.cc b/gcc/cp/call.cc
index f7c5d9da94b..a0afab9b26a 100644
--- a/gcc/cp/call.cc
+++ b/gcc/cp/call.cc
@@ -13583,7 +13583,7 @@ set_up_extended_ref_temp (tree decl, tree expr, vec **cleanups,
 /* If the initializer is constant, put it in DECL_INITIAL so we get
static initialization and use in constant expressions.  */
-  init = maybe_constant_init (expr);
+  init = maybe_constant_init (expr, var);


We should also pass true for manifestly_const_eval as in store_init_value.


Done.

Bootstrapped/regtested on x86_64-pc-linux-gnu, ok for trunk?


OK.


-- >8 --
We ICE on the simple:

   struct X { const X* x = this; };
   constexpr const X& x = X{};

where store_init_value initializes 'x' with

   &TARGET_EXPR }>

but we must lifetime-extend via extend_ref_init_temps and we get

   _ZGR1x_.x = (const struct X *) & >>>;, (const struct X 
&) &_ZGR1x_;

Since 'x' was declared constexpr, we do cxx_constant_init and we hit
the preeval code added in r269003 while evaluating the INIT_EXPR:

   _ZGR1x_.x = (const struct X *) & >>>

but we have no ctx.ctor or ctx.object here so lookup_placeholder won't
find anything that could replace X and we ICE on
  7861   /* A placeholder without a referent.  We can get here when
  7862  checking whether NSDMIs are noexcept, or in massage_init_elt;
  7863  just say it's non-constant for now.  */
  7864   gcc_assert (ctx->quiet);
because cxx_constant_init means !ctx->quiet.  It's not correct that
there isn't a referent.  I think the following patch is a pretty
straightforward fix: pass the _ZGR var down to maybe_constant_init so
that it can replace the PLACEHOLDER_EXPR with _ZGR1x_.

The commented assert in the test doesn't pass: we complain that _ZGR1x_
isn't a constexpr variable because we don't implement DR2126 (PR101588).

PR c++/107079

gcc/cp/ChangeLog:

* call.cc (set_up_extended_ref_temp): Pass var to maybe_constant_init.

gcc/testsuite/ChangeLog:

* g++.dg/cpp0x/constexpr-nsdmi2.C: New test.
---
  gcc/cp/call.cc| 2 +-
  gcc/testsuite/g++.dg/cpp0x/constexpr-nsdmi2.C | 9 +
  2 files changed, 10 insertions(+), 1 deletion(-)
  create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-nsdmi2.C

diff --git a/gcc/cp/call.cc b/gcc/cp/call.cc
index f7c5d9da94b..a349d8e79db 100644
--- a/gcc/cp/call.cc
+++ b/gcc/cp/call.cc
@@ -13583,7 +13583,7 @@ set_up_extended_ref_temp (tree decl, tree expr, vec **cleanups,
  
/* If the initializer is constant, put it in DECL_INITIAL so we get

   static initialization and use in constant expressions.  */
-  init = maybe_constant_init (expr);
+  init = maybe_constant_init (expr, var, /*manifestly_const_eval=*/true);
/* As in store_init_value.  */
init = cp_fully_fold (init);
if (TREE_CONSTANT (init))
diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-nsdmi2.C 
b/gcc/testsuite/g++.dg/cpp0x/constexpr-nsdmi2.C
new file mode 100644
inde

[PATCH] PR tree-optimization/108520 - Add function context for querying global ranges.

[Andrew MacLeod via Gcc-patches]

I was about to ping on this, and then found it in my drafts.. Doh!


get_range_global() can invoke tree.cc::nonnull_arg_p() if the item being 
queried is a pointer and a parameter.  This routine assumes the context 
is CFUN, and this is not always true.


This patch simply adds a function context to the get_range_global query, 
and defaults it to cfun. If the context passed in is anything different 
than cfun, then it simply chooses not to invoke nonnull_arg_p().


The check_assume function now directly calls gimple_range_global with 
the correct function context instead of indirectly calling it through 
the global_range_query->range_of_expr () method. Thats all it should 
have been doing in the first place really since its always an ssa name.


Bootstraps on x86_64-pc-linux-gnu with no regressions.  OK for trunk?

Andrew


From e64f04f15a47ef91a21668318728a49a90e8dae1 Mon Sep 17 00:00:00 2001
From: Andrew MacLeod 
Date: Mon, 6 Feb 2023 13:07:01 -0500
Subject: [PATCH] Add function context for querying global ranges.

When processing arguments for assume functions, call get_global_range
directly and utilize a function context pointer to avoid any assumptions
about using cfun.

	PR tree-optimization/108520
	gcc/
	* gimple-range-infer.cc (check_assume_func): Invoke
	gimple_range_global directly instead using global_range_query.
	* value-query.cc (get_range_global): Add function context and
	avoid calling nonnull_arg_p if not cfun.
	(gimple_range_global): Add function context pointer.
	* value-query.h (imple_range_global): Add function context.

	gcc/testsuite/
	* g++.dg/pr108520.C: New.
---
 gcc/gimple-range-infer.cc   |  2 +-
 gcc/testsuite/g++.dg/pr108520.C | 17 +
 gcc/value-query.cc  | 10 +-
 gcc/value-query.h   |  4 +++-
 4 files changed, 26 insertions(+), 7 deletions(-)
 create mode 100644 gcc/testsuite/g++.dg/pr108520.C

diff --git a/gcc/gimple-range-infer.cc b/gcc/gimple-range-infer.cc
index 4677ae21ccc..c765e072731 100644
--- a/gcc/gimple-range-infer.cc
+++ b/gcc/gimple-range-infer.cc
@@ -84,7 +84,7 @@ gimple_infer_range::check_assume_func (gcall *call)
 	continue;
 	  // Query the global range of the default def in the assume function.
 	  Value_Range assume_range (type);
-	  global_ranges.range_of_expr (assume_range, default_def);
+	  gimple_range_global (assume_range, default_def, fun);
 	  // If there is a non-varying result, add it as an inferred range.
 	  if (!assume_range.varying_p ())
 	{
diff --git a/gcc/testsuite/g++.dg/pr108520.C b/gcc/testsuite/g++.dg/pr108520.C
new file mode 100644
index 000..6cd677a852d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/pr108520.C
@@ -0,0 +1,17 @@
+// { dg-do compile { target c++23 } }
+// { dg-options "-O2" }
+
+static void foo () {}
+struct S { void (*f) (); };
+
+[[gnu::nonnull (1)]]
+void
+bar (void *x)
+{
+  struct S a[3] = { { foo }, { foo }, { foo } };
+  for (struct S *i = a, *e = a + 3; i != e; i++)
+{
+  [[assume (i->f)]];
+  i->f ();
+}
+}
diff --git a/gcc/value-query.cc b/gcc/value-query.cc
index 5345bb47718..f936e878080 100644
--- a/gcc/value-query.cc
+++ b/gcc/value-query.cc
@@ -312,7 +312,7 @@ get_ssa_name_ptr_info_nonnull (const_tree name)
 // return VARYING.
 
 static void
-get_range_global (vrange &r, tree name)
+get_range_global (vrange &r, tree name, struct function *fun = cfun)
 {
   tree type = TREE_TYPE (name);
 
@@ -327,7 +327,7 @@ get_range_global (vrange &r, tree name)
 	  // anti-ranges for pointers.  Note that this is only valid with
 	  // default definitions of PARM_DECLs.
 	  if (POINTER_TYPE_P (type)
-	  && ((cfun && nonnull_arg_p (sym))
+	  && ((cfun && fun == cfun && nonnull_arg_p (sym))
 		  || get_ssa_name_ptr_info_nonnull (name)))
 	r.set_nonzero (type);
 	  else if (!POINTER_TYPE_P (type))
@@ -378,15 +378,15 @@ get_range_global (vrange &r, tree name)
 // https://gcc.gnu.org/pipermail/gcc-patches/2021-June/571709.html
 
 void
-gimple_range_global (vrange &r, tree name)
+gimple_range_global (vrange &r, tree name, struct function *fun)
 {
   tree type = TREE_TYPE (name);
   gcc_checking_assert (TREE_CODE (name) == SSA_NAME);
 
-  if (SSA_NAME_IS_DEFAULT_DEF (name) || (cfun && cfun->after_inlining)
+  if (SSA_NAME_IS_DEFAULT_DEF (name) || (fun && fun->after_inlining)
   || is_a (SSA_NAME_DEF_STMT (name)))
 {
-  get_range_global (r, name);
+  get_range_global (r, name, fun);
   return;
 }
   r.set_varying (type);
diff --git a/gcc/value-query.h b/gcc/value-query.h
index 03be0be9178..63878968118 100644
--- a/gcc/value-query.h
+++ b/gcc/value-query.h
@@ -143,6 +143,8 @@ get_range_query (const struct function *fun)
   return fun->x_range_query ? fun->x_range_query : &global_ranges;
 }
 
-extern void gimple_range_global (vrange &v, tree name);
+// Query the global range of NAME in function F.  Default to cfun.
+extern void gimple_range_global (vrange &v, tree name,
+ struct function *f = cfun);
 
 #endif // GCC_Q

[committed] c: Allow conversions of null pointer constants to nullptr_t

[Joseph Myers]

WG14 has agreed to allow conversions (explicit and implicit) from null
pointer constants to nullptr_t; update GCC's nullptr_t implementation
to match.

Bootstrapped with no regressions for x86_64-pc-linux-gnu.

gcc/c/
* c-convert.cc (c_convert): Allow conversion of a null pointer
constant to nullptr_t.
* c-typeck.cc (null_pointer_constant_p): Remove static.
(convert_for_assignment): Allow conversion of a null pointer
constant to nullptr_t.
(digest_init): Handle NULLPTR_TYPE among scalar conversions.
* c-tree.h (null_pointer_constant_p): Declare.

gcc/testsuite/
* gcc.dg/c2x-nullptr-1.c: Test conversion of null pointer
constants to nullptr_t.
* gcc.dg/c2x-nullptr-3.c: Do not expect errors for conversion of
null pointer constants to nullptr_t.  Do test errors for
conversion of other values to nullptr_t and for unary '+' on
nullptr_t.

diff --git a/gcc/c/c-convert.cc b/gcc/c/c-convert.cc
index dccd245dfc3..0f35dc4fe9a 100644
--- a/gcc/c/c-convert.cc
+++ b/gcc/c/c-convert.cc
@@ -157,6 +157,19 @@ c_convert (tree type, tree expr, bool init_const)
   ret = convert_to_pointer (type, e);
   goto maybe_fold;
 
+case NULLPTR_TYPE:
+  /* A null pointer constant or value of type nullptr_t may be
+converted to nullptr_t.  The latter case has already been
+handled.  build_c_cast will create an additional NOP_EXPR to
+ensure the result of the conversion is not itself a null
+pointer constant.  */
+  if (null_pointer_constant_p (expr))
+   {
+ ret = build_int_cst (type, 0);
+ goto maybe_fold;
+   }
+  break;
+
 case REAL_TYPE:
   ret = convert_to_real (type, e);
   goto maybe_fold;
@@ -201,12 +214,14 @@ c_convert (tree type, tree expr, bool init_const)
 }
 
   /* If we are converting to nullptr_t, don't say "non-scalar type" because
- the nullptr_t type is a scalar type.  Only nullptr_t shall be converted
- to nullptr_t.  */
+ the nullptr_t type is a scalar type.  Only nullptr_t or a null pointer
+ constant shall be converted to nullptr_t.  */
   if (code == NULLPTR_TYPE)
 {
   error ("conversion from %qT to %qT", TREE_TYPE (e), type);
-  inform (input_location, "only %qT can be converted to %qT", type, type);
+  inform (input_location,
+ "only %qT or a null pointer constant can be converted to %qT",
+ type, type);
 }
   else
 error ("conversion to non-scalar type requested");
diff --git a/gcc/c/c-tree.h b/gcc/c/c-tree.h
index 00ccf87e6e6..e5eefe6bbba 100644
--- a/gcc/c/c-tree.h
+++ b/gcc/c/c-tree.h
@@ -728,6 +728,7 @@ extern location_t c_last_sizeof_loc;
 
 extern struct c_switch *c_switch_stack;
 
+extern bool null_pointer_constant_p (const_tree);
 extern bool char_type_p (tree);
 extern tree c_objc_common_truthvalue_conversion (location_t, tree);
 extern tree require_complete_type (location_t, tree);
diff --git a/gcc/c/c-typeck.cc b/gcc/c/c-typeck.cc
index 157b77eda95..e37b0973cd6 100644
--- a/gcc/c/c-typeck.cc
+++ b/gcc/c/c-typeck.cc
@@ -89,7 +89,6 @@ static bool require_constant_value;
 static bool require_constant_elements;
 static bool require_constexpr_value;
 
-static bool null_pointer_constant_p (const_tree);
 static tree qualify_type (tree, tree);
 static int tagged_types_tu_compatible_p (const_tree, const_tree, bool *,
 bool *);
@@ -130,7 +129,7 @@ static int comptypes_internal (const_tree, const_tree, bool 
*, bool *);
 
 /* Return true if EXP is a null pointer constant, false otherwise.  */
 
-static bool
+bool
 null_pointer_constant_p (const_tree expr)
 {
   /* This should really operate on c_expr structures, but they aren't
@@ -7837,6 +7836,8 @@ convert_for_assignment (location_t location, location_t 
expr_loc, tree type,
   in_late_binary_op = save;
   return ret;
 }
+  else if (codel == NULLPTR_TYPE && null_pointer_constant)
+return convert (type, rhs);
 
   switch (errtype)
 {
@@ -8596,7 +8597,7 @@ digest_init (location_t init_loc, tree type, tree init, 
tree origtype,
 
   if (code == INTEGER_TYPE || code == REAL_TYPE || code == FIXED_POINT_TYPE
   || code == POINTER_TYPE || code == ENUMERAL_TYPE || code == BOOLEAN_TYPE
-  || code == COMPLEX_TYPE || code == VECTOR_TYPE)
+  || code == COMPLEX_TYPE || code == VECTOR_TYPE || code == NULLPTR_TYPE)
 {
   tree unconverted_init = inside_init;
   if (TREE_CODE (TREE_TYPE (init)) == ARRAY_TYPE
diff --git a/gcc/testsuite/gcc.dg/c2x-nullptr-1.c 
b/gcc/testsuite/gcc.dg/c2x-nullptr-1.c
index 04f9901bb12..4e440234d52 100644
--- a/gcc/testsuite/gcc.dg/c2x-nullptr-1.c
+++ b/gcc/testsuite/gcc.dg/c2x-nullptr-1.c
@@ -11,8 +11,9 @@ void f2 (int *) { }
 void f3 (_Bool) { }
 nullptr_t cmp (void) { return nullptr; }
 
-/* The type nullptr_t shall not be converted to any type other than void, bool 
or
-   a pointer type.  No type othe

Re: [PATCH 2/2] c++: speculative constexpr and is_constant_evaluated [PR108243]

[Patrick Palka via Gcc-patches]

On Thu, 9 Feb 2023, Jason Merrill wrote:

> On 2/9/23 09:36, Patrick Palka wrote:
> > On Sun, 5 Feb 2023, Jason Merrill wrote:
> > 
> > > On 2/3/23 15:51, Patrick Palka wrote:
> > > > On Mon, 30 Jan 2023, Jason Merrill wrote:
> > > > 
> > > > > On 1/27/23 17:02, Patrick Palka wrote:
> > > > > > This PR illustrates that __builtin_is_constant_evaluated currently
> > > > > > acts
> > > > > > as an optimization barrier for our speculative constexpr evaluation,
> > > > > > since we don't want to prematurely fold the builtin to false if the
> > > > > > expression in question would be later manifestly constant evaluated
> > > > > > (in
> > > > > > which case it must be folded to true).
> > > > > > 
> > > > > > This patch fixes this by permitting __builtin_is_constant_evaluated
> > > > > > to get folded as false during cp_fold_function, since at that point
> > > > > > we're sure we're doing manifestly constant evaluation.  To that end
> > > > > > we add a flags parameter to cp_fold that controls what mce_value the
> > > > > > CALL_EXPR case passes to maybe_constant_value.
> > > > > > 
> > > > > > bootstrapped and rgetsted no x86_64-pc-linux-gnu, does this look OK
> > > > > > for
> > > > > > trunk?
> > > > > > 
> > > > > > PR c++/108243
> > > > > > 
> > > > > > gcc/cp/ChangeLog:
> > > > > > 
> > > > > > * cp-gimplify.cc (enum fold_flags): Define.
> > > > > > (cp_fold_data::genericize): Replace this data member with ...
> > > > > > (cp_fold_data::fold_flags): ... this.
> > > > > > (cp_fold_r): Adjust cp_fold_data use and cp_fold_calls.
> > > > > > (cp_fold_function): Likewise.
> > > > > > (cp_fold_maybe_rvalue): Likewise.
> > > > > > (cp_fully_fold_init): Likewise.
> > > > > > (cp_fold): Add fold_flags parameter.  Don't cache if flags
> > > > > > isn't empty.
> > > > > > : Pass mce_false to maybe_constant_value
> > > > > > if if ff_genericize is set.
> > > > > > 
> > > > > > gcc/testsuite/ChangeLog:
> > > > > > 
> > > > > > * g++.dg/opt/pr108243.C: New test.
> > > > > > ---
> > > > > > gcc/cp/cp-gimplify.cc   | 76
> > > > > > ++---
> > > > > > gcc/testsuite/g++.dg/opt/pr108243.C | 29 +++
> > > > > > 2 files changed, 76 insertions(+), 29 deletions(-)
> > > > > > create mode 100644 gcc/testsuite/g++.dg/opt/pr108243.C
> > > > > > 
> > > > > > diff --git a/gcc/cp/cp-gimplify.cc b/gcc/cp/cp-gimplify.cc
> > > > > > index a35cedd05cc..d023a63768f 100644
> > > > > > --- a/gcc/cp/cp-gimplify.cc
> > > > > > +++ b/gcc/cp/cp-gimplify.cc
> > > > > > @@ -43,12 +43,20 @@ along with GCC; see the file COPYING3.  If not
> > > > > > see
> > > > > > #include "omp-general.h"
> > > > > > #include "opts.h"
> > > > > > +/* Flags for cp_fold and cp_fold_r.  */
> > > > > > +
> > > > > > +enum fold_flags {
> > > > > > +  ff_none = 0,
> > > > > > +  /* Whether we're being called from cp_fold_function.  */
> > > > > > +  ff_genericize = 1 << 0,
> > > > > > +};
> > > > > > +
> > > > > > /* Forward declarations.  */
> > > > > >   static tree cp_genericize_r (tree *, int *, void *);
> > > > > > static tree cp_fold_r (tree *, int *, void *);
> > > > > > static void cp_genericize_tree (tree*, bool);
> > > > > > -static tree cp_fold (tree);
> > > > > > +static tree cp_fold (tree, fold_flags);
> > > > > >   /* Genericize a TRY_BLOCK.  */
> > > > > > @@ -996,9 +1004,8 @@ struct cp_genericize_data
> > > > > > struct cp_fold_data
> > > > > > {
> > > > > >   hash_set pset;
> > > > > > -  bool genericize; // called from cp_fold_function?
> > > > > > -
> > > > > > -  cp_fold_data (bool g): genericize (g) {}
> > > > > > +  fold_flags flags;
> > > > > > +  cp_fold_data (fold_flags flags): flags (flags) {}
> > > > > > };
> > > > > >   static tree
> > > > > > @@ -1039,7 +1046,7 @@ cp_fold_r (tree *stmt_p, int *walk_subtrees,
> > > > > > void
> > > > > > *data_)
> > > > > >   break;
> > > > > > }
> > > > > > -  *stmt_p = stmt = cp_fold (*stmt_p);
> > > > > > +  *stmt_p = stmt = cp_fold (*stmt_p, data->flags);
> > > > > > if (data->pset.add (stmt))
> > > > > > {
> > > > > > @@ -1119,12 +1126,12 @@ cp_fold_r (tree *stmt_p, int *walk_subtrees,
> > > > > > void
> > > > > > *data_)
> > > > > >  here rather than in cp_genericize to avoid problems 
> > > > > > with the
> > > > > > invisible
> > > > > >  reference transition.  */
> > > > > > case INIT_EXPR:
> > > > > > -  if (data->genericize)
> > > > > > +  if (data->flags & ff_genericize)
> > > > > > cp_genericize_init_expr (stmt_p);
> > > > > >   break;
> > > > > >   case TARGET_EXPR:
> > > > > > -  if (data->genericize)
> > > > > > +  if (data->flags & ff_genericize)
> > > > > > cp_genericize_target_expr (stmt_p);
> > > > > > /* Folding might replace e.g. a COND_EXPR with a
> > > > > > TARGET_EXPR;
> > > > > > in
> > 

[COMMITTED] tree-optimization: [PR108684] ICE in verify_ssa due to simple_dce_from_worklist

[Andrew Pinski via Gcc-patches]

In simple_dce_from_worklist, we were removing an inline-asm which had a vdef.
We should not be removing inline-asm which have a vdef as this code
does not check to the store.
This fixes that oversight. This was a latent bug exposed recently
by both VRP and removal of stores to static starting to use
simple_dce_from_worklist.

Committed as approved.
Bootstrapped and tested on x86_64-linux-gnu with no regressions.

PR tree-optimization/108684

gcc/ChangeLog:

* tree-ssa-dce.cc (simple_dce_from_worklist):
Check all ssa names and not just non-vdef ones
before accepting the inline-asm.
Call unlink_stmt_vdef on the statement before
removing it.

gcc/testsuite/ChangeLog:

* gcc.c-torture/compile/dce-inline-asm-1.c: New test.
* gcc.c-torture/compile/dce-inline-asm-2.c: New test.
* gcc.dg/tree-ssa/pr108684-1.c: New test.

co-authored-by: Andrew Macleod  
---
 .../gcc.c-torture/compile/dce-inline-asm-1.c   | 15 +++
 .../gcc.c-torture/compile/dce-inline-asm-2.c   | 16 
 gcc/testsuite/gcc.dg/tree-ssa/pr108684-1.c | 18 ++
 gcc/tree-ssa-dce.cc|  5 +++--
 4 files changed, 52 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c
 create mode 100644 gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr108684-1.c

diff --git a/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c 
b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c
new file mode 100644
index 000..a9f02e44bd7
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c
@@ -0,0 +1,15 @@
+/* PR tree-optimization/108684 */
+/* This used to ICE as when we remove the store to
+   `t`, we also would remove the inline-asm which
+   had a VDEF on it but we didn't update the
+   VUSE that was later on.  */
+static int t;
+
+int f (int *a)
+{
+  int t1;
+  asm (" " : "=X" (t1) : : "memory");
+  t = t1;
+  return *a;
+}
+
diff --git a/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c 
b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c
new file mode 100644
index 000..a41b16e4bd0
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c
@@ -0,0 +1,16 @@
+/* PR tree-optimization/108684 */
+/* This used to ICE as when we removed the
+   __builtin_unreachable in VRP, as we
+   would also remove the branch and the
+   inline-asm. The inline-asm had a VDEF on it,
+   which we didn't update further along and
+   not have the VDEF on the return statement
+   updated.  */
+
+int f (int a)
+{
+  asm (" " : "=X" (a) : : "memory");
+  if (a)
+return 0;
+  __builtin_unreachable();
+}
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr108684-1.c 
b/gcc/testsuite/gcc.dg/tree-ssa/pr108684-1.c
new file mode 100644
index 000..3ba206f765e
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr108684-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+
+
+static int t;
+
+int f (int *a)
+{
+  int t1, t2 = 0;
+  asm ("shouldshowupstill %1" : "=r" (t1), "=m"(t2) : : );
+  t = t1;
+  return t2;
+}
+
+/* Check to make sure DCE does not remove the inline-asm as it writes to t2. */
+/* We used to DCE this inline-asm when removing the store to t. */
+/* { dg-final { scan-assembler "shouldshowupstill" } } */
+/* { dg-final { scan-tree-dump-times "shouldshowupstill" 1 "optimized" } } */
diff --git a/gcc/tree-ssa-dce.cc b/gcc/tree-ssa-dce.cc
index b2fe9f4f55e..1f1ec2c8710 100644
--- a/gcc/tree-ssa-dce.cc
+++ b/gcc/tree-ssa-dce.cc
@@ -2108,9 +2108,9 @@ simple_dce_from_worklist (bitmap worklist)
 
   /* The defining statement needs to be defining only this name.
 ASM is the only statement that can define more than one
-(non-virtual) name. */
+name. */
   if (is_a(t)
- && !single_ssa_def_operand (t, SSA_OP_DEF))
+ && !single_ssa_def_operand (t, SSA_OP_ALL_DEFS))
continue;
 
   /* Don't remove statements that are needed for non-call
@@ -2140,6 +2140,7 @@ simple_dce_from_worklist (bitmap worklist)
remove_phi_node (&gsi, true);
   else
{
+ unlink_stmt_vdef (t);
  gsi_remove (&gsi, true);
  release_defs (t);
}
-- 
2.27.0

[PATCH] PR tree-optimization/108687 - Query rangers cache in readonly mode only internally

[Andrew MacLeod via Gcc-patches]

The change for 108356 allowed the cache to scan the dominator trees when 
it was attempting a lookup rather than using the local value.  I 
inadvertantly changed the external interface to also do this, so all the 
GORI queries via range_on_edge of the cache could also do lookups in 
this mode.


This triggered a quadratic, possible exponential time increase when the 
right conditions were presented. That being a cascading series of
recomputations on outgoing edge calculations that at then searched the 
dom tree instead of being a simple calculation using whats easily available.


The fix is to use the internal API within the cache rather than the 
extrenal one that GORI uses.   This leaves GORI computations to be 
resolved in linear time.  GORI is designed to only use what immediately 
available and should never trigger new lookups of its own.  Doh.


This may possibly fix a a few other new large time growth issues in DOM 
and friends,  such as 108705.


bootstrapped on x86_64-pc-linux-gnu, regtesting ongoing.. assuming no 
issues, OK for trunk?


Andrew
From 39f573402e92ab07fbe8a2ced513d8de63881135 Mon Sep 17 00:00:00 2001
From: Andrew MacLeod 
Date: Thu, 9 Feb 2023 17:50:07 -0500
Subject: [PATCH 2/4] Query rangers cache in readonly mode only from within

The change for 108356 allowed the cache to scan the dominator trees when
it was attempting a lookup rather than using the local value.  I
inadvertantly changed the externbal interface to also do this, so all
the GORI queries via range_on_edge of the cache could also do lookups.

This triggered a quadratic, possible expoential time increase when
the right conditions were presented. That being a cascading series of
recomputaions on outgoing edge calucaltions that at then searched the dom tree
instead of being a simple calcualtion using whats easily available.

The fix is to use the internal API within the cache rather than the
extrenal one that GORI uses.   This leaves GORI computations to be
resovled in linear time.

	PR tree-optimization/108687
	gcc/
	* gimple-range-cache.cc (ranger_cache::range_on_edge): Revert
	back to RFD_NONE mode for calculations.
	(ranger_cache::propagate_cache): Call the internal edge range API
	with RFD_READ_ONLY instead of changing the external routine.
---
 gcc/gimple-range-cache.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/gimple-range-cache.cc b/gcc/gimple-range-cache.cc
index 20c444bc4f4..546262c4794 100644
--- a/gcc/gimple-range-cache.cc
+++ b/gcc/gimple-range-cache.cc
@@ -998,7 +998,7 @@ bool
 ranger_cache::range_on_edge (vrange &r, edge e, tree expr)
 {
   if (gimple_range_ssa_p (expr))
-return edge_range (r, e, expr, RFD_READ_ONLY);
+return edge_range (r, e, expr, RFD_NONE);
   return get_tree_range (r, expr, NULL);
 }
 
@@ -1081,7 +1081,7 @@ ranger_cache::propagate_cache (tree name)
   new_range.set_undefined ();
   FOR_EACH_EDGE (e, ei, bb->preds)
 	{
-	  range_on_edge (e_range, e, name);
+	  edge_range (e_range, e, name, RFD_READ_ONLY);
 	  if (DEBUG_RANGE_CACHE)
 	{
 	  fprintf (dump_file, "   edge %d->%d :", e->src->index, bb->index);
-- 
2.39.0

[PATCH v4] rs6000: Fix incorrect RTL for Power LE when removing the UNSPECS [PR106069]

[Xionghu Luo via Gcc-patches]

Resend this patch...

v4: Update per comments.
v3: rename altivec_vmrghb_direct_le to altivec_vmrglb_direct_le to match
the actual output ASM vmrglb. Likewise for all similar xxx_direct_le
patterns.
v2: Split the direct pattern to be and le with same RTL but different insn.

The native RTL expression for vec_mrghw should be same for BE and LE as
they are register and endian-independent.  So both BE and LE need
generate exactly same RTL with index [0 4 1 5] when expanding vec_mrghw
with vec_select and vec_concat.

(set (reg:V4SI 141) (vec_select:V4SI (vec_concat:V8SI
   (subreg:V4SI (reg:V16QI 139) 0)
   (subreg:V4SI (reg:V16QI 140) 0))
   [const_int 0 4 1 5]))

Then combine pass could do the nested vec_select optimization
in simplify-rtx.c:simplify_binary_operation_1 also on both BE and LE:

21: r150:V4SI=vec_select(vec_concat(r141:V4SI,r146:V4SI),parallel [0 4 1 5])
24: {r151:SI=vec_select(r150:V4SI,parallel [const_int 3]);}

=>

21: r150:V4SI=vec_select(vec_concat(r141:V4SI,r146:V4SI),parallel)
24: {r151:SI=vec_select(r146:V4SI,parallel [const_int 1]);}

The endianness check need only once at ASM generation finally.
ASM would be better due to nested vec_select simplified to simple scalar
load.

Regression tested pass for Power8{LE,BE}{32,64} and Power{9,10}LE{32,64}
Linux.

gcc/ChangeLog:

PR target/106069
* config/rs6000/altivec.md (altivec_vmrghb_direct): Remove.
(altivec_vmrghb_direct_be): New pattern for BE.
(altivec_vmrghb_direct_le): New pattern for LE.
(altivec_vmrghh_direct): Remove.
(altivec_vmrghh_direct_be): New pattern for BE.
(altivec_vmrghh_direct_le): New pattern for LE.
(altivec_vmrghw_direct_): Remove.
(altivec_vmrghw_direct__be): New pattern for BE.
(altivec_vmrghw_direct__le): New pattern for LE.
(altivec_vmrglb_direct): Remove.
(altivec_vmrglb_direct_be): New pattern for BE.
(altivec_vmrglb_direct_le): New pattern for LE.
(altivec_vmrglh_direct): Remove.
(altivec_vmrglh_direct_be): New pattern for BE.
(altivec_vmrglh_direct_le): New pattern for LE.
(altivec_vmrglw_direct_): Remove.
(altivec_vmrglw_direct__be): New pattern for BE.
(altivec_vmrglw_direct__le): New pattern for LE.
* config/rs6000/rs6000.cc (altivec_expand_vec_perm_const):
Adjust.
* config/rs6000/vsx.md: Likewise.

gcc/testsuite/ChangeLog:

PR target/106069
* g++.target/powerpc/pr106069.C: New test.

Signed-off-by: Xionghu Luo 
---
 gcc/config/rs6000/altivec.md| 222 ++--
 gcc/config/rs6000/rs6000.cc |  24 +--
 gcc/config/rs6000/vsx.md|  28 +--
 gcc/testsuite/g++.target/powerpc/pr106069.C | 118 +++
 4 files changed, 307 insertions(+), 85 deletions(-)
 create mode 100644 gcc/testsuite/g++.target/powerpc/pr106069.C

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 30606b8ab21..4bfeecec224 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1144,15 +1144,16 @@ (define_expand "altivec_vmrghb"
(use (match_operand:V16QI 2 "register_operand"))]
   "TARGET_ALTIVEC"
 {
-  rtx (*fun) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN ? gen_altivec_vmrghb_direct
-   : gen_altivec_vmrglb_direct;
-  if (!BYTES_BIG_ENDIAN)
-std::swap (operands[1], operands[2]);
-  emit_insn (fun (operands[0], operands[1], operands[2]));
+  if (BYTES_BIG_ENDIAN)
+emit_insn (
+  gen_altivec_vmrghb_direct_be (operands[0], operands[1], operands[2]));
+  else
+emit_insn (
+  gen_altivec_vmrglb_direct_le (operands[0], operands[2], operands[1]));
   DONE;
 })
 
-(define_insn "altivec_vmrghb_direct"
+(define_insn "altivec_vmrghb_direct_be"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
(vec_select:V16QI
  (vec_concat:V32QI
@@ -1166,7 +1167,25 @@ (define_insn "altivec_vmrghb_direct"
 (const_int 5) (const_int 21)
 (const_int 6) (const_int 22)
 (const_int 7) (const_int 23)])))]
-  "TARGET_ALTIVEC"
+  "TARGET_ALTIVEC && BYTES_BIG_ENDIAN"
+  "vmrghb %0,%1,%2"
+  [(set_attr "type" "vecperm")])
+
+(define_insn "altivec_vmrghb_direct_le"
+  [(set (match_operand:V16QI 0 "register_operand" "=v")
+   (vec_select:V16QI
+ (vec_concat:V32QI
+   (match_operand:V16QI 2 "register_operand" "v")
+   (match_operand:V16QI 1 "register_operand" "v"))
+ (parallel [(const_int  8) (const_int 24)
+(const_int  9) (const_int 25)
+(const_int 10) (const_int 26)
+(const_int 11) (const_int 27)
+(const_int 12) (const_int 28)
+(const_int 13) (const_int 29)
+(const_int 14) (const_int 30)
+(const_int 15) (const_int 31)]))

[PATCHv4] [AARCH64] Fix PR target/103100 -mstrict-align and memset on not aligned buffers

[Andrew Pinski via Gcc-patches]

The problem here is that aarch64_expand_setmem does not change the alignment
for strict alignment case.
This is version 4 of the fix, major changes from the last version is fixing
the way store pairs are handled which allows handling of storing 2 SI mode
at a time.
This also adds a testcase to show a case with -mstrict-align we can do
the store word pair stores.

OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions.

PR target/103100

gcc/ChangeLog:

* config/aarch64/aarch64.cc (aarch64_gen_store_pair):
Add support for SImode.
(aarch64_set_one_block_and_progress_pointer):
Add use_pair argument and rewrite and simplifying the
code.
(aarch64_can_use_pair_load_stores): New function.
(aarch64_expand_setmem): Rewrite mode selection to
better handle strict alignment and non ld/stp pair case.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/memset-strict-align-1.c: Update test.
Reduce the size down to 207 and make s1 global and aligned
to 16 bytes.
* gcc.target/aarch64/memset-strict-align-2.c: New test.
* gcc.target/aarch64/memset-strict-align-3.c: New test.
---
 gcc/config/aarch64/aarch64.cc | 136 ++
 .../aarch64/memset-strict-align-1.c   |  19 ++-
 .../aarch64/memset-strict-align-2.c   |  14 ++
 .../aarch64/memset-strict-align-3.c   |  15 ++
 4 files changed, 113 insertions(+), 71 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/memset-strict-align-2.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/memset-strict-align-3.c

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 5c40b6ed22a..3eaf9bd608a 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -8850,6 +8850,9 @@ aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx 
reg1, rtx mem2,
 {
   switch (mode)
 {
+case E_SImode:
+  return gen_store_pair_sw_sisi (mem1, reg1, mem2, reg2);
+
 case E_DImode:
   return gen_store_pair_dw_didi (mem1, reg1, mem2, reg2);
 
@@ -24896,42 +24899,49 @@ aarch64_expand_cpymem (rtx *operands)
SRC is a register we have created with the duplicated value to be set.  */
 static void
 aarch64_set_one_block_and_progress_pointer (rtx src, rtx *dst,
-   machine_mode mode)
+   machine_mode mode, bool use_pairs)
 {
+  rtx reg = src;
   /* If we are copying 128bits or 256bits, we can do that straight from
  the SIMD register we prepared.  */
-  if (known_eq (GET_MODE_BITSIZE (mode), 256))
-{
-  mode = GET_MODE (src);
-  /* "Cast" the *dst to the correct mode.  */
-  *dst = adjust_address (*dst, mode, 0);
-  /* Emit the memset.  */
-  emit_insn (aarch64_gen_store_pair (mode, *dst, src,
-aarch64_progress_pointer (*dst), src));
-
-  /* Move the pointers forward.  */
-  *dst = aarch64_move_pointer (*dst, 32);
-  return;
-}
   if (known_eq (GET_MODE_BITSIZE (mode), 128))
-{
-  /* "Cast" the *dst to the correct mode.  */
-  *dst = adjust_address (*dst, GET_MODE (src), 0);
-  /* Emit the memset.  */
-  emit_move_insn (*dst, src);
-  /* Move the pointers forward.  */
-  *dst = aarch64_move_pointer (*dst, 16);
-  return;
-}
-  /* For copying less, we have to extract the right amount from src.  */
-  rtx reg = lowpart_subreg (mode, src, GET_MODE (src));
+mode = GET_MODE(src);
+  else
+/* For copying less, we have to extract the right amount from src.  */
+reg = lowpart_subreg (mode, src, GET_MODE (src));
 
   /* "Cast" the *dst to the correct mode.  */
   *dst = adjust_address (*dst, mode, 0);
   /* Emit the memset.  */
-  emit_move_insn (*dst, reg);
+  if (use_pairs)
+emit_insn (aarch64_gen_store_pair (mode, *dst, reg,
+  aarch64_progress_pointer (*dst),
+  reg));
+  else
+emit_move_insn (*dst, reg);
+
   /* Move the pointer forward.  */
   *dst = aarch64_progress_pointer (*dst);
+  if (use_pairs)
+*dst = aarch64_progress_pointer (*dst);
+}
+
+/* Returns true if size can be used as a store/load pair.
+   This is a helper function for aarch64_expand_setmem and others. */
+static bool
+aarch64_can_use_pair_load_stores (unsigned HOST_WIDE_INT size)
+{
+  /* For DI and SI modes, we can use store pairs.  */
+  if (size == GET_MODE_BITSIZE (DImode)
+  || size == GET_MODE_BITSIZE (SImode))
+return true;
+  /* For TI mode, we will use store pairs only if
+ the target wants to. */
+  else if (size == GET_MODE_BITSIZE (TImode)
+  && !(aarch64_tune_params.extra_tuning_flags
+  & AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS))
+return true;
+  return false;
 }
 
 /* Expand a setmem using the MOPS instructions.  OPERANDS are the same
@@ -24974,9 +24984,21 @@ aarch64_e

[PATCH] RISC-V: Add fixed-point support

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc (class sat_op): New class.
(class vnclip): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vaadd): Ditto.
(vasub): Ditto.
(vaaddu): Ditto.
(vasubu): Ditto.
(vsmul): Ditto.
(vssra): Ditto.
(vssrl): Ditto.
(vnclipu): Ditto.
(vnclip): Ditto.
* config/riscv/vector-iterators.md (su): Add instruction.
(aadd): Ditto.
(vaalu): Ditto.
* config/riscv/vector.md (@pred_): New pattern.
(@pred__scalar): Ditto.
(*pred__scalar): Ditto.
(*pred__extended_scalar): Ditto.
(@pred_narrow_clip): Ditto.
(@pred_narrow_clip_scalar): Ditto.

---
 .../riscv/riscv-vector-builtins-bases.cc  |  59 +
 .../riscv/riscv-vector-builtins-bases.h   |  12 +-
 .../riscv/riscv-vector-builtins-functions.def |  18 ++
 gcc/config/riscv/vector-iterators.md  |  32 ++-
 gcc/config/riscv/vector.md| 238 +-
 5 files changed, 346 insertions(+), 13 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 30f9734c36b..6eb6dab3149 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -464,6 +464,47 @@ public:
   }
 };
 
+/* Implements vaadd/vasub/vsmul/vssra/vssrl.  */
+template
+class sat_op : public function_base
+{
+public:
+  rtx expand (function_expander &e) const override
+  {
+switch (e.op_info->op)
+  {
+  case OP_TYPE_vx:
+   return e.use_exact_insn (
+ code_for_pred_scalar (UNSPEC, e.vector_mode ()));
+  case OP_TYPE_vv:
+   return e.use_exact_insn (code_for_pred (UNSPEC, e.vector_mode ()));
+  default:
+   gcc_unreachable ();
+  }
+  }
+};
+
+/* Implements vnclip/vnclipu.  */
+template
+class vnclip : public function_base
+{
+public:
+  rtx expand (function_expander &e) const override
+  {
+switch (e.op_info->op)
+  {
+  case OP_TYPE_wx:
+   return e.use_exact_insn (
+ code_for_pred_narrow_clip_scalar (UNSPEC, e.vector_mode ()));
+  case OP_TYPE_wv:
+   return e.use_exact_insn (
+ code_for_pred_narrow_clip (UNSPEC, e.vector_mode ()));
+  default:
+   gcc_unreachable ();
+  }
+  }
+};
+
 static CONSTEXPR const vsetvl vsetvl_obj;
 static CONSTEXPR const vsetvl vsetvlmax_obj;
 static CONSTEXPR const loadstore vle_obj;
@@ -535,6 +576,15 @@ static CONSTEXPR const binop vsadd_obj;
 static CONSTEXPR const binop vssub_obj;
 static CONSTEXPR const binop vsaddu_obj;
 static CONSTEXPR const binop vssubu_obj;
+static CONSTEXPR const sat_op vaaddu_obj;
+static CONSTEXPR const sat_op vaadd_obj;
+static CONSTEXPR const sat_op vasubu_obj;
+static CONSTEXPR const sat_op vasub_obj;
+static CONSTEXPR const sat_op vsmul_obj;
+static CONSTEXPR const sat_op vssrl_obj;
+static CONSTEXPR const sat_op vssra_obj;
+static CONSTEXPR const vnclip vnclip_obj;
+static CONSTEXPR const vnclip vnclipu_obj;
 
 /* Declare the function base NAME, pointing it to an instance
of class _obj.  */
@@ -612,5 +662,14 @@ BASE (vsadd)
 BASE (vssub)
 BASE (vsaddu)
 BASE (vssubu)
+BASE (vaadd)
+BASE (vasub)
+BASE (vaaddu)
+BASE (vasubu)
+BASE (vsmul)
+BASE (vssra)
+BASE (vssrl)
+BASE (vnclip)
+BASE (vnclipu)
 
 } // end namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h 
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 411db5627ee..dcc706ea805 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -95,7 +95,17 @@ extern const function_base *const vsadd;
 extern const function_base *const vssub;
 extern const function_base *const vsaddu;
 extern const function_base *const vssubu;
-
+extern const function_base *const vaadd;
+extern const function_base *const vasub;
+extern const function_base *const vaaddu;
+extern const function_base *const vasubu;
+extern const function_base *const vsmul;
+extern const function_base *const vssra;
+extern const function_base *const vssrl;
+extern const function_base *const vnclip;
+extern const function_base *const vnclip;
+extern const function_base *const vnclipu;
+extern const function_base *const vnclipu;
 }
 
 } // end namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def 
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 28483463d64..cea44c8fb20 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -166,5 +166,23 @@ DEF_RVV_FUNCTION (vsadd, alu, full_preds, i_vvx_ops)
 DEF_RVV_FUNCTION (vssub, alu, full_preds, i_vvx_ops)
 DEF_RVV_FUNCTION (vsaddu, alu, full_preds, u_vvx_ops)
 DEF_RVV_FUNCTION (vssubu, alu, full_preds, u_vv

[PATCH] RISC-V: Add vssrl.vx C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vssrl_vx-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_m-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_m-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_m-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vssrl_vx-1.c| 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vx-2.c| 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vx-3.c| 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vx_m-1.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vx_m-2.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vx_m-3.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vx_mu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vx_mu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vx_mu-3.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vx_tu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vx_tu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vx_tu-3.c | 160 ++
 .../riscv/rvv/base/vssrl_vx_tum-1.c   | 160 ++
 .../riscv/rvv/base/vssrl_vx_tum-2.c   | 160 ++
 .../riscv/rvv/base/vssrl_vx_tum-3.c   | 160 ++
 .../riscv/rvv/base/vssrl_vx_tumu-1.c  | 160 ++
 .../riscv/rvv/base/vssrl_vx_tumu-2.c  | 160 ++
 .../riscv/rvv/base/vssrl_vx_tumu-3.c  | 160 ++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx-1.c
new file mode 100644
index 000..90be4248938
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssrl_vx_u8mf8(vuint8mf8_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl_vx_u8mf8(op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssrl_vx_u8mf4(vuint8mf4_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl_vx_u8mf4(op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssrl_vx_u8mf2(vuint8mf2_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl_vx_u8mf2(op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vssrl_vx_u8m1(vuint8m1_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl_vx_u8m1(op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vssrl_vx_u8m2(vuint8m2_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl_vx_u8m2(op1,shift,vl);
+}
+
+
+

[PATCH] RISC-V: Add vssrl.vv C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vssrl_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vssrl_vv-1.c| 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vv-2.c| 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vv-3.c| 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vv_m-1.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vv_m-2.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vv_m-3.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vv_mu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vv_mu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vv_mu-3.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vv_tu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vv_tu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssrl_vv_tu-3.c | 160 ++
 .../riscv/rvv/base/vssrl_vv_tum-1.c   | 160 ++
 .../riscv/rvv/base/vssrl_vv_tum-2.c   | 160 ++
 .../riscv/rvv/base/vssrl_vv_tum-3.c   | 160 ++
 .../riscv/rvv/base/vssrl_vv_tumu-1.c  | 160 ++
 .../riscv/rvv/base/vssrl_vv_tumu-2.c  | 160 ++
 .../riscv/rvv/base/vssrl_vv_tumu-3.c  | 160 ++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-1.c
new file mode 100644
index 000..8e38ad6096f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssrl_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t 
shift,size_t vl)
+{
+return __riscv_vssrl_vv_u8mf8(op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssrl_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t 
shift,size_t vl)
+{
+return __riscv_vssrl_vv_u8mf4(op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssrl_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t 
shift,size_t vl)
+{
+return __riscv_vssrl_vv_u8mf2(op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vssrl_vv_u8m1(vuint8m1_t op1,vuint8m1_t shift,size_t 
vl)
+{
+return __riscv_vssrl_vv_u8m1(op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vssrl_vv_u8m2(vuint8m2_t op1,vuint8m2_t shift,size_t 
vl)
+{
+return __riscv_vssrl_vv_

[PATCH] RISC-V: Add vssra.vx C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vssra_vx-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_m-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_m-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_m-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vssra_vx-1.c| 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vx-2.c| 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vx-3.c| 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vx_m-1.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vx_m-2.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vx_m-3.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vx_mu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vx_mu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vx_mu-3.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vx_tu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vx_tu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vx_tu-3.c | 160 ++
 .../riscv/rvv/base/vssra_vx_tum-1.c   | 160 ++
 .../riscv/rvv/base/vssra_vx_tum-2.c   | 160 ++
 .../riscv/rvv/base/vssra_vx_tum-3.c   | 160 ++
 .../riscv/rvv/base/vssra_vx_tumu-1.c  | 160 ++
 .../riscv/rvv/base/vssra_vx_tumu-2.c  | 160 ++
 .../riscv/rvv/base/vssra_vx_tumu-3.c  | 160 ++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-1.c
new file mode 100644
index 000..2feeadcd933
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8(vint8mf8_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra_vx_i8mf8(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4(vint8mf4_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra_vx_i8mf4(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2(vint8mf2_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra_vx_i8mf2(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1(vint8m1_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra_vx_i8m1(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2(vint8m2_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra_vx_i8m2(op1,shift,vl);
+}
+
+
+vint8m4_t 

[PATCH] RISC-V: Add vssra.vv C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vssra_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vssra_vv-1.c| 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vv-2.c| 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vv-3.c| 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vv_m-1.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vv_m-2.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vv_m-3.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vv_mu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vv_mu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vv_mu-3.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vv_tu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vv_tu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vssra_vv_tu-3.c | 160 ++
 .../riscv/rvv/base/vssra_vv_tum-1.c   | 160 ++
 .../riscv/rvv/base/vssra_vv_tum-2.c   | 160 ++
 .../riscv/rvv/base/vssra_vv_tum-3.c   | 160 ++
 .../riscv/rvv/base/vssra_vv_tumu-1.c  | 160 ++
 .../riscv/rvv/base/vssra_vv_tumu-2.c  | 160 ++
 .../riscv/rvv/base/vssra_vv_tumu-3.c  | 160 ++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv-1.c
new file mode 100644
index 000..63d4b0e5887
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vv_i8mf8(vint8mf8_t op1,vuint8mf8_t shift,size_t 
vl)
+{
+return __riscv_vssra_vv_i8mf8(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_vv_i8mf4(vint8mf4_t op1,vuint8mf4_t shift,size_t 
vl)
+{
+return __riscv_vssra_vv_i8mf4(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_vv_i8mf2(vint8mf2_t op1,vuint8mf2_t shift,size_t 
vl)
+{
+return __riscv_vssra_vv_i8mf2(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_vv_i8m1(vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+return __riscv_vssra_vv_i8m1(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_vv_i8m2(vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+return __riscv_vssra_vv_i8m2(op1,shi

[PATCH] RISC-V: Add vsmul.vv C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vsmul_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vsmul_vv-1.c| 160 ++
 .../gcc.target/riscv/rvv/base/vsmul_vv-2.c| 160 ++
 .../gcc.target/riscv/rvv/base/vsmul_vv-3.c| 160 ++
 .../gcc.target/riscv/rvv/base/vsmul_vv_m-1.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vsmul_vv_m-2.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vsmul_vv_m-3.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vsmul_vv_mu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vsmul_vv_mu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vsmul_vv_mu-3.c | 160 ++
 .../gcc.target/riscv/rvv/base/vsmul_vv_tu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vsmul_vv_tu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vsmul_vv_tu-3.c | 160 ++
 .../riscv/rvv/base/vsmul_vv_tum-1.c   | 160 ++
 .../riscv/rvv/base/vsmul_vv_tum-2.c   | 160 ++
 .../riscv/rvv/base/vsmul_vv_tum-3.c   | 160 ++
 .../riscv/rvv/base/vsmul_vv_tumu-1.c  | 160 ++
 .../riscv/rvv/base/vsmul_vv_tumu-2.c  | 160 ++
 .../riscv/rvv/base/vsmul_vv_tumu-3.c  | 160 ++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv-1.c
new file mode 100644
index 000..6d770260cfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsmul_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+return __riscv_vsmul_vv_i8mf8(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsmul_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+return __riscv_vsmul_vv_i8mf4(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsmul_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+return __riscv_vsmul_vv_i8mf2(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsmul_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+return __riscv_vsmul_vv_i8m1(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsmul_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+return __riscv_vsmul_vv_i8m2(op1,op2,vl);
+}
+
+
+vint8m4_t te

[PATCH] RISC-V: Add vasubu.vv C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vasubu_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vasubu_vv-1.c   | 160 ++
 .../gcc.target/riscv/rvv/base/vasubu_vv-2.c   | 160 ++
 .../gcc.target/riscv/rvv/base/vasubu_vv-3.c   | 160 ++
 .../gcc.target/riscv/rvv/base/vasubu_vv_m-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vasubu_vv_m-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vasubu_vv_m-3.c | 160 ++
 .../riscv/rvv/base/vasubu_vv_mu-1.c   | 160 ++
 .../riscv/rvv/base/vasubu_vv_mu-2.c   | 160 ++
 .../riscv/rvv/base/vasubu_vv_mu-3.c   | 160 ++
 .../riscv/rvv/base/vasubu_vv_tu-1.c   | 160 ++
 .../riscv/rvv/base/vasubu_vv_tu-2.c   | 160 ++
 .../riscv/rvv/base/vasubu_vv_tu-3.c   | 160 ++
 .../riscv/rvv/base/vasubu_vv_tum-1.c  | 160 ++
 .../riscv/rvv/base/vasubu_vv_tum-2.c  | 160 ++
 .../riscv/rvv/base/vasubu_vv_tum-3.c  | 160 ++
 .../riscv/rvv/base/vasubu_vv_tumu-1.c | 160 ++
 .../riscv/rvv/base/vasubu_vv_tumu-2.c | 160 ++
 .../riscv/rvv/base/vasubu_vv_tumu-3.c | 160 ++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv-1.c
new file mode 100644
index 000..0203a221f09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vasubu_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t 
op2,size_t vl)
+{
+return __riscv_vasubu_vv_u8mf8(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vasubu_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t 
op2,size_t vl)
+{
+return __riscv_vasubu_vv_u8mf4(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vasubu_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t 
op2,size_t vl)
+{
+return __riscv_vasubu_vv_u8mf2(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vasubu_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+return __riscv_vasubu_vv_u8m1(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vasubu_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+

[PATCH] RISC-V: Add vasub.vv C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vasub_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vasub_vv-1.c| 160 ++
 .../gcc.target/riscv/rvv/base/vasub_vv-2.c| 160 ++
 .../gcc.target/riscv/rvv/base/vasub_vv-3.c| 160 ++
 .../gcc.target/riscv/rvv/base/vasub_vv_m-1.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vasub_vv_m-2.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vasub_vv_m-3.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vasub_vv_mu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vasub_vv_mu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vasub_vv_mu-3.c | 160 ++
 .../gcc.target/riscv/rvv/base/vasub_vv_tu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vasub_vv_tu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vasub_vv_tu-3.c | 160 ++
 .../riscv/rvv/base/vasub_vv_tum-1.c   | 160 ++
 .../riscv/rvv/base/vasub_vv_tum-2.c   | 160 ++
 .../riscv/rvv/base/vasub_vv_tum-3.c   | 160 ++
 .../riscv/rvv/base/vasub_vv_tumu-1.c  | 160 ++
 .../riscv/rvv/base/vasub_vv_tumu-2.c  | 160 ++
 .../riscv/rvv/base/vasub_vv_tumu-3.c  | 160 ++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv-1.c
new file mode 100644
index 000..e9befbbcceb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vasub_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+return __riscv_vasub_vv_i8mf8(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vasub_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+return __riscv_vasub_vv_i8mf4(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vasub_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+return __riscv_vasub_vv_i8mf2(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vasub_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+return __riscv_vasub_vv_i8m1(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vasub_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+return __riscv_vasub_vv_i8m2(op1,op2,vl);
+}
+
+
+vint8m4_t te

[PATCH] RISC-V: Add vaaddu.vv C api tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vaaddu_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vaaddu_vv-1.c   | 160 ++
 .../gcc.target/riscv/rvv/base/vaaddu_vv-2.c   | 160 ++
 .../gcc.target/riscv/rvv/base/vaaddu_vv-3.c   | 160 ++
 .../gcc.target/riscv/rvv/base/vaaddu_vv_m-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vaaddu_vv_m-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vaaddu_vv_m-3.c | 160 ++
 .../riscv/rvv/base/vaaddu_vv_mu-1.c   | 160 ++
 .../riscv/rvv/base/vaaddu_vv_mu-2.c   | 160 ++
 .../riscv/rvv/base/vaaddu_vv_mu-3.c   | 160 ++
 .../riscv/rvv/base/vaaddu_vv_tu-1.c   | 160 ++
 .../riscv/rvv/base/vaaddu_vv_tu-2.c   | 160 ++
 .../riscv/rvv/base/vaaddu_vv_tu-3.c   | 160 ++
 .../riscv/rvv/base/vaaddu_vv_tum-1.c  | 160 ++
 .../riscv/rvv/base/vaaddu_vv_tum-2.c  | 160 ++
 .../riscv/rvv/base/vaaddu_vv_tum-3.c  | 160 ++
 .../riscv/rvv/base/vaaddu_vv_tumu-1.c | 160 ++
 .../riscv/rvv/base/vaaddu_vv_tumu-2.c | 160 ++
 .../riscv/rvv/base/vaaddu_vv_tumu-3.c | 160 ++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv-1.c
new file mode 100644
index 000..36ec60316ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vaaddu_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t 
op2,size_t vl)
+{
+return __riscv_vaaddu_vv_u8mf8(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vaaddu_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t 
op2,size_t vl)
+{
+return __riscv_vaaddu_vv_u8mf4(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vaaddu_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t 
op2,size_t vl)
+{
+return __riscv_vaaddu_vv_u8mf2(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vaaddu_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+return __riscv_vaaddu_vv_u8m1(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vaaddu_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+

[PATCH] RISC-V: Finish fixed-point C API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/binop_vx_constraint-122.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tumu-3.c: New test.

---
 .../riscv/rvv/base/binop_vx_constraint-122.c  |  21 +++
 .../gcc.target/riscv/rvv/base/vaadd_vv-1.c| 160 ++
 .../gcc.target/riscv/rvv/base/vaadd_vv-2.c| 160 ++
 .../gcc.target/riscv/rvv/base/vaadd_vv-3.c| 160 ++
 .../gcc.target/riscv/rvv/base/vaadd_vv_m-1.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vaadd_vv_m-2.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vaadd_vv_m-3.c  | 160 ++
 .../gcc.target/riscv/rvv/base/vaadd_vv_mu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vaadd_vv_mu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vaadd_vv_mu-3.c | 160 ++
 .../gcc.target/riscv/rvv/base/vaadd_vv_tu-1.c | 160 ++
 .../gcc.target/riscv/rvv/base/vaadd_vv_tu-2.c | 160 ++
 .../gcc.target/riscv/rvv/base/vaadd_vv_tu-3.c | 160 ++
 .../riscv/rvv/base/vaadd_vv_tum-1.c   | 160 ++
 .../riscv/rvv/base/vaadd_vv_tum-2.c   | 160 ++
 .../riscv/rvv/base/vaadd_vv_tum-3.c   | 160 ++
 .../riscv/rvv/base/vaadd_vv_tumu-1.c  | 160 ++
 .../riscv/rvv/base/vaadd_vv_tumu-2.c  | 160 ++
 .../riscv/rvv/base/vaadd_vv_tumu-3.c  | 160 ++
 19 files changed, 2901 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-122.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-122.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-122.c
new file mode 100644
index 000..c5fd4701dec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-122.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+#include "riscv_vector.h"
+
+void f1 (void * in, void *out, int32_t x)
+{
+vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, 4);
+__riscv_vse32_v_i32m1 (out, v3, 4);
+}
+
+void f2 (void * in, void *out, int32_t x)
+{
+vint64m1_t v = __riscv_vle64_v_i64m1 (in, 4);
+vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in, 4);
+vint64m1_t v3 = __riscv_vaadd_vx_i64m1 (v2, 0, 4);
+__riscv_vse64_

[PATCH] RISC-V: Add vssrl.vx C++ API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vssrl_vx-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_mu-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_mu-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_mu-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tu-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tu-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tu-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tum-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tum-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tum-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vssrl_vx-1.C| 314 ++
 .../g++.target/riscv/rvv/base/vssrl_vx-2.C| 314 ++
 .../g++.target/riscv/rvv/base/vssrl_vx-3.C| 314 ++
 .../g++.target/riscv/rvv/base/vssrl_vx_mu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vssrl_vx_mu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vssrl_vx_mu-3.C | 160 +
 .../g++.target/riscv/rvv/base/vssrl_vx_tu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vssrl_vx_tu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vssrl_vx_tu-3.C | 160 +
 .../riscv/rvv/base/vssrl_vx_tum-1.C   | 160 +
 .../riscv/rvv/base/vssrl_vx_tum-2.C   | 160 +
 .../riscv/rvv/base/vssrl_vx_tum-3.C   | 160 +
 .../riscv/rvv/base/vssrl_vx_tumu-1.C  | 160 +
 .../riscv/rvv/base/vssrl_vx_tumu-2.C  | 160 +
 .../riscv/rvv/base/vssrl_vx_tumu-3.C  | 160 +
 15 files changed, 2862 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-1.C
new file mode 100644
index 000..2a3d21a8948
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssrl(vuint8mf8_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssrl(vuint8mf4_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssrl(vuint8mf2_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vssrl(vuint8m1_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vssrl(vuint8m2_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint8m4_t test___riscv_vssrl(vuint8m4_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint8m8_t test___riscv_vssrl(vuint8m8_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint16mf4_t test___riscv_vssrl(vuint16mf4_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint16mf2_t test___riscv_vssrl(vuint16mf2_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint16m1_t test___riscv_vssrl(vuint16m1_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint16m2_t test___riscv_vssrl(vuint16m2_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint16m4_t test___riscv_vssrl(vuint16m4_t op1,size_t shift,size_t vl)
+{
+retu

[PATCH] RISC-V: Add vssrl.vv C++ API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vssrl_vv-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tumu-3.C: New test.


---
 .../g++.target/riscv/rvv/base/vssrl_vv-1.C| 314 ++
 .../g++.target/riscv/rvv/base/vssrl_vv-2.C| 314 ++
 .../g++.target/riscv/rvv/base/vssrl_vv-3.C| 314 ++
 .../g++.target/riscv/rvv/base/vssrl_vv_mu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vssrl_vv_mu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vssrl_vv_mu-3.C | 160 +
 .../g++.target/riscv/rvv/base/vssrl_vv_tu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vssrl_vv_tu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vssrl_vv_tu-3.C | 160 +
 .../riscv/rvv/base/vssrl_vv_tum-1.C   | 160 +
 .../riscv/rvv/base/vssrl_vv_tum-2.C   | 160 +
 .../riscv/rvv/base/vssrl_vv_tum-3.C   | 160 +
 .../riscv/rvv/base/vssrl_vv_tumu-1.C  | 160 +
 .../riscv/rvv/base/vssrl_vv_tumu-2.C  | 160 +
 .../riscv/rvv/base/vssrl_vv_tumu-3.C  | 160 +
 15 files changed, 2862 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv-1.C
new file mode 100644
index 000..fb3ec457001
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vssrl(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint8mf4_t test___riscv_vssrl(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint8mf2_t test___riscv_vssrl(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint8m1_t test___riscv_vssrl(vuint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint8m2_t test___riscv_vssrl(vuint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint8m4_t test___riscv_vssrl(vuint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint8m8_t test___riscv_vssrl(vuint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint16mf4_t test___riscv_vssrl(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint16mf2_t test___riscv_vssrl(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint16m1_t test___riscv_vssrl(vuint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint16m2_t test___riscv_vssrl(vuint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+return __riscv_vssrl(op1,shift,vl);
+}
+
+
+vuint16m4_t test___riscv_vssr

[PATCH] RISC-V: Add vssra.vx C++ API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vssra_vx-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_mu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_mu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_mu-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tu-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tum-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tum-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tum-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vssra_vx-1.C| 314 ++
 .../g++.target/riscv/rvv/base/vssra_vx-2.C| 314 ++
 .../g++.target/riscv/rvv/base/vssra_vx-3.C| 314 ++
 .../g++.target/riscv/rvv/base/vssra_vx_mu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vssra_vx_mu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vssra_vx_mu-3.C | 160 +
 .../g++.target/riscv/rvv/base/vssra_vx_tu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vssra_vx_tu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vssra_vx_tu-3.C | 160 +
 .../riscv/rvv/base/vssra_vx_tum-1.C   | 160 +
 .../riscv/rvv/base/vssra_vx_tum-2.C   | 160 +
 .../riscv/rvv/base/vssra_vx_tum-3.C   | 160 +
 .../riscv/rvv/base/vssra_vx_tumu-1.C  | 160 +
 .../riscv/rvv/base/vssra_vx_tumu-2.C  | 160 +
 .../riscv/rvv/base/vssra_vx_tumu-3.C  | 160 +
 15 files changed, 2862 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-1.C
new file mode 100644
index 000..23985cd3ebb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra(vint8mf8_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra(vint8mf4_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra(vint8mf2_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra(vint8m1_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra(vint8m2_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra(vint8m4_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra(vint8m8_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra(vint16mf4_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra(vint16mf2_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra(vint16m1_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra(vint16m2_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra(vint16m4_t op1,size_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shi

[PATCH] RISC-V: Add vssra.vv C++ API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vssra_vv-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vv-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vv-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vssra_vv-1.C| 314 ++
 .../g++.target/riscv/rvv/base/vssra_vv-2.C| 314 ++
 .../g++.target/riscv/rvv/base/vssra_vv-3.C| 314 ++
 .../g++.target/riscv/rvv/base/vssra_vv_mu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vssra_vv_mu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vssra_vv_mu-3.C | 160 +
 .../g++.target/riscv/rvv/base/vssra_vv_tu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vssra_vv_tu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vssra_vv_tu-3.C | 160 +
 .../riscv/rvv/base/vssra_vv_tum-1.C   | 160 +
 .../riscv/rvv/base/vssra_vv_tum-2.C   | 160 +
 .../riscv/rvv/base/vssra_vv_tum-3.C   | 160 +
 .../riscv/rvv/base/vssra_vv_tumu-1.C  | 160 +
 .../riscv/rvv/base/vssra_vv_tumu-2.C  | 160 +
 .../riscv/rvv/base/vssra_vv_tumu-3.C  | 160 +
 15 files changed, 2862 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-1.C
new file mode 100644
index 000..0664da7ffe8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra(vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra(vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra(vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra(vint8m1_t op1,vuint8m1_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra(vint8m2_t op1,vuint8m2_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra(vint8m4_t op1,vuint8m4_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra(vint8m8_t op1,vuint8m8_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra(vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra(vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra(vint16m1_t op1,vuint16m1_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra(vint16m2_t op1,vuint16m2_t shift,size_t vl)
+{
+return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra(vint16m4_t op1,vuint16

[PATCH] RISC-V: Add vsmul.vv C++ API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vsmul_vv-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vsmul_vv-1.C| 314 ++
 .../g++.target/riscv/rvv/base/vsmul_vv-2.C| 314 ++
 .../g++.target/riscv/rvv/base/vsmul_vv-3.C| 314 ++
 .../g++.target/riscv/rvv/base/vsmul_vv_mu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vsmul_vv_mu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vsmul_vv_mu-3.C | 160 +
 .../g++.target/riscv/rvv/base/vsmul_vv_tu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vsmul_vv_tu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vsmul_vv_tu-3.C | 160 +
 .../riscv/rvv/base/vsmul_vv_tum-1.C   | 160 +
 .../riscv/rvv/base/vsmul_vv_tum-2.C   | 160 +
 .../riscv/rvv/base/vsmul_vv_tum-3.C   | 160 +
 .../riscv/rvv/base/vsmul_vv_tumu-1.C  | 160 +
 .../riscv/rvv/base/vsmul_vv_tumu-2.C  | 160 +
 .../riscv/rvv/base/vsmul_vv_tumu-3.C  | 160 +
 15 files changed, 2862 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv-1.C
new file mode 100644
index 000..58fe4115862
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsmul(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+return __riscv_vsmul(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsmul(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+return __riscv_vsmul(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsmul(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+return __riscv_vsmul(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsmul(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+return __riscv_vsmul(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsmul(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+return __riscv_vsmul(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsmul(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+return __riscv_vsmul(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsmul(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+return __riscv_vsmul(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsmul(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+return __riscv_vsmul(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsmul(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+return __riscv_vsmul(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsmul(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+return __riscv_vsmul(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsmul(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+return __riscv_vsmul(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsmul(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+return __riscv_vsmul(op1,op2

[PATCH] RISC-V: Add vasubu.vv C++ API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vasubu_vv-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vasubu_vv-1.C   | 314 ++
 .../g++.target/riscv/rvv/base/vasubu_vv-2.C   | 314 ++
 .../g++.target/riscv/rvv/base/vasubu_vv-3.C   | 314 ++
 .../riscv/rvv/base/vasubu_vv_mu-1.C   | 160 +
 .../riscv/rvv/base/vasubu_vv_mu-2.C   | 160 +
 .../riscv/rvv/base/vasubu_vv_mu-3.C   | 160 +
 .../riscv/rvv/base/vasubu_vv_tu-1.C   | 160 +
 .../riscv/rvv/base/vasubu_vv_tu-2.C   | 160 +
 .../riscv/rvv/base/vasubu_vv_tu-3.C   | 160 +
 .../riscv/rvv/base/vasubu_vv_tum-1.C  | 160 +
 .../riscv/rvv/base/vasubu_vv_tum-2.C  | 160 +
 .../riscv/rvv/base/vasubu_vv_tum-3.C  | 160 +
 .../riscv/rvv/base/vasubu_vv_tumu-1.C | 160 +
 .../riscv/rvv/base/vasubu_vv_tumu-2.C | 160 +
 .../riscv/rvv/base/vasubu_vv_tumu-3.C | 160 +
 15 files changed, 2862 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv-1.C
new file mode 100644
index 000..f305e2b42d2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vasubu(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+return __riscv_vasubu(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vasubu(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+return __riscv_vasubu(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vasubu(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+return __riscv_vasubu(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vasubu(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+return __riscv_vasubu(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vasubu(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+return __riscv_vasubu(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vasubu(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+return __riscv_vasubu(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vasubu(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+return __riscv_vasubu(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vasubu(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+return __riscv_vasubu(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vasubu(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+return __riscv_vasubu(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vasubu(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+return __riscv_vasubu(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vasubu(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+return __riscv_vasubu(op1,op2,vl);
+}
+
+
+vuint16m4_t test___

[PATCH] RISC-V: Add vasub.vv C++ api tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vasub_vv-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vv-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vv-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vasub_vv-1.C| 314 ++
 .../g++.target/riscv/rvv/base/vasub_vv-2.C| 314 ++
 .../g++.target/riscv/rvv/base/vasub_vv-3.C| 314 ++
 .../g++.target/riscv/rvv/base/vasub_vv_mu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vasub_vv_mu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vasub_vv_mu-3.C | 160 +
 .../g++.target/riscv/rvv/base/vasub_vv_tu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vasub_vv_tu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vasub_vv_tu-3.C | 160 +
 .../riscv/rvv/base/vasub_vv_tum-1.C   | 160 +
 .../riscv/rvv/base/vasub_vv_tum-2.C   | 160 +
 .../riscv/rvv/base/vasub_vv_tum-3.C   | 160 +
 .../riscv/rvv/base/vasub_vv_tumu-1.C  | 160 +
 .../riscv/rvv/base/vasub_vv_tumu-2.C  | 160 +
 .../riscv/rvv/base/vasub_vv_tumu-3.C  | 160 +
 15 files changed, 2862 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv-1.C
new file mode 100644
index 000..33561525000
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vasub(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+return __riscv_vasub(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vasub(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+return __riscv_vasub(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vasub(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+return __riscv_vasub(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vasub(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+return __riscv_vasub(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vasub(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+return __riscv_vasub(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vasub(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+return __riscv_vasub(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vasub(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+return __riscv_vasub(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vasub(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+return __riscv_vasub(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vasub(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+return __riscv_vasub(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vasub(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+return __riscv_vasub(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vasub(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+return __riscv_vasub(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vasub(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+return __riscv_vasub(op1,op2

[PATCH] RISC-V: Add vaaddu.vv C++ api tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vaaddu_vv-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vaaddu_vv-1.C   | 314 ++
 .../g++.target/riscv/rvv/base/vaaddu_vv-2.C   | 314 ++
 .../g++.target/riscv/rvv/base/vaaddu_vv-3.C   | 314 ++
 .../riscv/rvv/base/vaaddu_vv_mu-1.C   | 160 +
 .../riscv/rvv/base/vaaddu_vv_mu-2.C   | 160 +
 .../riscv/rvv/base/vaaddu_vv_mu-3.C   | 160 +
 .../riscv/rvv/base/vaaddu_vv_tu-1.C   | 160 +
 .../riscv/rvv/base/vaaddu_vv_tu-2.C   | 160 +
 .../riscv/rvv/base/vaaddu_vv_tu-3.C   | 160 +
 .../riscv/rvv/base/vaaddu_vv_tum-1.C  | 160 +
 .../riscv/rvv/base/vaaddu_vv_tum-2.C  | 160 +
 .../riscv/rvv/base/vaaddu_vv_tum-3.C  | 160 +
 .../riscv/rvv/base/vaaddu_vv_tumu-1.C | 160 +
 .../riscv/rvv/base/vaaddu_vv_tumu-2.C | 160 +
 .../riscv/rvv/base/vaaddu_vv_tumu-3.C | 160 +
 15 files changed, 2862 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv-1.C
new file mode 100644
index 000..d9dba2e3217
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vaaddu(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+return __riscv_vaaddu(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vaaddu(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+return __riscv_vaaddu(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vaaddu(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+return __riscv_vaaddu(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vaaddu(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+return __riscv_vaaddu(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vaaddu(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+return __riscv_vaaddu(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vaaddu(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+return __riscv_vaaddu(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vaaddu(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+return __riscv_vaaddu(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vaaddu(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+return __riscv_vaaddu(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vaaddu(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+return __riscv_vaaddu(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vaaddu(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+return __riscv_vaaddu(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vaaddu(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+return __riscv_vaaddu(op1,op2,vl);
+}
+
+
+vuint16m4_t test___

[PATCH] RISC-V: Add vaadd.vv C++ API tests

[juzhe . zhong]

From: Ju-Zhe Zhong 

gcc/testsuite/ChangeLog:

* g++.target/riscv/rvv/base/vaadd_vv-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vaadd_vv-1.C| 314 ++
 .../g++.target/riscv/rvv/base/vaadd_vv-2.C| 314 ++
 .../g++.target/riscv/rvv/base/vaadd_vv-3.C| 314 ++
 .../g++.target/riscv/rvv/base/vaadd_vv_mu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vaadd_vv_mu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vaadd_vv_mu-3.C | 160 +
 .../g++.target/riscv/rvv/base/vaadd_vv_tu-1.C | 160 +
 .../g++.target/riscv/rvv/base/vaadd_vv_tu-2.C | 160 +
 .../g++.target/riscv/rvv/base/vaadd_vv_tu-3.C | 160 +
 .../riscv/rvv/base/vaadd_vv_tum-1.C   | 160 +
 .../riscv/rvv/base/vaadd_vv_tum-2.C   | 160 +
 .../riscv/rvv/base/vaadd_vv_tum-3.C   | 160 +
 .../riscv/rvv/base/vaadd_vv_tumu-1.C  | 160 +
 .../riscv/rvv/base/vaadd_vv_tumu-2.C  | 160 +
 .../riscv/rvv/base/vaadd_vv_tumu-3.C  | 160 +
 15 files changed, 2862 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-1.C 
b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-1.C
new file mode 100644
index 000..c75b9398e6b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
-fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd(vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd(vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd(vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd(vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd(vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd(vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd(vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+return __riscv_vaadd(op1,op2

Re: [PATCH] PR tree-optimization/108520 - Add function context for querying global ranges.

[Richard Biener via Gcc-patches]

On Fri, Feb 10, 2023 at 1:02 AM Andrew MacLeod via Gcc-patches
 wrote:
>
> I was about to ping on this, and then found it in my drafts.. Doh!
>
>
> get_range_global() can invoke tree.cc::nonnull_arg_p() if the item being
> queried is a pointer and a parameter.  This routine assumes the context
> is CFUN, and this is not always true.

Can you share the backtrace where the context is different and cfun not NULL?
I'm curious ..

> This patch simply adds a function context to the get_range_global query,
> and defaults it to cfun. If the context passed in is anything different
> than cfun, then it simply chooses not to invoke nonnull_arg_p().
>
> The check_assume function now directly calls gimple_range_global with
> the correct function context instead of indirectly calling it through
> the global_range_query->range_of_expr () method. Thats all it should
> have been doing in the first place really since its always an ssa name.
>
> Bootstraps on x86_64-pc-linux-gnu with no regressions.  OK for trunk?

OK.

Note that in the end nonnull_arg_p should get a struct function argument
as well, and its flag_delete_null_pointer_checks then need to become
opt_for_fn (fn->decl, flag_delete_null_pointer_checks).

I'll also note that for functions with many arguments nonnull_arg_p is
quite expensive and nonnull_arg_p on a PARM_DECL default-def
should be reflected on its range by a pass and we shouldn't re-query
this in any on-demand called function.

Richard.

> Andrew
>
>

Re: [COMMITTED] tree-optimization: [PR108684] ICE in verify_ssa due to simple_dce_from_worklist

[Richard Biener via Gcc-patches]

On Fri, Feb 10, 2023 at 2:47 AM Andrew Pinski via Gcc-patches
 wrote:
>
> In simple_dce_from_worklist, we were removing an inline-asm which had a vdef.
> We should not be removing inline-asm which have a vdef as this code
> does not check to the store.
> This fixes that oversight. This was a latent bug exposed recently
> by both VRP and removal of stores to static starting to use
> simple_dce_from_worklist.
>
> Committed as approved.
> Bootstrapped and tested on x86_64-linux-gnu with no regressions.
>
> PR tree-optimization/108684
>
> gcc/ChangeLog:
>
> * tree-ssa-dce.cc (simple_dce_from_worklist):
> Check all ssa names and not just non-vdef ones
> before accepting the inline-asm.
> Call unlink_stmt_vdef on the statement before
> removing it.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.c-torture/compile/dce-inline-asm-1.c: New test.
> * gcc.c-torture/compile/dce-inline-asm-2.c: New test.
> * gcc.dg/tree-ssa/pr108684-1.c: New test.
>
> co-authored-by: Andrew Macleod  
> ---
>  .../gcc.c-torture/compile/dce-inline-asm-1.c   | 15 +++
>  .../gcc.c-torture/compile/dce-inline-asm-2.c   | 16 
>  gcc/testsuite/gcc.dg/tree-ssa/pr108684-1.c | 18 ++
>  gcc/tree-ssa-dce.cc|  5 +++--
>  4 files changed, 52 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c
>  create mode 100644 gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c
>  create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr108684-1.c
>
> diff --git a/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c 
> b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c
> new file mode 100644
> index 000..a9f02e44bd7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c
> @@ -0,0 +1,15 @@
> +/* PR tree-optimization/108684 */
> +/* This used to ICE as when we remove the store to
> +   `t`, we also would remove the inline-asm which
> +   had a VDEF on it but we didn't update the
> +   VUSE that was later on.  */
> +static int t;
> +
> +int f (int *a)
> +{
> +  int t1;
> +  asm (" " : "=X" (t1) : : "memory");
> +  t = t1;
> +  return *a;
> +}
> +
> diff --git a/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c 
> b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c
> new file mode 100644
> index 000..a41b16e4bd0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c
> @@ -0,0 +1,16 @@
> +/* PR tree-optimization/108684 */
> +/* This used to ICE as when we removed the
> +   __builtin_unreachable in VRP, as we
> +   would also remove the branch and the
> +   inline-asm. The inline-asm had a VDEF on it,
> +   which we didn't update further along and
> +   not have the VDEF on the return statement
> +   updated.  */
> +
> +int f (int a)
> +{
> +  asm (" " : "=X" (a) : : "memory");
> +  if (a)
> +return 0;
> +  __builtin_unreachable();
> +}
> diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr108684-1.c 
> b/gcc/testsuite/gcc.dg/tree-ssa/pr108684-1.c
> new file mode 100644
> index 000..3ba206f765e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr108684-1.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -fdump-tree-optimized" } */
> +
> +
> +static int t;
> +
> +int f (int *a)
> +{
> +  int t1, t2 = 0;
> +  asm ("shouldshowupstill %1" : "=r" (t1), "=m"(t2) : : );
> +  t = t1;
> +  return t2;
> +}
> +
> +/* Check to make sure DCE does not remove the inline-asm as it writes to t2. 
> */
> +/* We used to DCE this inline-asm when removing the store to t. */
> +/* { dg-final { scan-assembler "shouldshowupstill" } } */
> +/* { dg-final { scan-tree-dump-times "shouldshowupstill" 1 "optimized" } } */
> diff --git a/gcc/tree-ssa-dce.cc b/gcc/tree-ssa-dce.cc
> index b2fe9f4f55e..1f1ec2c8710 100644
> --- a/gcc/tree-ssa-dce.cc
> +++ b/gcc/tree-ssa-dce.cc
> @@ -2108,9 +2108,9 @@ simple_dce_from_worklist (bitmap worklist)
>
>/* The defining statement needs to be defining only this name.
>  ASM is the only statement that can define more than one
> -(non-virtual) name. */
> +name. */
>if (is_a(t)
> - && !single_ssa_def_operand (t, SSA_OP_DEF))
> + && !single_ssa_def_operand (t, SSA_OP_ALL_DEFS))
> continue;
>
>/* Don't remove statements that are needed for non-call
> @@ -2140,6 +2140,7 @@ simple_dce_from_worklist (bitmap worklist)
> remove_phi_node (&gsi, true);
>else
> {
> + unlink_stmt_vdef (t);

note this should never do anything

>   gsi_remove (&gsi, true);
>   release_defs (t);
> }
> --
> 2.27.0
>

Re: [PATCH] PR tree-optimization/108687 - Query rangers cache in readonly mode only internally

[Richard Biener via Gcc-patches]

On Fri, Feb 10, 2023 at 3:38 AM Andrew MacLeod  wrote:
>
>
> The change for 108356 allowed the cache to scan the dominator trees when
> it was attempting a lookup rather than using the local value.  I
> inadvertantly changed the external interface to also do this, so all the
> GORI queries via range_on_edge of the cache could also do lookups in
> this mode.
>
> This triggered a quadratic, possible exponential time increase when the
> right conditions were presented. That being a cascading series of
> recomputations on outgoing edge calculations that at then searched the
> dom tree instead of being a simple calculation using whats easily available.
>
> The fix is to use the internal API within the cache rather than the
> extrenal one that GORI uses.   This leaves GORI computations to be
> resolved in linear time.  GORI is designed to only use what immediately
> available and should never trigger new lookups of its own.  Doh.
>
> This may possibly fix a a few other new large time growth issues in DOM
> and friends,  such as 108705.
>
> bootstrapped on x86_64-pc-linux-gnu, regtesting ongoing.. assuming no
> issues, OK for trunk?

OK.

Thanks,
Richard.

> Andrew