Re: [PATCH] target/108738 - limit STV chain discovery

[Uros Bizjak via Gcc-patches]

On Thu, Mar 2, 2023 at 2:28 PM Richard Biener  wrote:
>
> The following puts a hard limit on the inherently quadratic STV chain
> discovery.  Without a limit for the compiler.i testcase in PR26854
> we see at -O2
>
>  machine dep reorg  : 574.45 ( 53%)
>
> with release checking while with the proposed limit it's
>
>  machine dep reorg  :   2.86 (  1%)
>
> Bootstrapped and tested on x86_64-unknown-linux-gnu.
>
> OK?
>
> Thanks,
> Richard.
>
> PR target/108738
> * config/i386/i386.opt (--param x86-stv-max-visits): New param.
> * doc/invoke.texi (--param x86-stv-max-visits): Document it.
> * config/i386/i386-features.h (scalar_chain::max_visits): New.
> (scalar_chain::build): Add bitmap parameter, return boolean.
> (scalar_chain::add_insn): Likewise.
> (scalar_chain::analyze_register_chain): Likewise.
> * config/i386/i386-features.cc (scalar_chain::scalar_chain):
> Initialize max_visits.
> (scalar_chain::analyze_register_chain): When we exhaust
> max_visits, abort.  Also abort when running into any
> disallowed insn.
> (scalar_chain::add_insn): Propagate abort.
> (scalar_chain::build): Likewise.  When aborting amend
> the set of disallowed insn with the insns set.
> (convert_scalars_to_vector): Adjust.  Do not convert aborted
> chains.

LGTM.

Thanks,
Uros.

> ---
>  gcc/config/i386/i386-features.cc | 77 +++-
>  gcc/config/i386/i386-features.h  | 10 +++--
>  gcc/config/i386/i386.opt |  4 ++
>  gcc/doc/invoke.texi  |  4 ++
>  4 files changed, 70 insertions(+), 25 deletions(-)
>
> diff --git a/gcc/config/i386/i386-features.cc 
> b/gcc/config/i386/i386-features.cc
> index eff91301009..c09abf8fc20 100644
> --- a/gcc/config/i386/i386-features.cc
> +++ b/gcc/config/i386/i386-features.cc
> @@ -296,6 +296,8 @@ scalar_chain::scalar_chain (enum machine_mode smode_, 
> enum machine_mode vmode_)
>
>n_sse_to_integer = 0;
>n_integer_to_sse = 0;
> +
> +  max_visits = x86_stv_max_visits;
>  }
>
>  /* Free chain's data.  */
> @@ -354,10 +356,12 @@ scalar_chain::mark_dual_mode_def (df_ref def)
>  }
>
>  /* Check REF's chain to add new insns into a queue
> -   and find registers requiring conversion.  */
> +   and find registers requiring conversion.  Return true if OK, false
> +   if the analysis was aborted.  */
>
> -void
> -scalar_chain::analyze_register_chain (bitmap candidates, df_ref ref)
> +bool
> +scalar_chain::analyze_register_chain (bitmap candidates, df_ref ref,
> + bitmap disallowed)
>  {
>df_link *chain;
>bool mark_def = false;
> @@ -371,6 +375,9 @@ scalar_chain::analyze_register_chain (bitmap candidates, 
> df_ref ref)
>if (!NONDEBUG_INSN_P (DF_REF_INSN (chain->ref)))
> continue;
>
> +  if (--max_visits == 0)
> +   return false;
> +
>if (!DF_REF_REG_MEM_P (chain->ref))
> {
>   if (bitmap_bit_p (insns, uid))
> @@ -381,6 +388,10 @@ scalar_chain::analyze_register_chain (bitmap candidates, 
> df_ref ref)
>   add_to_queue (uid);
>   continue;
> }
> +
> + /* If we run into parts of an aborted chain discovery abort.  */
> + if (bitmap_bit_p (disallowed, uid))
> +   return false;
> }
>
>if (DF_REF_REG_DEF_P (chain->ref))
> @@ -401,15 +412,19 @@ scalar_chain::analyze_register_chain (bitmap 
> candidates, df_ref ref)
>
>if (mark_def)
>  mark_dual_mode_def (ref);
> +
> +  return true;
>  }
>
> -/* Add instruction into a chain.  */
> +/* Add instruction into a chain.  Return true if OK, false if the search
> +   was aborted.  */
>
> -void
> -scalar_chain::add_insn (bitmap candidates, unsigned int insn_uid)
> +bool
> +scalar_chain::add_insn (bitmap candidates, unsigned int insn_uid,
> +   bitmap disallowed)
>  {
>if (!bitmap_set_bit (insns, insn_uid))
> -return;
> +return true;
>
>if (dump_file)
>  fprintf (dump_file, "  Adding insn %d to chain #%d\n", insn_uid, 
> chain_id);
> @@ -426,22 +441,27 @@ scalar_chain::add_insn (bitmap candidates, unsigned int 
> insn_uid)
>df_ref ref;
>for (ref = DF_INSN_UID_DEFS (insn_uid); ref; ref = DF_REF_NEXT_LOC (ref))
>  if (!HARD_REGISTER_P (DF_REF_REG (ref)))
> -  analyze_register_chain (candidates, ref);
> +  if (!analyze_register_chain (candidates, ref, disallowed))
> +   return false;
>
>/* The operand(s) of VEC_SELECT don't need to be converted/convertible.  */
>if (def_set && GET_CODE (SET_SRC (def_set)) == VEC_SELECT)
> -return;
> +return true;
>
>for (ref = DF_INSN_UID_USES (insn_uid); ref; ref = DF_REF_NEXT_LOC (ref))
>  if (!DF_REF_REG_MEM_P (ref))
> -  analyze_register_chain (candidates, ref);
> +  if (!analyze_register_chain (candidates, ref, disallowed))
> +   return false;
> +
> +  retu

Re: [PATCH 01/07] RISC-V: Add auto-vectorization support

[Xi Ruoyao via Gcc-patches]

Please don't use the same title for all the patches.  This will puzzle
people running "git log" once they are committed.

And when you send 01-07, use "reply" instead of "new" so they will show
up in the correct location in a mail client.  Or use git send-email
which is much eaiser to use.

On Thu, 2023-03-02 at 23:52 -0500, Michael Collison wrote:
> This patch adds foundational support in the form of:
> 
> 1. New predicates
> 
> 2. New function prototypes
> 
> 3. Exporting emit_vlmax_vsetvl to global scope
> 
> 4. Add a new command line option -mriscv_vector_lmul
> 
> gcc/ChangeLog:
> 
>  * config/riscv/riscv-protos.h (riscv_classify_vlmul_field):

The change log entries should be indented with one tab, not some
whitespaces.

-- 
Xi Ruoyao 
School of Aerospace Science and Technology, Xidian University

[PATCH 07/07] RISC-V: Add auto-vectorization support

[Michael Collison]

This patch adds tests for autovectorization of integer add and subtract.

gcc/testsuite/ChangeLog:

    * gcc.target/riscv/rvv/autovec: New directory
    for autovectorization tests.
    * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New
    test to verify code generation of vector add on rv32.
    * gcc.target/riscv/rvv/autovec/loop-add.c: New
    test to verify code generation of vector add on rv64.
    * gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: New
    test to verify code generation of vector subtract on rv32.
    * gcc.target/riscv/rvv/autovec/loop-sub.c: New
    test to verify code generation of vector subtract on rv64.

---
 .../riscv/rvv/autovec/loop-add-rv32.c | 24 +++
 .../gcc.target/riscv/rvv/autovec/loop-add.c   | 24 +++
 .../riscv/rvv/autovec/loop-sub-rv32.c | 24 +++
 .../gcc.target/riscv/rvv/autovec/loop-sub.c   | 24 +++
 4 files changed, 96 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c

 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c

 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c

new file mode 100644
index 000..bdc3b6892e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv 
-mabi=ilp32d" } */

+
+#include 
+
+#define TEST_TYPE(TYPE)                 \
+  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)    \
+  {                            \
+    for (int i = 0; i < n; i++)                \
+  dst[i] = a[i] + b[i];                \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()    \
+ TEST_TYPE(int16_t)    \
+ TEST_TYPE(uint16_t)    \
+ TEST_TYPE(int32_t)    \
+ TEST_TYPE(uint32_t)    \
+ TEST_TYPE(int64_t)    \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c

new file mode 100644
index 000..d7f992c7d27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv 
-mabi=lp64d" } */

+
+#include 
+
+#define TEST_TYPE(TYPE)                 \
+  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)    \
+  {                            \
+    for (int i = 0; i < n; i++)                \
+  dst[i] = a[i] + b[i];                \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()    \
+ TEST_TYPE(int16_t)    \
+ TEST_TYPE(uint16_t)    \
+ TEST_TYPE(int32_t)    \
+ TEST_TYPE(uint32_t)    \
+ TEST_TYPE(int64_t)    \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c

new file mode 100644
index 000..7d0a40ec539
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv 
-mabi=ilp32d" } */

+
+#include 
+
+#define TEST_TYPE(TYPE)                 \
+  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)    \
+  {                            \
+    for (int i = 0; i < n; i++)                \
+  dst[i] = a[i] - b[i];                \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()    \
+ TEST_TYPE(int16_t)    \
+ TEST_TYPE(uint16_t)    \
+ TEST_TYPE(int32_t)    \
+ TEST_TYPE(uint32_t)    \
+ TEST_TYPE(int64_t)    \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c

new file mode 100644
index 000..c8900884f83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv 
-mabi=lp64d" } */

+
+#include 
+
+#define TEST_TYPE(TYPE)                 \
+  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)    \
+  {                            \
+    for (int i = 0; i < n; i++)                \
+  dst[i] = a[i] - b[i];                \
+  }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL()    \
+ TEST_TYPE(int16_t)    \
+ TEST_TYPE(uint16_t)    \
+ TEST_TYPE(int32_t)    \
+ TEST_TYPE(uint32_t)    \
+ TEST_TYPE(int64_t)    \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-time

[PATCH 06/07] RISC-V: Add auto-vectorization support

[Michael Collison]

This patch adds patterns that provide basic autovectorization support 
for integer adds and subtracts.


gcc/ChangeLog:

    * config/riscv/riscv.md (riscv_classify_vlmul_field):
    New external declaration.
    (riscv_vector_preferred_simd_mode): Include
    vector-iterators.md.
    * config/riscv/vector-auto.md: New file containing
    autovectorization patterns.
    * config/riscv/vector-iterators.md (UNSPEC_VADD/UNSPEC_VSUB):
    New unspecs for autovectorization patterns.
    * config/riscv/vector.md: Remove include of vector-iterators.md
    and include vector-auto.md.

---
 gcc/config/riscv/riscv.md    |   1 +
 gcc/config/riscv/vector-auto.md  | 172 +++
 gcc/config/riscv/vector-iterators.md |   2 +
 gcc/config/riscv/vector.md   |   4 +-
 4 files changed, 177 insertions(+), 2 deletions(-)
 create mode 100644 gcc/config/riscv/vector-auto.md

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 05924e9bbf1..c34124095f7 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -131,6 +131,7 @@
 (include "predicates.md")
 (include "constraints.md")
 (include "iterators.md")
+(include "vector-iterators.md")

 ;; 
 ;;
diff --git a/gcc/config/riscv/vector-auto.md 
b/gcc/config/riscv/vector-auto.md

new file mode 100644
index 000..e5a19663d18
--- /dev/null
+++ b/gcc/config/riscv/vector-auto.md
@@ -0,0 +1,172 @@
+;; Machine description for RISC-V 'V' Extension for GNU compiler.
+;; Copyright (C) 2022-2023 Free Software Foundation, Inc.
+;; Contributed by Juzhe Zhong (juzhe.zh...@rivai.ai), RiVAI 
Technologies Ltd.

+;; Contributed by Michael Collison (colli...@rivosinc.com, Rivos Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+
+;; 
-

+;;  [INT] Addition
+;; 
-

+;; Includes:
+;; - vadd.vv
+;; - vadd.vx
+;; - vadd.vi
+;; 
-

+
+(define_expand "add3"
+  [(match_operand:VI 0 "register_operand")
+   (match_operand:VI 1 "register_operand")
+   (match_operand:VI 2 "vector_arith_operand")]
+  "TARGET_VECTOR"
+{
+  using namespace riscv_vector;
+
+  rtx merge = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), 
UNSPEC_VUNDEF);

+  rtx vl = emit_vlmax_vsetvl (mode);
+  rtx mask_policy = get_mask_policy_no_pred();
+  rtx tail_policy = get_tail_policy_no_pred();
+  rtx mask = CONSTM1_RTX(mode);
+  rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
+
+  emit_insn(gen_pred_add(operands[0], mask, merge, operands[1], 
operands[2],

+                vl, tail_policy, mask_policy, vlmax_avl_p));
+
+  DONE;
+})
+
+(define_expand "cond_add"
+  [(match_operand:VI 0 "register_operand")
+   (match_operand: 1 "register_operand")
+   (match_operand:VI 2 "register_operand")
+   (match_operand:VI 3 "vector_reg_or_const_dup_operand")
+   (match_operand:VI 4 "register_operand")]
+  "TARGET_VECTOR"
+{
+  using namespace riscv_vector;
+
+  rtx merge = operands[4];
+  rtx vl = emit_vlmax_vsetvl (mode);
+  rtx mask_policy = get_mask_policy_no_pred();
+  rtx tail_policy = get_tail_policy_no_pred();
+  rtx mask = operands[1];
+  rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
+
+  emit_insn(gen_pred_add(operands[0], mask, merge, operands[2], 
operands[3],

+                vl, tail_policy, mask_policy, vlmax_avl_p));
+  DONE;
+})
+
+(define_expand "len_add"
+  [(match_operand:VI 0 "register_operand")
+   (match_operand:VI 1 "register_operand")
+   (match_operand:VI 2 "vector_reg_or_const_dup_operand")
+   (match_operand 3 "p_reg_or_const_csr_operand")]
+  "TARGET_VECTOR"
+{
+  using namespace riscv_vector;
+
+  rtx merge = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), 
UNSPEC_VUNDEF);

+  rtx vl = operands[3];
+  rtx mask_policy = get_mask_policy_no_pred();
+  rtx tail_policy = get_tail_policy_no_pred();
+  rtx mask = CONSTM1_RTX(mode);
+  rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
+
+  emit_insn(gen_pred_add(operands[0], mask, merge, operands[1], 
operands[2],

+                vl, tail_policy, mask_policy, vlmax_avl_p));
+  DONE;
+})
+
+
+;; 
-

+;;  [INT] Subtraction
+;; 

[PATCH 05/07] RISC-V: Add auto-vectorization support

[Michael Collison]

This patch adds support for registering target hooks for basic 
autovectorization support as well as basic tuning information for the 
vector extension.


gcc/ChangeLog:

    * config/riscv/riscv-cores.def (RISCV_TUNE):
    Add VECTOR_TUNE_INFO parameter and
    * common/config/riscv/riscv-common.cc (RISCV_TUNE):
    Add VECTOR_TUNE_INFO parameter.
    * config/riscv/riscv.cc (riscv_vector_tune_param):
    New struct for vector tuning information.
    (riscv_tune_info): add vector_tune_param.
    (vector_tune_param): New static variable.
    (riscv_vectorization_factor): New variable.
    (generic_rvv_insn_scale_table): New struct.
    (generic_rvv_stmt_scale_table): New struct.
    (generic_rvv_insn_cost_table): New vector insn cost table.
    (generic_rvv_stmt_cost_table): New vector statement cost table.
    (generic_rvv_tune_info): New rvv tuning table.
    (RISCV_TUNE): Add VECTOR_TUNE_INFO parameter.
    (riscv_rtx_costs): Return vector estimate if vector mode.
    (riscv_option_override): Set vector_tune_param.
    (riscv_option_override): Set riscv_vectorization_factor.
    (riscv_estimated_poly_value): Implement
    TARGET_ESTIMATED_POLY_VALUE.
    (riscv_preferred_simd_mode): Implement
    TARGET_VECTORIZE_PREFERRED_SIMD_MODE.
    (riscv_autovectorize_vector_modes): Implement
    TARGET_AUTOVECTORIZE_VECTOR_MODES.
    (riscv_get_mask_mode): Implement TARGET_VECTORIZE_GET_MASK_MODE.
    (riscv_empty_mask_is_expensive): Implement
    TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE.
    (riscv_builtin_vectorization_cost): Implement
    TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST.
    (riscv_vectorize_create_costs): Implement
    TARGET_VECTORIZE_CREATE_COSTS.
    (TARGET_ESTIMATED_POLY_VALUE): Register target macro.
    (TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST): Ditto.
    (TARGET_VECTORIZE_PREFERRED_SIMD_MODE): Ditto.
    (TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): Ditto.
    (TARGET_VECTORIZE_GET_MASK_MODE): Ditto.
    (TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE): Ditto.
    (TARGET_VECTORIZE_LOOP_LEN_OVERRIDE_MASK): Ditto.
    (TARGET_VECTORIZE_CREATE_COSTS): Ditto

---
 gcc/common/config/riscv/riscv-common.cc |   2 +-
 gcc/config/riscv/riscv-cores.def    |  14 +-
 gcc/config/riscv/riscv.cc   | 321 +++-
 3 files changed, 325 insertions(+), 12 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc

index ebc1ed7d7e4..6b8d92af986 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -246,7 +246,7 @@ static const riscv_cpu_info riscv_cpu_tables[] =

 static const char *riscv_tunes[] =
 {
-#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO) \
+#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO, 
VECTOR_TUNE_INFO)    \

 TUNE_NAME,
 #include "../../../config/riscv/riscv-cores.def"
 NULL
diff --git a/gcc/config/riscv/riscv-cores.def 
b/gcc/config/riscv/riscv-cores.def

index 2a834cae21d..4feb0366222 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -30,15 +30,15 @@
    identifier, reference to riscv.cc.  */

 #ifndef RISCV_TUNE
-#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO)
+#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO, VECTOR_TUNE_INFO)
 #endif

-RISCV_TUNE("rocket", generic, rocket_tune_info)
-RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
-RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
-RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
-RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
-RISCV_TUNE("size", generic, optimize_size_tune_info)
+RISCV_TUNE("rocket", generic, rocket_tune_info, generic_rvv_tune_info)
+RISCV_TUNE("sifive-3-series", generic, rocket_tune_info, 
generic_rvv_tune_info)
+RISCV_TUNE("sifive-5-series", generic, rocket_tune_info, 
generic_rvv_tune_info)
+RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info, 
generic_rvv_tune_info)
+RISCV_TUNE("thead-c906", generic, thead_c906_tune_info, 
generic_rvv_tune_info)

+RISCV_TUNE("size", generic, optimize_size_tune_info, generic_rvv_tune_info)

 #undef RISCV_TUNE

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f11b7949a49..16b38ba4d76 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -60,6 +60,16 @@ along with GCC; see the file COPYING3.  If not see
 #include "opts.h"
 #include "tm-constrs.h"
 #include "rtl-iter.h"
+#include "gimple.h"
+#include "cfghooks.h"
+#include "cfgloop.h"
+#include "cfgrtl.h"
+#include "sel-sched.h"
+#include "fold-const.h"
+#include "gimple-iterator.h"
+#include "gimple-expr.h"
+#include "tree-vectorizer.h"
+#include "riscv-vector-cost.h"

 /* This file should be included last.  */
 #include "target-def.h"
@@ -238,6 +248,12 @@ struct riscv_tune_param
   bool slow_unaligned_access;
 };

+/* Cost for vector insn classes.  */
+struct riscv_vector_tune_param {
+    const vector_insn_cost_table* rvv_insn_costs_table;

[PATCH 04/07] RISC-V: Add auto-vectorization support

[Michael Collison]

This patch adds support for functions used in implementing various 
portions of autovectorization support.


gcc/ChangeLog:

    * config/riscv/riscv-v.cc (riscv_classify_vlmul_field):
    New function.
    (riscv_vector_preferred_simd_mode): Ditto.
    (get_mask_policy_no_pred): Ditto.
    (get_tail_policy_no_pred): Ditto.
    (riscv_tuple_mode_p): Ditto.
    (riscv_classify_nf): Ditto.
    (riscv_vlmul_regsize): Ditto.
    (riscv_vector_mask_mode_p): Ditto.
    (riscv_vector_get_mask_mode): Ditto.

---
 gcc/config/riscv/riscv-v.cc | 176 
 1 file changed, 176 insertions(+)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 58007cc16eb..58f69e259c0 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -39,9 +39,11 @@
 #include "emit-rtl.h"
 #include "tm_p.h"
 #include "target.h"
+#include "targhooks.h"
 #include "expr.h"
 #include "optabs.h"
 #include "tm-constrs.h"
+#include "riscv-vector-builtins.h"

 using namespace riscv_vector;

@@ -108,6 +110,41 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT 
minval,

   && IN_RANGE (INTVAL (elt), minval, maxval));
 }

+/* Return the vlmul field for a specific machine mode. */
+unsigned int
+riscv_classify_vlmul_field (enum machine_mode mode)
+{
+  /* Make the decision based on the mode's enum value rather than its
+ properties, so that we keep the correct classification regardless
+ of -mriscv-vector-bits.  */
+  switch (mode)
+    {
+    case E_VNx8BImode:
+  return VLMUL_FIELD_111;
+
+    case E_VNx4BImode:
+  return VLMUL_FIELD_110;
+
+    case E_VNx2BImode:
+  return VLMUL_FIELD_101;
+
+    case E_VNx16BImode:
+  return VLMUL_FIELD_000;
+
+    case E_VNx32BImode:
+  return VLMUL_FIELD_001;
+
+    case E_VNx64BImode:
+  return VLMUL_FIELD_010;
+
+    default:
+  break;
+    }
+
+  /* we don't care about VLMUL for Mask */
+  return VLMUL_FIELD_000;
+}
+
 rtx
 emit_vlmax_vsetvl (machine_mode vmode)
 {
@@ -162,6 +199,64 @@ calculate_ratio (unsigned int sew, enum vlmul_type 
vlmul)

   return ratio;
 }

+/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV.  */
+
+machine_mode
+riscv_vector_preferred_simd_mode (scalar_mode mode, unsigned vf)
+{
+  if (!TARGET_VECTOR)
+    return word_mode;
+
+  switch (mode)
+    {
+    case E_QImode:
+  return vf == 1   ? VNx8QImode
+     : vf == 2 ? VNx16QImode
+     : vf == 4 ? VNx32QImode
+           : VNx64QImode;
+  break;
+    case E_HImode:
+  return vf == 1   ? VNx4HImode
+     : vf == 2 ? VNx8HImode
+     : vf == 4 ? VNx16HImode
+           : VNx32HImode;
+  break;
+    case E_SImode:
+  return vf == 1   ? VNx2SImode
+     : vf == 2 ? VNx4SImode
+     : vf == 4 ? VNx8SImode
+           : VNx16SImode;
+  break;
+    case E_DImode:
+  if (riscv_vector_elen_flags != MASK_VECTOR_ELEN_32
+      && riscv_vector_elen_flags != MASK_VECTOR_ELEN_FP_32)
+    return vf == 1     ? VNx1DImode
+       : vf == 2 ? VNx2DImode
+       : vf == 4 ? VNx4DImode
+             : VNx8DImode;
+  break;
+    case E_SFmode:
+  if (TARGET_HARD_FLOAT && riscv_vector_elen_flags != 
MASK_VECTOR_ELEN_32

+      && riscv_vector_elen_flags != MASK_VECTOR_ELEN_64)
+    return vf == 1     ? VNx2SFmode
+       : vf == 2 ? VNx4SFmode
+       : vf == 4 ? VNx8SFmode
+             : VNx16SFmode;
+  break;
+    case E_DFmode:
+  if (TARGET_DOUBLE_FLOAT && TARGET_VECTOR_ELEN_FP_64)
+    return vf == 1     ? VNx1DFmode
+       : vf == 2 ? VNx2DFmode
+       : vf == 4 ? VNx4DFmode
+             : VNx8DFmode;
+  break;
+    default:
+  break;
+    }
+
+  return word_mode;
+}
+
 /* Emit an RVV unmask && vl mov from SRC to DEST.  */
 static void
 emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len,
@@ -374,6 +469,87 @@ get_avl_type_rtx (enum avl_type type)
   return gen_int_mode (type, Pmode);
 }

+rtx
+get_mask_policy_no_pred ()
+{
+  return get_mask_policy_for_pred(PRED_TYPE_none);
+}
+
+rtx
+get_tail_policy_no_pred ()
+{
+  return get_mask_policy_for_pred(PRED_TYPE_none);
+}
+
+/* Return true if it is a RVV tuple mode. */
+bool
+riscv_tuple_mode_p (machine_mode mode ATTRIBUTE_UNUSED)
+{
+  return false;
+}
+
+/* Return nf for a machine mode. */
+int
+riscv_classify_nf (machine_mode mode)
+{
+  switch (mode)
+    {
+
+    default:
+  break;
+    }
+
+  return 1;
+}
+
+/* Return vlmul register size for a machine mode. */
+int
+riscv_vlmul_regsize (machine_mode mode)
+{
+  if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL)
+    return 1;
+  switch (riscv_classify_vlmul_field (mode))
+    {
+    case VLMUL_FIELD_001:
+  return 2;
+    case VLMUL_FIELD_010:
+  return 4;
+    case VLMUL_FIELD_011:
+  return 8;
+    case VLMUL_FIELD_100:
+  gcc_unreachable ();
+    default:
+  return 1;
+    }
+}
+
+/* Return true if it is a RVV mask mode. */
+bool
+riscv_vector_mask_mode_p (machine_mode mode)

[PATCH 03/07] RISC-V: Add auto-vectorization support

[Michael Collison]

This patches adds two new files to support the vector cost model and 
modifies the Makefile fragment to build the cost model c++ file. Due to 
the large size this patch is provided as an attachment.


gcc/ChangeLog:

    * gcc/config.gcc (riscv-vector-cost.o): New object file to build.
    * config/riscv/riscv-vector-cost.cc: New file for riscv vector cost
    model
    * config/riscv/riscv-vector-cost.h: New header file for riscv vector
    cost model.
    * config/riscv/t-riscv: Add make rule for riscv-vector-cost.o.


From eb995818cd5f77f85e8df93b690b00ce1fd1aa35 Mon Sep 17 00:00:00 2001
From: Michael Collison 
Date: Thu, 2 Mar 2023 12:27:36 -0500
Subject: [PATCH] Autovectorization patch set 2

---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/riscv-vector-cost.cc | 620 ++
 gcc/config/riscv/riscv-vector-cost.h  | 400 +
 gcc/config/riscv/t-riscv  |   5 +
 4 files changed, 1026 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/riscv-vector-cost.cc
 create mode 100644 gcc/config/riscv/riscv-vector-cost.h

diff --git a/gcc/config.gcc b/gcc/config.gcc
index c070e6ecd2e..a401187 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -530,7 +530,7 @@ pru-*-*)
 riscv*)
 	cpu_type=riscv
 	extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o"
-	extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
+	extra_objs="${extra_objs} riscv-vector-cost.o riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
 	d_target_objs="riscv-d.o"
 	extra_headers="riscv_vector.h"
 	target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc"
diff --git a/gcc/config/riscv/riscv-vector-cost.cc b/gcc/config/riscv/riscv-vector-cost.cc
new file mode 100644
index 000..5a33b20843a
--- /dev/null
+++ b/gcc/config/riscv/riscv-vector-cost.cc
@@ -0,0 +1,620 @@
+/* Cost model implementation for RISC-V 'V' Extension for GNU compiler.
+   Copyright (C) 2022-2023 Free Software Foundation, Inc.
+   Contributed by Juzhe Zhong (juzhe.zh...@rivai.ai), RiVAI Technologies Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   .  */
+
+#define INCLUDE_STRING
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "backend.h"
+#include "rtl.h"
+#include "regs.h"
+#include "insn-config.h"
+#include "insn-attr.h"
+#include "recog.h"
+#include "rtlanal.h"
+#include "output.h"
+#include "alias.h"
+#include "tree.h"
+#include "stringpool.h"
+#include "attribs.h"
+#include "varasm.h"
+#include "stor-layout.h"
+#include "calls.h"
+#include "function.h"
+#include "explow.h"
+#include "memmodel.h"
+#include "emit-rtl.h"
+#include "reload.h"
+#include "tm_p.h"
+#include "target.h"
+#include "basic-block.h"
+#include "expr.h"
+#include "optabs.h"
+#include "bitmap.h"
+#include "df.h"
+#include "diagnostic.h"
+#include "builtins.h"
+#include "predict.h"
+#include "tree-pass.h"
+#include "opts.h"
+#include "langhooks.h"
+#include "rtl-iter.h"
+#include "gimple.h"
+#include "cfghooks.h"
+#include "cfgloop.h"
+#include "fold-const.h"
+#include "gimple-iterator.h"
+#include "tree-vectorizer.h"
+#include "tree-ssa-loop-niter.h"
+#include "riscv-vector-builtins.h"
+
+/* This file should be included last.  */
+#include "riscv-vector-cost.h"
+#include "target-def.h"
+
+bool vector_insn_cost_table::get_cost(rtx x, machine_mode mode, int *cost,
+  bool speed) const {
+  rtx op0, op1, op2;
+  enum rtx_code code = GET_CODE(x);
+  scalar_int_mode int_mode;
+
+  /* By default, assume that everything has equivalent cost to the
+ cheapest instruction.  Any additional costs are applied as a delta
+ above this default.  */
+  *cost = COSTS_N_INSNS(1);
+
+  switch (code) {
+  case SET:
+/* The cost depends entirely on the operands to SET.  */
+*cost = 0;
+op0 = SET_DEST(x);
+op1 = SET_SRC(x);
+
+switch (GET_CODE(op0)) {
+case MEM:
+  if (speed) {
+*cost += store->cost(x, mode);
+  }
+
+  //*cost += rtx_cost(op1, mode, SET, 1, speed);
+  return true;
+
+case SUBREG:
+  if (!REG_P(SUBREG_REG(op0)))
+*cost += rtx_cost(SUBREG_REG(op0), VOIDmode, SET, 0, speed);
+
+  /* Fal

[PATCH 02/07] RISC-V: Add auto-vectorization support

[Michael Collison]

This patch adds foundational support by making two functions that handle 
predication policies visibly globally.


gcc/ChangeLog:

    * config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred):
    Remove static declaration to to make externally visible.
    (get_mask_policy_for_pred): Ditto.
    * config/riscv/riscv-vector-builtins.h (get_tail_policy_for_pred):
    New external declaration.
    (get_mask_policy_for_pred): Ditto.

---
 gcc/config/riscv/riscv-vector-builtins.cc | 4 ++--
 gcc/config/riscv/riscv-vector-builtins.h  | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-builtins.cc 
b/gcc/config/riscv/riscv-vector-builtins.cc

index 2e92ece3b64..90fc73a5bcf 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -1850,7 +1850,7 @@ use_real_merge_p (enum predication_type_index pred)

 /* Get TAIL policy for predication. If predication indicates TU, 
return the TU.

    Otherwise, return the prefer default configuration.  */
-static rtx
+rtx
 get_tail_policy_for_pred (enum predication_type_index pred)
 {
   if (pred == PRED_TYPE_tu || pred == PRED_TYPE_tum || pred == 
PRED_TYPE_tumu)
@@ -1860,7 +1860,7 @@ get_tail_policy_for_pred (enum 
predication_type_index pred)


 /* Get MASK policy for predication. If predication indicates MU, 
return the MU.

    Otherwise, return the prefer default configuration.  */
-static rtx
+rtx
 get_mask_policy_for_pred (enum predication_type_index pred)
 {
   if (pred == PRED_TYPE_tumu || pred == PRED_TYPE_mu)
diff --git a/gcc/config/riscv/riscv-vector-builtins.h 
b/gcc/config/riscv/riscv-vector-builtins.h

index ede08c6a480..135e2463b1e 100644
--- a/gcc/config/riscv/riscv-vector-builtins.h
+++ b/gcc/config/riscv/riscv-vector-builtins.h
@@ -433,6 +433,8 @@ extern const char *const operand_suffixes[NUM_OP_TYPES];
 extern const rvv_builtin_suffixes type_suffixes[NUM_VECTOR_TYPES + 1];
 extern const char *const predication_suffixes[NUM_PRED_TYPES];
 extern rvv_builtin_types_t builtin_types[NUM_VECTOR_TYPES + 1];
+extern rtx get_tail_policy_for_pred (enum predication_type_index pred);
+extern rtx get_mask_policy_for_pred (enum predication_type_index pred);

 inline bool
 function_instance::operator!= (const function_instance &other) const
--
2.34.1

[PATCH 01/07] RISC-V: Add auto-vectorization support

[Michael Collison]

This patch adds foundational support in the form of:

1. New predicates

2. New function prototypes

3. Exporting emit_vlmax_vsetvl to global scope

4. Add a new command line option -mriscv_vector_lmul

gcc/ChangeLog:

    * config/riscv/riscv-protos.h (riscv_classify_vlmul_field):
    New external declaration.
    (riscv_vector_preferred_simd_mode): Ditto.
    (riscv_tuple_mode_p): Ditto.
    (riscv_vector_mask_mode_p): Ditto.
    (riscv_classify_nf): Ditto.
    (riscv_vlmul_regsize): Ditto.
    (riscv_vector_preferred_simd_mode): Ditto.
    (riscv_vector_get_mask_mode): Ditto.
    (emit_vlmax_vsetvl): Ditto.
    (get_mask_policy_no_pred): Ditto.
    (get_tail_policy_no_pred): Ditto.
    * config/riscv/riscv-opts.h (riscv_vector_bits_enum): New enum.
    (riscv_vector_lmul_enum): Ditto.
    (vlmul_field_enum): Ditto.
    * config/riscv/riscv-v.cc (emit_vlmax_vsetvl):
    Remove static scope.
    * config/riscv/riscv.opt (riscv_vector_lmul):
    New option -mriscv_vector_lmul.
    * config/riscv/predicates.md (p_reg_or_const_csr_operand):
    New predicate.
    (vector_reg_or_const_dup_operand): Ditto.

---
 gcc/config/riscv/predicates.md  | 13 +++
 gcc/config/riscv/riscv-opts.h   | 40 +
 gcc/config/riscv/riscv-protos.h | 16 +
 gcc/config/riscv/riscv-v.cc |  2 +-
 gcc/config/riscv/riscv.opt  | 20 +
 5 files changed, 90 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 7bc7c0b4f4d..31517ae4606 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -264,6 +264,14 @@
 })

 ;; Predicates for the V extension.
+(define_special_predicate "p_reg_or_const_csr_operand"
+  (match_code "reg, subreg, const_int")
+{
+  if (CONST_INT_P (op))
+    return satisfies_constraint_K (op);
+  return GET_MODE (op) == Pmode;
+})
+
 (define_special_predicate "vector_length_operand"
   (ior (match_operand 0 "pmode_register_operand")
    (match_operand 0 "const_csr_operand")))
@@ -287,6 +295,11 @@
   (ior (match_operand 0 "register_operand")
    (match_test "op == CONSTM1_RTX (GET_MODE (op))")))

+(define_predicate "vector_reg_or_const_dup_operand"
+  (ior (match_operand 0 "register_operand")
+   (match_test "const_vec_duplicate_p (op)
+  && !CONST_POLY_INT_P (CONST_VECTOR_ELT (op, 0))")))
+
 (define_predicate "vector_mask_operand"
   (ior (match_operand 0 "register_operand")
    (match_operand 0 "vector_all_trues_mask_operand")))
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index ff398c0a2ae..2057a14e153 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -67,6 +67,46 @@ enum stack_protector_guard {
   SSP_GLOBAL            /* global canary */
 };

+/* RVV vector register sizes.  */
+enum riscv_vector_bits_enum
+{
+  RVV_SCALABLE,
+  RVV_NOT_IMPLEMENTED = RVV_SCALABLE,
+  RVV_64 = 64,
+  RVV_128 = 128,
+  RVV_256 = 256,
+  RVV_512 = 512,
+  RVV_1024 = 1024,
+  RVV_2048 = 2048,
+  RVV_4096 = 4096,
+  RVV_8192 = 8192,
+  RVV_16384 = 16384,
+  RVV_32768 = 32768,
+  RVV_65536 = 65536
+};
+
+/* vectorization factor.  */
+enum riscv_vector_lmul_enum
+{
+  RVV_LMUL1 = 1,
+  RVV_LMUL2 = 2,
+  RVV_LMUL4 = 4,
+  RVV_LMUL8 = 8
+};
+
+enum vlmul_field_enum
+{
+  VLMUL_FIELD_000, /* LMUL = 1 */
+  VLMUL_FIELD_001, /* LMUL = 2 */
+  VLMUL_FIELD_010, /* LMUL = 4 */
+  VLMUL_FIELD_011, /* LMUL = 8 */
+  VLMUL_FIELD_100, /* RESERVED */
+  VLMUL_FIELD_101, /* LMUL = 1/8 */
+  VLMUL_FIELD_110, /* LMUL = 1/4 */
+  VLMUL_FIELD_111, /* LMUL = 1/2 */
+  MAX_VLMUL_FIELD
+};
+
 #define MASK_ZICSR    (1 << 0)
 #define MASK_ZIFENCEI (1 << 1)

diff --git a/gcc/config/riscv/riscv-protos.h 
b/gcc/config/riscv/riscv-protos.h

index 37c634eca1d..70c8dc4ce69 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -200,4 +200,19 @@ const unsigned int RISCV_BUILTIN_SHIFT = 1;
 /* Mask that selects the riscv_builtin_class part of a function code.  */
 const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1;

+/* Routines implemented in riscv-v.cc*/
+
+namespace riscv_vector {
+extern unsigned int riscv_classify_vlmul_field (enum machine_mode m);
+extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode, 
unsigned vf);

+extern bool riscv_tuple_mode_p (machine_mode);
+extern bool riscv_vector_mask_mode_p (machine_mode);
+extern int riscv_classify_nf (machine_mode);
+extern int riscv_vlmul_regsize(machine_mode);
+extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode, 
unsigned vf);

+extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode);
+extern rtx emit_vlmax_vsetvl (machine_mode vmode);
+extern rtx get_mask_policy_no_pred ();
+extern rtx get_tail_policy_no_pred ();
+}
 #endif /* ! GCC_RISCV_PROTOS_H */
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 59c25c65cd5..58007cc16eb 100644
--- a/gcc/config/r

[PATCH 00/07] RISC-V: Add auto-vectorization support

[Michael Collison]

This series of patches adds foundational support for RISC-V 
autovectorization. These patches are based on the current upstream rvv 
vector intrinsic support and is not a new implementation. Most of the 
implementation consists of adding the new vector cost model, the 
autovectorization patterns themselves and target hooks.


This implementation only provides support for integer addition and 
subtraction as a proof of concept.


As discussed on this list, if these patches are approved they will be 
merged into a "auto-vectorization" branch once gcc-13 branches for release.


There are two known issues related to crashes (assert failures) 
associated with tree vectorization; one of which I have sent a patch for 
and have received feedback. I will be sending a patch for the second 
issue tomorrow.



 gcc/common/config/riscv/riscv-common.cc   |   2 +-
 gcc/config.gcc    |   2 +-
 gcc/config/riscv/predicates.md    |  13 +
 gcc/config/riscv/riscv-cores.def  |  14 +-
 gcc/config/riscv/riscv-opts.h |  40 ++
 gcc/config/riscv/riscv-protos.h   |  15 +
 gcc/config/riscv/riscv-v.cc   | 178 -
 gcc/config/riscv/riscv-vector-builtins.cc |   4 +-
 gcc/config/riscv/riscv-vector-builtins.h  |   2 +
 gcc/config/riscv/riscv-vector-cost.cc | 620 ++
 gcc/config/riscv/riscv-vector-cost.h  | 400 +++
 gcc/config/riscv/riscv.cc | 321 -
 gcc/config/riscv/riscv.md |   1 +
 gcc/config/riscv/riscv.opt    |  20 +
 gcc/config/riscv/t-riscv  |   5 +
 gcc/config/riscv/vector-auto.md   | 172 +
 gcc/config/riscv/vector-iterators.md  |   2 +
 gcc/config/riscv/vector.md    |   4 +-
 .../riscv/rvv/autovec/loop-add-rv32.c |  24 +
 .../gcc.target/riscv/rvv/autovec/loop-add.c   |  24 +
 .../riscv/rvv/autovec/loop-sub-rv32.c |  24 +
 .../gcc.target/riscv/rvv/autovec/loop-sub.c   |  24 +
 22 files changed, 1893 insertions(+), 18 deletions(-)
 create mode 100644 gcc/config/riscv/riscv-vector-cost.cc
 create mode 100644 gcc/config/riscv/riscv-vector-cost.h
 create mode 100644 gcc/config/riscv/vector-auto.md
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c

 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c

 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c

Re: [PATCH] LoongArch: Stop -mfpu from silently breaking ABI

[Xi Ruoyao via Gcc-patches]

On Fri, 2023-03-03 at 10:12 +0800, Yujie Yang wrote:
> However, "loongarch64" is defined to include the "fpu64" ISA module[1]
> (i.e. enable "-mfpu=64" when -mfpu is not explicitly used). So I believe
> the above behavior you observed is expected.

Ah this make things much simpler and aligns with my gut feeling :).  I
can drop the change in loongarch-opts.cc now.  And the smaller changeset
also makes me more confident about a backport to gcc-12.

V2 patch is being tested and I'll send it after the testing.  Meanwhile
I created PR109000 to track the issue.

-- 
Xi Ruoyao 
School of Aerospace Science and Technology, Xidian University

RE: [PATCH v2] RISC-V: Bugfix for rvv bool mode precision adjustment

[Li, Pan2 via Gcc-patches]

Got it. Thank you and very appreciate for your help and patient. Updated the 
PATCH to below link.

https://gcc.gnu.org/pipermail/gcc-patches/2023-March/613257.html

Pan

-Original Message-
From: Richard Sandiford  
Sent: Friday, March 3, 2023 1:55 AM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; 
rguent...@suse.de
Subject: Re: [PATCH v2] RISC-V: Bugfix for rvv bool mode precision adjustment

"Li, Pan2"  writes:
> Oops, looks I missed that part for assertion. Thank you for coaching.
> Added and tested the below changes at the end of emit_mode_adjustments 
> already but looks we may have other problems about the size, the precision 
> and the C types.
>
> Looks like I need to hold this PATCH for a while until we have a conclusion. 
> Feel free to let me know if there is mistake or misleading.
>
> + 
> +  for_all_modes (c, m)
> +printf ("  gcc_checking_assert (!mode_size[E_%smode].is_constant()"
> +   " || mode_size[E_%smode].coeffs[0] != -1);\n", m->name, 
> + m->name);
> +

Using:

  gcc_assert (maybe_ne (mode_size[E_%smode], -1));

would be simpler.  We might as well make it a full assert (rather than a 
checking assert) because this code isn't executed very often.

Thanks,
Richard

>
> Thank you and have a nice day!
>
> Pan
>
>
> -Original Message-
> From: Richard Sandiford 
> Sent: Thursday, March 2, 2023 5:44 PM
> To: Li, Pan2 
> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; 
> kito.ch...@sifive.com; rguent...@suse.de
> Subject: Re: [PATCH v2] RISC-V: Bugfix for rvv bool mode precision 
> adjustment
>
> pan2...@intel.com writes:
>> From: Pan Li 
>>
>>  Fix the bug of the rvv bool mode precision with the adjustment.
>>  The bits size of vbool*_t will be adjusted to
>>  [1, 2, 4, 8, 16, 32, 64] according to the rvv spec 1.0 isa. The
>>  adjusted mode precison of vbool*_t will help underlying pass to
>>  make the right decision for both the correctness and optimization.
>>
>>  Given below sample code:
>>  void test_1(int8_t * restrict in, int8_t * restrict out)
>>  {
>>vbool8_t v2 = *(vbool8_t*)in;
>>vbool16_t v5 = *(vbool16_t*)in;
>>*(vbool16_t*)(out + 200) = v5;
>>*(vbool8_t*)(out + 100) = v2;
>>  }
>>
>>  Before the precision adjustment:
>>  addia4,a1,100
>>  vsetvli a5,zero,e8,m1,ta,ma
>>  addia1,a1,200
>>  vlm.v   v24,0(a0)
>>  vsm.v   v24,0(a4)
>>  // Need one vsetvli and vlm.v for correctness here.
>>  vsm.v   v24,0(a1)
>>
>>  After the precision adjustment:
>>  csrrt0,vlenb
>>  sllit1,t0,1
>>  csrra3,vlenb
>>  sub sp,sp,t1
>>  sllia4,a3,1
>>  add a4,a4,sp
>>  sub a3,a4,a3
>>  vsetvli a5,zero,e8,m1,ta,ma
>>  addia2,a1,200
>>  vlm.v   v24,0(a0)
>>  vsm.v   v24,0(a3)
>>  addia1,a1,100
>>  vsetvli a4,zero,e8,mf2,ta,ma
>>  csrrt0,vlenb
>>  vlm.v   v25,0(a3)
>>  vsm.v   v25,0(a2)
>>  sllit1,t0,1
>>  vsetvli a5,zero,e8,m1,ta,ma
>>  vsm.v   v24,0(a1)
>>  add sp,sp,t1
>>  jr  ra
>>
>>  However, there may be some optimization opportunates after
>>  the mode precision adjustment. It can be token care of in
>>  the RISC-V backend in the underlying separted PR(s).
>>
>>  PR 108185
>>  PR 108654
>>
>> gcc/ChangeLog:
>>
>>  * config/riscv/riscv-modes.def (ADJUST_PRECISION):
>>  * config/riscv/riscv.cc (riscv_v_adjust_precision):
>>  * config/riscv/riscv.h (riscv_v_adjust_precision):
>>  * genmodes.cc (ADJUST_PRECISION):
>>  (emit_mode_adjustments):
>>
>> gcc/testsuite/ChangeLog:
>>
>>  * gcc.target/riscv/pr108185-1.c: New test.
>>  * gcc.target/riscv/pr108185-2.c: New test.
>>  * gcc.target/riscv/pr108185-3.c: New test.
>>  * gcc.target/riscv/pr108185-4.c: New test.
>>  * gcc.target/riscv/pr108185-5.c: New test.
>>  * gcc.target/riscv/pr108185-6.c: New test.
>>  * gcc.target/riscv/pr108185-7.c: New test.
>>  * gcc.target/riscv/pr108185-8.c: New test.
>>
>> Signed-off-by: Pan Li 
>> ---
>>  gcc/config/riscv/riscv-modes.def|  8 +++
>>  gcc/config/riscv/riscv.cc   | 12 
>>  gcc/config/riscv/riscv.h|  1 +
>>  gcc/genmodes.cc | 20 +-
>>  gcc/testsuite/gcc.target/riscv/pr108185-1.c | 68 ++ 
>> gcc/testsuite/gcc.target/riscv/pr108185-2.c | 68 ++ 
>> gcc/testsuite/gcc.target/riscv/pr108185-3.c | 68 ++ 
>> gcc/testsuite/gcc.target/riscv/pr108185-4.c | 68 ++ 
>> gcc/testsuite/gcc.target/riscv/pr108185-5.c | 68 ++ 
>> gcc/testsuite/gcc.target/riscv/pr108185-6.c | 68 ++ 
>> gcc/testsuite/gcc.target/riscv/pr108185-7.c | 68 ++ 
>> gcc/testsuite/gcc.target/riscv/pr108185-8.c | 77 
>> +
>>  12 files changed, 592 insertions(+), 2

[PATCH v3] RISC-V: Bugfix for rvv bool mode precision adjustment

[pan2.li--- via Gcc-patches]

From: Pan Li 

Fix the bug of the rvv bool mode precision with the adjustment.
The bits size of vbool*_t will be adjusted to
[1, 2, 4, 8, 16, 32, 64] according to the rvv spec 1.0 isa. The
adjusted mode precison of vbool*_t will help underlying pass to
make the right decision for both the correctness and optimization.

Given below sample code:
void test_1(int8_t * restrict in, int8_t * restrict out)
{
  vbool8_t v2 = *(vbool8_t*)in;
  vbool16_t v5 = *(vbool16_t*)in;
  *(vbool16_t*)(out + 200) = v5;
  *(vbool8_t*)(out + 100) = v2;
}

Before the precision adjustment:
addia4,a1,100
vsetvli a5,zero,e8,m1,ta,ma
addia1,a1,200
vlm.v   v24,0(a0)
vsm.v   v24,0(a4)
// Need one vsetvli and vlm.v for correctness here.
vsm.v   v24,0(a1)

After the precision adjustment:
csrrt0,vlenb
sllit1,t0,1
csrra3,vlenb
sub sp,sp,t1
sllia4,a3,1
add a4,a4,sp
sub a3,a4,a3
vsetvli a5,zero,e8,m1,ta,ma
addia2,a1,200
vlm.v   v24,0(a0)
vsm.v   v24,0(a3)
addia1,a1,100
vsetvli a4,zero,e8,mf2,ta,ma
csrrt0,vlenb
vlm.v   v25,0(a3)
vsm.v   v25,0(a2)
sllit1,t0,1
vsetvli a5,zero,e8,m1,ta,ma
vsm.v   v24,0(a1)
add sp,sp,t1
jr  ra

However, there may be some optimization opportunates after
the mode precision adjustment. It can be token care of in
the RISC-V backend in the underlying separted PR(s).

PR 108185
PR 108654

gcc/ChangeLog:

* config/riscv/riscv-modes.def (ADJUST_PRECISION):
* config/riscv/riscv.cc (riscv_v_adjust_precision):
* config/riscv/riscv.h (riscv_v_adjust_precision):
* genmodes.cc (ADJUST_PRECISION):
(emit_mode_adjustments):

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr108185-1.c: New test.
* gcc.target/riscv/pr108185-2.c: New test.
* gcc.target/riscv/pr108185-3.c: New test.
* gcc.target/riscv/pr108185-4.c: New test.
* gcc.target/riscv/pr108185-5.c: New test.
* gcc.target/riscv/pr108185-6.c: New test.
* gcc.target/riscv/pr108185-7.c: New test.
* gcc.target/riscv/pr108185-8.c: New test.

Signed-off-by: Pan Li 
---
 gcc/config/riscv/riscv-modes.def|  8 +++
 gcc/config/riscv/riscv.cc   | 12 
 gcc/config/riscv/riscv.h|  1 +
 gcc/genmodes.cc | 26 ++-
 gcc/testsuite/gcc.target/riscv/pr108185-1.c | 68 ++
 gcc/testsuite/gcc.target/riscv/pr108185-2.c | 68 ++
 gcc/testsuite/gcc.target/riscv/pr108185-3.c | 68 ++
 gcc/testsuite/gcc.target/riscv/pr108185-4.c | 68 ++
 gcc/testsuite/gcc.target/riscv/pr108185-5.c | 68 ++
 gcc/testsuite/gcc.target/riscv/pr108185-6.c | 68 ++
 gcc/testsuite/gcc.target/riscv/pr108185-7.c | 68 ++
 gcc/testsuite/gcc.target/riscv/pr108185-8.c | 77 +
 12 files changed, 598 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr108185-8.c

diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def
index d5305efa8a6..110bddce851 100644
--- a/gcc/config/riscv/riscv-modes.def
+++ b/gcc/config/riscv/riscv-modes.def
@@ -72,6 +72,14 @@ ADJUST_BYTESIZE (VNx16BI, riscv_vector_chunks * 
riscv_bytes_per_vector_chunk);
 ADJUST_BYTESIZE (VNx32BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
 ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 8));
 
+ADJUST_PRECISION (VNx1BI, riscv_v_adjust_precision (VNx1BImode, 1));
+ADJUST_PRECISION (VNx2BI, riscv_v_adjust_precision (VNx2BImode, 2));
+ADJUST_PRECISION (VNx4BI, riscv_v_adjust_precision (VNx4BImode, 4));
+ADJUST_PRECISION (VNx8BI, riscv_v_adjust_precision (VNx8BImode, 8));
+ADJUST_PRECISION (VNx16BI, riscv_v_adjust_precision (VNx16BImode, 16));
+ADJUST_PRECISION (VNx32BI, riscv_v_adjust_precision (VNx32BImode, 32));
+ADJUST_PRECISION (VNx64BI, riscv_v_adjust_precision (VNx64BImode, 64));
+
 /*
| Mode| MIN_VLEN=32 | MIN_VLEN=32 | MIN_VLEN=64 | MIN_VLEN=64 |
| | LMUL| SEW/LMUL| LMUL| SEW/LMUL|
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f11b7949a4

Re: [PATCH] LoongArch: Stop -mfpu from silently breaking ABI

[Yujie Yang]

On Fri, Mar 03, 2023 at 12:01:22AM +0800, Xi Ruoyao via Gcc-patches wrote:
> But then it causes "-mabi=lp64s -march=loongarch64" to generate code like:
> 
>   movgr2fr.d $fa0, $a0
>   frecip.d   $fa0, $fa0
>   movfr2gr.d $a0, $fa0
> 
> The problem here is "loongarch64" is never strictly defined.  So we
> consider "loongarch64" a "64-bit LoongArch CPU with the simplest FPU
> needed by the ABI", and if -march=loongarch64 but -mfpu is not
> explicitly used, we set -mfpu such a simplest one.

Thanks for the fix on TARGET_*_FLOAT_ABI usage! Certainly more testing
needs to be done on the soft-float side.

However, "loongarch64" is defined to include the "fpu64" ISA module[1]
(i.e. enable "-mfpu=64" when -mfpu is not explicitly used). So I believe
the above behavior you observed is expected.

[1] Table 5. Target CPU Models,
https://loongson.github.io/LoongArch-Documentation/LoongArch-toolchain-conventions-EN.html

[committed] d: vector float comparison doesn't result in 0 or -1 [PR108945]

[Iain Buclaw via Gcc-patches]

Hi,

When comparing two vectors, the type of vector was used as the result of
the condition result.  This meant that for floating point comparisons,
each value would either be `0.0' or `-1.0' reinterpreted as an integer,
not the expected integral bitmask values `0' and `-1'.

Instead, use the comparison type determined by truth_type_for as the
result of the comparison.  If a reinterpret is later required by the
final conversion for generating CmpExp, it is still only going to
reinterpret one integer kind as another.

Bootstrapped and regression tested on x86_64-linux-gnu/-m32, and
committed to mainline.

Regards,
Iain.

---
PR d/108945

gcc/d/ChangeLog:

* d-codegen.cc (build_boolop): Evaluate vector comparison as
the truth_type_for vector type.

gcc/testsuite/ChangeLog:

* gdc.dg/pr108945.d: New test.
---
 gcc/d/d-codegen.cc  |  9 -
 gcc/testsuite/gdc.dg/pr108945.d | 12 
 2 files changed, 16 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gdc.dg/pr108945.d

diff --git a/gcc/d/d-codegen.cc b/gcc/d/d-codegen.cc
index 0e8e07366ee..5a041927ec9 100644
--- a/gcc/d/d-codegen.cc
+++ b/gcc/d/d-codegen.cc
@@ -1453,13 +1453,12 @@ build_boolop (tree_code code, tree arg0, tree arg1)
 {
   /* Build a vector comparison.
 VEC_COND_EXPR ; */
-  tree type = TREE_TYPE (arg0);
-  tree cmptype = truth_type_for (type);
+  tree cmptype = truth_type_for (TREE_TYPE (arg0));
   tree cmp = fold_build2_loc (input_location, code, cmptype, arg0, arg1);
 
-  return fold_build3_loc (input_location, VEC_COND_EXPR, type, cmp,
- build_minus_one_cst (type),
- build_zero_cst (type));
+  return fold_build3_loc (input_location, VEC_COND_EXPR, cmptype, cmp,
+ build_minus_one_cst (cmptype),
+ build_zero_cst (cmptype));
 }
 
   if (code == EQ_EXPR || code == NE_EXPR)
diff --git a/gcc/testsuite/gdc.dg/pr108945.d b/gcc/testsuite/gdc.dg/pr108945.d
new file mode 100644
index 000..03b9de8e758
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/pr108945.d
@@ -0,0 +1,12 @@
+// { dg-options "-fdump-tree-gimple" }
+// { dg-additional-options "-mavx" { target avx_runtime } }
+// { dg-do compile { target { avx_runtime || vect_sizes_16B_8B } } }
+
+alias f4 = __vector(float[4]);
+
+auto pr108945(f4 a, f4 b)
+{
+return a < b;
+}
+
+// { dg-final { scan-tree-dump-not "VEC_COND_EXPR" "gimple" } }
-- 
2.37.2

[committed] d: Fix ICE on explicit immutable struct import [PR10887]

[Iain Buclaw via Gcc-patches]

Hi,

This patch fixes an ICE in the D front-end when importing an immutable
struct.  Const and immutable types are built as variants of the type
they are derived from, and TYPE_STUB_DECL is not set for these variants.

Bootstrapped and regression tested on x86_64-linux-gnu/-m32, committed
to mainline, and backported to the release branches for gcc-10, gcc-11,
and gcc-12.

Regards,
Iain.

---
PR d/108877

gcc/d/ChangeLog:

* imports.cc (ImportVisitor::visit (EnumDeclaration *)): Call
make_import on TYPE_MAIN_VARIANT.
(ImportVisitor::visit (AggregateDeclaration *)): Likewise.
(ImportVisitor::visit (ClassDeclaration *)): Likewise.

gcc/testsuite/ChangeLog:

* gdc.dg/imports/pr108877a.d: New test.
* gdc.dg/pr108877.d: New test.
---
 gcc/d/imports.cc | 7 ++-
 gcc/testsuite/gdc.dg/imports/pr108877a.d | 6 ++
 gcc/testsuite/gdc.dg/pr108877.d  | 9 +
 3 files changed, 21 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gdc.dg/imports/pr108877a.d
 create mode 100644 gcc/testsuite/gdc.dg/pr108877.d

diff --git a/gcc/d/imports.cc b/gcc/d/imports.cc
index 3b46d1b7560..2efef4ed54f 100644
--- a/gcc/d/imports.cc
+++ b/gcc/d/imports.cc
@@ -106,12 +106,16 @@ public:
 tree type = build_ctype (d->type);
 /* Not all kinds of D enums create a TYPE_DECL.  */
 if (TREE_CODE (type) == ENUMERAL_TYPE)
-  this->result_ = this->make_import (TYPE_STUB_DECL (type));
+  {
+   type = TYPE_MAIN_VARIANT (type);
+   this->result_ = this->make_import (TYPE_STUB_DECL (type));
+  }
   }
 
   void visit (AggregateDeclaration *d) final override
   {
 tree type = build_ctype (d->type);
+type = TYPE_MAIN_VARIANT (type);
 this->result_ = this->make_import (TYPE_STUB_DECL (type));
   }
 
@@ -119,6 +123,7 @@ public:
   {
 /* Want the RECORD_TYPE, not POINTER_TYPE.  */
 tree type = TREE_TYPE (build_ctype (d->type));
+type = TYPE_MAIN_VARIANT (type);
 this->result_ = this->make_import (TYPE_STUB_DECL (type));
   }
 
diff --git a/gcc/testsuite/gdc.dg/imports/pr108877a.d 
b/gcc/testsuite/gdc.dg/imports/pr108877a.d
new file mode 100644
index 000..a23c78ddf84
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/imports/pr108877a.d
@@ -0,0 +1,6 @@
+immutable struct ImmutableS { }
+const struct ConstS { }
+immutable class ImmutableC { }
+const class ConstC { }
+immutable enum ImmutableE { _ }
+const enum ConstE { _ }
diff --git a/gcc/testsuite/gdc.dg/pr108877.d b/gcc/testsuite/gdc.dg/pr108877.d
new file mode 100644
index 000..710551f3f9a
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/pr108877.d
@@ -0,0 +1,9 @@
+// { dg-options "-I $srcdir/gdc.dg" }
+// { dg-do compile }
+import imports.pr108877a :
+ImmutableS,
+ConstS,
+ImmutableC,
+ConstC,
+ImmutableE,
+ConstE;
-- 
2.37.2

[committed] d: Allow vectors to be compared for identity (PR108946)

[Iain Buclaw via Gcc-patches]

Hi,

Vector equality and comparisons are now accepted by the language
implementation, but identity wasn't.  This patch implements it as an
extra integer comparison of the bit-casted bitmask.

Bootstrapped and regression tested on x86_64-linux-gnu/-m32, and
committed to mainline.

Regards,
Iain.

---
PR d/108946

gcc/d/ChangeLog:

* d-target.cc (Target::isVectorOpSupported): Allow identity ops.
* expr.cc (ExprVisitor::visit (IdentityExp *)): Handle vector identity
comparisons.

gcc/testsuite/ChangeLog:

* gdc.dg/simd2a.d: Update test.
* gdc.dg/simd2b.d: Likewise.
* gdc.dg/simd2c.d: Likewise.
* gdc.dg/simd2d.d: Likewise.
* gdc.dg/simd2e.d: Likewise.
* gdc.dg/simd2f.d: Likewise.
* gdc.dg/simd2g.d: Likewise.
* gdc.dg/simd2h.d: Likewise.
* gdc.dg/simd2i.d: Likewise.
* gdc.dg/simd2j.d: Likewise.
---
 gcc/d/d-target.cc |  5 -
 gcc/d/expr.cc | 25 +
 gcc/testsuite/gdc.dg/simd2a.d |  5 +++--
 gcc/testsuite/gdc.dg/simd2b.d |  5 +++--
 gcc/testsuite/gdc.dg/simd2c.d |  5 +++--
 gcc/testsuite/gdc.dg/simd2d.d |  5 +++--
 gcc/testsuite/gdc.dg/simd2e.d |  5 +++--
 gcc/testsuite/gdc.dg/simd2f.d |  5 +++--
 gcc/testsuite/gdc.dg/simd2g.d |  5 +++--
 gcc/testsuite/gdc.dg/simd2h.d |  5 +++--
 gcc/testsuite/gdc.dg/simd2i.d |  5 +++--
 gcc/testsuite/gdc.dg/simd2j.d |  5 +++--
 12 files changed, 55 insertions(+), 25 deletions(-)

diff --git a/gcc/d/d-target.cc b/gcc/d/d-target.cc
index 5eab5706ead..4c7a212703e 100644
--- a/gcc/d/d-target.cc
+++ b/gcc/d/d-target.cc
@@ -323,11 +323,6 @@ Target::isVectorOpSupported (Type *type, EXP op, Type *)
   /* Logical operators must have a result type of bool.  */
   return false;
 
-case EXP::identity:
-case EXP::notIdentity:
-  /* Comparison operators must have a result type of bool.  */
-  return false;
-
 default:
   break;
 }
diff --git a/gcc/d/expr.cc b/gcc/d/expr.cc
index c8ec37d7103..4311edcc2d6 100644
--- a/gcc/d/expr.cc
+++ b/gcc/d/expr.cc
@@ -313,6 +313,31 @@ public:
 
this->result_ = build_struct_comparison (code, ts->sym, t1, t2);
   }
+else if (tb1->ty == TY::Tvector && tb2->ty == TY::Tvector)
+  {
+   /* For vectors, identity is defined as all values being equal.  */
+   tree t1 = build_expr (e->e1);
+   tree t2 = build_expr (e->e2);
+   tree mask = build_boolop (code, t1, t2);
+
+   /* To reinterpret the vector comparison as a boolean expression, bitcast
+  the bitmask result and generate an additional integer comparison.  */
+   opt_scalar_int_mode mode =
+ int_mode_for_mode (TYPE_MODE (TREE_TYPE (mask)));
+   gcc_assert (mode.exists ());
+
+   tree type = lang_hooks.types.type_for_mode (mode.require (), 1);
+   if (type == NULL_TREE)
+ type = make_unsigned_type (GET_MODE_BITSIZE (mode.require ()));
+
+   /* In `t1 is t2', all mask bits must be set for vectors to be equal.
+  Otherwise any bit set is enough for vectors to be not-equal.  */
+   tree mask_eq = (code == EQ_EXPR)
+ ? build_all_ones_cst (type) : build_zero_cst (type);
+
+   this->result_ = build_boolop (code, mask_eq,
+ build_vconvert (type, mask));
+  }
 else
   {
/* For operands of other types, identity is defined as being the
diff --git a/gcc/testsuite/gdc.dg/simd2a.d b/gcc/testsuite/gdc.dg/simd2a.d
index 373d5d1e229..d47175fd38b 100644
--- a/gcc/testsuite/gdc.dg/simd2a.d
+++ b/gcc/testsuite/gdc.dg/simd2a.d
@@ -5,6 +5,7 @@ import core.simd;
 void test2a()
 {
 byte16 v1, v2 = 1, v3 = 1;
+bool b1;
 v1 = v2;
 v1 = v2 + v3;
 v1 = v2 - v3;
@@ -16,8 +17,8 @@ void test2a()
 v1 = v2 ^ v3;
 static assert(!__traits(compiles, v1 ~ v2));
 static assert(!__traits(compiles, v1 ^^ v2));
-static assert(!__traits(compiles, v1 is v2));
-static assert(!__traits(compiles, v1 !is v2));
+b1 = v1 is v2;
+b1 = v1 !is v2;
 static assert( __traits(compiles, v1 == v2));
 static assert( __traits(compiles, v1 != v2));
 static assert( __traits(compiles, v1 < v2));
diff --git a/gcc/testsuite/gdc.dg/simd2b.d b/gcc/testsuite/gdc.dg/simd2b.d
index e72da0d9b77..a1b2a10caaf 100644
--- a/gcc/testsuite/gdc.dg/simd2b.d
+++ b/gcc/testsuite/gdc.dg/simd2b.d
@@ -5,6 +5,7 @@ import core.simd;
 void test2b()
 {
 ubyte16 v1, v2 = 1, v3 = 1;
+bool b1;
 v1 = v2;
 v1 = v2 + v3;
 v1 = v2 - v3;
@@ -16,8 +17,8 @@ void test2b()
 v1 = v2 ^ v3;
 static assert(!__traits(compiles, v1 ~ v2));
 static assert(!__traits(compiles, v1 ^^ v2));
-static assert(!__traits(compiles, v1 is v2));
-static assert(!__traits(compiles, v1 !is v2));
+b1 = v1 is v2;
+b1 = v1 !is v2;
 static assert( __traits(compiles, v1 == v2));
 static assert( __traits(compiles, v1 != v2));
 static assert( __traits(compiles, 

[committed] d: Add test for PR d/108167 to the testsuite [PR108167]

[Iain Buclaw via Gcc-patches]

Hi,

This patch adds the test for checking PR108167.  The D front-end
implementation got fixed in upstream, add test to the gdc testsuite to
check we don't regress on it.

Regression tested on x86_64-linux-gnu/-m32, and committed to mainline.

Regards,
Iain.

---
PR d/108167

gcc/testsuite/ChangeLog:

* gdc.dg/pr108167.d: New test.
---
 gcc/testsuite/gdc.dg/pr108167.d | 5 +
 1 file changed, 5 insertions(+)
 create mode 100644 gcc/testsuite/gdc.dg/pr108167.d

diff --git a/gcc/testsuite/gdc.dg/pr108167.d b/gcc/testsuite/gdc.dg/pr108167.d
new file mode 100644
index 000..1337a494171
--- /dev/null
+++ b/gcc/testsuite/gdc.dg/pr108167.d
@@ -0,0 +1,5 @@
+// { dg-do compile }
+auto pr108167(const(ubyte[32])[] a)
+{
+return cast(const(ubyte)*)&a[1][0];
+}
-- 
2.37.2

Re: [V4][PATCH 2/2] Update documentation to clarify a GCC extension

[Qing Zhao via Gcc-patches]

Ping.

Qing

> On Feb 24, 2023, at 1:35 PM, Qing Zhao  wrote:
> 
> on a structure with a C99 flexible array member being nested in
> another structure.
> 
> "GCC extension accepts a structure containing an ISO C99 "flexible array
> member", or a union containing such a structure (possibly recursively)
> to be a member of a structure.
> 
> There are two situations:
> 
>   * The structure with a C99 flexible array member is the last field of
> another structure, for example:
> 
>  struct flex  { int length; char data[]; };
>  union union_flex { int others; struct flex f; };
> 
>  struct out_flex_struct { int m; struct flex flex_data; };
>  struct out_flex_union { int n; union union_flex flex_data; };
> 
> In the above, both 'out_flex_struct.flex_data.data[]' and
> 'out_flex_union.flex_data.f.data[]' are considered as flexible
> arrays too.
> 
>   * The structure with a C99 flexible array member is the middle field
> of another structure, for example:
> 
>  struct flex  { int length; char data[]; };
> 
>  struct mid_flex { int m; struct flex flex_data; int n; };
> 
> In the above, 'mid_flex.flex_data.data[]' is allowed to be extended
> flexibly to the padding.  E.g, up to 4 elements.
> 
> However, relying on space in struct padding is a bad programming
> practice, compilers do not handle such extension consistently, Any
> code relying on this behavior should be modified to ensure that
> flexible array members only end up at the ends of structures.
> 
> Please use warning option '-Wgnu-variable-sized-type-not-at-end' to
> identify all such cases in the source code and modify them.  This
> extension will be deprecated from gcc in the next release.
> "
> 
> gcc/c-family/ChangeLog:
> 
>   * c.opt: New option -Wgnu-variable-sized-type-not-at-end.
> 
> gcc/c/ChangeLog:
> 
>   * c-decl.cc (finish_struct): Issue warnings for new option.
> 
> gcc/ChangeLog:
> 
>   * doc/extend.texi: Document GCC extension on a structure containing
>   a flexible array member to be a member of another structure.
> 
> gcc/testsuite/ChangeLog:
> 
>   * gcc.dg/variable-sized-type-flex-array.c: New test.
> ---
> gcc/c-family/c.opt|  5 ++
> gcc/c/c-decl.cc   |  7 +++
> gcc/doc/extend.texi   | 48 ++-
> .../gcc.dg/variable-sized-type-flex-array.c   | 31 
> 4 files changed, 90 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.dg/variable-sized-type-flex-array.c
> 
> diff --git a/gcc/c-family/c.opt b/gcc/c-family/c.opt
> index cddeece..660ac07f3d4 100644
> --- a/gcc/c-family/c.opt
> +++ b/gcc/c-family/c.opt
> @@ -737,6 +737,11 @@ Wformat-truncation=
> C ObjC C++ LTO ObjC++ Joined RejectNegative UInteger Var(warn_format_trunc) 
> Warning LangEnabledBy(C ObjC C++ LTO ObjC++,Wformat=, warn_format >= 1, 0) 
> IntegerRange(0, 2)
> Warn about calls to snprintf and similar functions that truncate output.
> 
> +Wgnu-variable-sized-type-not-at-end
> +C C++ Var(warn_variable_sized_type_not_at_end) Warning
> +Warn about structures or unions with C99 flexible array members are not
> +at the end of a structure.
> +
> Wif-not-aligned
> C ObjC C++ ObjC++ Var(warn_if_not_aligned) Init(1) Warning
> Warn when the field in a struct is not aligned.
> diff --git a/gcc/c/c-decl.cc b/gcc/c/c-decl.cc
> index f589a2f5192..c5b54f07965 100644
> --- a/gcc/c/c-decl.cc
> +++ b/gcc/c/c-decl.cc
> @@ -9296,6 +9296,13 @@ finish_struct (location_t loc, tree t, tree fieldlist, 
> tree attributes,
>  && is_last_field)
>   TYPE_INCLUDE_FLEXARRAY (t) = true;
> 
> +  if (warn_variable_sized_type_not_at_end
> +   && !is_last_field
> +   && TYPE_INCLUDE_FLEXARRAY (TREE_TYPE (x)))
> + warning_at (DECL_SOURCE_LOCATION (x),
> + OPT_Wgnu_variable_sized_type_not_at_end,
> + "variable sized type not at the end of a struct");
> +
>   if (DECL_NAME (x)
> || RECORD_OR_UNION_TYPE_P (TREE_TYPE (x)))
>   saw_named_field = true;
> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
> index c1122916255..e278148c332 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -1748,7 +1748,53 @@ Flexible array members may only appear as the last 
> member of a
> A structure containing a flexible array member, or a union containing
> such a structure (possibly recursively), may not be a member of a
> structure or an element of an array.  (However, these uses are
> -permitted by GCC as extensions.)
> +permitted by GCC as extensions, see details below.)
> +@end itemize
> +
> +GCC extension accepts a structure containing an ISO C99 @dfn{flexible array
> +member}, or a union containing such a structure (possibly recursively)
> +to be a member of a structure.
> +
> +There are two situations:
> +
> +@itemize @bullet
> +@item
> +The structure with a C99 flexible array me

Re: [v4][PATCH 1/2] Handle component_ref to a structre/union field including C99 FAM [PR101832]

[Qing Zhao via Gcc-patches]

Ping.

Qing

> On Feb 24, 2023, at 1:35 PM, Qing Zhao  wrote:
> 
> GCC extension accepts the case when a struct with a C99 flexible array member
> is embedded into another struct or union (possibly recursively).
> __builtin_object_size should treat such struct as flexible size.
> 
> gcc/c/ChangeLog:
> 
>   PR tree-optimization/101832
>   * c-decl.cc (finish_struct): Set TYPE_INCLUDE_FLEXARRAY for
>   struct/union type.
> 
> gcc/cp/ChangeLog:
> 
>   PR tree-optimization/101832
>   * module.cc (trees_out::core_bools): Stream out new bit
>   type_include_flexarray.
>   (trees_in::core_bools): Stream in new bit type_include_flexarray.
> 
> gcc/ChangeLog:
> 
>   PR tree-optimization/101832
>   * print-tree.cc (print_node): Print new bit type_include_flexarray.
>   * tree-core.h (struct tree_type_common): New bit
>   type_include_flexarray.
>   * tree-object-size.cc (addr_object_size): Handle structure/union type
>   when it has flexible size.
>   * tree-streamer-in.cc (unpack_ts_type_common_value_fields): Stream
>   in new bit type_include_flexarray.
>   * tree-streamer-out.cc (pack_ts_type_common_value_fields): Stream
>   out new bit type_include_flexarray.
>   * tree.h (TYPE_INCLUDE_FLEXARRAY): New macro
>   TYPE_INCLUDE_FLEXARRAY.
> 
> gcc/testsuite/ChangeLog:
> 
>   PR tree-optimization/101832
>   * gcc.dg/builtin-object-size-pr101832.c: New test.
> ---
> gcc/c/c-decl.cc   |  12 ++
> gcc/cp/module.cc  |   2 +
> gcc/print-tree.cc |   5 +
> .../gcc.dg/builtin-object-size-pr101832.c | 134 ++
> gcc/tree-core.h   |   4 +-
> gcc/tree-object-size.cc   |  79 +++
> gcc/tree-streamer-in.cc   |   1 +
> gcc/tree-streamer-out.cc  |   1 +
> gcc/tree.h|   6 +
> 9 files changed, 215 insertions(+), 29 deletions(-)
> create mode 100644 gcc/testsuite/gcc.dg/builtin-object-size-pr101832.c
> 
> diff --git a/gcc/c/c-decl.cc b/gcc/c/c-decl.cc
> index 08078eadeb8..f589a2f5192 100644
> --- a/gcc/c/c-decl.cc
> +++ b/gcc/c/c-decl.cc
> @@ -9284,6 +9284,18 @@ finish_struct (location_t loc, tree t, tree fieldlist, 
> tree attributes,
>   /* Set DECL_NOT_FLEXARRAY flag for FIELD_DECL x.  */
>   DECL_NOT_FLEXARRAY (x) = !is_flexible_array_member_p (is_last_field, x);
> 
> +  /* Set TYPE_INCLUDE_FLEXARRAY for the context of x, t
> +   * when x is an array.  */
> +  if (TREE_CODE (TREE_TYPE (x)) == ARRAY_TYPE)
> + TYPE_INCLUDE_FLEXARRAY (t) = flexible_array_member_type_p (TREE_TYPE 
> (x)) ;
> +  /* Recursively set TYPE_INCLUDE_FLEXARRAY for the context of x, t
> +  when x is the last field.  */
> +  else if ((TREE_CODE (TREE_TYPE (x)) == RECORD_TYPE
> + || TREE_CODE (TREE_TYPE (x)) == UNION_TYPE)
> +&& TYPE_INCLUDE_FLEXARRAY (TREE_TYPE (x))
> +&& is_last_field)
> + TYPE_INCLUDE_FLEXARRAY (t) = true;
> +
>   if (DECL_NAME (x)
> || RECORD_OR_UNION_TYPE_P (TREE_TYPE (x)))
>   saw_named_field = true;
> diff --git a/gcc/cp/module.cc b/gcc/cp/module.cc
> index ac2fe66b080..c750361b704 100644
> --- a/gcc/cp/module.cc
> +++ b/gcc/cp/module.cc
> @@ -5371,6 +5371,7 @@ trees_out::core_bools (tree t)
>   WB (t->type_common.lang_flag_5);
>   WB (t->type_common.lang_flag_6);
>   WB (t->type_common.typeless_storage);
> +  WB (t->type_common.type_include_flexarray);
> }
> 
>   if (CODE_CONTAINS_STRUCT (code, TS_DECL_COMMON))
> @@ -5551,6 +5552,7 @@ trees_in::core_bools (tree t)
>   RB (t->type_common.lang_flag_5);
>   RB (t->type_common.lang_flag_6);
>   RB (t->type_common.typeless_storage);
> +  RB (t->type_common.type_include_flexarray);
> }
> 
>   if (CODE_CONTAINS_STRUCT (code, TS_DECL_COMMON))
> diff --git a/gcc/print-tree.cc b/gcc/print-tree.cc
> index 1f3afcbbc86..efacdb7686f 100644
> --- a/gcc/print-tree.cc
> +++ b/gcc/print-tree.cc
> @@ -631,6 +631,11 @@ print_node (FILE *file, const char *prefix, tree node, 
> int indent,
> && TYPE_CXX_ODR_P (node))
>   fputs (" cxx-odr-p", file);
> 
> +  if ((code == RECORD_TYPE
> +|| code == UNION_TYPE)
> +   && TYPE_INCLUDE_FLEXARRAY (node))
> + fputs (" include-flexarray", file);
> +
>   /* The transparent-union flag is used for different things in
>different nodes.  */
>   if ((code == UNION_TYPE || code == RECORD_TYPE)
> diff --git a/gcc/testsuite/gcc.dg/builtin-object-size-pr101832.c 
> b/gcc/testsuite/gcc.dg/builtin-object-size-pr101832.c
> new file mode 100644
> index 000..60078e11634
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/builtin-object-size-pr101832.c
> @@ -0,0 +1,134 @@
> +/* PR 101832: 
> +   GCC extension accepts the case when a struct with a C99 flexible array
> +   member is embedded into ano

Re: [V4][PATCH 0/2] Handle component_ref to a structure/union field including FAM for builtin_object_size

[Qing Zhao via Gcc-patches]

Ping

Qing

> On Feb 24, 2023, at 1:35 PM, Qing Zhao  wrote:
> 
> Hi, Joseph and Richard,
> 
> Could you please review this patch and let me know whether it’s ready
> for committing into GCC13?
> 
> The fix to Bug PR101832 is an important patch for kernel security
> purpose. it's better to be put into GCC13.
> 
> =
> 
> These are the 4th version of the patches for PR101832, to fix
> builtin_object_size to correctly handle component_ref to a
> structure/union field that includes a flexible array member.
> 
> also includes a documentation update for the GCC extension on embedding
> a structure/union with flexible array member into another structure.
> which includes a fix to PR77650.
> 
> compared to the 3rd version of the patch, the major changes are:
> 
> 1. update the documentation part per Joseph's comments.
> 
> compared to the 2nd version of the patch, the major changes are:
> 
> 1. only include C99 flexible array member to this extension, trailing [0], [1]
>  and [4] are all excluded.
> 2. for the new bit type_include_flexarray in tree_type_common, print it
>  and also stream in/out it. 
> 3. update testing cases.
> 4. more clarification on the documentation. warnings for deprecating the 
>  case when the structure with C99 FAM is embedded in the middle of
>  another structure. 
> 5. add a new warning option -Wgnu-variable-sized-type-not-at-end for
>  identifing all such cases.
> 
> bootstrapped and regression tested on aarch64 and x86.
> 
> Okay for commit?
> 
> thanks.
> 
> Qing
> 
> Qing Zhao (2):
>  Handle component_ref to a structre/union field including C99 FAM
>[PR101832]
>  Update documentation to clarify a GCC extension
> 
> gcc/c-family/c.opt|   5 +
> gcc/c/c-decl.cc   |  19 +++
> gcc/cp/module.cc  |   2 +
> gcc/doc/extend.texi   |  48 ++-
> gcc/print-tree.cc |   5 +
> .../gcc.dg/builtin-object-size-pr101832.c | 134 ++
> .../gcc.dg/variable-sized-type-flex-array.c   |  31 
> gcc/tree-core.h   |   4 +-
> gcc/tree-object-size.cc   |  79 +++
> gcc/tree-streamer-in.cc   |   1 +
> gcc/tree-streamer-out.cc  |   1 +
> gcc/tree.h|   6 +
> 12 files changed, 305 insertions(+), 30 deletions(-)
> create mode 100644 gcc/testsuite/gcc.dg/builtin-object-size-pr101832.c
> create mode 100644 gcc/testsuite/gcc.dg/variable-sized-type-flex-array.c
> 
> -- 
> 2.31.1
> 

[committed] testsuite: Fix up memchr-3.c test [PR108991]

[Jakub Jelinek via Gcc-patches]

On Thu, Mar 02, 2023 at 01:43:30PM +, Jonathan Yong via Gcc-patches wrote:
> On 3/2/23 10:46, Richard Sandiford wrote:
> > > diff --git a/gcc/testsuite/gcc.dg/memchr-3.c 
> > > b/gcc/testsuite/gcc.dg/memchr-3.c
> > > index c38d9cf3349..af1b26ef3ae 100644
> > > --- a/gcc/testsuite/gcc.dg/memchr-3.c
> > > +++ b/gcc/testsuite/gcc.dg/memchr-3.c
> > > @@ -6,7 +6,7 @@
> > >   typedef __INT8_TYPE__  int8_t;
> > >   typedef __INT32_TYPE__ int32_t;
> > > -extern void* memchr (const void*, int, long);
> > > +extern void* memchr (const void*, int, long); /* { dg-warning 
> > > "-Wbuiltin-declaration-mismatch" { target llp64 } } */
> > >   struct SX
> > >   {
> > 
> > OK, thanks.
> 
> Thanks, pushed to master branch.

The newly added dg-warning directive was missing the comment argument,
so the target selector was treated as comment and the warning was expected
on all targets when it should be expected only on llp64 targets.

Tested on x86_64-linux -m32/-m64, committed to trunk as obvious:

2023-03-03  Jakub Jelinek  

PR testsuite/108991
* gcc.dg/memchr-3.c: Add missing comment argument to dg-warning
before target selector.

--- gcc/testsuite/gcc.dg/memchr-3.c.jj  2023-03-02 19:09:45.466594110 +0100
+++ gcc/testsuite/gcc.dg/memchr-3.c 2023-03-03 00:48:04.368348282 +0100
@@ -6,7 +6,7 @@
 typedef __INT8_TYPE__  int8_t;
 typedef __INT32_TYPE__ int32_t;
 
-extern void* memchr (const void*, int, long); /* { dg-warning 
"-Wbuiltin-declaration-mismatch" { target llp64 } } */
+extern void* memchr (const void*, int, long); /* { dg-warning 
"-Wbuiltin-declaration-mismatch" "" { target llp64 } } */
 
 struct SX
 {


Jakub

[PATCH v2] libcpp: Handle extended characters in user-defined literal suffix [PR103902]

[Lewis Hyatt via Gcc-patches]

The PR complains that we do not handle UTF-8 in the suffix for a user-defined
literal, such as:

bool operator ""_π (unsigned long long);

In fact we don't handle any extended identifier characters there, whether
UTF-8, UCNs, or the $ sign. We do handle it fine if the optional space after
the "" tokens is included, since then the identifier is lexed in the "normal"
way as its own token. But when it is lexed as part of the string token, this
is handled in lex_string() with a one-off loop that is not aware of extended
characters.

This patch fixes it by adding a new function scan_cur_identifier() that can be
used to lex an identifier while in the middle of lexing another token.

BTW, the other place that has been mis-lexing identifiers is
lex_identifier_intern(), which is used to implement #pragma push_macro
and #pragma pop_macro. This does not support extended characters either.
I will add that in a subsequent patch, because it can't directly reuse the
new function, but rather needs to lex from a string instead of a cpp_buffer.

With scan_cur_identifier(), we do also correctly warn about bidi and
normalization issues in the extended identifiers comprising the suffix.

libcpp/ChangeLog:

PR preprocessor/103902
* lex.cc (identifier_diagnostics_on_lex): New function refactoring
some common code.
(lex_identifier_intern): Use the new function.
(lex_identifier): Don't run identifier diagnostics here, rather let
the call site do it when needed.
(_cpp_lex_direct): Adjust the call sites of lex_identifier ()
acccordingly.
(struct scan_id_result): New struct.
(scan_cur_identifier): New function.
(create_literal2): New function.
(lit_accum::create_literal2): New function.
(is_macro): Folded into new function...
(maybe_ignore_udl_macro_suffix): ...here.
(is_macro_not_literal_suffix): Folded likewise.
(lex_raw_string): Handle UTF-8 in UDL suffix via scan_cur_identifier ().
(lex_string): Likewise.

gcc/testsuite/ChangeLog:

PR preprocessor/103902
* g++.dg/cpp0x/udlit-extended-id-1.C: New test.
* g++.dg/cpp0x/udlit-extended-id-2.C: New test.
* g++.dg/cpp0x/udlit-extended-id-3.C: New test.
* g++.dg/cpp0x/udlit-extended-id-4.C: New test.
---

Notes:
Hello-

This is the updated version of the patch, incorporating feedback from Jakub
and Jason, most recently discussed here:

https://gcc.gnu.org/pipermail/gcc-patches/2023-February/612073.html

Please let me know how it looks? It is simpler than before with the new
approach. Thanks!

One thing to note. As Jason clarified for me, a usage like this:

 #pragma GCC poison _x
const char * operator "" _x (const char *, unsigned long);

The space between the "" and the _x is currently allowed but will be
deprecated in C++23. GCC currently will complain about the poisoned use of
_x in this case, and this patch, which is just focused on handling UTF-8
properly, does not change this. But it seems that it would be correct
not to apply poison in this case. I can try to follow up with a patch to do
so, if it seems worthwhile? Given the syntax is deprecated, maybe it's not
worth it...

For the time being, this patch does add a testcase for the above and xfails
it. For the case where no space is present, which is the part touched by the
present patch, existing behavior is preserved correctly and no diagnostics
such as poison are issued for the UDL suffix. (Contrary to v1 of this
patch.)

Thanks! bootstrap + regtested all languages on x86-64 Linux with
no regressions.

-Lewis

 .../g++.dg/cpp0x/udlit-extended-id-1.C|  68 
 .../g++.dg/cpp0x/udlit-extended-id-2.C|   6 +
 .../g++.dg/cpp0x/udlit-extended-id-3.C|  15 +
 .../g++.dg/cpp0x/udlit-extended-id-4.C|  14 +
 libcpp/lex.cc | 382 ++
 5 files changed, 317 insertions(+), 168 deletions(-)
 create mode 100644 gcc/testsuite/g++.dg/cpp0x/udlit-extended-id-1.C
 create mode 100644 gcc/testsuite/g++.dg/cpp0x/udlit-extended-id-2.C
 create mode 100644 gcc/testsuite/g++.dg/cpp0x/udlit-extended-id-3.C
 create mode 100644 gcc/testsuite/g++.dg/cpp0x/udlit-extended-id-4.C

diff --git a/gcc/testsuite/g++.dg/cpp0x/udlit-extended-id-1.C 
b/gcc/testsuite/g++.dg/cpp0x/udlit-extended-id-1.C
new file mode 100644
index 000..411d4fdd0ba
--- /dev/null
+++ b/gcc/testsuite/g++.dg/cpp0x/udlit-extended-id-1.C
@@ -0,0 +1,68 @@
+// { dg-do run { target c++11 } }
+// { dg-additional-options "-Wno-error=normalized" }
+#include 
+using namespace std;
+
+constexpr unsigned long long operator "" _π (unsigned long long x)
+{
+  return 3 * x;
+}
+
+/* Historically we didn't parse properly as part of the "" token, so check that
+   as well.  */
+constexpr unsigned long long operator ""_Π2 (

Re: [wwwdocs] gcc-13/porting_to.html: Document C++ -fexcess-precision=standard

[Jakub Jelinek via Gcc-patches]

On Fri, Mar 03, 2023 at 12:05:09AM +0100, Gerald Pfeifer wrote:
> On Thu, 2 Mar 2023, Jakub Jelinek wrote:
> > +
> > +#include 
> 
> Oops, in HTML we need to spell "<" as "<" and ">" as "> - otherwise
> the above would be seen as a tag by the name of stdlib.h. ;-)
> 
> I pushed the follow-up patch below.

Oops, missed that.  Thanks.

Jakub

Re: [wwwdocs] gcc-13/porting_to.html: Document C++ -fexcess-precision=standard

[Gerald Pfeifer]

On Thu, 2 Mar 2023, Jakub Jelinek wrote:
> +
> +#include 

Oops, in HTML we need to spell "<" as "<" and ">" as "> - otherwise
the above would be seen as a tag by the name of stdlib.h. ;-)

I pushed the follow-up patch below.

Gerald


commit 935fcdebfb2fb4dcd89edb51ebed5f1be0fb41e5
Author: Gerald Pfeifer 
Date:   Thu Mar 2 23:58:29 2023 +0100

gcc-13: Use < and > where necessary

diff --git a/htdocs/gcc-13/porting_to.html b/htdocs/gcc-13/porting_to.html
index f0ccef69..953e1453 100644
--- a/htdocs/gcc-13/porting_to.html
+++ b/htdocs/gcc-13/porting_to.html
@@ -129,7 +129,7 @@ constants and expressions.  E.g. for 
FLT_EVAL_METHOD equal
 to 2 on ia32:
 
 
-#include 
+#include 
 void foo (void) { if (1.1f + 3.3f != 1.1L + 3.3L) abort (); }
 void bar (void) { double d = 4.2; if (d == 4.2) abort (); }
 

[r13-6414 Regression] FAIL: gcc.dg/memchr-3.c target llp64 (test for warnings, line 9) on Linux/x86_64

[haochen.jiang via Gcc-patches]

On Linux/x86_64,

62a8d31ecc07041af4a81353c2d57d9845c4b771 is the first bad commit
commit 62a8d31ecc07041af4a81353c2d57d9845c4b771
Author: Jonathan Yong <10wa...@gmail.com>
Date:   Mon Feb 27 10:02:32 2023 +

gcc.dg/memchr-3.c: Account for LLP64 warnings

caused

FAIL: gcc.dg/memchr-3.c  target llp64  (test for warnings, line 9)

with GCC configured with

../../gcc/configure 
--prefix=/export/users/haochenj/src/gcc-bisect/master/master/r13-6414/usr 
--enable-clocale=gnu --with-system-zlib --with-demangler-in-ld 
--with-fpmath=sse --enable-languages=c,c++,fortran --enable-cet --without-isl 
--enable-libmpx x86_64-linux --disable-bootstrap

To reproduce:

$ cd {build_dir}/gcc && make check RUNTESTFLAGS="dg.exp=gcc.dg/memchr-3.c 
--target_board='unix{-m32}'"
$ cd {build_dir}/gcc && make check RUNTESTFLAGS="dg.exp=gcc.dg/memchr-3.c 
--target_board='unix{-m32\ -march=cascadelake}'"
$ cd {build_dir}/gcc && make check RUNTESTFLAGS="dg.exp=gcc.dg/memchr-3.c 
--target_board='unix{-m64}'"
$ cd {build_dir}/gcc && make check RUNTESTFLAGS="dg.exp=gcc.dg/memchr-3.c 
--target_board='unix{-m64\ -march=cascadelake}'"

(Please do not reply to this email, for question about this report, contact me 
at haochen dot jiang at intel.com)

Re: [PATCH] libgccjit: Fix a failing test

[David Malcolm via Gcc-patches]

On Thu, 2023-03-02 at 23:35 +0100, Guillaume Gomez wrote:
> I don't have push rights so if you could push it, it'd be super
> appreciated!

Done, as r13-6425-g6b432c0f777ab9; I took the liberty of slightly
tweaking the subject line to add a "jit, testsuite: " prefix.

Thanks again for the patch
Dave

Ping: [PATCH 2/2] Rework 128-bit complex multiply and divide.

[Michael Meissner via Gcc-patches]

This patch is second in importance after the first patch in the series.  It is
needed to allow complex IBM 128-bit multiply/divide when long double is IEEE
128-bit.

| Date: Fri, 3 Feb 2023 00:53:05 -0500
| From: Michael Meissner 
| Subject: [PATCH 2/2] Rework 128-bit complex multiply and divide.
| Message-ID: 

-- 
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com

Ping: [PATCH 1/2] PR target/107299: Fix build issue when long double is IEEE 128-bit

[Michael Meissner via Gcc-patches]

This is the most important patch.  It is needed to allow the boostrap to work
again when long double is IEEE 128-bit.

| Date: Fri, 3 Feb 2023 00:49:12 -0500
| From: Michael Meissner 
| Subject: [PATCH 1/2] PR target/107299: Fix build issue when long double is 
IEEE 128-bit
| Message-ID: 

-- 
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com

Re: [PATCH] libgccjit: Fix a failing test

[Guillaume Gomez via Gcc-patches]

I don't have push rights so if you could push it, it'd be super appreciated!

Le jeu. 2 mars 2023 à 23:33, David Malcolm  a écrit :

> On Thu, 2023-03-02 at 23:29 +0100, Guillaume Gomez wrote:
> > Just realized I used whitespace and not a tab. Sorry about that.
> > Here's the
> > fixed version...
>
> Looks great.  Do you have push rights, or do you want me to push this?
>
> Thanks
> Dave
>
> >
> > Le jeu. 2 mars 2023 à 23:19, Guillaume Gomez
> >  a
> > écrit :
> >
> > > No problem, thanks for the explanations.
> > >
> > > I joined the patch with the fixed commit message.
> > >
> > > Le jeu. 2 mars 2023 à 22:58, David Malcolm  a
> > > écrit :
> > >
> > > > On Thu, 2022-12-15 at 08:34 +0100, Guillaume Gomez via Jit wrote:
> > > > > Forgot it indeed, thanks for notifying me!
> > > > >
> > > > > I modified the commit message to add it and added it into this
> > > > > email.
> > > >
> > > > Sorry about the delay in reviewing this; for some reason I didn't
> > > > see
> > > > the mail.
> > > >
> > > > The patch looks good for trunk, but please add a reference to
> > > >   PR jit/107999
> > > > to the subject line and ChangeLog message.
> > > >
> > > > Dave
> > > >
> > > > >
> > > > > Le mer. 14 déc. 2022 à 16:12, Antoni Boucher 
> > > > > a
> > > > > écrit :
> > > > >
> > > > > > Thanks!
> > > > > >
> > > > > > In your patch, you're missing this line at the end of the
> > > > > > commit
> > > > > > message:
> > > > > >
> > > > > >Signed-off-by: Guillaume Gomez
> > > > > > 
> > > > > >
> > > > > > On Wed, 2022-12-14 at 14:39 +0100, Guillaume Gomez via Jit
> > > > > > wrote:
> > > > > > > Hi,
> > > > > > >
> > > > > > > This fixes bug 107999.
> > > > > > >
> > > > > > > Thanks in advance for the review.
> > > > > >
> > > > > >
> > > >
> > > >
>
>

Re: [PATCH] libgccjit: Fix a failing test

[David Malcolm via Gcc-patches]

On Thu, 2023-03-02 at 23:29 +0100, Guillaume Gomez wrote:
> Just realized I used whitespace and not a tab. Sorry about that.
> Here's the
> fixed version...

Looks great.  Do you have push rights, or do you want me to push this?

Thanks
Dave

> 
> Le jeu. 2 mars 2023 à 23:19, Guillaume Gomez
>  a
> écrit :
> 
> > No problem, thanks for the explanations.
> > 
> > I joined the patch with the fixed commit message.
> > 
> > Le jeu. 2 mars 2023 à 22:58, David Malcolm  a
> > écrit :
> > 
> > > On Thu, 2022-12-15 at 08:34 +0100, Guillaume Gomez via Jit wrote:
> > > > Forgot it indeed, thanks for notifying me!
> > > > 
> > > > I modified the commit message to add it and added it into this
> > > > email.
> > > 
> > > Sorry about the delay in reviewing this; for some reason I didn't
> > > see
> > > the mail.
> > > 
> > > The patch looks good for trunk, but please add a reference to
> > >   PR jit/107999
> > > to the subject line and ChangeLog message.
> > > 
> > > Dave
> > > 
> > > > 
> > > > Le mer. 14 déc. 2022 à 16:12, Antoni Boucher 
> > > > a
> > > > écrit :
> > > > 
> > > > > Thanks!
> > > > > 
> > > > > In your patch, you're missing this line at the end of the
> > > > > commit
> > > > > message:
> > > > > 
> > > > >    Signed-off-by: Guillaume Gomez
> > > > > 
> > > > > 
> > > > > On Wed, 2022-12-14 at 14:39 +0100, Guillaume Gomez via Jit
> > > > > wrote:
> > > > > > Hi,
> > > > > > 
> > > > > > This fixes bug 107999.
> > > > > > 
> > > > > > Thanks in advance for the review.
> > > > > 
> > > > > 
> > > 
> > > 

Re: [PATCH] libgccjit: Fix a failing test

[Guillaume Gomez via Gcc-patches]

Just realized I used whitespace and not a tab. Sorry about that. Here's the
fixed version...

Le jeu. 2 mars 2023 à 23:19, Guillaume Gomez  a
écrit :

> No problem, thanks for the explanations.
>
> I joined the patch with the fixed commit message.
>
> Le jeu. 2 mars 2023 à 22:58, David Malcolm  a écrit :
>
>> On Thu, 2022-12-15 at 08:34 +0100, Guillaume Gomez via Jit wrote:
>> > Forgot it indeed, thanks for notifying me!
>> >
>> > I modified the commit message to add it and added it into this email.
>>
>> Sorry about the delay in reviewing this; for some reason I didn't see
>> the mail.
>>
>> The patch looks good for trunk, but please add a reference to
>>   PR jit/107999
>> to the subject line and ChangeLog message.
>>
>> Dave
>>
>> >
>> > Le mer. 14 déc. 2022 à 16:12, Antoni Boucher  a
>> > écrit :
>> >
>> > > Thanks!
>> > >
>> > > In your patch, you're missing this line at the end of the commit
>> > > message:
>> > >
>> > >Signed-off-by: Guillaume Gomez 
>> > >
>> > > On Wed, 2022-12-14 at 14:39 +0100, Guillaume Gomez via Jit wrote:
>> > > > Hi,
>> > > >
>> > > > This fixes bug 107999.
>> > > >
>> > > > Thanks in advance for the review.
>> > >
>> > >
>>
>>
From 0835c7ba8bdf4090c7fb102206e70c1ed235808e Mon Sep 17 00:00:00 2001
From: Guillaume Gomez 
Date: Wed, 14 Dec 2022 14:28:22 +0100
Subject: [PATCH] [PATCH] Fix a failing test by updating its error string
 [PR107999]

gcc/testsuite/ChangeLog:
	PR jit/107999
	* jit.dg/test-error-array-bounds.c: Update test.

Signed-off-by: Guillaume Gomez 
---
 gcc/testsuite/jit.dg/test-error-array-bounds.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/jit.dg/test-error-array-bounds.c b/gcc/testsuite/jit.dg/test-error-array-bounds.c
index b6c0ee526d4..a0dead13cb7 100644
--- a/gcc/testsuite/jit.dg/test-error-array-bounds.c
+++ b/gcc/testsuite/jit.dg/test-error-array-bounds.c
@@ -70,5 +70,5 @@ verify_code (gcc_jit_context *ctxt, gcc_jit_result *result)
   /* ...and that the message was captured by the API.  */
   CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt),
 		  "array subscript 10 is above array bounds of"
-		  " 'char[10]' [-Warray-bounds]");
+		  " 'char[10]' [-Warray-bounds=]");
 }
-- 
2.34.1

[pushed][PR90706] IRA: Use minimal cost for hard register movement

[Vladimir Makarov via Gcc-patches]

The following patch is for

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90706

The patch was successfully bootstrapped and tested on i686, x86-64, 
aarch64, ppc64le.


commit 23661e39df76e07fb4ce1ea015379c7601d947ef
Author: Vladimir N. Makarov 
Date:   Thu Mar 2 16:29:05 2023 -0500

IRA: Use minimal cost for hard register movement

This is the 2nd attempt to fix PR90706.  IRA calculates wrong AVR
costs for moving general hard regs of SFmode.  This was the reason for
spilling a pseudo in the PR.  In this patch we use smaller move cost
of hard reg in its natural and operand modes.

PR rtl-optimization/90706

gcc/ChangeLog:

* ira-costs.cc: Include print-rtl.h.
(record_reg_classes, scan_one_insn): Add code to print debug info.
(record_operand_costs): Find and use smaller cost for hard reg
move.

gcc/testsuite/ChangeLog:

* gcc.target/avr/pr90706.c: New.

diff --git a/gcc/ira-costs.cc b/gcc/ira-costs.cc
index 4c28171f27d..c0fdef807dd 100644
--- a/gcc/ira-costs.cc
+++ b/gcc/ira-costs.cc
@@ -34,6 +34,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "ira-int.h"
 #include "addresses.h"
 #include "reload.h"
+#include "print-rtl.h"
 
 /* The flags is set up every time when we calculate pseudo register
classes through function ira_set_pseudo_classes.  */
@@ -503,6 +504,18 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops,
   int insn_allows_mem[MAX_RECOG_OPERANDS];
   move_table *move_in_cost, *move_out_cost;
   short (*mem_cost)[2];
+  const char *p;
+
+  if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
+{
+  fprintf (ira_dump_file, "Processing insn %u", INSN_UID (insn));
+  if (INSN_CODE (insn) >= 0
+	  && (p = get_insn_name (INSN_CODE (insn))) != NULL)
+	fprintf (ira_dump_file, " {%s}", p);
+  fprintf (ira_dump_file, " (freq=%d)\n",
+	   REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn)));
+  dump_insn_slim (ira_dump_file, insn);
+  }
 
   for (i = 0; i < n_ops; i++)
 insn_allows_mem[i] = 0;
@@ -526,6 +539,21 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops,
 	  continue;
 	}
 
+  if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
+	{
+	  fprintf (ira_dump_file, "  Alt %d:", alt);
+	  for (i = 0; i < n_ops; i++)
+	{
+	  p = constraints[i];
+	  if (*p == '\0')
+		continue;
+	  fprintf (ira_dump_file, "  (%d) ", i);
+	  for (; *p != '\0' && *p != ',' && *p != '#'; p++)
+		fputc (*p, ira_dump_file);
+	}
+	  fprintf (ira_dump_file, "\n");
+	}
+
   for (i = 0; i < n_ops; i++)
 	{
 	  unsigned char c;
@@ -593,12 +621,16 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops,
 		 register, this alternative can't be used.  */
 
 		  if (classes[j] == NO_REGS)
-		alt_fail = 1;
-		  /* Otherwise, add to the cost of this alternative
-		 the cost to copy the other operand to the hard
-		 register used for this operand.  */
+		{
+		  alt_fail = 1;
+		}
 		  else
-		alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL);
+		/* Otherwise, add to the cost of this alternative the cost
+		   to copy the other operand to the hard register used for
+		   this operand.  */
+		{
+		  alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL);
+		}
 		}
 	  else
 		{
@@ -1021,18 +1053,45 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops,
   for (i = 0; i < n_ops; i++)
 	if (REG_P (ops[i]) && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
 	  {
+	int old_cost;
+	bool cost_change_p = false;
 	struct costs *pp = op_costs[i], *qq = this_op_costs[i];
 	int *pp_costs = pp->cost, *qq_costs = qq->cost;
 	int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
 	cost_classes_t cost_classes_ptr
 	  = regno_cost_classes[REGNO (ops[i])];
 
-	pp->mem_cost = MIN (pp->mem_cost,
+	old_cost = pp->mem_cost;
+	pp->mem_cost = MIN (old_cost,
 (qq->mem_cost + op_cost_add) * scale);
 
+	if (ira_dump_file != NULL && internal_flag_ira_verbose > 5
+		&& pp->mem_cost < old_cost)
+	  {
+		cost_change_p = true;
+		fprintf (ira_dump_file, "op %d(r=%u) new costs MEM:%d",
+			 i, REGNO(ops[i]), pp->mem_cost);
+	  }
 	for (k = cost_classes_ptr->num - 1; k >= 0; k--)
-	  pp_costs[k]
-		= MIN (pp_costs[k], (qq_costs[k] + op_cost_add) * scale);
+	  {
+		old_cost = pp_costs[k];
+		pp_costs[k]
+		  = MIN (old_cost, (qq_costs[k] + op_cost_add) * scale);
+		if (ira_dump_file != NULL && internal_flag_ira_verbose > 5
+		&& pp_costs[k] < old_cost)
+		  {
+		if (!cost_change_p)
+		  fprintf (ira_dump_file, "op %d(r=%u) new costs",
+			   i, REGNO(ops[i]));
+		cost_change_p = true;
+		fprintf (ira_dump_file, " %s:%d",
+			 reg_class_names[cost_classes_ptr->classes[k]],
+			 pp_costs[k]);
+		  }
+	  }
+	if (ira_dump_file != NULL && internal_flag_ira_verbose > 5
+

Re: [PATCH] libgccjit: Fix a failing test

[Guillaume Gomez via Gcc-patches]

No problem, thanks for the explanations.

I joined the patch with the fixed commit message.

Le jeu. 2 mars 2023 à 22:58, David Malcolm  a écrit :

> On Thu, 2022-12-15 at 08:34 +0100, Guillaume Gomez via Jit wrote:
> > Forgot it indeed, thanks for notifying me!
> >
> > I modified the commit message to add it and added it into this email.
>
> Sorry about the delay in reviewing this; for some reason I didn't see
> the mail.
>
> The patch looks good for trunk, but please add a reference to
>   PR jit/107999
> to the subject line and ChangeLog message.
>
> Dave
>
> >
> > Le mer. 14 déc. 2022 à 16:12, Antoni Boucher  a
> > écrit :
> >
> > > Thanks!
> > >
> > > In your patch, you're missing this line at the end of the commit
> > > message:
> > >
> > >Signed-off-by: Guillaume Gomez 
> > >
> > > On Wed, 2022-12-14 at 14:39 +0100, Guillaume Gomez via Jit wrote:
> > > > Hi,
> > > >
> > > > This fixes bug 107999.
> > > >
> > > > Thanks in advance for the review.
> > >
> > >
>
>
From 985228a76feecf16658b95a012e0b531e7e5c750 Mon Sep 17 00:00:00 2001
From: Guillaume Gomez 
Date: Wed, 14 Dec 2022 14:28:22 +0100
Subject: [PATCH] [PATCH] Fix a failing test by updating its error string
 [PR107999]

gcc/testsuite/ChangeLog:
PR jit/107999
	* jit.dg/test-error-array-bounds.c: Update test.

Signed-off-by: Guillaume Gomez 
---
 gcc/testsuite/jit.dg/test-error-array-bounds.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/jit.dg/test-error-array-bounds.c b/gcc/testsuite/jit.dg/test-error-array-bounds.c
index b6c0ee526d4..a0dead13cb7 100644
--- a/gcc/testsuite/jit.dg/test-error-array-bounds.c
+++ b/gcc/testsuite/jit.dg/test-error-array-bounds.c
@@ -70,5 +70,5 @@ verify_code (gcc_jit_context *ctxt, gcc_jit_result *result)
   /* ...and that the message was captured by the API.  */
   CHECK_STRING_VALUE (gcc_jit_context_get_first_error (ctxt),
 		  "array subscript 10 is above array bounds of"
-		  " 'char[10]' [-Warray-bounds]");
+		  " 'char[10]' [-Warray-bounds=]");
 }
-- 
2.34.1

[PATCH] Fortran: fix CLASS attribute handling [PR106856]

[Harald Anlauf via Gcc-patches]

Dear all,

the attached patch fixes a long-standing issue with CLASS attributes
when a declaration is scattered over multiple statements.

The major part ("draft") of the patch is by Tobias, which I took up
before it started to bit-rot too much, see PR.  It is mainly about
a proper updating and book-keeping of symbol attributes.

While debugging the draft patch, I fixed a few disturbing memleaks
in class.cc that showed up when looking at intermediate fallout.

This patch also addresses issues reported in a few other PRs:
pr53951, pr101101, pr104229, pr107380.  These are mostly
duplicates at some level.

Regtested on x86_64-pc-linux-gnu.  OK for mainline?

Thanks,
Harald

From 4600577e3ecceb2525618685f47c8a979cf9d244 Mon Sep 17 00:00:00 2001
From: Harald Anlauf 
Date: Thu, 2 Mar 2023 22:37:14 +0100
Subject: [PATCH] Fortran: fix CLASS attribute handling [PR106856]

gcc/fortran/ChangeLog:

	PR fortran/106856
	* class.cc (gfc_build_class_symbol): Handle update of attributes of
	existing class container.
	(gfc_find_derived_vtab): Fix several memory leaks.
	* decl.cc (attr_decl1): Manage update of symbol attributes from
	CLASS attributes.
	* primary.cc (gfc_variable_attr): OPTIONAL shall not be taken or
	updated from the class container.

gcc/testsuite/ChangeLog:

	PR fortran/106856
	* gfortran.dg/interface_41.f90: Remove dg-pattern from valid testcase.
	* gfortran.dg/class_74.f90: New test.
	* gfortran.dg/class_75.f90: New test.

Co-authored-by: Tobias Burnus  
---
 gcc/fortran/class.cc   | 23 +++--
 gcc/fortran/decl.cc| 59 +++---
 gcc/fortran/primary.cc |  1 -
 gcc/testsuite/gfortran.dg/class_74.f90 | 41 +++
 gcc/testsuite/gfortran.dg/class_75.f90 | 24 +
 gcc/testsuite/gfortran.dg/interface_41.f90 |  2 +-
 6 files changed, 115 insertions(+), 35 deletions(-)
 create mode 100644 gcc/testsuite/gfortran.dg/class_74.f90
 create mode 100644 gcc/testsuite/gfortran.dg/class_75.f90

diff --git a/gcc/fortran/class.cc b/gcc/fortran/class.cc
index ae653e74437..2eebdd4a3bb 100644
--- a/gcc/fortran/class.cc
+++ b/gcc/fortran/class.cc
@@ -638,6 +638,7 @@ gfc_build_class_symbol (gfc_typespec *ts, symbol_attribute *attr,
 {
   char tname[GFC_MAX_SYMBOL_LEN+1];
   char *name;
+  gfc_typespec *orig_ts = ts;
   gfc_symbol *fclass;
   gfc_symbol *vtab;
   gfc_component *c;
@@ -646,9 +647,21 @@ gfc_build_class_symbol (gfc_typespec *ts, symbol_attribute *attr,

   gcc_assert (as);

-  if (attr->class_ok)
-/* Class container has already been built.  */
+  /* Class container has already been built with same name.  */
+  if (attr->class_ok
+  && ts->u.derived->components->attr.dimension >= attr->dimension
+  && ts->u.derived->components->attr.codimension >= attr->codimension
+  && ts->u.derived->components->attr.class_pointer >= attr->pointer
+  && ts->u.derived->components->attr.allocatable >= attr->allocatable)
 return true;
+  if (attr->class_ok)
+{
+  attr->dimension |= ts->u.derived->components->attr.dimension;
+  attr->codimension |= ts->u.derived->components->attr.codimension;
+  attr->pointer |= ts->u.derived->components->attr.class_pointer;
+  attr->allocatable |= ts->u.derived->components->attr.allocatable;
+  ts = &ts->u.derived->components->ts;
+}

   attr->class_ok = attr->dummy || attr->pointer || attr->allocatable
 		   || attr->select_type_temporary || attr->associate_var;
@@ -790,7 +803,7 @@ gfc_build_class_symbol (gfc_typespec *ts, symbol_attribute *attr,
 }

   fclass->attr.is_class = 1;
-  ts->u.derived = fclass;
+  orig_ts->u.derived = fclass;
   attr->allocatable = attr->pointer = attr->dimension = attr->codimension = 0;
   (*as) = NULL;
   free (name);
@@ -2344,6 +2357,7 @@ gfc_find_derived_vtab (gfc_symbol *derived)
 	  vtab->attr.vtab = 1;
 	  vtab->attr.access = ACCESS_PUBLIC;
 	  gfc_set_sym_referenced (vtab);
+	  free (name);
 	  name = xasprintf ("__vtype_%s", tname);

 	  gfc_find_symbol (name, ns, 0, &vtype);
@@ -2447,6 +2461,7 @@ gfc_find_derived_vtab (gfc_symbol *derived)
 	  else
 		{
 		  /* Construct default initialization variable.  */
+		  free (name);
 		  name = xasprintf ("__def_init_%s", tname);
 		  gfc_get_symbol (name, ns, &def_init);
 		  def_init->attr.target = 1;
@@ -2480,6 +2495,7 @@ gfc_find_derived_vtab (gfc_symbol *derived)
 		  ns->contained = sub_ns;
 		  sub_ns->resolved = 1;
 		  /* Set up procedure symbol.  */
+		  free (name);
 		  name = xasprintf ("__copy_%s", tname);
 		  gfc_get_symbol (name, sub_ns, ©);
 		  sub_ns->proc_name = copy;
@@ -2558,6 +2574,7 @@ gfc_find_derived_vtab (gfc_symbol *derived)
 		  ns->contained = sub_ns;
 		  sub_ns->resolved = 1;
 		  /* Set up procedure symbol.  */
+		  free (name);
 		  name = xasprintf ("__deallocate_%s", tname);
 		  gfc_get_symbol (name, sub_ns, &dealloc);
 		  sub_ns->proc_name = dealloc;
diff --git a/gcc/fortran/decl.cc b/gcc/fortran/decl.cc
index eec0314cf4

Re: [PATCH] libgccjit: Fix a failing test

[David Malcolm via Gcc-patches]

On Thu, 2022-12-15 at 08:34 +0100, Guillaume Gomez via Jit wrote:
> Forgot it indeed, thanks for notifying me!
> 
> I modified the commit message to add it and added it into this email.

Sorry about the delay in reviewing this; for some reason I didn't see
the mail.

The patch looks good for trunk, but please add a reference to
  PR jit/107999
to the subject line and ChangeLog message.

Dave

> 
> Le mer. 14 déc. 2022 à 16:12, Antoni Boucher  a
> écrit :
> 
> > Thanks!
> > 
> > In your patch, you're missing this line at the end of the commit
> > message:
> > 
> >    Signed-off-by: Guillaume Gomez 
> > 
> > On Wed, 2022-12-14 at 14:39 +0100, Guillaume Gomez via Jit wrote:
> > > Hi,
> > > 
> > > This fixes bug 107999.
> > > 
> > > Thanks in advance for the review.
> > 
> > 

Re: [PATCH v4] c++: -Wdangling-reference with reference wrapper [PR107532]

[Marek Polacek via Gcc-patches]

On Wed, Mar 01, 2023 at 04:53:23PM -0500, Jason Merrill wrote:
> > @@ -13791,12 +13830,39 @@ std_pair_ref_ref_p (tree t)
> >const int& y = (f(1), 42); // NULL_TREE
> >const int& z = f(f(1)); // f(f(1))
> > -   EXPR is the initializer.  */
> > +   EXPR is the initializer.  If ARG_P is true, we're processing an argument
> > +   to a function; the point is to distinguish between, for example,
> > +
> > + Ref::inner (&TARGET_EXPR )
> > +
> > +   where we shouldn't warn, and
> > +
> > + Ref::inner (&TARGET_EXPR )>)
> > +
> > +   where we should warn (Ref is a reference_like_class_p so we see through
> > +   it.  */
> >   static tree
> > -do_warn_dangling_reference (tree expr)
> > +do_warn_dangling_reference (tree expr, bool arg_p)
> >   {
> > STRIP_NOPS (expr);
> > +  if (TREE_CODE (expr) == ADDR_EXPR)
> > +expr = TREE_OPERAND (expr, 0);
> 
> I think if we move this here, we also need to check that expr before
> STRIP_NOPS had REFERENCE_TYPE.  OK with that change.

Sorry but I don't think I can do that.  There can be CONVERT_EXPRs
that need to be stripped, whether arg_p or !arg_p.  For example, we can get
(const int *) f ((const int &) &TARGET_EXPR >)
for
const int& r5 = (42, f(10));

Is the patch OK as-is then?

Marek

[wwwdocs] Document allocator_traits::rebind_alloc assertion with GCC 13

[Jonathan Wakely via Gcc-patches]

Pushed to wwwdocs.

---
 htdocs/gcc-13/porting_to.html | 60 +++
 1 file changed, 60 insertions(+)

diff --git a/htdocs/gcc-13/porting_to.html b/htdocs/gcc-13/porting_to.html
index 5cbeefb6..f0ccef69 100644
--- a/htdocs/gcc-13/porting_to.html
+++ b/htdocs/gcc-13/porting_to.html
@@ -144,5 +144,65 @@ done in the i387 floating point stack or are spilled from 
it.
 The -fexcess-precision=fast option can be used to request the
 previous behavior.
 
+allocator_traits::rebind_alloc 
must be A
+
+
+GCC 13 now checks that allocators used with the standard library
+can be "rebound" to allocate memory for a different type,
+as required by the allocator requirements in the C++ standard.
+If an allocator type Alloc
+cannot be correctly rebound to another type Alloc,
+you will get an error like this:
+
+
+
+.../bits/alloc_traits.h:70:31: error: static assertion failed: 
allocator_traits::rebind_alloc must be A
+
+
+
+The assertion checks that rebinding an allocator to its own value type is a
+no-op, which will be true if its rebind member is defined correctly.
+If rebinding it to its own value type produces a different type,
+then the allocator cannot be used with the standard library.
+
+
+
+The most common cause of this error is an allocator type 
Alloc
+that derives from std::allocator but does not provide its own
+rebind member. When the standard library attempts to rebind the
+allocator using Alloc::rebind it finds the
+std::allocator::rebind member from the base class,
+and the result is std::allocator instead of
+Alloc.
+
+
+
+The solution is to provide a correct rebind member as shown below.
+A converting constructor must also be provided, so that that an
+Alloc can be constructed from an Alloc,
+and vice versa:
+
+
+template
+class Alloc
+{
+  Alloc();
+  
+  template Alloc(const Alloc);
+
+  template struct rebind { using other = Alloc; };
+  
+  // ...
+};
+
+
+
+Since C++20, there is no rebind member in std::allocator,
+so deriving your own allocator types from std::allocator is simpler
+and doesn't require the derived allocator to provide its own rebind.
+For compatibility with previous C++ standards, the member should still be
+provided. The converting constructor is still required even in C++20.
+
+
 
 
-- 
2.39.2