[PATCH] RISC-V: Pattern name fix mulm3_highpart -> smulm3_highpart.
gcc/ChangeLog:
* config/riscv/riscv.md
(muldi3_highpart): Rename to muldi3_highpart.
(mulditi3): Emit muldi3_highpart.
(mulsi3_highpart): Rename to mulsi3_highpart.
(mulsidi3): Emit mulsi3_highpart.
---
gcc/config/riscv/riscv.md | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f88877fd596..3115a508bdf 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -899,14 +899,14 @@
emit_insn (gen_muldi3 (low, operands[1], operands[2]));
rtx high = gen_reg_rtx (DImode);
- emit_insn (gen_muldi3_highpart (high, operands[1], operands[2]));
+ emit_insn (gen_muldi3_highpart (high, operands[1], operands[2]));
emit_move_insn (gen_lowpart (DImode, operands[0]), low);
emit_move_insn (gen_highpart (DImode, operands[0]), high);
DONE;
})
-(define_insn "muldi3_highpart"
+(define_insn "muldi3_highpart"
[(set (match_operand:DI0 "register_operand" "=r")
(truncate:DI
(lshiftrt:TI
@@ -961,13 +961,13 @@
{
rtx temp = gen_reg_rtx (SImode);
emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
- emit_insn (gen_mulsi3_highpart (riscv_subword (operands[0], true),
+ emit_insn (gen_mulsi3_highpart (riscv_subword (operands[0], true),
operands[1], operands[2]));
emit_insn (gen_movsi (riscv_subword (operands[0], false), temp));
DONE;
})
-(define_insn "mulsi3_highpart"
+(define_insn "mulsi3_highpart"
[(set (match_operand:SI0 "register_operand" "=r")
(truncate:SI
(lshiftrt:DI
--
2.22.0.windows.1
[PATCH] RISC-V: The 'multilib-generator' enhancement.
From: gengqi
gcc/ChangeLog:
* config/riscv/arch-canonicalize
(longext_sort): New function for sorting 'multi-letter'.
* config/riscv/multilib-generator: Skip to next loop when current
'alt' is 'arch'. The 'arch' may not be the first of 'alts'.
(_expand_combination): Add underline for the ext without '*'.
This is because, a single-letter extension can always be treated well
with a '_' prefix, but it cannot be separated out if it is appended
to a multi-letter.
---
gcc/config/riscv/arch-canonicalize | 14 +-
gcc/config/riscv/multilib-generator | 12 +++-
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/arch-canonicalize
b/gcc/config/riscv/arch-canonicalize
index 2b4289e..a1e4570 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -74,8 +74,20 @@ def arch_canonicalize(arch):
# becasue we just append extensions list to the arch string.
std_exts += list(filter(lambda x:len(x) == 1, long_exts))
+ def longext_sort (exts):
+if not exts.startswith("zxm") and exts.startswith("z"):
+ # If "Z" extensions are named, they should be ordered first by CANONICAL.
+ if exts[1] not in CANONICAL_ORDER:
+raise Exception("Unsupported extension `%s`" % exts)
+ canonical_sort = CANONICAL_ORDER.index(exts[1])
+else:
+ canonical_sort = -1
+return (exts.startswith("x"), exts.startswith("zxm"),
+LONG_EXT_PREFIXES.index(exts[0]), canonical_sort, exts[1:])
+
# Multi-letter extension must be in lexicographic order.
- long_exts = list(sorted(filter(lambda x:len(x) != 1, long_exts)))
+ long_exts = list(sorted(filter(lambda x:len(x) != 1, long_exts),
+ key=longext_sort))
# Put extensions in canonical order.
for ext in CANONICAL_ORDER:
diff --git a/gcc/config/riscv/multilib-generator
b/gcc/config/riscv/multilib-generator
index 64ff15f..7b22537 100755
--- a/gcc/config/riscv/multilib-generator
+++ b/gcc/config/riscv/multilib-generator
@@ -68,15 +68,15 @@ def arch_canonicalize(arch):
def _expand_combination(ext):
exts = list(ext.split("*"))
- # No need to expand if there is no `*`.
- if len(exts) == 1:
-return [(exts[0],)]
-
# Add underline to every extension.
# e.g.
# _b * zvamo => _b * _zvamo
exts = list(map(lambda x: '_' + x, exts))
+ # No need to expand if there is no `*`.
+ if len(exts) == 1:
+return [(exts[0],)]
+
# Generate combination!
ext_combs = []
for comb_len in range(1, len(exts)+1):
@@ -147,7 +147,9 @@ for cfg in sys.argv[1:]:
# Drop duplicated entry.
alts = unique(alts)
- for alt in alts[1:]:
+ for alt in alts:
+if alt == arch:
+ continue
arches[alt] = 1
reuse.append('march.%s/mabi.%s=march.%s/mabi.%s' % (arch, abi, alt, abi))
required.append('march=%s/mabi=%s' % (arch, abi))
--
2.7.4
[PATCH] C-SKY: Support fpuv2:fldrd/fstrd and fpuv3:fldr.64/fstr.64.
gcc/ChangeLog:
* config/csky/csky.c (ck810_legitimate_index_p): Modified for
support "base + index" with DF mode.
* config/csky/constraints.md ("Y"): New constraint for memory operands
without index register.
* config/csky/csky_insn_fpuv2.md
(fpuv3_movdf):At constraints, use "Y" instead of "m" where mov between
memory and general registers, and put them baskwards.
* config/csky/csky_insn_fpuv3.md
(fpuv2_movdf): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/csky/fldrd_fstrd.c: New.
* gcc.target/csky/fpuv3/fldr64_fstr64.c: New.
---
gcc/config/csky/constraints.md | 4
gcc/config/csky/csky.c | 3 ++-
gcc/config/csky/csky_insn_fpuv2.md | 4 ++--
gcc/config/csky/csky_insn_fpuv3.md | 16
gcc/testsuite/gcc.target/csky/fldrd_fstrd.c | 17 +
gcc/testsuite/gcc.target/csky/fpuv3/fldr64_fstr64.c | 18 ++
6 files changed, 51 insertions(+), 11 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/csky/fldrd_fstrd.c
create mode 100644 gcc/testsuite/gcc.target/csky/fpuv3/fldr64_fstr64.c
diff --git a/gcc/config/csky/constraints.md b/gcc/config/csky/constraints.md
index c9bc9f2..2641ab3 100644
--- a/gcc/config/csky/constraints.md
+++ b/gcc/config/csky/constraints.md
@@ -38,6 +38,10 @@
"Memory operands with base register, index register"
(match_test "csky_valid_mem_constraint_operand (op, \"W\")"))
+(define_memory_constraint "Y"
+ "Memory operands without index register"
+ (not (match_test "csky_valid_mem_constraint_operand (op, \"W\")")))
+
(define_constraint "R"
"Memory operands whose address is a label_ref"
(and (match_code "mem")
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index e4c92fe..e55821f 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -3136,7 +3136,8 @@ ck810_legitimate_index_p (machine_mode mode, rtx index,
int strict_p)
/* The follow index is for ldr instruction, the ldr cannot
load dword data, so the mode size should not be larger than
4. */
- else if (GET_MODE_SIZE (mode) <= 4)
+ else if (GET_MODE_SIZE (mode) <= 4
+ || (TARGET_HARD_FLOAT && CSKY_VREG_MODE_P (mode)))
{
if (is_csky_address_register_rtx_p (index, strict_p))
return 1;
diff --git a/gcc/config/csky/csky_insn_fpuv2.md
b/gcc/config/csky/csky_insn_fpuv2.md
index 0a680f8..5a06b22 100644
--- a/gcc/config/csky/csky_insn_fpuv2.md
+++ b/gcc/config/csky/csky_insn_fpuv2.md
@@ -461,8 +461,8 @@
)
(define_insn "*fpuv2_movdf"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r, r,m, v,?r,Q,v,v,v")
- (match_operand:DF 1 "general_operand" " r,m,mF,r,?r, v,v,Q,v,m"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r, v,?r,Q,v,v,v,r, r,Y")
+ (match_operand:DF 1 "general_operand" " r,?r, v,v,Q,v,m,Y,YF,r"))]
"CSKY_ISA_FEATURE (fpv2_df)"
"* return csky_output_movedouble(operands, DFmode);"
[(set (attr "length")
diff --git a/gcc/config/csky/csky_insn_fpuv3.md
b/gcc/config/csky/csky_insn_fpuv3.md
index 053673c..7849795 100644
--- a/gcc/config/csky/csky_insn_fpuv3.md
+++ b/gcc/config/csky/csky_insn_fpuv3.md
@@ -71,27 +71,27 @@
)
(define_insn "*fpv3_movdf"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r, r,m,v,?r,Q,v,v,v, v")
- (match_operand:DF 1 "general_operand" "
r,m,mF,r,?r,v,v,Q,v,m,Dv"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r, v,?r,Q,v,v,v, v,r,
r,Y")
+ (match_operand:DF 1 "general_operand" " r,?r,
v,v,Q,v,m,Dv,Y,YF,r"))]
"CSKY_ISA_FEATURE(fpv3_df)"
"*
switch (which_alternative)
{
-case 4:
+case 1:
if (TARGET_BIG_ENDIAN)
return \"fmtvr.64\\t%0, %R1, %1\";
return \"fmtvr.64\\t%0, %1, %R1\";
-case 5:
+case 2:
if (TARGET_BIG_ENDIAN)
return \"fmfvr.64\\t%R0, %0, %1\";
return \"fmfvr.64\\t%0, %R0, %1\";
+case 3:
+case 4:
case 6:
-case 7:
-case 9:
return fpuv3_output_move(operands);
-case 8:
+case 5:
return \"fmov.64\\t%0, %1\";
-case 10:
+case 7:
return \"fmovi.64\\t%0, %1\";
default:
return csky_output_movedouble(operands, DFmode);
diff --git a/gcc/testsuite/gcc.target/csky/fldrd_fstrd.c
b/gcc/testsuite/gcc.target/csky/fldrd_fstrd.c
new file mode 100644
index 000..024de18
--- /dev/null
+++ b/gcc/testsuite/gcc.target/csky/fldrd_fstrd.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-csky-options "-mcpu=ck810f -O1 -mhard-float" } */
+
+double fldrd (double *pd, int index)
+{
+ return pd[index];
+}
+
+/* { dg-final { scan-assembler "fldrd" } } */
+
+void fstrd (double *pd, int index, double d)
+{
+ pd[index] = d;
+}
+
+/* { dg-final { scan-assembler "fstrd" } } */
+
diff --git a/gcc/testsuite/gcc.target/csky/fpuv3/fldr64_fstr64.c
b/gcc/testsuite/gcc.target/csky/fpuv3/fldr
[PATCH] C-SKY: Add insn "ldbs".
gcc/
* config/csky/csky.md (cskyv2_sextend_ldbs): New insn.
gcc/testsuite/
* gcc/testsuite/gcc.target/csky/ldbs.c: New.
---
gcc/config/csky/csky.md | 10 ++
gcc/testsuite/gcc.target/csky/ldbs.c | 11 +++
2 files changed, 21 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/csky/ldbs.c
diff --git a/gcc/config/csky/csky.md b/gcc/config/csky/csky.md
index c27d627..b980d4c 100644
--- a/gcc/config/csky/csky.md
+++ b/gcc/config/csky/csky.md
@@ -1533,6 +1533,7 @@
}"
)
+;; hi -> si
(define_insn "extendhisi2"
[(set (match_operand:SI0 "register_operand" "=r")
(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
@@ -1557,6 +1558,15 @@
"sextb %0, %1"
)
+(define_insn "*cskyv2_sextend_ldbs"
+ [(set (match_operand:SI0 "register_operand" "=r")
+(sign_extend:SI (match_operand:QI 1 "csky_simple_mem_operand" "m")))]
+ "CSKY_ISA_FEATURE (E2)"
+ "ld.bs\t%0, %1"
+ [(set_attr "length" "4")
+ (set_attr "type" "load")]
+)
+
;; qi -> hi
(define_insn "extendqihi2"
[(set (match_operand:HI0 "register_operand" "=r")
diff --git a/gcc/testsuite/gcc.target/csky/ldbs.c
b/gcc/testsuite/gcc.target/csky/ldbs.c
new file mode 100644
index 000..27a0254
--- /dev/null
+++ b/gcc/testsuite/gcc.target/csky/ldbs.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-mcpu=ck801" "-march=ck801" } { "*" } } */
+/* { dg-csky-options "-O1" } */
+
+int foo (signed char *pb)
+{
+ return *pb;
+}
+
+/* { dg-final { scan-assembler "ld.bs" } } */
+
--
2.7.4
[PATCH 1/4] C-SKY: Add fpuv3 instructions and CK860 arch.
gcc/ChangeLog:
* config/csky/constraints.md ("W"): New constriant for mem operand
with base reg, index register.
("Q"): Renamed and modified "csky_valid_fpuv2_mem_operand" to
"csky_valid_mem_constraint_operand" to deal with both "Q" and "W"
constraint.
("Dv"): New constraint for const double value that can be used at
fmovi instruction.
* config/csky/csky-modes.def (HFmode): New mode.
* config/csky/csky-protos.h (csky_valid_fpuv2_mem_operand): Rename
to "csky_valid_mem_constraint_operand" and support new constraint
"W".
(csky_get_movedouble_length): New.
(fpuv3_output_move): New.
(fpuv3_const_double): New.
* config/csky/csky.c (csky_option_override): New arch CK860 with fpv3.
(decompose_csky_address): Refine.
(csky_print_operand): New "CONST_DOUBLE" operand.
(csky_output_move): Support fpv3 instructions.
(csky_get_movedouble_length): New.
(fpuv3_output_move): New.
(fpuv3_const_double): New.
(csky_emit_compare): Cover float comparsion.
(csky_emit_compare_float): Refine.
(csky_vaild_fpuv2_mem_operand): Rename to
"csky_valid_mem_constraint_operand" and support new constraint "W".
(ck860_rtx_costs): New.
(csky_rtx_costs): Add the cost calculation of CK860.
(regno_reg_class): New vregs for fpuv3.
(csky_dbx_regno): Likewise.
(csky_cpu_cpp_builtins): New builtin macro for fpuv3.
(csky_conditional_register_usage): Suporrot fpuv3.
(csky_dwarf_register_span): Suporrot fpuv3.
(csky_init_builtins, csky_mangle_type): Support "__fp16" type.
(ck810_legitimate_index_p): Support fp16.
* gcc/config/csky/csky.h (TARGET_TLS): ADD CK860.
(CSKY_VREG_P, CSKY_VREG_LO_P, CSKY_VREG_HI_P): Support fpuv3.
(TARGET_SINGLE_FPU): Support fpuv3.
(TARGET_SUPPORT_FPV3): New.
(FIRST_PSEUDO_REGISTER): Change to 202 to hold the new fpuv3 registers.
(FIXED_REGISTERS, CALL_REALLY_USED_REGISTERS, REGISTER_NAMES,
REG_CLASS_CONTENTS): Support fpuv3.
* gcc/config/csky/csky.md (movsf): Move to cksy_insn_fpu.md and refine.
(csky_movsf_fpv2): Likewise.
(ck801_movsf): Likewise.
(csky_movsf): Likewise.
(movdf): Likewise.
(csky_movdf_fpv2): Likewise.
(ck801_movdf): Likewise.
(csky_movdf): Likewise.
(movsicc): Refine. Use "comparison_operatior" instead of
"ordered_comparison_operatior".
(addsicc): Likewise.
(CSKY_FIRST_VFP3_REGNUM, CSKY_LAST_VFP3_REGNUM): New constant.
(call_value_internal_vh): New.
* config/csky/csky_cores.def (CK860): New arch and cpu.
(fpv3_hf): New.
(fpv3_hsf): New.
(fpv3_sdf): New.
(fpv3): New.
* config/csky/csky_insn_fpu.md: Refactor. Separate all float patterns
into emit-patterns and match-patterns, remain the emit-patterns here,
and move the match-patterns to csky_insn_fpuv2.md or
csky_insn_fpuv3.md.
* config/csky/csky_insn_fpuv2.md: New file for fpuv2 instructions.
* config/csky/csky_insn_fpuv3.md: New file and new patterns for fpuv3
isntructions.
* config/csky/csky_isa.def (fcr): New.
(fpv3_hi): New.
(fpv3_hf): New.
(fpv3_sf): New.
(fpv3_df): New.
(CK860): New definition for ck860.
* gcc/config/csky/csky_tables.opt (ck860): New processors ck860,
ck860f. And new arch ck860.
(fpv3_hf): New.
(fpv3_hsf): New.
(fpv3_hdf): New.
(fpv3): New.
* config/csky/predicates.md (csky_float_comparsion_operator): Delete
"geu", "gtu", "leu", "ltu", which will never appear at float comparison.
* config/cksy/t-csky-elf, config/csky/t-csky-linux: Support 860.
* doc/md.texi: Add "Q" and "W" constraints for C-SKY.
---
gcc/config/csky/constraints.md | 13 +-
gcc/config/csky/csky-modes.def | 2 +
gcc/config/csky/csky-protos.h | 7 +-
gcc/config/csky/csky.c | 644 ++
gcc/config/csky/csky.h | 162 ++--
gcc/config/csky/csky.md| 127 ++
gcc/config/csky/csky_cores.def | 13 +
gcc/config/csky/csky_insn_fpu.md | 798 +++--
gcc/config/csky/csky_insn_fpuv2.md | 470 ++
gcc/config/csky/csky_insn_fpuv3.md | 497 +++
gcc/config/csky/csky_isa.def | 15 +
gcc/config/csky/csky_tables.opt| 21 +
gcc/config/csky/predicates.md | 3 +-
gcc/config/csky/t-csky-elf | 9 +-
gcc/config/csky/t-csky-linux | 11 +-
gcc/doc/md.texi| 8 +
16 files changed, 2125 insertions(+), 675 deletions(-)
create mode 100644 gcc/config/csky/csky-modes.def
create mode 100644 gcc/config/csky/csky_insn_fpuv2.md
create mode 100644
[PATCH 4/4] C-SKY: Separate FRAME_POINTER_REGNUM into FRAME_POINTER_REGNUM and HARD_FRAME_POINTER_REGNUM.
gcc/ChangeLog:
* config/csky/csky.h
(FRAME_POINTER_REGNUM): Use HARD_FRAME_POINTER_REGNUM and
FRAME_POINTER_REGNUM instead of the signle definition. The
signle definition may not work well at simplify_subreg_regno().
(ELIMINABLE_REGS): Add for HARD_FRAME_POINTER_REGNUM.
* config/csky/csky.c (get_csky_live_regs, csky_can_eliminate,
csky_initial_elimination_offset, csky_expand_prologue,
csky_expand_epilogue): Add for HARD_FRAME_POINTER_REGNUM.
---
gcc/config/csky/csky.c | 15 +--
gcc/config/csky/csky.h | 7 +--
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index 1a6cfd7..7f2af82 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -1751,12 +1751,12 @@ get_csky_live_regs (int *count)
save = true;
/* Frame pointer marked used. */
- else if (frame_pointer_needed && reg == FRAME_POINTER_REGNUM)
+ else if (frame_pointer_needed && reg == HARD_FRAME_POINTER_REGNUM)
save = true;
/* This is required for CK801/802 where FP is a fixed reg, otherwise
we end up with no FP value available to the DWARF-2 unwinder. */
- else if (crtl->calls_eh_return && reg == FRAME_POINTER_REGNUM)
+ else if (crtl->calls_eh_return && reg == HARD_FRAME_POINTER_REGNUM)
save = true;
/* CK801/802 also need special handling for LR because it's clobbered
@@ -1832,6 +1832,8 @@ csky_layout_stack_frame (void)
static bool
csky_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
{
+ if (to == FRAME_POINTER_REGNUM)
+return from != ARG_POINTER_REGNUM;
if (to == STACK_POINTER_REGNUM)
return !frame_pointer_needed;
return true;
@@ -1852,6 +1854,7 @@ csky_initial_elimination_offset (int from, int to)
switch (from)
{
case FRAME_POINTER_REGNUM:
+case HARD_FRAME_POINTER_REGNUM:
offset = cfun->machine->reg_offset;
break;
@@ -1866,7 +1869,7 @@ csky_initial_elimination_offset (int from, int to)
/* If we are asked for the offset to the frame pointer instead,
then subtract the difference between the frame pointer and stack
pointer. */
- if (to == FRAME_POINTER_REGNUM)
+ if (to == FRAME_POINTER_REGNUM || to == HARD_FRAME_POINTER_REGNUM)
offset -= cfun->machine->reg_offset;
return offset;
}
@@ -5785,7 +5788,7 @@ csky_expand_prologue (void)
of the register save area. */
if (frame_pointer_needed)
{
- insn = emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
+ insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
RTX_FRAME_RELATED_P (insn) = 1;
}
@@ -5848,7 +5851,7 @@ csky_expand_epilogue (void)
/* Restore the SP to the base of the register save area. */
if (frame_pointer_needed)
{
- insn = emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
+ insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
RTX_FRAME_RELATED_P (insn) = 1;
}
else
@@ -6004,7 +6007,7 @@ csky_set_eh_return_address (rtx source, rtx scratch)
if (frame_pointer_needed)
{
- basereg = frame_pointer_rtx;
+ basereg = hard_frame_pointer_rtx;
delta = 0;
}
else
diff --git a/gcc/config/csky/csky.h b/gcc/config/csky/csky.h
index 1fd72d0..f2b0d1c 100644
--- a/gcc/config/csky/csky.h
+++ b/gcc/config/csky/csky.h
@@ -342,7 +342,8 @@ extern int csky_arch_isa_features[];
#define STACK_POINTER_REGNUM CSKY_SP_REGNUM
/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM 8
+#define FRAME_POINTER_REGNUM 36
+#define HARD_FRAME_POINTER_REGNUM 8
/* Base register for access to arguments of the function. This is a fake
register that is always eliminated. */
@@ -370,7 +371,9 @@ extern int csky_arch_isa_features[];
#define ELIMINABLE_REGS \
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},\
{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},\
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
+ { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },\
+ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
+ { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }}
/* Define the offset between two registers, one to be eliminated, and the
other its replacement, at the start of a routine. */
--
2.7.4
[PATCH 3/4] C-SKY: Bug fix for bad setting of TARGET_DSP and TARGET_DIV.
gcc/ChangeLog:
* config/csky/csky.c (csky_option_override):
Init csky_arch_isa_features[] advanced, so TARGET_DSP
and TARGET_DIV can be set well.
---
gcc/config/csky/csky.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index b2160b9..1a6cfd7 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -2680,6 +2680,18 @@ csky_option_override (void)
TARGET_FDIVDU = 0;
}
+ /* Initialize boolean versions of the architectural flags, for use
+ in the .md file. */
+
+#undef CSKY_ISA
+#define CSKY_ISA(IDENT, DESC)\
+ { \
+csky_arch_isa_features[CSKY_ISA_FEATURE_GET (IDENT)] =\
+ bitmap_bit_p (csky_active_target.isa, CSKY_ISA_FEATURE_GET (IDENT)); \
+ }
+#include "csky_isa.def"
+#undef CSKY_ISA
+
/* Extended LRW instructions are enabled by default on CK801, disabled
otherwise. */
if (TARGET_ELRW == -1)
@@ -2752,18 +2764,6 @@ csky_option_override (void)
TARGET_MULTIPLE_STLD = 0;
}
- /* Initialize boolean versions of the architectural flags, for use
- in the .md file. */
-
-#undef CSKY_ISA
-#define CSKY_ISA(IDENT, DESC)\
- { \
-csky_arch_isa_features[CSKY_ISA_FEATURE_GET (IDENT)] =\
- bitmap_bit_p (csky_active_target.isa, CSKY_ISA_FEATURE_GET (IDENT)); \
- }
-#include "csky_isa.def"
-#undef CSKY_ISA
-
/* TODO */
/* Resynchronize the saved target options. */
--
2.7.4
[PATCH 2/4] C-SKY: Delete LO_REGS and HI_REGS, use HILO_REGS instead.
gcc/ChangeLog:
* config/csky/constraints.md ("l", "h"): Delete.
* config/csky/csky.h (reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Delete LO_REGS and HI_REGS.
* config/csky/csky.c (regno_reg_classm,
csky_secondary_reload, csky_register_move_cost):
Use HILO_REGS instead of LO_REGS and HI_REGS.
---
gcc/config/csky/constraints.md | 2 --
gcc/config/csky/csky.c | 7 +++
gcc/config/csky/csky.h | 8
3 files changed, 3 insertions(+), 14 deletions(-)
diff --git a/gcc/config/csky/constraints.md b/gcc/config/csky/constraints.md
index 937cb81..c9bc9f2 100644
--- a/gcc/config/csky/constraints.md
+++ b/gcc/config/csky/constraints.md
@@ -24,8 +24,6 @@
(define_register_constraint "b" "LOW_REGS" "r0 - r15")
(define_register_constraint "c" "C_REGS" "C register")
(define_register_constraint "y" "HILO_REGS" "HI and LO registers")
-(define_register_constraint "l" "LO_REGS" "LO register")
-(define_register_constraint "h" "HI_REGS" "HI register")
(define_register_constraint "v" "V_REGS" "vector registers")
(define_register_constraint "z" "SP_REGS" "SP register")
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index 6e97994..b2160b9 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -112,7 +112,7 @@ enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
/* Reserved. */
RESERVE_REGS,
/* CC,HI,LO registers. */
- C_REGS, HI_REGS, LO_REGS,
+ C_REGS, HILO_REGS, HILO_REGS,
/* Reserved. */
RESERVE_REGS, RESERVE_REGS, RESERVE_REGS, RESERVE_REGS,
RESERVE_REGS, RESERVE_REGS, RESERVE_REGS, RESERVE_REGS,
@@ -2477,8 +2477,7 @@ csky_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
/* We always require a general register when copying anything to
HI/LO_REGNUM, except when copying an SImode value from HI/LO_REGNUM
to a general register, or when copying from register 0. */
- if ((rclass == HILO_REGS || rclass == LO_REGS || rclass == HI_REGS)
- && !CSKY_GENERAL_REGNO_P (regno))
+ if (rclass == HILO_REGS && !CSKY_GENERAL_REGNO_P (regno))
return GENERAL_REGS;
if (rclass == V_REGS && !CSKY_GENERAL_REGNO_P (regno))
@@ -6546,7 +6545,7 @@ csky_register_move_cost (machine_mode mode
ATTRIBUTE_UNUSED,
|| (CLASS) == LOW_REGS)
#define HILO_REG_CLASS_P(CLASS) \
- ((CLASS) == HI_REGS || (CLASS) == LO_REGS || (CLASS) == HILO_REGS)
+ ((CLASS) == HILO_REGS)
#define V_REG_CLASS_P(CLASS) \
((CLASS) == V_REGS)
diff --git a/gcc/config/csky/csky.h b/gcc/config/csky/csky.h
index f535c42..1fd72d0 100644
--- a/gcc/config/csky/csky.h
+++ b/gcc/config/csky/csky.h
@@ -685,8 +685,6 @@ enum reg_class
LOW_REGS,
GENERAL_REGS,
C_REGS,
- HI_REGS,
- LO_REGS,
HILO_REGS,
V_REGS,
OTHER_REGS,
@@ -706,8 +704,6 @@ enum reg_class
"LOW_REGS", \
"GENERAL_REGS", \
"C_REGS",\
- "HI_REGS", \
- "LO_REGS", \
"HILO_REGS", \
"V_REGS",\
"OTHER_REGS",\
@@ -731,10 +727,6 @@ enum reg_class
0x, 0x, 0x},/* GENERAL_REGS
*/ \
{0x, 0x0002, 0x, 0x, \
0x, 0x, 0x},/* C_REGS
*/ \
- {0x, 0x0004, 0x, 0x, \
- 0x, 0x, 0x},/* HI_REG
*/ \
- {0x, 0x0008, 0x, 0x, \
- 0x, 0x, 0x},/* LO_REG
*/ \
{0x, 0x000c, 0x, 0x, \
0x, 0x, 0x},/* HILO_REGS
*/ \
{0x, 0xFFF0, 0x007FFF8F, 0x, \
--
2.7.4
[PATCH] RISC-V: Properly parse the letter 'p' in '-march'.
gcc/ChangeLog:
* common/config/riscv/riscv-common.c
(riscv_subset_list::parsing_subset_version): Properly parse the letter
'p' in '-march'.
(riscv_subset_list::parse_std_ext,
riscv_subset_list::parse_multiletter_ext): To handle errors generated
in riscv_subset_list::parsing_subset_version.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-12.c: New.
* gcc.target/riscv/attribute-19.c: New.
---
gcc/common/config/riscv/riscv-common.c| 67 ++-
gcc/testsuite/gcc.target/riscv/arch-12.c | 4 ++
gcc/testsuite/gcc.target/riscv/attribute-19.c | 4 ++
3 files changed, 42 insertions(+), 33 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-19.c
diff --git a/gcc/common/config/riscv/riscv-common.c
b/gcc/common/config/riscv/riscv-common.c
index 34b74e5..65e5641 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -518,40 +518,38 @@ riscv_subset_list::parsing_subset_version (const char
*ext,
unsigned version = 0;
unsigned major = 0;
unsigned minor = 0;
- char np;
*explicit_version_p = false;
- for (; *p; ++p)
-{
- if (*p == 'p')
- {
- np = *(p + 1);
-
- if (!ISDIGIT (np))
- {
- /* Might be beginning of `p` extension. */
- if (std_ext_p)
- {
- get_default_version (ext, major_version, minor_version);
- return p;
- }
- else
- {
- error_at (m_loc, "%<-march=%s%>: Expect number "
- "after %<%dp%>.", m_arch, version);
- return NULL;
- }
- }
-
- major = version;
- major_p = false;
- version = 0;
- }
- else if (ISDIGIT (*p))
- version = (version * 10) + (*p - '0');
- else
- break;
-}
+ if (*p == 'p')
+gcc_assert (std_ext_p);
+ else {
+for (; *p; ++p)
+ {
+ if (*p == 'p')
+ {
+ if (!ISDIGIT (*(p+1)))
+ {
+ error_at (m_loc, "%<-march=%s%>: Expect number "
+ "after %<%dp%>.", m_arch, version);
+ return NULL;
+ }
+ if (!major_p)
+ {
+ error_at (m_loc, "%<-march=%s%>: For %<%s%dp%dp?%>, version "
+ "number with more than 2 level is not supported.",
+ m_arch, ext, major, version);
+ return NULL;
+ }
+ major = version;
+ major_p = false;
+ version = 0;
+ }
+ else if (ISDIGIT (*p))
+ version = (version * 10) + (*p - '0');
+ else
+ break;
+ }
+ }
if (major_p)
major = version;
@@ -643,7 +641,7 @@ riscv_subset_list::parse_std_ext (const char *p)
return NULL;
}
- while (*p)
+ while (p != NULL && *p)
{
char subset[2] = {0, 0};
@@ -771,6 +769,9 @@ riscv_subset_list::parse_multiletter_ext (const char *p,
/* std_ext_p= */ false, &explicit_version_p);
free (ext);
+ if (end_of_version == NULL)
+ return NULL;
+
*q = '\0';
if (strlen (subset) == 1)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-12.c
b/gcc/testsuite/gcc.target/riscv/arch-12.c
new file mode 100644
index 000..29e16c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-12.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64im1p2p3 -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64im1p2p3': For 'm1p2p\\?', version number with more
than 2 level is not supported." "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-19.c
b/gcc/testsuite/gcc.target/riscv/attribute-19.c
new file mode 100644
index 000..18f68d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-19.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv64imp0p9 -mabi=lp64" } */
+int foo() {}
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_p0p9\"" } } */
--
2.7.4
[PATCH] RISC-V: Properly parse the letter 'p' in '-march'.
gcc/ChangeLog:
* common/config/riscv/riscv-common.c
(riscv_subset_list::parsing_subset_version): Properly parse the letter
'p' in '-march'.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-12.c: New.
* gcc.target/riscv/attribute-19.c: New.
---
gcc/common/config/riscv/riscv-common.c| 64 +--
gcc/testsuite/gcc.target/riscv/arch-12.c | 4 ++
gcc/testsuite/gcc.target/riscv/attribute-19.c | 4 ++
3 files changed, 40 insertions(+), 32 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-19.c
diff --git a/gcc/common/config/riscv/riscv-common.c
b/gcc/common/config/riscv/riscv-common.c
index 34b74e5..76f544e 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -518,40 +518,38 @@ riscv_subset_list::parsing_subset_version (const char
*ext,
unsigned version = 0;
unsigned major = 0;
unsigned minor = 0;
- char np;
*explicit_version_p = false;
- for (; *p; ++p)
-{
- if (*p == 'p')
- {
- np = *(p + 1);
-
- if (!ISDIGIT (np))
- {
- /* Might be beginning of `p` extension. */
- if (std_ext_p)
- {
- get_default_version (ext, major_version, minor_version);
- return p;
- }
- else
- {
- error_at (m_loc, "%<-march=%s%>: Expect number "
- "after %<%dp%>.", m_arch, version);
- return NULL;
- }
- }
-
- major = version;
- major_p = false;
- version = 0;
- }
- else if (ISDIGIT (*p))
- version = (version * 10) + (*p - '0');
- else
- break;
-}
+ if (*p == 'p')
+gcc_assert (std_ext_p);
+ else {
+for (; *p; ++p)
+ {
+ if (*p == 'p')
+ {
+ if (!ISDIGIT (*(p+1)))
+ {
+ error_at (m_loc, "%<-march=%s%>: Expect number "
+ "after %<%dp%>.", m_arch, version);
+ return NULL;
+ }
+ if (!major_p)
+ {
+ error_at (m_loc, "%<-march=%s%>: For %<%s%dp%dp?%>, version "
+ "number with more than 2 level is not supported.",
+ m_arch, ext, major, version);
+ return NULL;
+ }
+ major = version;
+ major_p = false;
+ version = 0;
+ }
+ else if (ISDIGIT (*p))
+ version = (version * 10) + (*p - '0');
+ else
+ break;
+ }
+ }
if (major_p)
major = version;
@@ -681,6 +679,8 @@ riscv_subset_list::parse_std_ext (const char *p)
p = parsing_subset_version (subset, p, &major_version, &minor_version,
/* std_ext_p= */ true, &explicit_version_p);
+ if (p == NULL)
+ return NULL;
add (subset, major_version, minor_version, explicit_version_p, false);
}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-12.c
b/gcc/testsuite/gcc.target/riscv/arch-12.c
new file mode 100644
index 000..29e16c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-12.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64im1p2p3 -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64im1p2p3': For 'm1p2p\\?', version number with more
than 2 level is not supported." "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-19.c
b/gcc/testsuite/gcc.target/riscv/attribute-19.c
new file mode 100644
index 000..18f68d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-19.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv64imp0p9 -mabi=lp64" } */
+int foo() {}
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_p0p9\"" } } */
--
2.7.4
[PATCH] C-SKY: Support for fpuv2:fldrd/fstrd and fpuv3:fldr.64/fstr.64.
gcc/ChangeLog:
* config/csky/csky.c (ck810_legitimate_index_p): Modified for
support "base + index" with DF mode.
* config/csky/constraints.md ("Y"): New constraint for memory operands
without index register.
* config/csky/csky_insn_fpuv2.md
(fpuv3_movdf):At constraints, use "Y" instead of "m" where mov between
memory and general registers, and put them baskwards.
* config/csky/csky_insn_fpuv3.md
(fpuv2_movdf): Likewise.
---
gcc/config/csky/constraints.md | 4
gcc/config/csky/csky.c | 3 ++-
gcc/config/csky/csky_insn_fpuv2.md | 4 ++--
gcc/config/csky/csky_insn_fpuv3.md | 16
4 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/gcc/config/csky/constraints.md b/gcc/config/csky/constraints.md
index c9bc9f2..2641ab3 100644
--- a/gcc/config/csky/constraints.md
+++ b/gcc/config/csky/constraints.md
@@ -38,6 +38,10 @@
"Memory operands with base register, index register"
(match_test "csky_valid_mem_constraint_operand (op, \"W\")"))
+(define_memory_constraint "Y"
+ "Memory operands without index register"
+ (not (match_test "csky_valid_mem_constraint_operand (op, \"W\")")))
+
(define_constraint "R"
"Memory operands whose address is a label_ref"
(and (match_code "mem")
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index e4c92fe..e55821f 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -3136,7 +3136,8 @@ ck810_legitimate_index_p (machine_mode mode, rtx index,
int strict_p)
/* The follow index is for ldr instruction, the ldr cannot
load dword data, so the mode size should not be larger than
4. */
- else if (GET_MODE_SIZE (mode) <= 4)
+ else if (GET_MODE_SIZE (mode) <= 4
+ || (TARGET_HARD_FLOAT && CSKY_VREG_MODE_P (mode)))
{
if (is_csky_address_register_rtx_p (index, strict_p))
return 1;
diff --git a/gcc/config/csky/csky_insn_fpuv2.md
b/gcc/config/csky/csky_insn_fpuv2.md
index 0a680f8..5a06b22 100644
--- a/gcc/config/csky/csky_insn_fpuv2.md
+++ b/gcc/config/csky/csky_insn_fpuv2.md
@@ -461,8 +461,8 @@
)
(define_insn "*fpuv2_movdf"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r, r,m, v,?r,Q,v,v,v")
- (match_operand:DF 1 "general_operand" " r,m,mF,r,?r, v,v,Q,v,m"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r, v,?r,Q,v,v,v,r, r,Y")
+ (match_operand:DF 1 "general_operand" " r,?r, v,v,Q,v,m,Y,YF,r"))]
"CSKY_ISA_FEATURE (fpv2_df)"
"* return csky_output_movedouble(operands, DFmode);"
[(set (attr "length")
diff --git a/gcc/config/csky/csky_insn_fpuv3.md
b/gcc/config/csky/csky_insn_fpuv3.md
index 053673c..7849795 100644
--- a/gcc/config/csky/csky_insn_fpuv3.md
+++ b/gcc/config/csky/csky_insn_fpuv3.md
@@ -71,27 +71,27 @@
)
(define_insn "*fpv3_movdf"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r, r,m,v,?r,Q,v,v,v, v")
- (match_operand:DF 1 "general_operand" "
r,m,mF,r,?r,v,v,Q,v,m,Dv"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r, v,?r,Q,v,v,v, v,r,
r,Y")
+ (match_operand:DF 1 "general_operand" " r,?r,
v,v,Q,v,m,Dv,Y,YF,r"))]
"CSKY_ISA_FEATURE(fpv3_df)"
"*
switch (which_alternative)
{
-case 4:
+case 1:
if (TARGET_BIG_ENDIAN)
return \"fmtvr.64\\t%0, %R1, %1\";
return \"fmtvr.64\\t%0, %1, %R1\";
-case 5:
+case 2:
if (TARGET_BIG_ENDIAN)
return \"fmfvr.64\\t%R0, %0, %1\";
return \"fmfvr.64\\t%0, %R0, %1\";
+case 3:
+case 4:
case 6:
-case 7:
-case 9:
return fpuv3_output_move(operands);
-case 8:
+case 5:
return \"fmov.64\\t%0, %1\";
-case 10:
+case 7:
return \"fmovi.64\\t%0, %1\";
default:
return csky_output_movedouble(operands, DFmode);
--
2.7.4
[PATCH] C-SKY: Use default for TARGET_PROMOTE_PROTOTYPES.
gcc/ChangeLog: * config/csky/csky.c (TARGET_PROMOTE_PROTOTYPES): Use default. --- gcc/config/csky/csky.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c index 67cdf9c..e4c92fe 100644 --- a/gcc/config/csky/csky.c +++ b/gcc/config/csky/csky.c @@ -512,9 +512,6 @@ csky_cpu_cpp_builtins (cpp_reader *pfile) #undef TARGET_SPLIT_COMPLEX_ARG #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true -#undef TARGET_PROMOTE_PROTOTYPES -#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true - #undef TARGET_MUST_PASS_IN_STACK #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size -- 2.7.4
[PATCH] C-SKY: Fix for gcc.dg/torture/stackalign/builtin-return-2.c.
gcc/ChangeLog:
* config/csky/csky.md (untyped_call): Emit clobber for return
registers to mark them used.
---
gcc/config/csky/csky.md | 4
1 file changed, 4 insertions(+)
diff --git a/gcc/config/csky/csky.md b/gcc/config/csky/csky.md
index b980d4c..f91d851 100644
--- a/gcc/config/csky/csky.md
+++ b/gcc/config/csky/csky.md
@@ -3258,6 +3258,10 @@
emit_call_insn (gen_call (operands[0], const0_rtx));
+ for (int i = 0; i < XVECLEN (operands[2], 0); i++)
+emit_clobber (SET_SRC (XVECEXP (operands[2], 0, i)));
+ emit_insn (gen_blockage ());
+
for (i = 0; i < XVECLEN (operands[2], 0); i++)
{
rtx set = XVECEXP (operands[2], 0, i);
--
2.7.4
[PATCH] C-SKY: Use default for TARGET_CAN_CHANGE_MODE_CLASS.
gcc/ChangeLog:
* config/csky/csky.c (csky_can_change_mode_class): Delete.
For csky, HF/SF mode use the low bits of VREGS.
---
gcc/config/csky/csky.c | 16
1 file changed, 16 deletions(-)
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index 7f2af82..67cdf9c 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -611,9 +611,6 @@ csky_default_logical_op_non_short_circuit (void)
#undef TARGET_MODES_TIEABLE_P
#define TARGET_MODES_TIEABLE_P csky_modes_tieable_p
-#undef TARGET_CAN_CHANGE_MODE_CLASS
-#define TARGET_CAN_CHANGE_MODE_CLASS csky_can_change_mode_class
-
#undef TARGET_CONDITIONAL_REGISTER_USAGE
#define TARGET_CONDITIONAL_REGISTER_USAGE csky_conditional_register_usage
@@ -2373,19 +2370,6 @@ csky_modes_tieable_p (machine_mode mode1, machine_mode
mode2)
&& (mode1 == DFmode || mode2 == DFmode));
}
-/* Implement TARGET_CAN_CHANGE_MODE_CLASS.
- V_REG registers can't do subreg as all values are reformatted to
- internal precision. */
-
-static bool
-csky_can_change_mode_class (machine_mode from,
- machine_mode to,
- reg_class_t rclass)
-{
- return (GET_MODE_SIZE (from) == GET_MODE_SIZE (to)
- || !reg_classes_intersect_p (V_REGS, rclass));
-}
-
/* Implement TARGET_CLASS_LIKELY_SPILLED_P.
We need to define this for MINI_REGS when we only use r0 - r7.
Otherwise we can end up using r0-r4 for function arguments, and don't
--
2.7.4
[PATCH] C-SKY: Cases for csky fpuv3 instructions.
gcc/testsuite/ChangeLog: * gcc/testsuite/gcc.target/csky/fpuv3/fpuv3.exp: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_div.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fadd.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fdtos.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fftoi_rm.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fftoi_rz.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fhtos.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fitof.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fmov.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fmovi.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fmula.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fmuls.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fneg.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fnmula.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fnmuls.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fstod.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fstoh.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fsub.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fxtof.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_h.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_hs.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_hsz.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_hz.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_ls.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_lsz.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_lt.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_ltz.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_max.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_min.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_mul.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_mula.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_muls.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_ne.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_nez.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_recip.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_sqrt.c: New. * gcc/testsuite/gcc.target/csky/fpuv3/fpv3_unordered.c: New. --- gcc/testsuite/gcc.target/csky/fpuv3/fpuv3.exp | 50 +++ gcc/testsuite/gcc.target/csky/fpuv3/fpv3_div.c | 15 gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fadd.c| 23 ++ gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fdtos.c | 11 +++ .../gcc.target/csky/fpuv3/fpv3_fftoi_rm.c | 55 + .../gcc.target/csky/fpuv3/fpv3_fftoi_rz.c | 41 + gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fhtos.c | 11 +++ gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fitof.c | 72 gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fmov.c| 96 ++ gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fmovi.c | 31 +++ gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fmula.c | 23 ++ gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fmuls.c | 23 ++ gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fneg.c| 22 + gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fnmula.c | 14 gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fnmuls.c | 14 gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fstod.c | 11 +++ gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fstoh.c | 11 +++ gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fsub.c| 23 ++ gcc/testsuite/gcc.target/csky/fpuv3/fpv3_fxtof.c | 76 + gcc/testsuite/gcc.target/csky/fpuv3/fpv3_h.c | 20 + gcc/testsuite/gcc.target/csky/fpuv3/fpv3_hs.c | 19 + gcc/testsuite/gcc.target/csky/fpuv3/fpv3_hsz.c | 21 + gcc/testsuite/gcc.target/csky/fpuv3/fpv3_hz.c | 20 + gcc/testsuite/gcc.target/csky/fpuv3/fpv3_ls.c | 19 + gcc/testsuite/gcc.target/csky/fpuv3/fpv3_lsz.c | 20 + gcc/testsuite/gcc.target/csky/fpuv3/fpv3_lt.c | 19 + gcc/testsuite/gcc.target/csky/fpuv3/fpv3_ltz.c | 20 + gcc/testsuite/gcc.target/csky/fpuv3/fpv3_max.c | 16 gcc/testsuite/gcc.target/csky/fpuv3/fpv3_min.c | 16 gcc/testsuite/gcc.target/csky/fpuv3/fpv3_mul.c | 15 gcc/testsuite/gcc.target/csky/fpuv3/fpv3_mula.c| 16 gcc/testsuite/gcc.target/csky/fpuv3/fpv3_muls.c| 16 gcc/testsuite/gcc.target/csky/fpuv3/fpv3_ne.c | 19 + gcc/testsuite/gcc.target/csky/fpuv3/fpv3_nez.c | 21 + gcc/testsuite/gcc.target/csky/fpuv3/fpv3_recip.c | 14 gcc/testsuite/gcc.target/csky/fpuv3/fpv3_sqrt.c| 16 .../gcc.target/csky/fpuv3/fpv3_unordered.c | 29 +++ 37 files changed, 958 insertions(+) create mode 100644 gcc/testsuite/gcc.target/csky/fpuv3/fpuv3.exp create mode 100644 gcc/testsuite/gcc.target/csky/fpuv3/fpv3_div.c create mode 100644 gcc/testsuite/gcc.target/csk
[PATCH] C-SKY: Add insn "ldbs".
gcc/ChangeLog: config/csky/csky.md (cskyv2_sextend_ldbs): New insn. --- gcc/config/csky/csky.md | 10 ++ 1 file changed, 10 insertions(+) diff --git a/gcc/config/csky/csky.md b/gcc/config/csky/csky.md index c27d627..b980d4c 100644 --- a/gcc/config/csky/csky.md +++ b/gcc/config/csky/csky.md @@ -1533,6 +1533,7 @@ }" ) +;; hi -> si (define_insn "extendhisi2" [(set (match_operand:SI0 "register_operand" "=r") (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))] @@ -1557,6 +1558,15 @@ "sextb %0, %1" ) +(define_insn "*cskyv2_sextend_ldbs" + [(set (match_operand:SI0 "register_operand" "=r") +(sign_extend:SI (match_operand:QI 1 "csky_simple_mem_operand" "m")))] + "CSKY_ISA_FEATURE (E2)" + "ld.bs\t%0, %1" + [(set_attr "length" "4") + (set_attr "type" "load")] +) + ;; qi -> hi (define_insn "extendqihi2" [(set (match_operand:HI0 "register_operand" "=r") -- 2.7.4
[PATCH] C-SKY: Separate FRAME_POINTER_REGNUM into FRAME_POINTER_REGNUM and HARD_FRAME_POINTER_REGNUM.
gcc/ChangeLog:
* config/csky/csky.h
(FRAME_POINTER_REGNUM): Use HARD_FRAME_POINTER_REGNUM and
FRAME_POINTER_REGNUM instead of the signle definition. The
signle definition may not work well at simplify_subreg_regno().
(ELIMINABLE_REGS): Add for HARD_FRAME_POINTER_REGNUM.
* config/csky/csky.c (get_csky_live_regs, csky_can_eliminate,
csky_initial_elimination_offset, csky_expand_prologue,
csky_expand_epilogue): Add for HARD_FRAME_POINTER_REGNUM.
---
gcc/config/csky/csky.c | 15 +--
gcc/config/csky/csky.h | 7 +--
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index 1a6cfd7..7f2af82 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -1751,12 +1751,12 @@ get_csky_live_regs (int *count)
save = true;
/* Frame pointer marked used. */
- else if (frame_pointer_needed && reg == FRAME_POINTER_REGNUM)
+ else if (frame_pointer_needed && reg == HARD_FRAME_POINTER_REGNUM)
save = true;
/* This is required for CK801/802 where FP is a fixed reg, otherwise
we end up with no FP value available to the DWARF-2 unwinder. */
- else if (crtl->calls_eh_return && reg == FRAME_POINTER_REGNUM)
+ else if (crtl->calls_eh_return && reg == HARD_FRAME_POINTER_REGNUM)
save = true;
/* CK801/802 also need special handling for LR because it's clobbered
@@ -1832,6 +1832,8 @@ csky_layout_stack_frame (void)
static bool
csky_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
{
+ if (to == FRAME_POINTER_REGNUM)
+return from != ARG_POINTER_REGNUM;
if (to == STACK_POINTER_REGNUM)
return !frame_pointer_needed;
return true;
@@ -1852,6 +1854,7 @@ csky_initial_elimination_offset (int from, int to)
switch (from)
{
case FRAME_POINTER_REGNUM:
+case HARD_FRAME_POINTER_REGNUM:
offset = cfun->machine->reg_offset;
break;
@@ -1866,7 +1869,7 @@ csky_initial_elimination_offset (int from, int to)
/* If we are asked for the offset to the frame pointer instead,
then subtract the difference between the frame pointer and stack
pointer. */
- if (to == FRAME_POINTER_REGNUM)
+ if (to == FRAME_POINTER_REGNUM || to == HARD_FRAME_POINTER_REGNUM)
offset -= cfun->machine->reg_offset;
return offset;
}
@@ -5785,7 +5788,7 @@ csky_expand_prologue (void)
of the register save area. */
if (frame_pointer_needed)
{
- insn = emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
+ insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
RTX_FRAME_RELATED_P (insn) = 1;
}
@@ -5848,7 +5851,7 @@ csky_expand_epilogue (void)
/* Restore the SP to the base of the register save area. */
if (frame_pointer_needed)
{
- insn = emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
+ insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
RTX_FRAME_RELATED_P (insn) = 1;
}
else
@@ -6004,7 +6007,7 @@ csky_set_eh_return_address (rtx source, rtx scratch)
if (frame_pointer_needed)
{
- basereg = frame_pointer_rtx;
+ basereg = hard_frame_pointer_rtx;
delta = 0;
}
else
diff --git a/gcc/config/csky/csky.h b/gcc/config/csky/csky.h
index 1fd72d0..f2b0d1c 100644
--- a/gcc/config/csky/csky.h
+++ b/gcc/config/csky/csky.h
@@ -342,7 +342,8 @@ extern int csky_arch_isa_features[];
#define STACK_POINTER_REGNUM CSKY_SP_REGNUM
/* Base register for access to local variables of the function. */
-#define FRAME_POINTER_REGNUM 8
+#define FRAME_POINTER_REGNUM 36
+#define HARD_FRAME_POINTER_REGNUM 8
/* Base register for access to arguments of the function. This is a fake
register that is always eliminated. */
@@ -370,7 +371,9 @@ extern int csky_arch_isa_features[];
#define ELIMINABLE_REGS \
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},\
{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},\
- { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
+ { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },\
+ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
+ { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }}
/* Define the offset between two registers, one to be eliminated, and the
other its replacement, at the start of a routine. */
--
2.7.4
[PATCH] C-SKY: Bug fix for bad setting of TARGET_DSP and TARGET_DIV.
gcc/ChangeLog:
* config/csky/csky.c (csky_option_override):
Init csky_arch_isa_features[] advanced, so TARGET_DSP
and TARGET_DIV can be set well.
---
gcc/config/csky/csky.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index b2160b9..1a6cfd7 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -2680,6 +2680,18 @@ csky_option_override (void)
TARGET_FDIVDU = 0;
}
+ /* Initialize boolean versions of the architectural flags, for use
+ in the .md file. */
+
+#undef CSKY_ISA
+#define CSKY_ISA(IDENT, DESC)\
+ { \
+csky_arch_isa_features[CSKY_ISA_FEATURE_GET (IDENT)] =\
+ bitmap_bit_p (csky_active_target.isa, CSKY_ISA_FEATURE_GET (IDENT)); \
+ }
+#include "csky_isa.def"
+#undef CSKY_ISA
+
/* Extended LRW instructions are enabled by default on CK801, disabled
otherwise. */
if (TARGET_ELRW == -1)
@@ -2752,18 +2764,6 @@ csky_option_override (void)
TARGET_MULTIPLE_STLD = 0;
}
- /* Initialize boolean versions of the architectural flags, for use
- in the .md file. */
-
-#undef CSKY_ISA
-#define CSKY_ISA(IDENT, DESC)\
- { \
-csky_arch_isa_features[CSKY_ISA_FEATURE_GET (IDENT)] =\
- bitmap_bit_p (csky_active_target.isa, CSKY_ISA_FEATURE_GET (IDENT)); \
- }
-#include "csky_isa.def"
-#undef CSKY_ISA
-
/* TODO */
/* Resynchronize the saved target options. */
--
2.7.4
[PATCH] C-SKY: Delete LO_REGS and HI_REGS, use HILO_REGS instead.
gcc/ChangeLog:
* config/csky/constraints.md ("l", "h"): Delete.
* config/csky/csky.h (reg_class, REG_CLASS_NAMES,
REG_CLASS_CONTENTS): Delete LO_REGS and HI_REGS.
* config/csky/csky.c (regno_reg_classm,
csky_secondary_reload, csky_register_move_cost):
Use HILO_REGS instead of LO_REGS and HI_REGS.
---
gcc/config/csky/constraints.md | 2 --
gcc/config/csky/csky.c | 7 +++
gcc/config/csky/csky.h | 8
3 files changed, 3 insertions(+), 14 deletions(-)
diff --git a/gcc/config/csky/constraints.md b/gcc/config/csky/constraints.md
index 937cb81..c9bc9f2 100644
--- a/gcc/config/csky/constraints.md
+++ b/gcc/config/csky/constraints.md
@@ -24,8 +24,6 @@
(define_register_constraint "b" "LOW_REGS" "r0 - r15")
(define_register_constraint "c" "C_REGS" "C register")
(define_register_constraint "y" "HILO_REGS" "HI and LO registers")
-(define_register_constraint "l" "LO_REGS" "LO register")
-(define_register_constraint "h" "HI_REGS" "HI register")
(define_register_constraint "v" "V_REGS" "vector registers")
(define_register_constraint "z" "SP_REGS" "SP register")
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index 6e97994..b2160b9 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -112,7 +112,7 @@ enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
/* Reserved. */
RESERVE_REGS,
/* CC,HI,LO registers. */
- C_REGS, HI_REGS, LO_REGS,
+ C_REGS, HILO_REGS, HILO_REGS,
/* Reserved. */
RESERVE_REGS, RESERVE_REGS, RESERVE_REGS, RESERVE_REGS,
RESERVE_REGS, RESERVE_REGS, RESERVE_REGS, RESERVE_REGS,
@@ -2477,8 +2477,7 @@ csky_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
/* We always require a general register when copying anything to
HI/LO_REGNUM, except when copying an SImode value from HI/LO_REGNUM
to a general register, or when copying from register 0. */
- if ((rclass == HILO_REGS || rclass == LO_REGS || rclass == HI_REGS)
- && !CSKY_GENERAL_REGNO_P (regno))
+ if (rclass == HILO_REGS && !CSKY_GENERAL_REGNO_P (regno))
return GENERAL_REGS;
if (rclass == V_REGS && !CSKY_GENERAL_REGNO_P (regno))
@@ -6546,7 +6545,7 @@ csky_register_move_cost (machine_mode mode
ATTRIBUTE_UNUSED,
|| (CLASS) == LOW_REGS)
#define HILO_REG_CLASS_P(CLASS) \
- ((CLASS) == HI_REGS || (CLASS) == LO_REGS || (CLASS) == HILO_REGS)
+ ((CLASS) == HILO_REGS)
#define V_REG_CLASS_P(CLASS) \
((CLASS) == V_REGS)
diff --git a/gcc/config/csky/csky.h b/gcc/config/csky/csky.h
index f535c42..1fd72d0 100644
--- a/gcc/config/csky/csky.h
+++ b/gcc/config/csky/csky.h
@@ -685,8 +685,6 @@ enum reg_class
LOW_REGS,
GENERAL_REGS,
C_REGS,
- HI_REGS,
- LO_REGS,
HILO_REGS,
V_REGS,
OTHER_REGS,
@@ -706,8 +704,6 @@ enum reg_class
"LOW_REGS", \
"GENERAL_REGS", \
"C_REGS",\
- "HI_REGS", \
- "LO_REGS", \
"HILO_REGS", \
"V_REGS",\
"OTHER_REGS",\
@@ -731,10 +727,6 @@ enum reg_class
0x, 0x, 0x},/* GENERAL_REGS
*/ \
{0x, 0x0002, 0x, 0x, \
0x, 0x, 0x},/* C_REGS
*/ \
- {0x, 0x0004, 0x, 0x, \
- 0x, 0x, 0x},/* HI_REG
*/ \
- {0x, 0x0008, 0x, 0x, \
- 0x, 0x, 0x},/* LO_REG
*/ \
{0x, 0x000c, 0x, 0x, \
0x, 0x, 0x},/* HILO_REGS
*/ \
{0x, 0xFFF0, 0x007FFF8F, 0x, \
--
2.7.4
[PATCH] C-SKY: Add fpuv3 instructions and CK860 arch.
gcc/ChangeLog:
* config/csky/constraints.md ("W"): New constriant for mem operand
with base reg, index register.
("Q"): Renamed and modified "csky_valid_fpuv2_mem_operand" to
"csky_valid_mem_constraint_operand" to deal with both "Q" and "W"
constraint.
("Dv"): New constraint for const double value that can be used at
fmovi instruction.
* config/csky/csky-modes.def (HFmode): New mode.
* config/csky/csky-protos.h (csky_valid_fpuv2_mem_operand): Rename
to "csky_valid_mem_constraint_operand" and new support for constraint
"W".
(csky_get_movedouble_length): New.
(fpuv3_output_move): New.
(fpuv3_const_double): New.
* config/csky/csky.c (csky_option_override): New arch CK860 with fpv3.
(decompose_csky_address): Robustness adjust.
(csky_print_operand): New "CONST_DOUBLE" operand.
(csky_output_move): New support for fpv3 instructions.
(csky_get_movedouble_length): New.
(fpuv3_output_move): New.
(fpuv3_const_double): New.
(csky_emit_compare): New cover for float comparsion.
(csky_emit_compare_float): Refine.
(csky_vaild_fpuv2_mem_operand): Rename to
"csky_valid_mem_constraint_operand" and new support for constraint "W".
(ck860_rtx_costs): New.
(csky_rtx_costs): New subcall for CK860.
(regno_reg_class): New vregs for fpuv3.
(csky_dbx_regno): Likewise.
(csky_cpu_cpp_builtins): New builtin macro for fpuv3.
(csky_conditional_register_usage): New suporrot for fpuv3.
(csky_dwarf_register_span): New suporrot for fpuv3.
(csky_init_builtins, csky_mangle_type): New support for "__fp16" type.
(ck810_legitimate_index_p): New support for fp16.
* gcc/config/csky/csky.h (TARGET_TLS): ADD CK860.
(CSKY_VREG_P, CSKY_VREG_LO_P, CSKY_VREG_HI_P): New support for fpuv3.
(TARGET_SINGLE_FPU): New support for fpuv3.
(TARGET_SUPPORT_FPV3): New macro.
(FIRST_PSEUDO_REGISTER): Value change, since the new fpuv3 regs.
(FIXED_REGISTERS, CALL_REALLY_USED_REGISTERS, REGISTER_NAMES,
REG_CLASS_CONTENTS): Support for fpuv3.
* gcc/config/csky/csky.md (movsf): Move to cksy_insn_fpu.md and adjust.
(csky_movsf_fpv2): Likewise.
(ck801_movsf): Likewise.
(csky_movsf): Likewise.
(movdf): Likewise.
(csky_movdf_fpv2): Likewise.
(ck801_movdf): Likewise.
(csky_movdf): Likewise.
(movsicc): Refine. Use "comparison_operatior" instead of
"ordered_comparison_operatior".
(addsicc): Likewise.
(CSKY_FIRST_VFP3_REGNUM, CSKY_LAST_VFP3_REGNUM): New constant.
(call_value_internal_vh): New insn.
* config/csky/csky_cores.def (CK860): New arch and cpu.
(fpv3): New 4 fpus: fpv3_hf, fpv3_hsf, fpv3_sdf and fpv3.
* config/csky/csky_insn_fpu.md (mov): Move the float mov
patterns from csky.md here.
(fpuv2 instructions): Refactor. Separate all float patterns into
emit-patterns and match-patterns, remain the emit-patterns here, and
move the match-patterns to csky_insn_fpuv2.md.
(fpuv3 instructions): Add patterns and fuse part of them with the
fpuv2's.
* config/csky/csky_insn_fpuv2.md: New file for fpuv2 instructions.
* config/csky/csky_insn_fpuv3.md: New flie and new patterns for fpuv3
isntructions.
* config/csky/csky_isa.def (fcr): New.
(fpv3): New 4 isa sets: fpv3_hi, fpv3_hf, fpv3_sf and fpv3_df.
(CK860): New definition for ck860.
* gcc/config/csky/csky_tables.opt (ck860): New processors ck860,
ck860f. And new arch ck860.
(fpv3): New 4 fpus: fpv3_hf, fpv3_hsf, fpv3_sdf and fpv3.
* config/csky/predicates.md (csky_float_comparsion_operator): Delete
"geu", "gtu", "leu", "ltu", which will never appear at float comparison.
* config/cksy/t-csky-elf, config/csky/t-csky-linux: New for ck860.
* doc/md.texi: Add "Q" and "W" constraints for C-SKY.
---
gcc/config/csky/constraints.md | 13 +-
gcc/config/csky/csky-modes.def | 2 +
gcc/config/csky/csky-protos.h | 7 +-
gcc/config/csky/csky.c | 644 ++
gcc/config/csky/csky.h | 162 ++--
gcc/config/csky/csky.md| 127 ++
gcc/config/csky/csky_cores.def | 13 +
gcc/config/csky/csky_insn_fpu.md | 798 +++--
gcc/config/csky/csky_insn_fpuv2.md | 470 ++
gcc/config/csky/csky_insn_fpuv3.md | 497 +++
gcc/config/csky/csky_isa.def | 15 +
gcc/config/csky/csky_tables.opt| 21 +
gcc/config/csky/predicates.md | 3 +-
gcc/config/csky/t-csky-elf | 9 +-
gcc/config/csky/t-csky-linux | 11 +-
gcc/doc/md.texi| 8 +
16 files changed, 2125 inserti
[PATCH] doc/options.texi: Fix the discription of 'Negative'.
gcc/ChangeLog:
* doc/options.texi (Negative): Fix the discription so that it matches
the code implementation of prune_options().
---
gcc/doc/options.texi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
index 2057629..37386ca 100644
--- a/gcc/doc/options.texi
+++ b/gcc/doc/options.texi
@@ -223,8 +223,8 @@ propagate through the @code{Negative} property of the
option to be
turned off. The driver will prune options, removing those that are
turned off by some later option. This pruning is not done for options
with @code{Joined} or @code{JoinedOrMissing} properties, unless the
-options have either @code{RejectNegative} property or the @code{Negative}
-property mentions an option other than itself.
+options have both @code{RejectNegative} property and the @code{Negative}
+property mentions itself.
As a consequence, if you have a group of mutually-exclusive
options, their @code{Negative} properties should form a circular chain.
--
2.7.4
[PATCH] RISC-V: For '-march' and '-mabi' options, add 'Negative' property mentions itself.
When use multi-lib riscv-tool-chain. A bug is triggered when there are two '-march' at command line. riscv64-unknown-elf-gcc -march=rv32gcp -mabi=ilp32f -march=rv32gcpzp64 HelloWorld.c /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/lib/crt0.o: ABI is incompatible with that of the selected emulation: target emulation `elf64-littleriscv' does not match `elf32-littleriscv' /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/lib/crt0.o /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/crtbegin.o: ABI is incompatible with that of the selected emulation: target emulation `elf64-littleriscv' does not match `elf32-littleriscv' /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/crtbegin.o .. This patch fix it. And the DIVER would prune the extra '-march' and '-mabi' options and keep only the last one valid. gcc/ChangeLog: * config/riscv/riscv.opt (march=,mabi=): Negative itself. --- gcc/config/riscv/riscv.opt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index e294e22..5ff85c2 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -38,7 +38,7 @@ Target Var(TARGET_PLT) Init(1) When generating -fpic code, allow the use of PLTs. Ignored for fno-pic. mabi= -Target RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32) +Target RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32) Negative(mabi=) Specify integer and floating-point calling convention. mpreferred-stack-boundary= @@ -79,7 +79,7 @@ Target Mask(DIV) Use hardware instructions for integer division. march= -Target RejectNegative Joined +Target RejectNegative Joined Negative(march=) -march=Generate code for given RISC-V ISA (e.g. RV64IM). ISA strings must be lower-case. -- 2.7.4
[PATCH] RISC-V: The 'multilib-generator' enhancement.
From: gengqi
Think about this case:
./multilib-generator rv32imc-ilp32-rv32imac,rv32imacxthead-f
Here are 2 problems:
1. A unexpected 'xtheadf' extension was made.
2. The arch 'rv32imac' was not be created.
This modification fix these two, and also sorts 'multi-letter'.
gcc/ChangeLog:
* config/riscv/arch-canonicalize
(longext_sort): New function for sorting 'multi-letter'.
* config/riscv/multilib-generator: Adjusting the loop of 'alt' in
'alts'. The 'arch' may not be the first of 'alts'.
(_expand_combination): Add underline for the 'ext' without '*'.
This is because, a single-letter extension can always be treated well
with a '_' prefix, but it cannot be separated out if it is appended
to a multi-letter.
---
gcc/config/riscv/arch-canonicalize | 14 +-
gcc/config/riscv/multilib-generator | 12 +++-
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/arch-canonicalize
b/gcc/config/riscv/arch-canonicalize
index 2b4289e..a1e4570 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -74,8 +74,20 @@ def arch_canonicalize(arch):
# becasue we just append extensions list to the arch string.
std_exts += list(filter(lambda x:len(x) == 1, long_exts))
+ def longext_sort (exts):
+if not exts.startswith("zxm") and exts.startswith("z"):
+ # If "Z" extensions are named, they should be ordered first by CANONICAL.
+ if exts[1] not in CANONICAL_ORDER:
+raise Exception("Unsupported extension `%s`" % exts)
+ canonical_sort = CANONICAL_ORDER.index(exts[1])
+else:
+ canonical_sort = -1
+return (exts.startswith("x"), exts.startswith("zxm"),
+LONG_EXT_PREFIXES.index(exts[0]), canonical_sort, exts[1:])
+
# Multi-letter extension must be in lexicographic order.
- long_exts = list(sorted(filter(lambda x:len(x) != 1, long_exts)))
+ long_exts = list(sorted(filter(lambda x:len(x) != 1, long_exts),
+ key=longext_sort))
# Put extensions in canonical order.
for ext in CANONICAL_ORDER:
diff --git a/gcc/config/riscv/multilib-generator
b/gcc/config/riscv/multilib-generator
index 64ff15f..7b22537 100755
--- a/gcc/config/riscv/multilib-generator
+++ b/gcc/config/riscv/multilib-generator
@@ -68,15 +68,15 @@ def arch_canonicalize(arch):
def _expand_combination(ext):
exts = list(ext.split("*"))
- # No need to expand if there is no `*`.
- if len(exts) == 1:
-return [(exts[0],)]
-
# Add underline to every extension.
# e.g.
# _b * zvamo => _b * _zvamo
exts = list(map(lambda x: '_' + x, exts))
+ # No need to expand if there is no `*`.
+ if len(exts) == 1:
+return [(exts[0],)]
+
# Generate combination!
ext_combs = []
for comb_len in range(1, len(exts)+1):
@@ -147,7 +147,9 @@ for cfg in sys.argv[1:]:
# Drop duplicated entry.
alts = unique(alts)
- for alt in alts[1:]:
+ for alt in alts:
+if alt == arch:
+ continue
arches[alt] = 1
reuse.append('march.%s/mabi.%s=march.%s/mabi.%s' % (arch, abi, alt, abi))
required.append('march=%s/mabi=%s' % (arch, abi))
--
2.7.4
[PATCH] RISC-V: The 'multilib-generator' enhancement.
From: gengqi
gcc/ChangeLog:
* config/riscv/arch-canonicalize
(longext_sort): New function for sorting 'multi-letter'.
* config/riscv/multilib-generator: Adjusting the loop of 'alt' in
'alts'. The 'arch' may not be the first of 'alts'.
(_expand_combination): Add underline for the 'ext' without '*'.
This is because, a single-letter extension can always be treated well
with a '_' prefix, but it cannot be separated out if it is appended
to a multi-letter.
---
gcc/config/riscv/arch-canonicalize | 14 +-
gcc/config/riscv/multilib-generator | 12 +++-
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/arch-canonicalize
b/gcc/config/riscv/arch-canonicalize
index 2b4289e..a1e4570 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -74,8 +74,20 @@ def arch_canonicalize(arch):
# becasue we just append extensions list to the arch string.
std_exts += list(filter(lambda x:len(x) == 1, long_exts))
+ def longext_sort (exts):
+if not exts.startswith("zxm") and exts.startswith("z"):
+ # If "Z" extensions are named, they should be ordered first by CANONICAL.
+ if exts[1] not in CANONICAL_ORDER:
+raise Exception("Unsupported extension `%s`" % exts)
+ canonical_sort = CANONICAL_ORDER.index(exts[1])
+else:
+ canonical_sort = -1
+return (exts.startswith("x"), exts.startswith("zxm"),
+LONG_EXT_PREFIXES.index(exts[0]), canonical_sort, exts[1:])
+
# Multi-letter extension must be in lexicographic order.
- long_exts = list(sorted(filter(lambda x:len(x) != 1, long_exts)))
+ long_exts = list(sorted(filter(lambda x:len(x) != 1, long_exts),
+ key=longext_sort))
# Put extensions in canonical order.
for ext in CANONICAL_ORDER:
diff --git a/gcc/config/riscv/multilib-generator
b/gcc/config/riscv/multilib-generator
index 64ff15f..7b22537 100755
--- a/gcc/config/riscv/multilib-generator
+++ b/gcc/config/riscv/multilib-generator
@@ -68,15 +68,15 @@ def arch_canonicalize(arch):
def _expand_combination(ext):
exts = list(ext.split("*"))
- # No need to expand if there is no `*`.
- if len(exts) == 1:
-return [(exts[0],)]
-
# Add underline to every extension.
# e.g.
# _b * zvamo => _b * _zvamo
exts = list(map(lambda x: '_' + x, exts))
+ # No need to expand if there is no `*`.
+ if len(exts) == 1:
+return [(exts[0],)]
+
# Generate combination!
ext_combs = []
for comb_len in range(1, len(exts)+1):
@@ -147,7 +147,9 @@ for cfg in sys.argv[1:]:
# Drop duplicated entry.
alts = unique(alts)
- for alt in alts[1:]:
+ for alt in alts:
+if alt == arch:
+ continue
arches[alt] = 1
reuse.append('march.%s/mabi.%s=march.%s/mabi.%s' % (arch, abi, alt, abi))
required.append('march=%s/mabi=%s' % (arch, abi))
--
2.7.4
