[PATCH v1] RISC-V: Support VLS mode for vec_set
From: Pan Li
This patch would like to add the VLS support vec_set, both INT
and FP are included.
Give sample code as below:
typedef long long vl_t \
__attribute__((vector_size(2 * sizeof (long long;
vl_t init_vl (vl_t v, unsigned index, unsigned value)
{
v[index] = value;
return v;
}
Before this patch:
init_vl:
addi sp,sp,-16
vsetivli zero,2,e64,m1,ta,ma
vle64.v v1,0(a1)
vse64.v v1,0(sp)
slli a4,a2,32
srli a2,a4,29
add a2,sp,a2
slli a3,a3,32
srli a3,a3,32
sd a3,0(a2)
vle64.v v1,0(sp)
vse64.v v1,0(a0)
addi sp,sp,16
jr ra
After this patch:
init_vl:
vsetivlizero,2,e64,m1,ta,ma
vle64.v v1,0(a1)
sllia3,a3,32
srlia3,a3,32
addia5,a2,1
vsetvli zero,a5,e64,m1,tu,ma
vmv.v.x v2,a3
vslideup.vx v1,v2,a2
vsetivlizero,2,e64,m1,ta,ma
vse64.v v1,0(a0)
ret
Please note this patch depends the RVV SCALAR_MOVE_MERGED_OP bugfix.
gcc/ChangeLog:
* config/riscv/autovec.md: Extend to vls mode.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: New macros.
* gcc.target/riscv/rvv/autovec/vls/vec-set-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-10.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-11.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-12.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-13.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-14.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-15.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-16.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-17.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-18.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-19.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-20.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-21.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-22.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-6.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-7.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-8.c: New test.
* gcc.target/riscv/rvv/autovec/vls/vec-set-9.c: New test.
Signed-off-by: Pan Li
---
gcc/config/riscv/autovec.md | 4 +--
.../gcc.target/riscv/rvv/autovec/vls/def.h| 18 ++
.../riscv/rvv/autovec/vls/vec-set-1.c | 35 +++
.../riscv/rvv/autovec/vls/vec-set-10.c| 31
.../riscv/rvv/autovec/vls/vec-set-11.c| 29 +++
.../riscv/rvv/autovec/vls/vec-set-12.c| 21 +++
.../riscv/rvv/autovec/vls/vec-set-13.c| 20 +++
.../riscv/rvv/autovec/vls/vec-set-14.c| 19 ++
.../riscv/rvv/autovec/vls/vec-set-15.c| 18 ++
.../riscv/rvv/autovec/vls/vec-set-16.c| 21 +++
.../riscv/rvv/autovec/vls/vec-set-17.c| 20 +++
.../riscv/rvv/autovec/vls/vec-set-18.c| 19 ++
.../riscv/rvv/autovec/vls/vec-set-19.c| 18 ++
.../riscv/rvv/autovec/vls/vec-set-2.c | 33 +
.../riscv/rvv/autovec/vls/vec-set-20.c| 20 +++
.../riscv/rvv/autovec/vls/vec-set-21.c| 19 ++
.../riscv/rvv/autovec/vls/vec-set-22.c| 18 ++
.../riscv/rvv/autovec/vls/vec-set-3.c | 31
.../riscv/rvv/autovec/vls/vec-set-4.c | 29 +++
.../riscv/rvv/autovec/vls/vec-set-5.c | 35 +++
.../riscv/rvv/autovec/vls/vec-set-6.c | 33 +
.../riscv/rvv/autovec/vls/vec-set-7.c | 31
.../riscv/rvv/autovec/vls/vec-set-8.c | 29 +++
.../riscv/rvv/autovec/vls/vec-set-9.c | 33 +
24 files changed, 582 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c
create
[PATCH v1] RISC-V: Bugfix for scalar move with merged operand
From: Pan Li
Given below example for VLS mode
void
test (vl_t *u)
{
vl_t t;
long long *p = (long long *)
p[0] = p[1] = 2;
*u = t;
}
The vec_set will simplify the insn to vmv.s.x when index is 0, without
merged operand. That will result in some problems in DCE, aka:
1: 137[DI] = a0
2: 138[V2DI] = 134[V2DI] // deleted by DCE
3: 139[DI] = #2 // deleted by DCE
4: 140[DI] = #2 // deleted by DCE
5: 141[V2DI] = vec_dup:V2DI (139[DI]) // deleted by DCE
6: 138[V2DI] = vslideup_imm (138[V2DI], 141[V2DI], 1) // deleted by DCE
7: 135[V2DI] = 138[V2DI] // deleted by DCE
8: 142[V2DI] = 135[V2DI] // deleted by DCE
9: 143[DI] = #2
10: 142[V2DI] = vec_dup:V2DI (143[DI])
11: (137[DI]) = 142[V2DI]
The higher 64 bits of 142[V2DI] is unknown here and it generated incorrect
code when store back to memory. This patch would like to fix this issue
by adding a new SCALAR_MOVE_MERGED_OP for vec_set.
Please note this patch doesn't enable VLS for vec_set, the underlying
patches will support this soon.
gcc/ChangeLog:
* config/riscv/autovec.md: Bugfix.
* config/riscv/riscv-protos.h (SCALAR_MOVE_MERGED_OP): New enum.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c: New test.
Signed-off-by: Pan Li
---
gcc/config/riscv/autovec.md | 4 +--
gcc/config/riscv/riscv-protos.h | 4 +++
.../riscv/rvv/base/scalar-move-merged-run-1.c | 29 +++
3 files changed, 35 insertions(+), 2 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index aca86554a94..01291ad9830 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1401,9 +1401,9 @@ (define_expand "vec_set"
/* If we set the first element, emit an v(f)mv.s.[xf]. */
if (operands[2] == const0_rtx)
{
- rtx ops[] = {operands[0], operands[1]};
+ rtx ops[] = {operands[0], operands[0], operands[1]};
riscv_vector::emit_nonvlmax_insn (code_for_pred_broadcast (mode),
- riscv_vector::SCALAR_MOVE_OP, ops,
CONST1_RTX (Pmode));
+ riscv_vector::SCALAR_MOVE_MERGED_OP,
ops, CONST1_RTX (Pmode));
}
else
{
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 5a2d218d67b..6d9367d9602 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -345,6 +345,10 @@ enum insn_type : unsigned int
SCALAR_MOVE_OP = HAS_DEST_P | HAS_MASK_P | USE_ONE_TRUE_MASK_P | HAS_MERGE_P
| USE_VUNDEF_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P
| UNARY_OP_P,
+
+ SCALAR_MOVE_MERGED_OP = HAS_DEST_P | HAS_MASK_P | USE_ONE_TRUE_MASK_P
+ | HAS_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P
+ | UNARY_OP_P,
};
enum vlmul_type
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c
new file mode 100644
index 000..7aee75c6940
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c
@@ -0,0 +1,29 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-options "-O3 -Wno-psabi" } */
+
+#define TEST_VAL 2
+
+typedef long long vl_t __attribute__((vector_size(2 * sizeof (long long;
+
+void init_vl (vl_t *u)
+{
+ vl_t t;
+ long long *p = (long long *)
+
+ p[0] = p[1] = TEST_VAL;
+
+ *u = t;
+}
+
+int
+main ()
+{
+ vl_t vl = {};
+
+ init_vl ();
+
+ if (vl[0] != TEST_VAL || vl[1] != TEST_VAL)
+__builtin_abort ();
+
+ return 0;
+}
--
2.34.1
[PATCH v1] RISC-V: Support FP SGNJX autovec for VLS mode
From: Pan Li
This patch would like to allow the VLS mode autovec for the
floating-point binary operation SGNJX.
Give sample code as below:
void
test (float * restrict out, float * restrict in1, float * restrict in2)
{
for (int i = 0; i < 128; i++)
out[i] = in1[i] * copysignf (1.0, in2[i]);
}
Before this patch:
test:
li a5,128
vsetvli zero,a5,e32,m1,ta,ma
vle32.v v2,0(a1)
lui a4,%hi(.LC0)
flw fa5,%lo(.LC0)(a4)
vfmv.v.fv1,fa5
vle32.v v3,0(a2)
vfsgnj.vv v1,v1,v3
vfmul.vvv1,v1,v2
vse32.v v1,0(a0)
ret
After this patch:
test:
li a5,128
vsetvli zero,a5,e32,m1,ta,ma
vle32.v v1,0(a1)
vle32.v v2,0(a2)
vfsgnjx.vv v1,v1,v2
vse32.v v1,0(a0)
ret
This SGNJX autovec acts on function call copysignf/copysignf
in math.h too. And it depends on the option -ffast-math.
gcc/ChangeLog:
* config/riscv/autovec-vls.md (xorsign3): New pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: New macro.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c: New test.
Signed-off-by: Pan Li
---
gcc/config/riscv/autovec-vls.md | 21 +
.../gcc.target/riscv/rvv/autovec/vls/def.h| 8
.../rvv/autovec/vls/floating-point-sgnjx-1.c | 43 +++
.../rvv/autovec/vls/floating-point-sgnjx-2.c | 31 +
4 files changed, 103 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c
diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index 6f48f7d6232..d4ed2081537 100644
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -289,6 +289,27 @@ (define_insn_and_split "copysign3"
[(set_attr "type" "vector")]
)
+;; -
+;; Includes:
+;; - vfsgnjx.vv
+;; - vfsgnjx.vf
+;; -
+(define_insn_and_split "xorsign3"
+ [(set (match_operand:VLSF 0 "register_operand")
+(unspec:VLSF
+ [(match_operand:VLSF 1 "register_operand")
+ (match_operand:VLSF 2 "register_operand")] UNSPEC_VXORSIGN))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VXORSIGN, mode),
+ riscv_vector::BINARY_OP, operands);
+DONE;
+ }
+)
+
;;
---
;; [INT] Unary operations
;;
---
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 1edc1910920..81c4570836b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -258,3 +258,11 @@ typedef double v512df __attribute__ ((vector_size (4096)));
for (int i = 0; i < NUM; ++i)
\
a[i] = (b[i] > c[i]) OP (d[i] < e[i]);
\
}
+
+#define DEF_SGNJX_VV(PREFIX, NUM, TYPE, CALL)
\
+ void __attribute__ ((noinline, noclone))
\
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c)
\
+ {
\
+for (int i = 0; i < NUM; ++i)
\
+ a[i] = b[i] * CALL (1.0, c[i]);
\
+ }
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
new file mode 100644
index 000..86c23ef0436
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
-fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8
-ffast-math" } */
+
+#include "def.h"
+
+DEF_SGNJX_VV (sgnj, 1, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 2, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 4, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 8, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 16, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 32, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 64, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 128, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 256, _Float16, __builtin_copysignf16)
+DEF_SGNJX_VV (sgnj, 512, _Float16, __builtin_copysignf16)
[PATCH v1] RISC-V: Bugfix PR111362 for incorrect frm emit
From: Pan Li
When the mode switching from NONE to CALL, we will restore the
frm but lack some check if we have static frm insn in cfun.
This patch would like to fix this by adding static frm insn check.
gcc/ChangeLog:
* PR target/111362
* config/riscv/riscv.cc (riscv_emit_frm_mode_set): Bugfix.
gcc/testsuite/ChangeLog:
* PR target/111362
* gcc.target/riscv/rvv/base/no-honor-frm-1.c: New test.
Signed-off-by: Pan Li
---
gcc/config/riscv/riscv.cc| 2 +-
.../gcc.target/riscv/rvv/base/no-honor-frm-1.c | 12
2 files changed, 13 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 9d04ddd69e0..762937b0e37 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -9173,7 +9173,7 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
rtx frm = gen_int_mode (mode, SImode);
if (mode == riscv_vector::FRM_DYN_CALL
- && prev_mode != riscv_vector::FRM_DYN)
+ && prev_mode != riscv_vector::FRM_DYN && STATIC_FRM_P (cfun))
/* No need to emit when prev mode is DYN already. */
emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
new file mode 100644
index 000..b2e0f217bfa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/no-honor-frm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+void foo (void) {
+ for (unsigned i = 0; i < sizeof(foo); i++)
+__builtin_printf("%d", i);
+}
+
+/* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */
+/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */
+/* { dg-final { scan-assembler-not {fsrm\s+[axs][0-9]+} } } */
+/* { dg-final { scan-assembler-not {frrm\s+[axs][0-9]+} } } */
--
2.34.1
[PATCH v1] RISC-V: Remove unused structure in cost model
From: Pan Li
The struct range is unused, remove it.
gcc/ChangeLog:
* config/riscv/riscv-vector-costs.h (struct range): Removed.
Signed-off-by: Pan Li
---
gcc/config/riscv/riscv-vector-costs.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-costs.h
b/gcc/config/riscv/riscv-vector-costs.h
index 7f120b79619..7b5814a4cff 100644
--- a/gcc/config/riscv/riscv-vector-costs.h
+++ b/gcc/config/riscv/riscv-vector-costs.h
@@ -40,13 +40,6 @@ struct autovec_info
bool end_p;
};
-struct range
-{
- unsigned int pt;
- bool start;
- unsigned int nregs;
-};
-
/* rvv-specific vector costs. */
class costs : public vector_costs
{
--
2.34.1
[PATCH v3] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
From: Pan Li
Update in v3:
* Rewrite comment for overloaded function add.
* Move get_non_overloaded_instance to function_base.
Update in v2:
* Add get_non_overloaded_instance for function instance.
* Fix overload check for policy function.
* Enrich the test cases check.
Original log:
This patch would like add the framework to support the RVV overloaded
intrinsic API in riscv-xxx-xxx-gcc, like riscv-xxx-xxx-g++ did.
However, it almost leverage the hook TARGET_RESOLVE_OVERLOADED_BUILTIN
with below steps.
* Register overloaded functions.
* Add function_resolver for overloaded function resolving.
* Add resolve API for function shape with default implementation.
* Implement HOOK for navigating the overloaded API to non-overloaded API.
We validated this framework by the vmv_v intrinsic API(s), and we will
add more intrins API support in the underlying patches.
gcc/ChangeLog:
* config/riscv/riscv-c.cc
(riscv_resolve_overloaded_builtin): New function for the hook.
(riscv_register_pragmas): Register the hook
* config/riscv/riscv-protos.h (resolve_overloaded_builtin): New decl.
* config/riscv/riscv-vector-builtins-shapes.cc (build_one):
Register overloaded function.
(struct overloaded_base): New struct for overloaded shape.
(struct non_overloaded_base): New struct for non overloaded shape.
(struct move_def): Inherit overloaded shape.
* config/riscv/riscv-vector-builtins.cc
(function_base::get_non_overloaded_instance): New API impl.
(function_builder::add_function): Add overloaded arg.
(function_resolver::function_resolver): New constructor.
(function_builder::add_overloaded_function): New API impl.
(function_resolver::resolve): Ditto.
(function_resolver::lookup): Ditto.
(function_resolver::get_sub_code): Ditto.
(resolve_overloaded_builtin): New function impl.
* config/riscv/riscv-vector-builtins.h:
(class function_resolver): New class.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/overloaded_rv32_vmv_v.c: New test.
* gcc.target/riscv/rvv/base/overloaded_rv64_vmv_v.c: New test.
* gcc.target/riscv/rvv/base/overloaded_vmv_v.h: New test.
Signed-off-by: Pan Li
---
gcc/config/riscv/riscv-c.cc | 36
gcc/config/riscv/riscv-protos.h | 1 +
.../riscv/riscv-vector-builtins-shapes.cc | 20 ++-
gcc/config/riscv/riscv-vector-builtins.cc | 155 +-
gcc/config/riscv/riscv-vector-builtins.h | 36 +++-
.../riscv/rvv/base/overloaded_rv32_vmv_v.c| 8 +
.../riscv/rvv/base/overloaded_rv64_vmv_v.c| 8 +
.../riscv/rvv/base/overloaded_vmv_v.h | 27 +++
8 files changed, 288 insertions(+), 3 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vmv_v.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vmv_v.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_vmv_v.h
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 283052ae313..060edd3129d 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -220,11 +220,47 @@ riscv_check_builtin_call (location_t loc, vec
arg_loc, tree fndecl,
gcc_unreachable ();
}
+/* Implement TARGET_RESOLVE_OVERLOADED_BUILTIN. */
+static tree
+riscv_resolve_overloaded_builtin (unsigned int uncast_location, tree fndecl,
+ void *uncast_arglist)
+{
+ vec empty = {};
+ location_t loc = (location_t) uncast_location;
+ vec *arglist = (vec *) uncast_arglist;
+ unsigned int code = DECL_MD_FUNCTION_CODE (fndecl);
+ unsigned int subcode = code >> RISCV_BUILTIN_SHIFT;
+ tree new_fndecl = NULL_TREE;
+
+ if (!arglist)
+arglist =
+
+ switch (code & RISCV_BUILTIN_CLASS)
+{
+case RISCV_BUILTIN_GENERAL:
+ break;
+case RISCV_BUILTIN_VECTOR:
+ new_fndecl = riscv_vector::resolve_overloaded_builtin (loc, subcode,
+arglist);
+ break;
+default:
+ gcc_unreachable ();
+}
+
+ if (new_fndecl == NULL_TREE)
+return new_fndecl;
+
+ return build_function_call_vec (loc, vNULL, new_fndecl, arglist, NULL,
+ fndecl);
+}
+
/* Implement REGISTER_TARGET_PRAGMAS. */
void
riscv_register_pragmas (void)
{
+ targetm.resolve_overloaded_builtin = riscv_resolve_overloaded_builtin;
targetm.check_builtin_call = riscv_check_builtin_call;
+
c_register_pragma ("riscv", "intrinsic", riscv_pragma_intrinsic);
}
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 6dbf6b9f943..5d2492dd031 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -381,6 +381,7 @@ gimple *gimple_fold_builtin (unsigned int,
gimple_stmt_iterator *, gcall *);
rtx expand_builtin (unsigned int, tree, rtx);
[PATCH v2] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
From: Pan Li
Update in v2:
* Add get_non_overloaded_instance for function instance.
* Fix overload check for policy function.
* Enrich the test cases check.
Original log:
This patch would like add the framework to support the RVV overloaded
intrinsic API in riscv-xxx-xxx-gcc, like riscv-xxx-xxx-g++ did.
However, it almost leverage the hook TARGET_RESOLVE_OVERLOADED_BUILTIN
with below steps.
* Register overloaded functions.
* Add function_resolver for overloaded function resolving.
* Add resolve API for function shape with default implementation.
* Implement HOOK for navigating the overloaded API to non-overloaded API.
We validated this framework by the vmv_v intrinsic API(s), and we will
add more intrins API support in the underlying patches.
gcc/ChangeLog:
* config/riscv/riscv-c.cc
(riscv_resolve_overloaded_builtin): New function for the hook.
(riscv_register_pragmas): Register the hook
* config/riscv/riscv-protos.h (resolve_overloaded_builtin): New decl.
* config/riscv/riscv-vector-builtins-shapes.cc (build_one):
Register overloaded function.
(struct overloaded_base): New struct for overloaded shape.
(struct non_overloaded_base): New struct for non overloaded shape.
(struct move_def): Inherit overloaded shape.
* config/riscv/riscv-vector-builtins.cc
(function_instance::get_non_overloaded_instance): New API impl.
(function_builder::add_function): Add overloaded arg.
(function_resolver::function_resolver): New constructor.
(function_builder::add_overloaded_function): New API impl.
(function_resolver::resolve): Ditto.
(function_resolver::lookup): Ditto.
(function_resolver::get_sub_code): Ditto.
(resolve_overloaded_builtin): New function impl.
* config/riscv/riscv-vector-builtins.h:
(class function_resolver): New class.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/overloaded_rv32_vmv_v.c: New test.
* gcc.target/riscv/rvv/base/overloaded_rv64_vmv_v.c: New test.
* gcc.target/riscv/rvv/base/overloaded_vmv_v.h: New test.
Signed-off-by: Pan Li
---
gcc/config/riscv/riscv-c.cc | 36
gcc/config/riscv/riscv-protos.h | 1 +
.../riscv/riscv-vector-builtins-shapes.cc | 20 ++-
gcc/config/riscv/riscv-vector-builtins.cc | 155 +-
gcc/config/riscv/riscv-vector-builtins.h | 35 +++-
.../riscv/rvv/base/overloaded_rv32_vmv_v.c| 8 +
.../riscv/rvv/base/overloaded_rv64_vmv_v.c| 8 +
.../riscv/rvv/base/overloaded_vmv_v.h | 27 +++
8 files changed, 287 insertions(+), 3 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vmv_v.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vmv_v.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_vmv_v.h
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 283052ae313..060edd3129d 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -220,11 +220,47 @@ riscv_check_builtin_call (location_t loc, vec
arg_loc, tree fndecl,
gcc_unreachable ();
}
+/* Implement TARGET_RESOLVE_OVERLOADED_BUILTIN. */
+static tree
+riscv_resolve_overloaded_builtin (unsigned int uncast_location, tree fndecl,
+ void *uncast_arglist)
+{
+ vec empty = {};
+ location_t loc = (location_t) uncast_location;
+ vec *arglist = (vec *) uncast_arglist;
+ unsigned int code = DECL_MD_FUNCTION_CODE (fndecl);
+ unsigned int subcode = code >> RISCV_BUILTIN_SHIFT;
+ tree new_fndecl = NULL_TREE;
+
+ if (!arglist)
+arglist =
+
+ switch (code & RISCV_BUILTIN_CLASS)
+{
+case RISCV_BUILTIN_GENERAL:
+ break;
+case RISCV_BUILTIN_VECTOR:
+ new_fndecl = riscv_vector::resolve_overloaded_builtin (loc, subcode,
+arglist);
+ break;
+default:
+ gcc_unreachable ();
+}
+
+ if (new_fndecl == NULL_TREE)
+return new_fndecl;
+
+ return build_function_call_vec (loc, vNULL, new_fndecl, arglist, NULL,
+ fndecl);
+}
+
/* Implement REGISTER_TARGET_PRAGMAS. */
void
riscv_register_pragmas (void)
{
+ targetm.resolve_overloaded_builtin = riscv_resolve_overloaded_builtin;
targetm.check_builtin_call = riscv_check_builtin_call;
+
c_register_pragma ("riscv", "intrinsic", riscv_pragma_intrinsic);
}
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 6dbf6b9f943..5d2492dd031 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -381,6 +381,7 @@ gimple *gimple_fold_builtin (unsigned int,
gimple_stmt_iterator *, gcall *);
rtx expand_builtin (unsigned int, tree, rtx);
bool check_builtin_call (location_t, vec, unsigned int,
tree, unsigned int, tree *);
[PATCH v1] RISC-V: Implement RESOLVE_OVERLOADED_BUILTIN for RVV intrinsic
From: Pan Li
This patch would like add the framework to support the RVV overloaded
intrinsic API in riscv-xxx-xxx-gcc, like riscv-xxx-xxx-g++ did.
However, it almost leverage the hook TARGET_RESOLVE_OVERLOADED_BUILTIN
with below steps.
* Register overloaded functions.
* Add function_resolver for overloaded function resolving.
* Add resolve API for function shape with default implementation.
* Implement HOOK for navigating the overloaded API to non-overloaded API.
We validated this framework by the vmv_v intrinsic API(s), and we will
add more intrins API support in the underlying patches.
gcc/ChangeLog:
* config/riscv/riscv-c.cc
(riscv_resolve_overloaded_builtin): New function for the hook.
(riscv_register_pragmas): Register the hook
* config/riscv/riscv-protos.h (resolve_overloaded_builtin): New decl.
* config/riscv/riscv-vector-builtins-shapes.cc (build_one):
Register overloaded function.
(struct overloaded_base): New struct for overloaded shape.
(struct non_overloaded_base): New struct for non overloaded shape.
(struct move_def): Inherit overloaded shape.
* config/riscv/riscv-vector-builtins.cc
(function_builder::add_function): Add overloaded arg.
(function_builder::add_overloaded_function): New function impl.
(function_resolver::function_resolver): New constructor.
(function_resolver::get_sub_code): New API impl.
(function_resolver::resolve): New API impl.
(function_resolver::lookup): New API impl.
(resolve_overloaded_builtin): New func impl.
* config/riscv/riscv-vector-builtins.h
(class function_resolver): New class.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/overloaded_rv32_vmv_v.c: New test.
* gcc.target/riscv/rvv/base/overloaded_rv64_vmv_v.c: New test.
* gcc.target/riscv/rvv/base/overloaded_vmv_v.h: New test.
Signed-off-by: Pan Li
---
gcc/config/riscv/riscv-c.cc | 36 +
gcc/config/riscv/riscv-protos.h | 1 +
.../riscv/riscv-vector-builtins-shapes.cc | 22 ++-
gcc/config/riscv/riscv-vector-builtins.cc | 138 +-
gcc/config/riscv/riscv-vector-builtins.h | 30 +++-
.../riscv/rvv/base/overloaded_rv32_vmv_v.c| 4 +
.../riscv/rvv/base/overloaded_rv64_vmv_v.c| 4 +
.../riscv/rvv/base/overloaded_vmv_v.h | 17 +++
8 files changed, 248 insertions(+), 4 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vmv_v.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vmv_v.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_vmv_v.h
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 283052ae313..060edd3129d 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -220,11 +220,47 @@ riscv_check_builtin_call (location_t loc, vec
arg_loc, tree fndecl,
gcc_unreachable ();
}
+/* Implement TARGET_RESOLVE_OVERLOADED_BUILTIN. */
+static tree
+riscv_resolve_overloaded_builtin (unsigned int uncast_location, tree fndecl,
+ void *uncast_arglist)
+{
+ vec empty = {};
+ location_t loc = (location_t) uncast_location;
+ vec *arglist = (vec *) uncast_arglist;
+ unsigned int code = DECL_MD_FUNCTION_CODE (fndecl);
+ unsigned int subcode = code >> RISCV_BUILTIN_SHIFT;
+ tree new_fndecl = NULL_TREE;
+
+ if (!arglist)
+arglist =
+
+ switch (code & RISCV_BUILTIN_CLASS)
+{
+case RISCV_BUILTIN_GENERAL:
+ break;
+case RISCV_BUILTIN_VECTOR:
+ new_fndecl = riscv_vector::resolve_overloaded_builtin (loc, subcode,
+arglist);
+ break;
+default:
+ gcc_unreachable ();
+}
+
+ if (new_fndecl == NULL_TREE)
+return new_fndecl;
+
+ return build_function_call_vec (loc, vNULL, new_fndecl, arglist, NULL,
+ fndecl);
+}
+
/* Implement REGISTER_TARGET_PRAGMAS. */
void
riscv_register_pragmas (void)
{
+ targetm.resolve_overloaded_builtin = riscv_resolve_overloaded_builtin;
targetm.check_builtin_call = riscv_check_builtin_call;
+
c_register_pragma ("riscv", "intrinsic", riscv_pragma_intrinsic);
}
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 6dbf6b9f943..5d2492dd031 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -381,6 +381,7 @@ gimple *gimple_fold_builtin (unsigned int,
gimple_stmt_iterator *, gcall *);
rtx expand_builtin (unsigned int, tree, rtx);
bool check_builtin_call (location_t, vec, unsigned int,
tree, unsigned int, tree *);
+tree resolve_overloaded_builtin (location_t, unsigned int, vec *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
bool legitimize_move (rtx, rtx);
void emit_vlmax_vsetvl
[PATCH v1] RISC-V: Fix incorrect folder for VRGATHERI16 test case
From: Pan Li
Put the test file to the incorrect folder, this patch would like to
fix it.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/intrisinc-vrgatherei16.c: Moved to...
* gcc.target/riscv/rvv/base/intrisinc-vrgatherei16.c: ...here.
Signed-off-by: Pan Li
---
.../gcc.target/riscv/rvv/{ => base}/intrisinc-vrgatherei16.c | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename gcc/testsuite/gcc.target/riscv/rvv/{ => base}/intrisinc-vrgatherei16.c
(100%)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/intrisinc-vrgatherei16.c
similarity index 100%
rename from gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c
rename to gcc/testsuite/gcc.target/riscv/rvv/base/intrisinc-vrgatherei16.c
--
2.34.1
[PATCH v1] RISC-V: Support FP SGNJ autovec for VLS mode
From: Pan Li
This patch would like to allow the VLS mode autovec for the
floating-point binary operation MAX/MIN.
Given below code example:
void test(float * restrict out, float * restrict in1, float * restrict in2)
{
for (int i = 0; i < 128; i++)
out[i] = __builtin_copysignf (in1[i], in2[i]);
}
Before this patch:
test:
csrra4,vlenb
sllia4,a4,1
li a5,128
bleua5,a4,.L2
mv a5,a4
.L2:
vsetvli zero,a5,e32,m8,ta,ma
vle32.v v8,0(a1)
vle32.v v16,0(a2)
vsetvli a4,zero,e32,m8,ta,ma
vfsgnj.vv v8,v8,v16
vsetvli zero,a5,e32,m8,ta,ma
vse32.v v8,0(a0)
ret
After this patch:
test:
li a5,128
vsetvli zero,a5,e32,m1,ta,ma
vle32.v v1,0(a1)
vle32.v v2,0(a2)
vfsgnj.vv v1,v1,v2
vse32.v v1,0(a0)
ret
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/autovec-vls.md (copysign3): New pattern.
* config/riscv/vector.md: Extend iterator for VLS.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: New macro.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c: New test.
---
gcc/config/riscv/autovec-vls.md | 22 ++
gcc/config/riscv/vector.md| 24 +--
.../gcc.target/riscv/rvv/autovec/vls/def.h| 8
.../rvv/autovec/vls/floating-point-sgnj-1.c | 43 +++
.../rvv/autovec/vls/floating-point-sgnj-2.c | 43 +++
5 files changed, 128 insertions(+), 12 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c
diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index 7ef29637e33..31b6c4ae714 100644
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -255,6 +255,28 @@ (define_insn_and_split "3"
[(set_attr "type" "vector")]
)
+;; -
+;; Includes:
+;; - vfsgnj.vv
+;; - vfsgnj.vf
+;; -
+(define_insn_and_split "copysign3"
+ [(set (match_operand:VLSF 0 "register_operand")
+(unspec:VLSF
+ [(match_operand:VLSF 1 "register_operand")
+ (match_operand:VLSF 2 "register_operand")] UNSPEC_VCOPYSIGN))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VCOPYSIGN,
mode),
+ riscv_vector::BINARY_OP, operands);
+DONE;
+ }
+ [(set_attr "type" "vector")]
+)
+
;;
---
;; [INT] Unary operations
;;
---
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 9d7b4bbe1d4..fc985ff6a01 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6166,8 +6166,8 @@ (define_insn "@pred__reverse_scalar"
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_"
- [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
+ (if_then_else:V_VLSF
(unspec:
[(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand"" rK, rK, rK, rK")
@@ -6176,10 +6176,10 @@ (define_insn "@pred_"
(match_operand 8 "const_int_operand"" i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (unspec:VF
- [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
-(match_operand:VF 4 "register_operand" " vr, vr, vr, vr")]
VCOPYSIGNS)
- (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (unspec:V_VLSF
+ [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
+(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")]
VCOPYSIGNS)
+ (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfsgnj.vv\t%0,%3,%4%p1"
[(set_attr "type" "vfsgnj")
@@ -6207,8 +6207,8 @@ (define_insn "@pred_ncopysign"
(set_attr "mode" "")])
(define_insn "@pred__scalar"
- [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
+ (if_then_else:V_VLSF
(unspec:
[(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand"" rK, rK, rK, rK")
@@ -6217,11 +6217,11 @@ (define_insn
[PATCH v1] RISC-V: Support FP16 for RVV VRGATHEREI16 intrinsic
From: Pan Li
This patch would like to add FP16 support for the VRGATHEREI16
intrinsic. Aka:
* __riscv_vrgatherei16_vv_f16mf4
* __riscv_vrgatherei16_vv_f16mf4_m
As well as f16mf2 to f16m8 types.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-types.def
(vfloat16mf4_t): Add FP16 intrinsic def.
(vfloat16mf2_t): Ditto.
(vfloat16m1_t): Ditto.
(vfloat16m2_t): Ditto.
(vfloat16m4_t): Ditto.
(vfloat16m8_t): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/intrisinc-vrgatherei16.c: New test.
---
.../riscv/riscv-vector-builtins-types.def | 9 ++
.../riscv/rvv/intrisinc-vrgatherei16.c| 28 +++
2 files changed, 37 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def
b/gcc/config/riscv/riscv-vector-builtins-types.def
index 1c3cc0eb222..6aa45ae9a7e 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -689,11 +689,20 @@ DEF_RVV_EI16_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_EI16_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_EI16_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_EI16_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
+
+DEF_RVV_EI16_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 |
RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_EI16_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_EI16_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_EI16_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_EI16_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_EI16_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16)
+
DEF_RVV_EI16_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 |
RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_EI16_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_EI16_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_EI16_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_EI16_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
+
DEF_RVV_EI16_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
DEF_RVV_EI16_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
DEF_RVV_EI16_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c
b/gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c
new file mode 100644
index 000..59c6d7c887d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef _Float16 float16_t;
+
+vfloat16mf4_t test_vrgatherei16_vv_f16mf4(vfloat16mf4_t op1, vuint16mf4_t op2,
+ size_t vl) {
+ return __riscv_vrgatherei16_vv_f16mf4(op1, op2, vl);
+}
+
+vfloat16m8_t test_vrgatherei16_vv_f16m8(vfloat16m8_t op1, vuint16m8_t op2,
+ size_t vl) {
+ return __riscv_vrgatherei16_vv_f16m8(op1, op2, vl);
+}
+
+vfloat16mf4_t test_vrgatherei16_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t op1,
+ vuint16mf4_t op2, size_t vl) {
+ return __riscv_vrgatherei16_vv_f16mf4_m(mask, op1, op2, vl);
+}
+
+vfloat16m8_t test_vrgatherei16_vv_f16m8_m(vbool2_t mask, vfloat16m8_t op1,
+ vuint16m8_t op2, size_t vl) {
+ return __riscv_vrgatherei16_vv_f16m8_m(mask, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times
{vrgatherei16.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
--
2.34.1
[PATCH v1] RISC-V: Support FP MAX/MIN autovec for VLS mode
From: Pan Li
This patch would like to allow the VLS mode autovec for the
floating-point binary operation MAX/MIN.
Given below code example:
test (float *out, float *in1, float *in2)
{
for (int i = 0; i < 128; i++)
out[i] = in1[i] > in2[i] ? in1[i] : in2[i];
// Or out[i] = fmax (in1[i], in2[i]);
}
Before this patch:
test:
csrra4,vlenb
sllia4,a4,1
li a5,128
bleua5,a4,.L2
mv a5,a4
.L2:
vsetvli zero,a5,e32,m8,ta,ma
vle32.v v16,0(a1)
vle32.v v8,0(a2)
vsetvli a3,zero,e32,m8,ta,ma
vmfgt.vvv0,v16,v8
vmerge.vvm v8,v8,v16,v0
vsetvli zero,a5,e32,m8,ta,ma
vse32.v v8,0(a0)
ret
After this patch:
test:
li a5,128
vsetvli zero,a5,e32,m1,ta,ma
vle32.v v1,0(a1)
vle32.v v2,0(a2)
vfmax.vvv1,v1,v2
vse32.v v1,0(a0)
ret
This MAX/MIN autovec acts on function call like fmaxf/fmax in math.h
too. And it depends on the option -ffast-math.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/autovec-vls.md (3): New pattern for
fmax/fmin
* config/riscv/vector.md: Add VLS modes to vfmax/vfmin.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: New macros.
* gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c: New test.
---
gcc/config/riscv/autovec-vls.md | 23 ++
gcc/config/riscv/vector.md| 12 +++---
.../gcc.target/riscv/rvv/autovec/vls/def.h| 16 +++
.../rvv/autovec/vls/floating-point-max-1.c| 43 +++
.../rvv/autovec/vls/floating-point-max-2.c| 43 +++
.../rvv/autovec/vls/floating-point-max-3.c| 43 +++
.../rvv/autovec/vls/floating-point-max-4.c| 43 +++
.../rvv/autovec/vls/floating-point-max-5.c| 31 +
.../rvv/autovec/vls/floating-point-min-1.c| 43 +++
.../rvv/autovec/vls/floating-point-min-2.c| 43 +++
.../rvv/autovec/vls/floating-point-min-3.c| 43 +++
.../rvv/autovec/vls/floating-point-min-4.c| 43 +++
.../rvv/autovec/vls/floating-point-min-5.c| 31 +
13 files changed, 451 insertions(+), 6 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-3.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-5.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-3.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-5.c
diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index 4ca640c11e2..7ef29637e33 100644
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -232,6 +232,29 @@ (define_insn_and_split "3"
[(set_attr "type" "vector")]
)
+;; -
+;; Includes:
+;; - vfmin.vv/vfmax.vv
+;; - vfmin.vf/vfmax.vf
+;; - fmax/fmaxf in math.h
+;; -
+(define_insn_and_split "3"
+ [(set (match_operand:VLSF 0 "register_operand")
+(any_float_binop_nofrm:VLSF
+ (match_operand:VLSF 1 "")
+ (match_operand:VLSF 2 "")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ riscv_vector::emit_vlmax_insn (code_for_pred (, mode),
+riscv_vector::BINARY_OP, operands);
+ DONE;
+}
+[(set_attr "type" "vector")]
+)
+
;;
---
;; [INT] Unary operations
;;
---
diff --git
[PATCH v1] RISC-V: Support FP ADD/SUB/MUL/DIV autovec for VLS mode
From: Pan Li
This patch would like to allow the VLS mode autovec for the
floating-point binary operation ADD/SUB/MUL/DIV.
Given below code example:
test (float *out, float *in1, float *in2)
{
for (int i = 0; i < 128; i++)
out[i] = in1[i] + in2[i];
}
Before this patch:
test:
csrr a4,vlenb
slli a4,a4,1
li a5,128
bleu a5,a4,.L38
mv a5,a4
.L38:
vsetvli zero,a5,e32,m8,ta,ma
vle32.v v16,0(a1)
vsetvli a4,zero,e32,m8,ta,ma
vmv.v.i v8,0
vsetvli zero,a5,e32,m8,tu,ma
vle32.v v24,0(a2)
vfadd.vv v8,v24,v16
vse32.v v8,0(a0)
ret
After this patch:
test:
li a5,128
vsetvli zero,a5,e32,m1,ta,ma
vle32.v v1,0(a2)
vle32.v v2,0(a1)
vfadd.vv v1,v1,v2
vse32.v v1,0(a0)
ret
Please note this patch also fix the execution failure of below
vect test cases.
* vect-alias-check-10.c
* vect-alias-check-11.c
* vect-alias-check-12.c
* vect-alias-check-14.c
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/autovec-vls.md (3): New pattern for
vls floating-point autovec.
* config/riscv/vector-iterators.md: New iterator for
floating-point V and VLS.
* config/riscv/vector.md: Add VLS to floating-point binop.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h:
* gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c: New test.
---
gcc/config/riscv/autovec-vls.md | 24 ++
gcc/config/riscv/vector-iterators.md | 80 +++
gcc/config/riscv/vector.md| 12 +--
.../gcc.target/riscv/rvv/autovec/vls/def.h| 8 ++
.../rvv/autovec/vls/floating-point-add-1.c| 43 ++
.../rvv/autovec/vls/floating-point-add-2.c| 43 ++
.../rvv/autovec/vls/floating-point-add-3.c| 43 ++
.../rvv/autovec/vls/floating-point-div-1.c| 43 ++
.../rvv/autovec/vls/floating-point-div-2.c| 43 ++
.../rvv/autovec/vls/floating-point-div-3.c| 43 ++
.../rvv/autovec/vls/floating-point-mul-1.c| 43 ++
.../rvv/autovec/vls/floating-point-mul-2.c| 43 ++
.../rvv/autovec/vls/floating-point-mul-3.c| 43 ++
.../rvv/autovec/vls/floating-point-sub-1.c| 43 ++
.../rvv/autovec/vls/floating-point-sub-2.c| 43 ++
.../rvv/autovec/vls/floating-point-sub-3.c| 43 ++
16 files changed, 634 insertions(+), 6 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-add-3.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-div-3.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sub-3.c
diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index 503ad691b9a..4ca640c11e2 100644
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -208,6 +208,30 @@ (define_insn_and_split "3"
[(set_attr "type" "vector")]
)
+;; -
+;; [FP] Binary operations
+;; -
+;; Includes:
+;; - vfadd.vv/vfsub.vv/vfmul.vv/vfdiv.vv
+;; - vfadd.vf/vfsub.vf/vfmul.vf/vfdiv.vf
+;; -
[PATCH v1] RISC-V: Fix one ICE for vect test vect-multitypes-5
From: Pan Li
There will be one ICE when build vect-multitypes-5.c similar as below:
riscv64-unknown-elf-gcc -O3 \
-march=rv64imafdcv -mabi=lp64d -mcmodel=medlow \
-fdiagnostics-plain-output -flto -ffat-lto-objects \
--param riscv-autovec-preference=scalable -Wno-psabi \
-ftree-vectorize -fno-tree-loop-distribute-patterns \
-fno-vect-cost-model -fno-common -O2 -fdump-tree-vect-details \
gcc/testsuite/gcc.dg/vect/vect-multitypes-5.c -o test.elf -lm
The below RTL is not well handled in riscv_legitimize_const_move, and
then fall through to the default pass. Then the
default force_const_mem will NULL_RTX, and will have ICE when operating
one the NULL_RTX.
(const:DI
(plus:DI
(symbol_ref:DI ("ic") [flags 0x2] )
(const_poly_int:DI [16, 16])))
This patch would like to take care of this rtl in riscv_legitimize_const_move.
Signed-off-by: Pan Li
Co-Authored-By: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_poly_move): New declaration.
(riscv_legitimize_const_move): Handle ref plus const poly.
---
gcc/config/riscv/riscv.cc | 23 +++
1 file changed, 23 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 1d6e278ea90..bab6ed70b2d 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -366,6 +366,7 @@ static const struct riscv_tune_param
optimize_size_tune_info = {
static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
+static void riscv_legitimize_poly_move (machine_mode, rtx, rtx, rtx);
/* Defining target-specific uses of __attribute__. */
static const struct attribute_spec riscv_attribute_table[] =
@@ -2118,6 +2119,28 @@ riscv_legitimize_const_move (machine_mode mode, rtx
dest, rtx src)
return;
}
+ /* Handle below format.
+ (const:DI
+ (plus:DI
+(symbol_ref:DI ("ic") [flags 0x2] ) <- op_0
+(const_poly_int:DI [16, 16]) // <- op_1
+ ))
+ */
+ rtx src_op_0 = XEXP (src, 0);
+
+ if (GET_CODE (src) == CONST && GET_CODE (src_op_0) == PLUS
+&& CONST_POLY_INT_P (XEXP (src_op_0, 1)))
+{
+ rtx dest_tmp = gen_reg_rtx (mode);
+ rtx tmp = gen_reg_rtx (mode);
+
+ riscv_emit_move (dest, XEXP (src_op_0, 0));
+ riscv_legitimize_poly_move (mode, dest_tmp, tmp, XEXP (src_op_0, 1));
+
+ emit_insn (gen_rtx_SET (dest, gen_rtx_PLUS (mode, dest, dest_tmp)));
+ return;
+}
+
src = force_const_mem (mode, src);
/* When using explicit relocs, constant pool references are sometimes
--
2.34.1
[PATCH v2] Mode-Switching: Add optional EMIT_AFTER hook
From: Pan Li
Update in v2:
* Remove control flow check in BB_END.
* Passed x86 bootstrap and regression test.
Original log:
We have EMIT hook in mode switching already, which will insert the
insn before in most cases. However, in some arch like RISC-V, it
requires the additional insn to be inserted after when meet a call.
|
| <- EMIT HOOK, insert the insn before.
+---+
| ptr->insn |
+---+
| <- EMIT_AFTER HOOK, insert the insn after.
|
Thus, this patch would like to add one optional EMIT_AFTER hook, which
will try to insert the emitted insn after. The end-user can either
implement this HOOK or leave it NULL as is.
If the backend ignore this optinal hook, there is no impact to the
original mode switching stuff. If the backend implement this optional
hook, the mode switching will try to insert the insn after. Please note
the EMIT_AFTER doen't have any impact to EMIT hook.
Signed-off-by: Pan Li
gcc/ChangeLog:
* doc/tm.texi: Add hook def and update the description.
* doc/tm.texi.in: Ditto.
* mode-switching.cc (optimize_mode_switching): Insert the
emitted insn after ptr->insn.
* target.def (insn): Define emit_after hook.
---
gcc/doc/tm.texi | 12 ++--
gcc/doc/tm.texi.in| 6 --
gcc/mode-switching.cc | 43 +++
gcc/target.def| 9 +
4 files changed, 66 insertions(+), 4 deletions(-)
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index d0d47b0d471..9b93a85f634 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -10334,8 +10334,8 @@ return nonzero for any @var{entity} that needs
mode-switching.
If you define this macro, you also have to define
@code{NUM_MODES_FOR_MODE_SWITCHING}, @code{TARGET_MODE_NEEDED},
@code{TARGET_MODE_PRIORITY} and @code{TARGET_MODE_EMIT}.
-@code{TARGET_MODE_AFTER}, @code{TARGET_MODE_ENTRY}, and @code{TARGET_MODE_EXIT}
-are optional.
+@code{TARGET_MODE_AFTER}, @code{TARGET_MODE_ENTRY},
@code{TARGET_MODE_EMIT_AFTER},
+and @code{TARGET_MODE_EXIT} are optional.
@end defmac
@defmac NUM_MODES_FOR_MODE_SWITCHING
@@ -10359,6 +10359,14 @@ to switch from. Sets of a lower numbered entity will
be emitted before
sets of a higher numbered entity to a mode of the same or lower priority.
@end deftypefn
+@deftypefn {Target Hook} void TARGET_MODE_EMIT_AFTER (int @var{entity}, int
@var{mode}, int @var{prev_mode}, HARD_REG_SET @var{regs_live})
+Generate one or more insns to set @var{entity} to @var{mode}.
+@var{hard_reg_live} is the set of hard registers live at the point where
+the insn(s) are to be inserted after. @var{prev_moxde} indicates the mode
+to switch from. Sets of a lower numbered entity will be emitted before
+sets of a higher numbered entity to a mode of the same or lower priority.
+@end deftypefn
+
@deftypefn {Target Hook} int TARGET_MODE_NEEDED (int @var{entity}, rtx_insn
*@var{insn})
@var{entity} is an integer specifying a mode-switched entity.
If @code{OPTIMIZE_MODE_SWITCHING} is defined, you must define this macro
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 4ac96dc357d..2942ce0be3b 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -6911,8 +6911,8 @@ return nonzero for any @var{entity} that needs
mode-switching.
If you define this macro, you also have to define
@code{NUM_MODES_FOR_MODE_SWITCHING}, @code{TARGET_MODE_NEEDED},
@code{TARGET_MODE_PRIORITY} and @code{TARGET_MODE_EMIT}.
-@code{TARGET_MODE_AFTER}, @code{TARGET_MODE_ENTRY}, and @code{TARGET_MODE_EXIT}
-are optional.
+@code{TARGET_MODE_AFTER}, @code{TARGET_MODE_ENTRY},
@code{TARGET_MODE_EMIT_AFTER},
+and @code{TARGET_MODE_EXIT} are optional.
@end defmac
@defmac NUM_MODES_FOR_MODE_SWITCHING
@@ -6930,6 +6930,8 @@ switch is needed / supplied.
@hook TARGET_MODE_EMIT
+@hook TARGET_MODE_EMIT_AFTER
+
@hook TARGET_MODE_NEEDED
@hook TARGET_MODE_AFTER
diff --git a/gcc/mode-switching.cc b/gcc/mode-switching.cc
index f483c831c35..0127fb42330 100644
--- a/gcc/mode-switching.cc
+++ b/gcc/mode-switching.cc
@@ -34,6 +34,7 @@ along with GCC; see the file COPYING3. If not see
#include "lcm.h"
#include "cfgcleanup.h"
#include "tree-pass.h"
+#include "gcse.h"
/* We want target macros for the mode switching code to be able to refer
to instruction attribute values. */
@@ -831,6 +832,48 @@ optimize_mode_switching (void)
emit_insn_before (mode_set, ptr->insn_ptr);
}
+ if (targetm.mode_switching.emit_after)
+ {
+ if (ptr->insn_ptr != BB_END (bb))
+ {
+ start_sequence ();
+ targetm.mode_switching.emit_after (entity_map[j],
+ ptr->mode, cur_mode, ptr->regs_live);
+ mode_set = get_insns ();
+ end_sequence ();
+
+ if (mode_set != NULL_RTX)
+
[PATCH v1] RISC-V: Support rounding mode for VFNMADD/VFNMACC autovec
From: Pan Li
There will be a case like below for intrinsic and autovec combination.
vfadd RTZ <- intrinisc static rounding
vfnmadd <- autovec/autovec-opt
The autovec generated vfnmadd should take DYN mode, and the
frm must be restored before the vfnmadd insn. This patch
would like to fix this issue by:
* Add the frm operand to the autovec/autovec-opt pattern.
* Set the frm_mode attr to DYN.
Thus, the frm flow when combine autovec and intrinsic should be.
+
| frrm a5
| ...
| fsrmi 4
| vfadd <- intrinsic static rounding.
| ...
| fsrm a5
| vfnmadd <- autovec/autovec-opt
| ...
+
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Add FRM_REGNUM to vfnmadd/vfnmacc.
* config/riscv/autovec.md: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c: New test.
---
gcc/config/riscv/autovec-opt.md | 38
gcc/config/riscv/autovec.md | 34 ---
.../rvv/base/float-point-frm-autovec-4.c | 88 +++
3 files changed, 130 insertions(+), 30 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-4.c
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 54ca6df721c..2922f370a17 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -655,14 +655,16 @@ (define_insn_and_split "*single_widen_fms"
;; vect__13.182_33 = .FNMS (vect__11.180_35, vect__8.176_40, vect__4.172_45);
(define_insn_and_split "*double_widen_fnms"
[(set (match_operand:VWEXTF 0 "register_operand")
- (fma:VWEXTF
- (neg:VWEXTF
+ (unspec:VWEXTF
+ [(fma:VWEXTF
+ (neg:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand: 2 "register_operand")))
(float_extend:VWEXTF
- (match_operand: 2 "register_operand")))
- (float_extend:VWEXTF
- (match_operand: 3 "register_operand"))
- (neg:VWEXTF
- (match_operand:VWEXTF 1 "register_operand"]
+ (match_operand: 3 "register_operand"))
+ (neg:VWEXTF
+ (match_operand:VWEXTF 1 "register_operand")))
+ (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -673,18 +675,21 @@ (define_insn_and_split "*double_widen_fnms"
DONE;
}
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "")])
+ (set_attr "mode" "")
+ (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
;; This helps to match ext + fnms.
(define_insn_and_split "*single_widen_fnms"
[(set (match_operand:VWEXTF 0 "register_operand")
- (fma:VWEXTF
- (neg:VWEXTF
- (float_extend:VWEXTF
- (match_operand: 2 "register_operand")))
- (match_operand:VWEXTF 3 "register_operand")
- (neg:VWEXTF
- (match_operand:VWEXTF 1 "register_operand"]
+ (unspec:VWEXTF
+ [(fma:VWEXTF
+ (neg:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand: 2 "register_operand")))
+ (match_operand:VWEXTF 3 "register_operand")
+ (neg:VWEXTF
+ (match_operand:VWEXTF 1 "register_operand")))
+ (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -701,4 +706,5 @@ (define_insn_and_split "*single_widen_fnms"
DONE;
}
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "")])
+ (set_attr "mode" "")
+ (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 28396c6175d..5f16ac53712 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1274,26 +1274,31 @@ (define_insn_and_split "*fms"
(define_expand "fnms4"
[(parallel
[(set (match_operand:VF 0 "register_operand")
- (fma:VF
- (neg:VF
- (match_operand:VF 1 "register_operand"))
- (match_operand:VF 2 "register_operand")
- (neg:VF
- (match_operand:VF 3 "register_operand"
+ (unspec:VF
+ [(fma:VF
+ (neg:VF
+ (match_operand:VF 1 "register_operand"))
+ (match_operand:VF 2 "register_operand")
+ (neg:VF
+ (match_operand:VF 3 "register_operand")))
+(reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
(clobber (match_dup 4))])]
"TARGET_VECTOR"
{
operands[4] = gen_reg_rtx (Pmode);
- })
+ }
+ [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
(define_insn_and_split "*fnms"
[(set (match_operand:VF 0 "register_operand" "=vr, vr, ?")
- (fma:VF
- (neg:VF
- (match_operand:VF 1 "register_operand" " %0, vr, vr"))
- (match_operand:VF 2 "register_operand" " vr, vr, vr")
- (neg:VF
- (match_operand:VF 3
[PATCH v1] RISC-V: Support rounding mode for VFNMSAC/VFNMSUB autovec
From: Pan Li
There will be a case like below for intrinsic and autovec combination.
vfadd RTZ <- intrinisc static rounding
vfnmsub <- autovec/autovec-opt
The autovec generated vfnmsub should take DYN mode, and the
frm must be restored before the vfnmsub insn. This patch
would like to fix this issue by:
* Add the frm operand to the autovec/autovec-opt pattern.
* Set the frm_mode attr to DYN.
Thus, the frm flow when combine autovec and intrinsic should be.
+
| frrm a5
| ...
| fsrmi 4
| vfadd <- intrinsic static rounding.
| ...
| fsrm a5
| vfnmsub <- autovec/autovec-opt
| ...
+
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Add FRM_REGNUM to vfnmsac/vfnmsub
* config/riscv/autovec.md: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c: New test.
---
gcc/config/riscv/autovec-opt.md | 34 ---
gcc/config/riscv/autovec.md | 30 ---
.../rvv/base/float-point-frm-autovec-3.c | 88 +++
3 files changed, 126 insertions(+), 26 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-3.c
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 732a51edacd..54ca6df721c 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -523,13 +523,15 @@ (define_insn_and_split "*single_widen_fma"
;; vect__13.182_33 = .FNMA (vect__11.180_35, vect__8.176_40, vect__4.172_45);
(define_insn_and_split "*double_widen_fnma"
[(set (match_operand:VWEXTF 0 "register_operand")
- (fma:VWEXTF
- (neg:VWEXTF
+ (unspec:VWEXTF
+ [(fma:VWEXTF
+ (neg:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand: 2 "register_operand")))
(float_extend:VWEXTF
- (match_operand: 2 "register_operand")))
- (float_extend:VWEXTF
- (match_operand: 3 "register_operand"))
- (match_operand:VWEXTF 1 "register_operand")))]
+ (match_operand: 3 "register_operand"))
+ (match_operand:VWEXTF 1 "register_operand"))
+ (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -540,17 +542,20 @@ (define_insn_and_split "*double_widen_fnma"
DONE;
}
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "")])
+ (set_attr "mode" "")
+ (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
;; This helps to match ext + fnma.
(define_insn_and_split "*single_widen_fnma"
[(set (match_operand:VWEXTF 0 "register_operand")
- (fma:VWEXTF
- (neg:VWEXTF
- (float_extend:VWEXTF
- (match_operand: 2 "register_operand")))
- (match_operand:VWEXTF 3 "register_operand")
- (match_operand:VWEXTF 1 "register_operand")))]
+ (unspec:VWEXTF
+ [(fma:VWEXTF
+ (neg:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand: 2 "register_operand")))
+ (match_operand:VWEXTF 3 "register_operand")
+ (match_operand:VWEXTF 1 "register_operand"))
+ (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -567,7 +572,8 @@ (define_insn_and_split "*single_widen_fnma"
DONE;
}
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "")])
+ (set_attr "mode" "")
+ (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
;; -
;; [FP] VFWMSAC
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 0c1c546817a..28396c6175d 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1174,24 +1174,29 @@ (define_insn_and_split "*fma"
(define_expand "fnma4"
[(parallel
[(set (match_operand:VF 0 "register_operand")
- (fma:VF
- (neg:VF
- (match_operand:VF 1 "register_operand"))
- (match_operand:VF 2 "register_operand")
- (match_operand:VF 3 "register_operand")))
+ (unspec:VF
+ [(fma:VF
+ (neg:VF
+ (match_operand:VF 1 "register_operand"))
+ (match_operand:VF 2 "register_operand")
+ (match_operand:VF 3 "register_operand"))
+(reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
(clobber (match_dup 4))])]
"TARGET_VECTOR"
{
operands[4] = gen_reg_rtx (Pmode);
- })
+ }
+ [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
(define_insn_and_split "*fnma"
[(set (match_operand:VF 0 "register_operand" "=vr, vr, ?")
- (fma:VF
- (neg:VF
- (match_operand:VF 1 "register_operand" " %0, vr, vr"))
- (match_operand:VF 2 "register_operand" " vr, vr, vr")
- (match_operand:VF 3 "register_operand" " vr, 0, vr")))
+ (unspec:VF
+ [(fma:VF
+
[PATCH v2] RISC-V: Fix one typo in autovec.md pattern comment
From: Pan Li vfmsac => vfnmacc vfmsub => vfnmadd Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/autovec.md: Fix typo. --- gcc/config/riscv/autovec.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index e1addc07036..e9659b2b157 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1253,11 +1253,11 @@ (define_insn_and_split "*fms" (set_attr "mode" "")]) ;; - -;; [FP] VFMSAC and VFMSUB +;; [FP] VFNMACC and VFNMADD ;; - ;; Includes: -;; - vfmsac -;; - vfmsub +;; - vfnmacc +;; - vfnmadd ;; - (define_expand "fnms4" -- 2.34.1
[PATCH v1] RISC-V: Fix one typo in autovec.md pattern comment
From: Pan Li Fix below typo for the pattern comment. vfmsac => vfnmsac vfmsub => vfnmsub Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/autovec.md: Fix typo. --- gcc/config/riscv/autovec.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index d9f1a10eb66..18950ac7c4f 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1258,11 +1258,11 @@ (define_insn_and_split "*fms" (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) ;; - -;; [FP] VFMSAC and VFMSUB +;; [FP] VFNMSAC and VFNMSUB ;; - ;; Includes: -;; - vfmsac -;; - vfmsub +;; - vfnmsac +;; - vfnmsub ;; - (define_expand "fnms4" -- 2.34.1
[PATCH v1] RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec
From: Pan Li
There will be a case like below for intrinsic and autovec combination.
vfadd RTZ <- intrinisc static rounding
vfmsub <- autovec/autovec-opt
The autovec generated vfmsub should take DYN mode, and the
frm must be restored before the vfmsub insn. This patch
would like to fix this issue by:
* Add the frm operand to the autovec/autovec-opt pattern.
* Set the frm_mode attr to DYN.
Thus, the frm flow when combine autovec and intrinsic should be.
+
| frrm a5
| ...
| fsrmi 4
| vfadd <- intrinsic static rounding.
| ...
| fsrm a5
| vfmsub <- autovec/autovec-opt
| ...
+
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmsac/vfmsub
* config/riscv/autovec.md: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: New test.
---
gcc/config/riscv/autovec-opt.md | 36
gcc/config/riscv/autovec.md | 30 ---
.../rvv/base/float-point-frm-autovec-2.c | 88 +++
3 files changed, 127 insertions(+), 27 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 4b07e80ad95..732a51edacd 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -583,13 +583,15 @@ (define_insn_and_split "*single_widen_fnma"
;; vect__13.182_33 = .FMS (vect__11.180_35, vect__8.176_40, vect__4.172_45);
(define_insn_and_split "*double_widen_fms"
[(set (match_operand:VWEXTF 0 "register_operand")
- (fma:VWEXTF
- (float_extend:VWEXTF
- (match_operand: 2 "register_operand"))
- (float_extend:VWEXTF
- (match_operand: 3 "register_operand"))
- (neg:VWEXTF
- (match_operand:VWEXTF 1 "register_operand"]
+ (unspec:VWEXTF
+ [(fma:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand: 2 "register_operand"))
+ (float_extend:VWEXTF
+ (match_operand: 3 "register_operand"))
+ (neg:VWEXTF
+ (match_operand:VWEXTF 1 "register_operand")))
+ (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -600,17 +602,20 @@ (define_insn_and_split "*double_widen_fms"
DONE;
}
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "")])
+ (set_attr "mode" "")
+ (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
;; This helps to match ext + fms.
(define_insn_and_split "*single_widen_fms"
[(set (match_operand:VWEXTF 0 "register_operand")
- (fma:VWEXTF
- (float_extend:VWEXTF
- (match_operand: 2 "register_operand"))
- (match_operand:VWEXTF 3 "register_operand")
- (neg:VWEXTF
- (match_operand:VWEXTF 1 "register_operand"]
+ (unspec:VWEXTF
+ [(fma:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand: 2 "register_operand"))
+ (match_operand:VWEXTF 3 "register_operand")
+ (neg:VWEXTF
+ (match_operand:VWEXTF 1 "register_operand")))
+ (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -627,7 +632,8 @@ (define_insn_and_split "*single_widen_fms"
DONE;
}
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "")])
+ (set_attr "mode" "")
+ (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
;; -
;; [FP] VFWNMACC
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 4894986d2a5..d9f1a10eb66 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1218,24 +1218,29 @@ (define_insn_and_split "*fnma"
(define_expand "fms4"
[(parallel
[(set (match_operand:VF 0 "register_operand")
- (fma:VF
- (match_operand:VF 1 "register_operand")
- (match_operand:VF 2 "register_operand")
- (neg:VF
- (match_operand:VF 3 "register_operand"
+ (unspec:VF
+ [(fma:VF
+ (match_operand:VF 1 "register_operand")
+ (match_operand:VF 2 "register_operand")
+ (neg:VF
+ (match_operand:VF 3 "register_operand")))
+(reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
(clobber (match_dup 4))])]
"TARGET_VECTOR"
{
operands[4] = gen_reg_rtx (Pmode);
- })
+ }
+ [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
(define_insn_and_split "*fms"
[(set (match_operand:VF 0 "register_operand" "=vr, vr, ?")
- (fma:VF
- (match_operand:VF 1 "register_operand" " %0, vr, vr")
- (match_operand:VF 2 "register_operand" " vr, vr, vr")
- (neg:VF
- (match_operand:VF 3 "register_operand" " vr, 0, vr"
+ (unspec:VF
+
[PATCH v1] RISC-V: Support rounding mode for VFMADD/VFMACC autovec
From: Pan Li There will be a case like below for intrinsic and autovec combination vfadd RTZ <- intrinisc static rounding vfmadd <- autovec/autovec-opt The autovec generated vfmadd should take DYN mode, and the frm must be restored before the vfmadd insn. This patch would like to fix this issue by: * Add the frm operand to the vfmadd/vfmacc autovec/autovec-opt pattern. * Set the frm_mode attr to DYN. Thus, the frm flow when combine autovec and intrinsic should be. + | frrm a5 | ... | fsrmi 4 | vfadd <- intrinsic static rounding. | ... | fsrm a5 | vfmadd <- autovec/autovec-opt | ... + However, we leverage unspec instead of use to consume the FRM register because there are some restrictions from the combine pass. Some code path of try_combine may require the XVECLEN(pat, 0) == 2 for the recog_for_combine, and add new use will make the XVECLEN(pat, 0) == 3 and result in the vfwmacc optimization failure. For example, in the test widen-complicate-5.c and widen-8.c Finally, there will be other fma cases and they will be covered in the underlying patches. Signed-off-by: Pan Li Co-Authored-By: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmadd/vfmacc. * config/riscv/autovec.md: Ditto. * config/riscv/vector-iterators.md: Add UNSPEC_VFFMA. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c: New test. --- gcc/config/riscv/autovec-opt.md | 32 --- gcc/config/riscv/autovec.md | 26 +++--- gcc/config/riscv/vector-iterators.md | 2 + .../rvv/base/float-point-frm-autovec-1.c | 88 +++ 4 files changed, 125 insertions(+), 23 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-1.c diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 99b609a99d9..4b07e80ad95 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -459,12 +459,14 @@ (define_insn_and_split "*pred_single_widen_mul" ;; vect__13.182_33 = .FMA (vect__11.180_35, vect__8.176_40, vect__4.172_45); (define_insn_and_split "*double_widen_fma" [(set (match_operand:VWEXTF 0 "register_operand") - (fma:VWEXTF - (float_extend:VWEXTF - (match_operand: 2 "register_operand")) - (float_extend:VWEXTF - (match_operand: 3 "register_operand")) - (match_operand:VWEXTF 1 "register_operand")))] + (unspec:VWEXTF + [(fma:VWEXTF + (float_extend:VWEXTF + (match_operand: 2 "register_operand")) + (float_extend:VWEXTF + (match_operand: 3 "register_operand")) + (match_operand:VWEXTF 1 "register_operand")) + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -475,16 +477,19 @@ (define_insn_and_split "*double_widen_fma" DONE; } [(set_attr "type" "vfwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) ;; This helps to match ext + fma. (define_insn_and_split "*single_widen_fma" [(set (match_operand:VWEXTF 0 "register_operand") - (fma:VWEXTF - (float_extend:VWEXTF - (match_operand: 2 "register_operand")) - (match_operand:VWEXTF 3 "register_operand") - (match_operand:VWEXTF 1 "register_operand")))] + (unspec:VWEXTF + [(fma:VWEXTF + (float_extend:VWEXTF + (match_operand: 2 "register_operand")) + (match_operand:VWEXTF 3 "register_operand") + (match_operand:VWEXTF 1 "register_operand")) + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -501,7 +506,8 @@ (define_insn_and_split "*single_widen_fma" DONE; } [(set_attr "type" "vfwmuladd") - (set_attr "mode" "")]) + (set_attr "mode" "") + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))]) ;; - ;; [FP] VFWNMSAC diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index acca4c22b90..4894986d2a5 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1126,22 +1126,27 @@ (define_insn_and_split "*fnma" (define_expand "fma4" [(parallel [(set (match_operand:VF 0 "register_operand") - (fma:VF - (match_operand:VF 1 "register_operand") - (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand"))) + (unspec:VF + [(fma:VF + (match_operand:VF 1 "register_operand") + (match_operand:VF 2 "register_operand") + (match_operand:VF 3 "register_operand")) +(reg:SI FRM_REGNUM)] UNSPEC_VFFMA)) (clobber (match_dup 4))])] "TARGET_VECTOR"
[PATCH v2] RISC-V: Refactor RVV class by frm_op_type template arg
From: Pan Li
Update in v2:
* Added gcc_assert for vx format in binop.
* Passed riscv/rvv.exp test.
Original Log:
As suggested by kito, we will add new frm_opt_type template arg
to the op class, to avoid the duplicated function expand.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class binop_frm): Removed.
(class reverse_binop_frm): Ditto.
(class widen_binop_frm): Ditto.
(class vfmacc_frm): Ditto.
(class vfnmacc_frm): Ditto.
(class vfmsac_frm): Ditto.
(class vfnmsac_frm): Ditto.
(class vfmadd_frm): Ditto.
(class vfnmadd_frm): Ditto.
(class vfmsub_frm): Ditto.
(class vfnmsub_frm): Ditto.
(class vfwmacc_frm): Ditto.
(class vfwnmacc_frm): Ditto.
(class vfwmsac_frm): Ditto.
(class vfwnmsac_frm): Ditto.
(class unop_frm): Ditto.
(class vfrec7_frm): Ditto.
(class binop): Add frm_op_type template arg.
(class unop): Ditto.
(class widen_binop): Ditto.
(class widen_binop_fp): Ditto.
(class reverse_binop): Ditto.
(class vfmacc): Ditto.
(class vfnmsac): Ditto.
(class vfmadd): Ditto.
(class vfnmsub): Ditto.
(class vfnmacc): Ditto.
(class vfmsac): Ditto.
(class vfnmadd): Ditto.
(class vfmsub): Ditto.
(class vfwmacc): Ditto.
(class vfwnmacc): Ditto.
(class vfwmsac): Ditto.
(class vfwnmsac): Ditto.
(class float_misc): Ditto.
---
.../riscv/riscv-vector-builtins-bases.cc | 571 +-
1 file changed, 143 insertions(+), 428 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 5ee7d3119db..54582ee130c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -262,41 +262,21 @@ public:
vremu/vsadd/vsaddu/vssub/vssubu
vfadd/vfsub/
*/
-template
+template
class binop : public function_base
{
public:
- rtx expand (function_expander ) const override
+ bool has_rounding_mode_operand_p () const override
{
-switch (e.op_info->op)
- {
- case OP_TYPE_vx:
- case OP_TYPE_vf:
- return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode ()));
- case OP_TYPE_vv:
- return e.use_exact_insn (code_for_pred (CODE, e.vector_mode ()));
- default:
- gcc_unreachable ();
- }
+return FRM_OP == HAS_FRM;
}
-};
-
-/* Implements below instructions for now.
- - vfadd
- - vfsub
- - vfmul
- - vfdiv
-*/
-template
-class binop_frm : public function_base
-{
-public:
- bool has_rounding_mode_operand_p () const override { return true; }
rtx expand (function_expander ) const override
{
switch (e.op_info->op)
{
+ case OP_TYPE_vx:
+ gcc_assert (FRM_OP == NO_FRM);
case OP_TYPE_vf:
return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode ()));
case OP_TYPE_vv:
@@ -307,365 +287,6 @@ public:
}
};
-/* Implements below instructions for frm
- - vfrsub
- - vfrdiv
-*/
-template
-class reverse_binop_frm : public function_base
-{
-public:
- bool has_rounding_mode_operand_p () const override { return true; }
-
-public:
- rtx expand (function_expander ) const override
- {
-return e.use_exact_insn (
- code_for_pred_reverse_scalar (CODE, e.vector_mode ()));
- }
-};
-
-/* Implements below instructions for frm
- - vfwadd
- - vfwsub
- - vfwmul
-*/
-template
-class widen_binop_frm : public function_base
-{
-public:
- bool has_rounding_mode_operand_p () const override { return true; }
-
- rtx expand (function_expander ) const override
- {
-switch (e.op_info->op)
- {
- case OP_TYPE_vv:
- return e.use_exact_insn (
- code_for_pred_dual_widen (CODE, e.vector_mode ()));
- case OP_TYPE_vf:
- return e.use_exact_insn (
- code_for_pred_dual_widen_scalar (CODE, e.vector_mode ()));
- case OP_TYPE_wv:
- if (CODE == PLUS)
- return e.use_exact_insn (
- code_for_pred_single_widen_add (e.vector_mode ()));
- else
- return e.use_exact_insn (
- code_for_pred_single_widen_sub (e.vector_mode ()));
- case OP_TYPE_wf:
- return e.use_exact_insn (
- code_for_pred_single_widen_scalar (CODE, e.vector_mode ()));
- default:
- gcc_unreachable ();
- }
- }
-};
-
-/* Implements below instructions for frm
- - vfmacc
-*/
-class vfmacc_frm : public function_base
-{
-public:
- bool has_rounding_mode_operand_p () const override { return true; }
-
- bool has_merge_operand_p () const override { return false; }
-
- rtx expand (function_expander ) const override
- {
-if (e.op_info->op == OP_TYPE_vf)
- return e.use_ternop_insn (true,
- code_for_pred_mul_scalar (PLUS,
-
[PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook
From: Pan Li
We have EMIT hook in mode switching already, which will insert the
insn before in most cases. However, in some arch like RISC-V, it
requires the additional insn to be inserted after when meet a call.
|
| <- EMIT HOOK, insert the insn before.
+---+
| ptr->insn |
+---+
| <- EMIT_AFTER HOOK, insert the insn after.
|
Thus, this patch would like to add one optional EMIT_AFTER hook, which
will try to insert the emitted insn after. The end-user can either
implement this HOOK or leave it NULL as is.
If the backend ignore this optinal hook, there is no impact to the
original mode switching stuff. If the backend implement this optional
hook, the mode switching will try to insert the insn after. Please note
the EMIT_AFTER doen't have any impact to EMIT hook.
Passed both the regression and bootstrap test in x86.
Signed-off-by: Pan Li
gcc/ChangeLog:
* doc/tm.texi: Add hook def and update the description.
* doc/tm.texi.in: Ditto.
* mode-switching.cc (optimize_mode_switching): Insert the
emitted insn after ptr->insn.
* target.def (insn): Define emit_after hook.
---
gcc/doc/tm.texi | 12 ++--
gcc/doc/tm.texi.in| 6 --
gcc/mode-switching.cc | 45 +++
gcc/target.def| 9 +
4 files changed, 68 insertions(+), 4 deletions(-)
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index e4d0cc43f41..a0798d4468b 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -10334,8 +10334,8 @@ return nonzero for any @var{entity} that needs
mode-switching.
If you define this macro, you also have to define
@code{NUM_MODES_FOR_MODE_SWITCHING}, @code{TARGET_MODE_NEEDED},
@code{TARGET_MODE_PRIORITY} and @code{TARGET_MODE_EMIT}.
-@code{TARGET_MODE_AFTER}, @code{TARGET_MODE_ENTRY}, and @code{TARGET_MODE_EXIT}
-are optional.
+@code{TARGET_MODE_AFTER}, @code{TARGET_MODE_ENTRY},
@code{TARGET_MODE_EMIT_AFTER},
+and @code{TARGET_MODE_EXIT} are optional.
@end defmac
@defmac NUM_MODES_FOR_MODE_SWITCHING
@@ -10359,6 +10359,14 @@ to switch from. Sets of a lower numbered entity will
be emitted before
sets of a higher numbered entity to a mode of the same or lower priority.
@end deftypefn
+@deftypefn {Target Hook} void TARGET_MODE_EMIT_AFTER (int @var{entity}, int
@var{mode}, int @var{prev_mode}, HARD_REG_SET @var{regs_live})
+Generate one or more insns to set @var{entity} to @var{mode}.
+@var{hard_reg_live} is the set of hard registers live at the point where
+the insn(s) are to be inserted after. @var{prev_moxde} indicates the mode
+to switch from. Sets of a lower numbered entity will be emitted before
+sets of a higher numbered entity to a mode of the same or lower priority.
+@end deftypefn
+
@deftypefn {Target Hook} int TARGET_MODE_NEEDED (int @var{entity}, rtx_insn
*@var{insn})
@var{entity} is an integer specifying a mode-switched entity.
If @code{OPTIMIZE_MODE_SWITCHING} is defined, you must define this macro
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 4ac96dc357d..2942ce0be3b 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -6911,8 +6911,8 @@ return nonzero for any @var{entity} that needs
mode-switching.
If you define this macro, you also have to define
@code{NUM_MODES_FOR_MODE_SWITCHING}, @code{TARGET_MODE_NEEDED},
@code{TARGET_MODE_PRIORITY} and @code{TARGET_MODE_EMIT}.
-@code{TARGET_MODE_AFTER}, @code{TARGET_MODE_ENTRY}, and @code{TARGET_MODE_EXIT}
-are optional.
+@code{TARGET_MODE_AFTER}, @code{TARGET_MODE_ENTRY},
@code{TARGET_MODE_EMIT_AFTER},
+and @code{TARGET_MODE_EXIT} are optional.
@end defmac
@defmac NUM_MODES_FOR_MODE_SWITCHING
@@ -6930,6 +6930,8 @@ switch is needed / supplied.
@hook TARGET_MODE_EMIT
+@hook TARGET_MODE_EMIT_AFTER
+
@hook TARGET_MODE_NEEDED
@hook TARGET_MODE_AFTER
diff --git a/gcc/mode-switching.cc b/gcc/mode-switching.cc
index f483c831c35..98051dff487 100644
--- a/gcc/mode-switching.cc
+++ b/gcc/mode-switching.cc
@@ -34,6 +34,8 @@ along with GCC; see the file COPYING3. If not see
#include "lcm.h"
#include "cfgcleanup.h"
#include "tree-pass.h"
+#include "cfgbuild.h"
+#include "gcse.h"
/* We want target macros for the mode switching code to be able to refer
to instruction attribute values. */
@@ -831,6 +833,49 @@ optimize_mode_switching (void)
emit_insn_before (mode_set, ptr->insn_ptr);
}
+ if (targetm.mode_switching.emit_after)
+ {
+ if (control_flow_insn_p (ptr->insn_ptr)
+ && ptr->insn_ptr == BB_END (bb))
+ {
+ edge eg;
+ edge_iterator eg_iterator;
+
+ FOR_EACH_EDGE (eg, eg_iterator, bb->succs)
+ {
+ start_sequence ();
+ targetm.mode_switching.emit_after (entity_map[j],
+
[PATCH v1] RISC-V: Refactor RVV class by frm_op_type template arg
From: Pan Li
As suggested by kito, we will add new frm_opt_type template arg
to the op class, to avoid the duplicated function expand.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class binop_frm): Removed.
(class reverse_binop_frm): Ditto.
(class widen_binop_frm): Ditto.
(class vfmacc_frm): Ditto.
(class vfnmacc_frm): Ditto.
(class vfmsac_frm): Ditto.
(class vfnmsac_frm): Ditto.
(class vfmadd_frm): Ditto.
(class vfnmadd_frm): Ditto.
(class vfmsub_frm): Ditto.
(class vfnmsub_frm): Ditto.
(class vfwmacc_frm): Ditto.
(class vfwnmacc_frm): Ditto.
(class vfwmsac_frm): Ditto.
(class vfwnmsac_frm): Ditto.
(class unop_frm): Ditto.
(class vfrec7_frm): Ditto.
(class binop): Add frm_op_type template arg.
(class unop): Ditto.
(class widen_binop): Ditto.
(class widen_binop_fp): Ditto.
(class reverse_binop): Ditto.
(class vfmacc): Ditto.
(class vfnmsac): Ditto.
(class vfmadd): Ditto.
(class vfnmsub): Ditto.
(class vfnmacc): Ditto.
(class vfmsac): Ditto.
(class vfnmadd): Ditto.
(class vfmsub): Ditto.
(class vfwmacc): Ditto.
(class vfwnmacc): Ditto.
(class vfwmsac): Ditto.
(class vfwnmsac): Ditto.
(class float_misc): Ditto.
---
.../riscv/riscv-vector-builtins-bases.cc | 570 +-
1 file changed, 142 insertions(+), 428 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 5ee7d3119db..c1f50fdd987 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -262,41 +262,20 @@ public:
vremu/vsadd/vsaddu/vssub/vssubu
vfadd/vfsub/
*/
-template
+template
class binop : public function_base
{
public:
- rtx expand (function_expander ) const override
+ bool has_rounding_mode_operand_p () const override
{
-switch (e.op_info->op)
- {
- case OP_TYPE_vx:
- case OP_TYPE_vf:
- return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode ()));
- case OP_TYPE_vv:
- return e.use_exact_insn (code_for_pred (CODE, e.vector_mode ()));
- default:
- gcc_unreachable ();
- }
+return FRM_OP == HAS_FRM;
}
-};
-
-/* Implements below instructions for now.
- - vfadd
- - vfsub
- - vfmul
- - vfdiv
-*/
-template
-class binop_frm : public function_base
-{
-public:
- bool has_rounding_mode_operand_p () const override { return true; }
rtx expand (function_expander ) const override
{
switch (e.op_info->op)
{
+ case OP_TYPE_vx:
case OP_TYPE_vf:
return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode ()));
case OP_TYPE_vv:
@@ -307,365 +286,6 @@ public:
}
};
-/* Implements below instructions for frm
- - vfrsub
- - vfrdiv
-*/
-template
-class reverse_binop_frm : public function_base
-{
-public:
- bool has_rounding_mode_operand_p () const override { return true; }
-
-public:
- rtx expand (function_expander ) const override
- {
-return e.use_exact_insn (
- code_for_pred_reverse_scalar (CODE, e.vector_mode ()));
- }
-};
-
-/* Implements below instructions for frm
- - vfwadd
- - vfwsub
- - vfwmul
-*/
-template
-class widen_binop_frm : public function_base
-{
-public:
- bool has_rounding_mode_operand_p () const override { return true; }
-
- rtx expand (function_expander ) const override
- {
-switch (e.op_info->op)
- {
- case OP_TYPE_vv:
- return e.use_exact_insn (
- code_for_pred_dual_widen (CODE, e.vector_mode ()));
- case OP_TYPE_vf:
- return e.use_exact_insn (
- code_for_pred_dual_widen_scalar (CODE, e.vector_mode ()));
- case OP_TYPE_wv:
- if (CODE == PLUS)
- return e.use_exact_insn (
- code_for_pred_single_widen_add (e.vector_mode ()));
- else
- return e.use_exact_insn (
- code_for_pred_single_widen_sub (e.vector_mode ()));
- case OP_TYPE_wf:
- return e.use_exact_insn (
- code_for_pred_single_widen_scalar (CODE, e.vector_mode ()));
- default:
- gcc_unreachable ();
- }
- }
-};
-
-/* Implements below instructions for frm
- - vfmacc
-*/
-class vfmacc_frm : public function_base
-{
-public:
- bool has_rounding_mode_operand_p () const override { return true; }
-
- bool has_merge_operand_p () const override { return false; }
-
- rtx expand (function_expander ) const override
- {
-if (e.op_info->op == OP_TYPE_vf)
- return e.use_ternop_insn (true,
- code_for_pred_mul_scalar (PLUS,
- e.vector_mode ()));
-if (e.op_info->op == OP_TYPE_vv)
- return e.use_ternop_insn (true,
-
[PATCH v1] RISC-V: Support RVV VFWREDUSUM.VS rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFWREDUSUM.VS as the below samples
* __riscv_vfwredusum_vs_f32m1_f64m1_rm
* __riscv_vfwredusum_vs_f32m1_f64m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(vfwredusum_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwredusum_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wredusum.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 2 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 1 +
.../riscv/rvv/base/float-point-wredusum.c | 33 +++
4 files changed, 37 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredusum.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index abf03bab0da..5ee7d3119db 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2548,6 +2548,7 @@ static CONSTEXPR const freducop
vfredosum_frm_obj;
static CONSTEXPR const reducop vfredmax_obj;
static CONSTEXPR const reducop vfredmin_obj;
static CONSTEXPR const widen_freducop vfwredusum_obj;
+static CONSTEXPR const widen_freducop
vfwredusum_frm_obj;
static CONSTEXPR const widen_freducop vfwredosum_obj;
static CONSTEXPR const widen_freducop
vfwredosum_frm_obj;
static CONSTEXPR const vmv vmv_x_obj;
@@ -2810,6 +2811,7 @@ BASE (vfredmin)
BASE (vfwredosum)
BASE (vfwredosum_frm)
BASE (vfwredusum)
+BASE (vfwredusum_frm)
BASE (vmv_x)
BASE (vmv_s)
BASE (vfmv_f)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index c1bb164a712..69d4562091f 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -247,6 +247,7 @@ extern const function_base *const vfredmin;
extern const function_base *const vfwredosum;
extern const function_base *const vfwredosum_frm;
extern const function_base *const vfwredusum;
+extern const function_base *const vfwredusum_frm;
extern const function_base *const vmv_x;
extern const function_base *const vmv_s;
extern const function_base *const vfmv_f;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index da1157f5a56..3ce06dc60b7 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -508,6 +508,7 @@ DEF_RVV_FUNCTION (vfwredosum, reduc_alu, no_mu_preds,
wf_vs_ops)
DEF_RVV_FUNCTION (vfwredusum, reduc_alu, no_mu_preds, wf_vs_ops)
DEF_RVV_FUNCTION (vfwredosum_frm, reduc_alu_frm, no_mu_preds, wf_vs_ops)
+DEF_RVV_FUNCTION (vfwredusum_frm, reduc_alu_frm, no_mu_preds, wf_vs_ops)
/* 15. Vector Mask Instructions. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredusum.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredusum.c
new file mode 100644
index 000..6c888c10c0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredusum.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+test_riscv_vfwredusum_vs_f32m1_f64m1_rm (vfloat32m1_t op1, vfloat64m1_t op2,
+size_t vl) {
+ return __riscv_vfwredusum_vs_f32m1_f64m1_rm (op1, op2, 0, vl);
+}
+
+vfloat64m1_t
+test_vfwredusum_vs_f32m1_f64m1_rm_m (vbool32_t mask, vfloat32m1_t op1,
+vfloat64m1_t op2, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m1_f64m1_rm_m (mask, op1, op2, 1, vl);
+}
+
+vfloat64m1_t
+test_riscv_vfwredusum_vs_f32m1_f64m1 (vfloat32m1_t op1, vfloat64m1_t op2,
+ size_t vl) {
+ return __riscv_vfwredusum_vs_f32m1_f64m1 (op1, op2, vl);
+}
+
+vfloat64m1_t
+test_vfwredusum_vs_f32m1_f64m1_m (vbool32_t mask, vfloat32m1_t op1,
+ vfloat64m1_t op2, size_t vl) {
+ return __riscv_vfwredusum_vs_f32m1_f64m1_m (mask, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+} 4 }
} */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
--
2.34.1
[PATCH v1] RISC-V: Support RVV VFWREDOSUM.VS rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFWREDOSUM.VS as the below samples
* __riscv_vfwredosum_vs_f32m1_f64m1_rm
* __riscv_vfwredosum_vs_f32m1_f64m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(widen_freducop): Add frm_opt_type template arg.
(vfwredosum_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwredosum_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wredosum.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 9 -
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 ++
.../riscv/rvv/base/float-point-wredosum.c | 33 +++
4 files changed, 44 insertions(+), 1 deletion(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index ef2991359da..abf03bab0da 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1866,10 +1866,15 @@ public:
};
/* Implements widening floating-point reduction instructions. */
-template
+template
class widen_freducop : public function_base
{
public:
+ bool has_rounding_mode_operand_p () const override
+ {
+return FRM_OP == HAS_FRM;
+ }
+
bool apply_mask_policy_p () const override { return false; }
rtx expand (function_expander ) const override
@@ -2544,6 +2549,7 @@ static CONSTEXPR const reducop vfredmax_obj;
static CONSTEXPR const reducop vfredmin_obj;
static CONSTEXPR const widen_freducop vfwredusum_obj;
static CONSTEXPR const widen_freducop vfwredosum_obj;
+static CONSTEXPR const widen_freducop
vfwredosum_frm_obj;
static CONSTEXPR const vmv vmv_x_obj;
static CONSTEXPR const vmv_s vmv_s_obj;
static CONSTEXPR const vmv vfmv_f_obj;
@@ -2802,6 +2808,7 @@ BASE (vfredosum_frm)
BASE (vfredmax)
BASE (vfredmin)
BASE (vfwredosum)
+BASE (vfwredosum_frm)
BASE (vfwredusum)
BASE (vmv_x)
BASE (vmv_s)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index da8412b66df..c1bb164a712 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -245,6 +245,7 @@ extern const function_base *const vfredosum_frm;
extern const function_base *const vfredmax;
extern const function_base *const vfredmin;
extern const function_base *const vfwredosum;
+extern const function_base *const vfwredosum_frm;
extern const function_base *const vfwredusum;
extern const function_base *const vmv_x;
extern const function_base *const vmv_s;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 80e65bfb14b..da1157f5a56 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -507,6 +507,8 @@ DEF_RVV_FUNCTION (vfredosum_frm, reduc_alu_frm,
no_mu_preds, f_vs_ops)
DEF_RVV_FUNCTION (vfwredosum, reduc_alu, no_mu_preds, wf_vs_ops)
DEF_RVV_FUNCTION (vfwredusum, reduc_alu, no_mu_preds, wf_vs_ops)
+DEF_RVV_FUNCTION (vfwredosum_frm, reduc_alu_frm, no_mu_preds, wf_vs_ops)
+
/* 15. Vector Mask Instructions. */
// 15.1. Vector Mask-Register Logical Instructions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c
new file mode 100644
index 000..acf79569a22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredosum.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+test_riscv_vfwredosum_vs_f32m1_f64m1_rm (vfloat32m1_t op1, vfloat64m1_t op2,
+size_t vl) {
+ return __riscv_vfwredosum_vs_f32m1_f64m1_rm (op1, op2, 0, vl);
+}
+
+vfloat64m1_t
+test_vfwredosum_vs_f32m1_f64m1_rm_m (vbool32_t mask, vfloat32m1_t op1,
+vfloat64m1_t op2, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m1_f64m1_rm_m (mask, op1, op2, 1, vl);
+}
+
+vfloat64m1_t
+test_riscv_vfwredosum_vs_f32m1_f64m1 (vfloat32m1_t op1, vfloat64m1_t op2,
+ size_t vl) {
+ return __riscv_vfwredosum_vs_f32m1_f64m1 (op1, op2, vl);
+}
+
+vfloat64m1_t
+test_vfwredosum_vs_f32m1_f64m1_m (vbool32_t mask, vfloat32m1_t op1,
+ vfloat64m1_t op2, size_t vl) {
+ return __riscv_vfwredosum_vs_f32m1_f64m1_m (mask, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+} 4 }
} */
+/* { dg-final {
[PATCH v1] RISC-V: Support RVV VFREDOSUM.VS rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFREDOSUM.VS as the below samples.
* __riscv_vfredosum_vs_f32m1_f32m1_rm
* __riscv_vfredosum_vs_f32m1_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(vfredosum_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfredosum_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-redosum.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 2 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 1 +
.../riscv/rvv/base/float-point-redosum.c | 33 +++
4 files changed, 37 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 65f1d9c8ff7..ef2991359da 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2539,6 +2539,7 @@ static CONSTEXPR const widen_reducop
vwredsumu_obj;
static CONSTEXPR const freducop vfredusum_obj;
static CONSTEXPR const freducop vfredusum_frm_obj;
static CONSTEXPR const freducop vfredosum_obj;
+static CONSTEXPR const freducop vfredosum_frm_obj;
static CONSTEXPR const reducop vfredmax_obj;
static CONSTEXPR const reducop vfredmin_obj;
static CONSTEXPR const widen_freducop vfwredusum_obj;
@@ -2797,6 +2798,7 @@ BASE (vwredsumu)
BASE (vfredusum)
BASE (vfredusum_frm)
BASE (vfredosum)
+BASE (vfredosum_frm)
BASE (vfredmax)
BASE (vfredmin)
BASE (vfwredosum)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index fd1a84f3e68..da8412b66df 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -241,6 +241,7 @@ extern const function_base *const vwredsumu;
extern const function_base *const vfredusum;
extern const function_base *const vfredusum_frm;
extern const function_base *const vfredosum;
+extern const function_base *const vfredosum_frm;
extern const function_base *const vfredmax;
extern const function_base *const vfredmin;
extern const function_base *const vfwredosum;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 90a83c02d52..80e65bfb14b 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -501,6 +501,7 @@ DEF_RVV_FUNCTION (vfredmax, reduc_alu, no_mu_preds,
f_vs_ops)
DEF_RVV_FUNCTION (vfredmin, reduc_alu, no_mu_preds, f_vs_ops)
DEF_RVV_FUNCTION (vfredusum_frm, reduc_alu_frm, no_mu_preds, f_vs_ops)
+DEF_RVV_FUNCTION (vfredosum_frm, reduc_alu_frm, no_mu_preds, f_vs_ops)
// 14.4. Vector Widening Floating-Point Reduction Instructions
DEF_RVV_FUNCTION (vfwredosum, reduc_alu, no_mu_preds, wf_vs_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c
new file mode 100644
index 000..2e6a3c28a89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+test_riscv_vfredosum_vs_f32m1_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfredosum_vs_f32m1_f32m1_rm (op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfredosum_vs_f32m1_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfredosum_vs_f32m1_f32m1_rm_m (mask, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfredosum_vs_f32m1_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2,
+size_t vl) {
+ return __riscv_vfredosum_vs_f32m1_f32m1 (op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfredosum_vs_f32m1_f32m1_m (vbool32_t mask, vfloat32m1_t op1,
+vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfredosum_vs_f32m1_f32m1_m (mask, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times
{vfredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
--
2.34.1
[PATCH v1] RISC-V: Support RVV VFREDUSUM.VS rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFREDUSUM.VS as the below samples.
* __riscv_vfredusum_vs_f32m1_f32m1_rm
* __riscv_vfredusum_vs_f32m1_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class freducop): Add frm_op_type template arg.
(vfredusum_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfredusum_frm): New intrinsic function def.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct reduc_alu_frm_def): New class for frm shape.
(SHAPE): New declaration.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-redusum.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 9 -
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/riscv-vector-builtins-shapes.cc | 39 +++
.../riscv/riscv-vector-builtins-shapes.h | 1 +
.../riscv/rvv/base/float-point-redusum.c | 33
6 files changed, 84 insertions(+), 1 deletion(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redusum.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index ad04647f9ba..65f1d9c8ff7 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1847,10 +1847,15 @@ public:
};
/* Implements floating-point reduction instructions. */
-template
+template
class freducop : public function_base
{
public:
+ bool has_rounding_mode_operand_p () const override
+ {
+return FRM_OP == HAS_FRM;
+ }
+
bool apply_mask_policy_p () const override { return false; }
rtx expand (function_expander ) const override
@@ -2532,6 +2537,7 @@ static CONSTEXPR const reducop vredxor_obj;
static CONSTEXPR const widen_reducop vwredsum_obj;
static CONSTEXPR const widen_reducop vwredsumu_obj;
static CONSTEXPR const freducop vfredusum_obj;
+static CONSTEXPR const freducop vfredusum_frm_obj;
static CONSTEXPR const freducop vfredosum_obj;
static CONSTEXPR const reducop vfredmax_obj;
static CONSTEXPR const reducop vfredmin_obj;
@@ -2789,6 +2795,7 @@ BASE (vredxor)
BASE (vwredsum)
BASE (vwredsumu)
BASE (vfredusum)
+BASE (vfredusum_frm)
BASE (vfredosum)
BASE (vfredmax)
BASE (vfredmin)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index c8c649c4bb0..fd1a84f3e68 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -239,6 +239,7 @@ extern const function_base *const vredxor;
extern const function_base *const vwredsum;
extern const function_base *const vwredsumu;
extern const function_base *const vfredusum;
+extern const function_base *const vfredusum_frm;
extern const function_base *const vfredosum;
extern const function_base *const vfredmax;
extern const function_base *const vfredmin;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index cfbc125dcd8..90a83c02d52 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -500,6 +500,8 @@ DEF_RVV_FUNCTION (vfredosum, reduc_alu, no_mu_preds,
f_vs_ops)
DEF_RVV_FUNCTION (vfredmax, reduc_alu, no_mu_preds, f_vs_ops)
DEF_RVV_FUNCTION (vfredmin, reduc_alu, no_mu_preds, f_vs_ops)
+DEF_RVV_FUNCTION (vfredusum_frm, reduc_alu_frm, no_mu_preds, f_vs_ops)
+
// 14.4. Vector Widening Floating-Point Reduction Instructions
DEF_RVV_FUNCTION (vfwredosum, reduc_alu, no_mu_preds, wf_vs_ops)
DEF_RVV_FUNCTION (vfwredusum, reduc_alu, no_mu_preds, wf_vs_ops)
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 80329113af3..f8fdec863e6 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -371,6 +371,44 @@ struct narrow_alu_frm_def : public build_frm_base
}
};
+/* reduc_alu_frm_def class. */
+struct reduc_alu_frm_def : public build_frm_base
+{
+ char *get_name (function_builder , const function_instance ,
+ bool overloaded_p) const override
+ {
+char base_name[BASE_NAME_MAX_LEN] = {};
+
+normalize_base_name (base_name, instance.base_name, sizeof (base_name));
+
+b.append_base_name (base_name);
+
+/* vop_ --> vop__. */
+if (!overloaded_p)
+ {
+ b.append_name (operand_suffixes[instance.op_info->op]);
+ b.append_name (type_suffixes[instance.type.index].vector);
+ vector_type_index ret_type_idx
+ =
[PATCH v1] RISC-V: Support RVV VFNCVT.F.{X|XU|F}.W rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFNCVT.F.{X|XU|F}.W as the below samples.
* __riscv_vfncvt_f_x_w_f32m1_rm
* __riscv_vfncvt_f_x_w_f32m1_rm_m
* __riscv_vfncvt_f_xu_w_f32m1_rm
* __riscv_vfncvt_f_xu_w_f32m1_rm_m
* __riscv_vfncvt_f_f_w_f32m1_rm
* __riscv_vfncvt_f_f_w_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfncvt_f): Add frm_op_type template arg.
(vfncvt_f_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfncvt_f_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-ncvt-f.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 10 ++-
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 3 +
.../riscv/rvv/base/float-point-ncvt-f.c | 69 +++
4 files changed, 82 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index acadec2afca..ad04647f9ba 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1786,9 +1786,15 @@ public:
}
};
+template
class vfncvt_f : public function_base
{
public:
+ bool has_rounding_mode_operand_p () const override
+ {
+return FRM_OP == HAS_FRM;
+ }
+
rtx expand (function_expander ) const override
{
if (e.op_info->op == OP_TYPE_f_w)
@@ -2512,7 +2518,8 @@ static CONSTEXPR const vfncvt_x
vfncvt_xu_obj;
static CONSTEXPR const vfncvt_x
vfncvt_xu_frm_obj;
static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_x_obj;
static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_xu_obj;
-static CONSTEXPR const vfncvt_f vfncvt_f_obj;
+static CONSTEXPR const vfncvt_f vfncvt_f_obj;
+static CONSTEXPR const vfncvt_f vfncvt_f_frm_obj;
static CONSTEXPR const vfncvt_rod_f vfncvt_rod_f_obj;
static CONSTEXPR const reducop vredsum_obj;
static CONSTEXPR const reducop vredmaxu_obj;
@@ -2769,6 +2776,7 @@ BASE (vfncvt_xu_frm)
BASE (vfncvt_rtz_x)
BASE (vfncvt_rtz_xu)
BASE (vfncvt_f)
+BASE (vfncvt_f_frm)
BASE (vfncvt_rod_f)
BASE (vredsum)
BASE (vredmaxu)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 9bd09a41960..c8c649c4bb0 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -226,6 +226,7 @@ extern const function_base *const vfncvt_xu_frm;
extern const function_base *const vfncvt_rtz_x;
extern const function_base *const vfncvt_rtz_xu;
extern const function_base *const vfncvt_f;
+extern const function_base *const vfncvt_f_frm;
extern const function_base *const vfncvt_rod_f;
extern const function_base *const vredsum;
extern const function_base *const vredmaxu;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 1e0e989fc2a..cfbc125dcd8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -474,6 +474,9 @@ DEF_RVV_FUNCTION (vfncvt_rod_f, narrow_alu, full_preds,
f_to_nf_f_w_ops)
DEF_RVV_FUNCTION (vfncvt_x_frm, narrow_alu_frm, full_preds, f_to_ni_f_w_ops)
DEF_RVV_FUNCTION (vfncvt_xu_frm, narrow_alu_frm, full_preds, f_to_nu_f_w_ops)
+DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds, i_to_nf_x_w_ops)
+DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds, u_to_nf_xu_w_ops)
+DEF_RVV_FUNCTION (vfncvt_f_frm, narrow_alu_frm, full_preds, f_to_nf_f_w_ops)
/* 14. Vector Reduction Operations. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c
new file mode 100644
index 000..d6d4be5e98e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-f.c
@@ -0,0 +1,69 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+test_riscv_vfncvt_f_x_w_f32m1_rm (vint64m2_t op1, size_t vl) {
+ return __riscv_vfncvt_f_x_w_f32m1_rm (op1, 0, vl);
+}
+
+vfloat32m1_t
+test_vfncvt_f_x_w_f32m1_rm_m (vbool32_t mask, vint64m2_t op1, size_t vl) {
+ return __riscv_vfncvt_f_x_w_f32m1_rm_m (mask, op1, 1, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfncvt_f_xu_w_f32m1_rm (vuint64m2_t op1, size_t vl) {
+ return __riscv_vfncvt_f_xu_w_f32m1_rm (op1, 0, vl);
+}
+
+vfloat32m1_t
+test_vfncvt_f_xu_w_f32m1_rm_m (vbool32_t mask, vuint64m2_t op1, size_t vl) {
+ return __riscv_vfncvt_f_xu_w_f32m1_rm_m (mask, op1, 1, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfncvt_f_f_w_f32m1_rm (vfloat64m2_t op1, size_t vl) {
+ return
[PATCH v1] RISC-V: Support RVV VFNCVT.XU.F.W rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFNCVT.XU.F.W as the below samples.
* __riscv_vfncvt_xu_f_w_u16mf2_rm
* __riscv_vfncvt_xu_f_w_u16mf2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(vfncvt_xu_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfncvt_xu_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-ncvt-xu.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 2 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 1 +
.../riscv/rvv/base/float-point-ncvt-xu.c | 29 +++
4 files changed, 33 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 2f40eeaeda5..acadec2afca 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2509,6 +2509,7 @@ static CONSTEXPR const vfwcvt_f vfwcvt_f_obj;
static CONSTEXPR const vfncvt_x vfncvt_x_obj;
static CONSTEXPR const vfncvt_x vfncvt_x_frm_obj;
static CONSTEXPR const vfncvt_x vfncvt_xu_obj;
+static CONSTEXPR const vfncvt_x
vfncvt_xu_frm_obj;
static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_x_obj;
static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_xu_obj;
static CONSTEXPR const vfncvt_f vfncvt_f_obj;
@@ -2764,6 +2765,7 @@ BASE (vfwcvt_f)
BASE (vfncvt_x)
BASE (vfncvt_x_frm)
BASE (vfncvt_xu)
+BASE (vfncvt_xu_frm)
BASE (vfncvt_rtz_x)
BASE (vfncvt_rtz_xu)
BASE (vfncvt_f)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index edff0de2715..9bd09a41960 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -222,6 +222,7 @@ extern const function_base *const vfwcvt_f;
extern const function_base *const vfncvt_x;
extern const function_base *const vfncvt_x_frm;
extern const function_base *const vfncvt_xu;
+extern const function_base *const vfncvt_xu_frm;
extern const function_base *const vfncvt_rtz_x;
extern const function_base *const vfncvt_rtz_xu;
extern const function_base *const vfncvt_f;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 5e37bae318a..1e0e989fc2a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -473,6 +473,7 @@ DEF_RVV_FUNCTION (vfncvt_f, narrow_alu, full_preds,
f_to_nf_f_w_ops)
DEF_RVV_FUNCTION (vfncvt_rod_f, narrow_alu, full_preds, f_to_nf_f_w_ops)
DEF_RVV_FUNCTION (vfncvt_x_frm, narrow_alu_frm, full_preds, f_to_ni_f_w_ops)
+DEF_RVV_FUNCTION (vfncvt_xu_frm, narrow_alu_frm, full_preds, f_to_nu_f_w_ops)
/* 14. Vector Reduction Operations. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c
new file mode 100644
index 000..82c3e1364bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vuint16mf2_t
+test_riscv_vfncvt_xu_f_w_u16mf2_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfncvt_xu_f_w_u16mf2_rm (op1, 0, vl);
+}
+
+vuint16mf2_t
+test_vfncvt_xu_f_w_u16mf2_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfncvt_xu_f_w_u16mf2_rm_m (mask, op1, 1, vl);
+}
+
+vuint16mf2_t
+test_riscv_vfncvt_xu_f_w_u16mf2 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfncvt_xu_f_w_u16mf2 (op1, vl);
+}
+
+vuint16mf2_t
+test_vfncvt_xu_f_w_u16mf2_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfncvt_xu_f_w_u16mf2_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfncvt\.xu\.f\.w\s+v[0-9]+,\s*v[0-9]+} 4
} } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
--
2.34.1
[PATCH v1] RISC-V: Support RVV VFNCVT.X.F.W rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFNCVT.X.F.W as the below samples.
* __riscv_vfncvt_x_f_w_i16mf2_rm
* __riscv_vfncvt_x_f_w_i16mf2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfncvt_x): Add frm_op_type template arg.
(BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfncvt_x_frm): New intrinsic function def.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct narrow_alu_frm_def): New shape function for frm.
(SHAPE): New declaration.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-ncvt-x.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 9 -
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/riscv-vector-builtins-shapes.cc | 39 +++
.../riscv/riscv-vector-builtins-shapes.h | 1 +
.../riscv/rvv/base/float-point-ncvt-x.c | 29 ++
6 files changed, 80 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-x.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 050ecbe780c..2f40eeaeda5 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1759,10 +1759,15 @@ public:
};
/* Implements vfncvt.x. */
-template
+template
class vfncvt_x : public function_base
{
public:
+ bool has_rounding_mode_operand_p () const override
+ {
+return FRM_OP == HAS_FRM;
+ }
+
rtx expand (function_expander ) const override
{
return e.use_exact_insn (
@@ -2502,6 +2507,7 @@ static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_x_obj;
static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_xu_obj;
static CONSTEXPR const vfwcvt_f vfwcvt_f_obj;
static CONSTEXPR const vfncvt_x vfncvt_x_obj;
+static CONSTEXPR const vfncvt_x vfncvt_x_frm_obj;
static CONSTEXPR const vfncvt_x vfncvt_xu_obj;
static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_x_obj;
static CONSTEXPR const vfncvt_rtz_x vfncvt_rtz_xu_obj;
@@ -2756,6 +2762,7 @@ BASE (vfwcvt_rtz_x)
BASE (vfwcvt_rtz_xu)
BASE (vfwcvt_f)
BASE (vfncvt_x)
+BASE (vfncvt_x_frm)
BASE (vfncvt_xu)
BASE (vfncvt_rtz_x)
BASE (vfncvt_rtz_xu)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 6565740c597..edff0de2715 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -220,6 +220,7 @@ extern const function_base *const vfwcvt_rtz_x;
extern const function_base *const vfwcvt_rtz_xu;
extern const function_base *const vfwcvt_f;
extern const function_base *const vfncvt_x;
+extern const function_base *const vfncvt_x_frm;
extern const function_base *const vfncvt_xu;
extern const function_base *const vfncvt_rtz_x;
extern const function_base *const vfncvt_rtz_xu;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 22c039c8cbb..5e37bae318a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -472,6 +472,8 @@ DEF_RVV_FUNCTION (vfncvt_f, narrow_alu, full_preds,
u_to_nf_xu_w_ops)
DEF_RVV_FUNCTION (vfncvt_f, narrow_alu, full_preds, f_to_nf_f_w_ops)
DEF_RVV_FUNCTION (vfncvt_rod_f, narrow_alu, full_preds, f_to_nf_f_w_ops)
+DEF_RVV_FUNCTION (vfncvt_x_frm, narrow_alu_frm, full_preds, f_to_ni_f_w_ops)
+
/* 14. Vector Reduction Operations. */
// 14.1. Vector Single-Width Integer Reduction Instructions
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 1d14fa21e81..80329113af3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -333,6 +333,44 @@ struct widen_alu_frm_def : public build_frm_base
}
};
+/* narrow_alu_frm_def class. */
+struct narrow_alu_frm_def : public build_frm_base
+{
+ char *get_name (function_builder , const function_instance ,
+ bool overloaded_p) const override
+ {
+char base_name[BASE_NAME_MAX_LEN] = {};
+
+normalize_base_name (base_name, instance.base_name, sizeof (base_name));
+
+b.append_base_name (base_name);
+
+if (!overloaded_p)
+ {
+ /* vop --> vop_. */
+ b.append_name (operand_suffixes[instance.op_info->op]);
+ /* vop_ --> vop__. */
+ vector_type_index ret_type_idx
+ = instance.op_info->ret.get_function_type_index (instance.type.index);
+ b.append_name (type_suffixes[ret_type_idx].vector);
+ }
+
+/* According to
[PATCH v1] RISC-V: Fix one build error for template default arg
From: Pan Li In some build option combination, the default value may result in below error. This patch would like to fix it by passing a explict argument. riscv-vector-builtins-bases.cc:2495:24: error: invalid use of template-name \ ‘riscv_vector::vfcvt_f’ without an argument list Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Use explicit argument. --- gcc/config/riscv/riscv-vector-builtins-bases.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 22640745398..18453e54b51 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -2492,7 +2492,7 @@ static CONSTEXPR const vfcvt_x vfcvt_xu_obj; static CONSTEXPR const vfcvt_x vfcvt_xu_frm_obj; static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj; static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj; -static CONSTEXPR const vfcvt_f vfcvt_f_obj; +static CONSTEXPR const vfcvt_f vfcvt_f_obj; static CONSTEXPR const vfcvt_f vfcvt_f_frm_obj; static CONSTEXPR const vfwcvt_x vfwcvt_x_obj; static CONSTEXPR const vfwcvt_x vfwcvt_x_frm_obj; -- 2.34.1
[PATCH v2] RISC-V: Support RVV VFWCVT.XU.F.V rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFWCVT.X.F.V as the below samples.
* __riscv_vfwcvt_xu_f_v_u64m2_rm
* __riscv_vfwcvt_xu_f_v_u64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwcvt_xu_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wcvt-xu.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 2 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 1 +
.../riscv/rvv/base/float-point-wcvt-xu.c | 29 +++
4 files changed, 33 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 22640745398..6621c77c3f2 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2497,6 +2497,7 @@ static CONSTEXPR const vfcvt_f vfcvt_f_frm_obj;
static CONSTEXPR const vfwcvt_x vfwcvt_x_obj;
static CONSTEXPR const vfwcvt_x vfwcvt_x_frm_obj;
static CONSTEXPR const vfwcvt_x vfwcvt_xu_obj;
+static CONSTEXPR const vfwcvt_x
vfwcvt_xu_frm_obj;
static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_x_obj;
static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_xu_obj;
static CONSTEXPR const vfwcvt_f vfwcvt_f_obj;
@@ -2750,6 +2751,7 @@ BASE (vfcvt_f_frm)
BASE (vfwcvt_x)
BASE (vfwcvt_x_frm)
BASE (vfwcvt_xu)
+BASE (vfwcvt_xu_frm)
BASE (vfwcvt_rtz_x)
BASE (vfwcvt_rtz_xu)
BASE (vfwcvt_f)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index dd711846cbe..6565740c597 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -215,6 +215,7 @@ extern const function_base *const vfcvt_f_frm;
extern const function_base *const vfwcvt_x;
extern const function_base *const vfwcvt_x_frm;
extern const function_base *const vfwcvt_xu;
+extern const function_base *const vfwcvt_xu_frm;
extern const function_base *const vfwcvt_rtz_x;
extern const function_base *const vfwcvt_rtz_xu;
extern const function_base *const vfwcvt_f;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 4e6cc793447..22c039c8cbb 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -460,6 +460,7 @@ DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds,
u_to_wf_xu_v_ops)
DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, f_to_wf_f_v_ops)
DEF_RVV_FUNCTION (vfwcvt_x_frm, alu_frm, full_preds, f_to_wi_f_v_ops)
+DEF_RVV_FUNCTION (vfwcvt_xu_frm, alu_frm, full_preds, f_to_wu_f_v_ops)
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
DEF_RVV_FUNCTION (vfncvt_x, narrow_alu, full_preds, f_to_ni_f_w_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
new file mode 100644
index 000..29449e79b69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vuint64m2_t
+test_riscv_vfwcvt_xu_f_v_u64m2_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_xu_f_v_u64m2_rm (op1, 0, vl);
+}
+
+vuint64m2_t
+test_vfwcvt_xu_f_v_u64m2_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_xu_f_v_u64m2_rm_m (mask, op1, 1, vl);
+}
+
+vuint64m2_t
+test_riscv_vfwcvt_xu_f_v_u64m2 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_xu_f_v_u64m2 (op1, vl);
+}
+
+vuint64m2_t
+test_vfwcvt_xu_f_v_u64m2_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_xu_f_v_u64m2_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4
} } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
--
2.34.1
[PATCH v2] RISC-V: Support RVV VFWCVT.X.F.V rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFWCVT.X.F.V as the below samples.
* __riscv_vfwcvt_x_f_v_i64m2_rm
* __riscv_vfwcvt_x_f_v_i64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwcvt_x_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wcvt-x.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 9 +-
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 ++
.../riscv/rvv/base/float-point-wcvt-x.c | 29 +++
4 files changed, 40 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index c78fa8e5b62..22640745398 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1715,10 +1715,15 @@ public:
};
/* Implements vfwcvt.x. */
-template
+template
class vfwcvt_x : public function_base
{
public:
+ bool has_rounding_mode_operand_p () const override
+ {
+return FRM_OP == HAS_FRM;
+ }
+
rtx expand (function_expander ) const override
{
return e.use_exact_insn (
@@ -2490,6 +2495,7 @@ static CONSTEXPR const vfcvt_rtz_x
vfcvt_rtz_xu_obj;
static CONSTEXPR const vfcvt_f vfcvt_f_obj;
static CONSTEXPR const vfcvt_f vfcvt_f_frm_obj;
static CONSTEXPR const vfwcvt_x vfwcvt_x_obj;
+static CONSTEXPR const vfwcvt_x vfwcvt_x_frm_obj;
static CONSTEXPR const vfwcvt_x vfwcvt_xu_obj;
static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_x_obj;
static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_xu_obj;
@@ -2742,6 +2748,7 @@ BASE (vfcvt_rtz_xu)
BASE (vfcvt_f)
BASE (vfcvt_f_frm)
BASE (vfwcvt_x)
+BASE (vfwcvt_x_frm)
BASE (vfwcvt_xu)
BASE (vfwcvt_rtz_x)
BASE (vfwcvt_rtz_xu)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 08452587180..dd711846cbe 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -213,6 +213,7 @@ extern const function_base *const vfcvt_rtz_xu;
extern const function_base *const vfcvt_f;
extern const function_base *const vfcvt_f_frm;
extern const function_base *const vfwcvt_x;
+extern const function_base *const vfwcvt_x_frm;
extern const function_base *const vfwcvt_xu;
extern const function_base *const vfwcvt_rtz_x;
extern const function_base *const vfwcvt_rtz_xu;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 8dbcd946d11..4e6cc793447 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -459,6 +459,8 @@ DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds,
i_to_wf_x_v_ops)
DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, u_to_wf_xu_v_ops)
DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, f_to_wf_f_v_ops)
+DEF_RVV_FUNCTION (vfwcvt_x_frm, alu_frm, full_preds, f_to_wi_f_v_ops)
+
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
DEF_RVV_FUNCTION (vfncvt_x, narrow_alu, full_preds, f_to_ni_f_w_ops)
DEF_RVV_FUNCTION (vfncvt_xu, narrow_alu, full_preds, f_to_nu_f_w_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c
new file mode 100644
index 000..8f67ec00966
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vint64m2_t
+test_riscv_vfwcvt_x_f_v_i64m2_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_x_f_v_i64m2_rm (op1, 0, vl);
+}
+
+vint64m2_t
+test_vfwcvt_x_f_v_i64m2_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_x_f_v_i64m2_rm_m (mask, op1, 1, vl);
+}
+
+vint64m2_t
+test_riscv_vfwcvt_x_f_v_i64m2 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_x_f_v_i64m2 (op1, vl);
+}
+
+vint64m2_t
+test_vfwcvt_x_f_v_i64m2_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_x_f_v_i64m2_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfwcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4
} } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
--
2.34.1
[PATCH v2] RISC-V: Support RVV VFCVT.F.X.V and VFCVT.F.XU.V rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFCVT.F.X.V and VFCVT.F.XU.V as the below samples.
* __riscv_vfcvt_f_x_v_f32m1_rm
* __riscv_vfcvt_f_x_v_f32m1_rm_m
* __riscv_vfcvt_f_xu_v_f32m1_rm
* __riscv_vfcvt_f_xu_v_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfcvt_f_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cvt-f.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 8 +++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/rvv/base/float-point-cvt-f.c| 50 +++
4 files changed, 61 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 421f4096db8..c78fa8e5b62 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1694,9 +1694,15 @@ public:
}
};
+template
class vfcvt_f : public function_base
{
public:
+ bool has_rounding_mode_operand_p () const override
+ {
+return FRM_OP == HAS_FRM;
+ }
+
rtx expand (function_expander ) const override
{
if (e.op_info->op == OP_TYPE_x_v)
@@ -2482,6 +2488,7 @@ static CONSTEXPR const vfcvt_x vfcvt_xu_frm_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj;
static CONSTEXPR const vfcvt_f vfcvt_f_obj;
+static CONSTEXPR const vfcvt_f vfcvt_f_frm_obj;
static CONSTEXPR const vfwcvt_x vfwcvt_x_obj;
static CONSTEXPR const vfwcvt_x vfwcvt_xu_obj;
static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_x_obj;
@@ -2733,6 +2740,7 @@ BASE (vfcvt_xu_frm)
BASE (vfcvt_rtz_x)
BASE (vfcvt_rtz_xu)
BASE (vfcvt_f)
+BASE (vfcvt_f_frm)
BASE (vfwcvt_x)
BASE (vfwcvt_xu)
BASE (vfwcvt_rtz_x)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 98b61655692..08452587180 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -211,6 +211,7 @@ extern const function_base *const vfcvt_xu_frm;
extern const function_base *const vfcvt_rtz_x;
extern const function_base *const vfcvt_rtz_xu;
extern const function_base *const vfcvt_f;
+extern const function_base *const vfcvt_f_frm;
extern const function_base *const vfwcvt_x;
extern const function_base *const vfwcvt_xu;
extern const function_base *const vfwcvt_rtz_x;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 613bbe7a855..8dbcd946d11 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -447,6 +447,8 @@ DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, u_to_f_xu_v_ops)
DEF_RVV_FUNCTION (vfcvt_x_frm, alu_frm, full_preds, f_to_i_f_v_ops)
DEF_RVV_FUNCTION (vfcvt_xu_frm, alu_frm, full_preds, f_to_u_f_v_ops)
+DEF_RVV_FUNCTION (vfcvt_f_frm, alu_frm, full_preds, i_to_f_x_v_ops)
+DEF_RVV_FUNCTION (vfcvt_f_frm, alu_frm, full_preds, u_to_f_xu_v_ops)
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
DEF_RVV_FUNCTION (vfwcvt_x, alu, full_preds, f_to_wi_f_v_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
new file mode 100644
index 000..424a38ede13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+test_riscv_vfcvt_f_x_v_f32m1_rm (vint32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_f_x_v_f32m1_rm (op1, 0, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfcvt_f_x_v_f32m1_rm_m (vbool32_t mask, vint32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_f_x_v_f32m1_rm_m (mask, op1, 0, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfcvt_f_xu_v_f32m1_rm (vuint32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_f_xu_v_f32m1_rm (op1, 0, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfcvt_f_xu_v_f32m1_rm_m (vbool32_t mask, vuint32m1_t op1,
+ size_t vl) {
+ return __riscv_vfcvt_f_xu_v_f32m1_rm_m (mask, op1, 0, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfcvt_f_x_v_f32m1 (vint32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_f_x_v_f32m1 (op1, vl);
+}
+
+vfloat32m1_t
+test_vfcvt_f_x_v_f32m1_m (vbool32_t mask, vint32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_f_x_v_f32m1_m (mask, op1, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfcvt_f_xu_v_f32m1 (vuint32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_f_xu_v_f32m1
[PATCH v2] RISC-V: Support RVV VFCVT.XU.F.V rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFCVT.XU.F.V as the below samples.
* __riscv_vfcvt_xu_f_v_u32m1_rm
* __riscv_vfcvt_xu_f_v_u32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfcvt_xu_frm): New intrinsic function def..
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cvt-xu.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 2 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 1 +
.../riscv/rvv/base/float-point-cvt-xu.c | 29 +++
4 files changed, 33 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 817d2ed016a..421f4096db8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2478,6 +2478,7 @@ static CONSTEXPR const vmv_v vfmv_v_obj;
static CONSTEXPR const vfcvt_x vfcvt_x_obj;
static CONSTEXPR const vfcvt_x vfcvt_x_frm_obj;
static CONSTEXPR const vfcvt_x vfcvt_xu_obj;
+static CONSTEXPR const vfcvt_x
vfcvt_xu_frm_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj;
static CONSTEXPR const vfcvt_f vfcvt_f_obj;
@@ -2728,6 +2729,7 @@ BASE (vfmv_v)
BASE (vfcvt_x)
BASE (vfcvt_x_frm)
BASE (vfcvt_xu)
+BASE (vfcvt_xu_frm)
BASE (vfcvt_rtz_x)
BASE (vfcvt_rtz_xu)
BASE (vfcvt_f)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 50a7d7ffb6f..98b61655692 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -207,6 +207,7 @@ extern const function_base *const vfmv_v;
extern const function_base *const vfcvt_x;
extern const function_base *const vfcvt_x_frm;
extern const function_base *const vfcvt_xu;
+extern const function_base *const vfcvt_xu_frm;
extern const function_base *const vfcvt_rtz_x;
extern const function_base *const vfcvt_rtz_xu;
extern const function_base *const vfcvt_f;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 8b6a7cc49f3..613bbe7a855 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -446,6 +446,7 @@ DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, i_to_f_x_v_ops)
DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, u_to_f_xu_v_ops)
DEF_RVV_FUNCTION (vfcvt_x_frm, alu_frm, full_preds, f_to_i_f_v_ops)
+DEF_RVV_FUNCTION (vfcvt_xu_frm, alu_frm, full_preds, f_to_u_f_v_ops)
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
DEF_RVV_FUNCTION (vfwcvt_x, alu, full_preds, f_to_wi_f_v_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
new file mode 100644
index 000..bb164b2b001
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vuint32m1_t
+test_riscv_vfcvt_xu_f_v_u32m1_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_xu_f_v_u32m1_rm (op1, 0, vl);
+}
+
+vuint32m1_t
+test_vfcvt_xu_f_v_u32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_xu_f_v_u32m1_rm_m (mask, op1, 1, vl);
+}
+
+vuint32m1_t
+test_riscv_vfcvt_xu_f_vv_u32m1 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_xu_f_v_u32m1 (op1, vl);
+}
+
+vuint32m1_t
+test_vfcvt_xu_f_v_u32m1_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_xu_f_v_u32m1_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfcvt\.xu\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4
} } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
--
2.34.1
[PATCH v2] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFCVT.X.F.V as the below samples.
* __riscv_vfcvt_x_f_v_i32m1_rm
* __riscv_vfcvt_x_f_v_i32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(enum frm_op_type): New type for frm.
(BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfcvt_x_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cvt-x.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 15 +-
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 ++
.../riscv/rvv/base/float-point-cvt-x.c| 29 +++
4 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index f2124080ef9..817d2ed016a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -58,6 +58,12 @@ enum lst_type
LST_INDEXED,
};
+enum frm_op_type
+{
+ NO_FRM,
+ HAS_FRM,
+};
+
/* Helper function to fold vleff and vlsegff. */
static gimple *
fold_fault_load (gimple_folder )
@@ -1662,10 +1668,15 @@ public:
};
/* Implements vfcvt.x. */
-template
+template
class vfcvt_x : public function_base
{
public:
+ bool has_rounding_mode_operand_p () const override
+ {
+return FRM_OP == HAS_FRM;
+ }
+
rtx expand (function_expander ) const override
{
return e.use_exact_insn (code_for_pred_fcvt_x_f (UNSPEC, e.arg_mode (0)));
@@ -2465,6 +2476,7 @@ static CONSTEXPR const vfclass vfclass_obj;
static CONSTEXPR const vmerge vfmerge_obj;
static CONSTEXPR const vmv_v vfmv_v_obj;
static CONSTEXPR const vfcvt_x vfcvt_x_obj;
+static CONSTEXPR const vfcvt_x vfcvt_x_frm_obj;
static CONSTEXPR const vfcvt_x vfcvt_xu_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj;
@@ -2714,6 +2726,7 @@ BASE (vfclass)
BASE (vfmerge)
BASE (vfmv_v)
BASE (vfcvt_x)
+BASE (vfcvt_x_frm)
BASE (vfcvt_xu)
BASE (vfcvt_rtz_x)
BASE (vfcvt_rtz_xu)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 2a9381eec5e..50a7d7ffb6f 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -205,6 +205,7 @@ extern const function_base *const vfclass;
extern const function_base *const vfmerge;
extern const function_base *const vfmv_v;
extern const function_base *const vfcvt_x;
+extern const function_base *const vfcvt_x_frm;
extern const function_base *const vfcvt_xu;
extern const function_base *const vfcvt_rtz_x;
extern const function_base *const vfcvt_rtz_xu;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 34def6bb82f..8b6a7cc49f3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -445,6 +445,8 @@ DEF_RVV_FUNCTION (vfcvt_rtz_xu, alu, full_preds,
f_to_u_f_v_ops)
DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, i_to_f_x_v_ops)
DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, u_to_f_xu_v_ops)
+DEF_RVV_FUNCTION (vfcvt_x_frm, alu_frm, full_preds, f_to_i_f_v_ops)
+
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
DEF_RVV_FUNCTION (vfwcvt_x, alu, full_preds, f_to_wi_f_v_ops)
DEF_RVV_FUNCTION (vfwcvt_xu, alu, full_preds, f_to_wu_f_v_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
new file mode 100644
index 000..e090f0f97e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+test_riscv_vfcvt_x_f_vv_i32m1_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1_rm (op1, 0, vl);
+}
+
+vint32m1_t
+test_vfcvt_x_f_vv_i32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1_rm_m (mask, op1, 1, vl);
+}
+
+vint32m1_t
+test_riscv_vfcvt_x_f_vv_i32m1 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1 (op1, vl);
+}
+
+vint32m1_t
+test_vfcvt_x_f_vv_i32m1_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4 }
} */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final {
[PATCH v1] RISC-V: Support RVV VFWCVT.XU.F.V rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFWCVT.X.F.V as the below samples.
* __riscv_vfwcvt_xu_f_v_u64m2_rm
* __riscv_vfwcvt_xu_f_v_u64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(vfwcvt_xu_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwcvt_xu_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wcvt-xu.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 2 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 1 +
.../riscv/rvv/base/float-point-wcvt-xu.c | 29 +++
4 files changed, 33 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 7bd72653b9c..5acb9404d4a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2526,6 +2526,7 @@ static CONSTEXPR const vfcvt_f_frm vfcvt_f_frm_obj;
static CONSTEXPR const vfwcvt_x vfwcvt_x_obj;
static CONSTEXPR const vfwcvt_x_frm vfwcvt_x_frm_obj;
static CONSTEXPR const vfwcvt_x vfwcvt_xu_obj;
+static CONSTEXPR const vfwcvt_x_frm vfwcvt_xu_frm_obj;
static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_x_obj;
static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_xu_obj;
static CONSTEXPR const vfwcvt_f vfwcvt_f_obj;
@@ -2779,6 +2780,7 @@ BASE (vfcvt_f_frm)
BASE (vfwcvt_x)
BASE (vfwcvt_x_frm)
BASE (vfwcvt_xu)
+BASE (vfwcvt_xu_frm)
BASE (vfwcvt_rtz_x)
BASE (vfwcvt_rtz_xu)
BASE (vfwcvt_f)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index dd711846cbe..6565740c597 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -215,6 +215,7 @@ extern const function_base *const vfcvt_f_frm;
extern const function_base *const vfwcvt_x;
extern const function_base *const vfwcvt_x_frm;
extern const function_base *const vfwcvt_xu;
+extern const function_base *const vfwcvt_xu_frm;
extern const function_base *const vfwcvt_rtz_x;
extern const function_base *const vfwcvt_rtz_xu;
extern const function_base *const vfwcvt_f;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 4e6cc793447..22c039c8cbb 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -460,6 +460,7 @@ DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds,
u_to_wf_xu_v_ops)
DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, f_to_wf_f_v_ops)
DEF_RVV_FUNCTION (vfwcvt_x_frm, alu_frm, full_preds, f_to_wi_f_v_ops)
+DEF_RVV_FUNCTION (vfwcvt_xu_frm, alu_frm, full_preds, f_to_wu_f_v_ops)
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
DEF_RVV_FUNCTION (vfncvt_x, narrow_alu, full_preds, f_to_ni_f_w_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
new file mode 100644
index 000..29449e79b69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-xu.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vuint64m2_t
+test_riscv_vfwcvt_xu_f_v_u64m2_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_xu_f_v_u64m2_rm (op1, 0, vl);
+}
+
+vuint64m2_t
+test_vfwcvt_xu_f_v_u64m2_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_xu_f_v_u64m2_rm_m (mask, op1, 1, vl);
+}
+
+vuint64m2_t
+test_riscv_vfwcvt_xu_f_v_u64m2 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_xu_f_v_u64m2 (op1, vl);
+}
+
+vuint64m2_t
+test_vfwcvt_xu_f_v_u64m2_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_xu_f_v_u64m2_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfwcvt\.xu\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4
} } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
--
2.34.1
[PATCH v1] RISC-V: Support RVV VFWCVT.X.F.V rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFWCVT.X.F.V as the below samples.
* __riscv_vfwcvt_x_f_v_i64m2_rm
* __riscv_vfwcvt_x_f_v_i64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfwcvt_x_frm): New class for frm.
(vfwcvt_x_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwcvt_x_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wcvt-x.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 18
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 ++
.../riscv/rvv/base/float-point-wcvt-x.c | 29 +++
4 files changed, 50 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 3c2bc13b586..7bd72653b9c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -695,6 +695,22 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfwcvt_x
+*/
+template
+class vfwcvt_x_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ rtx expand (function_expander ) const override
+ {
+return e.use_exact_insn (
+ code_for_pred_widen_fcvt_x_f (UNSPEC, e.vector_mode ()));
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2508,6 +2524,7 @@ static CONSTEXPR const vfcvt_rtz_x
vfcvt_rtz_xu_obj;
static CONSTEXPR const vfcvt_f vfcvt_f_obj;
static CONSTEXPR const vfcvt_f_frm vfcvt_f_frm_obj;
static CONSTEXPR const vfwcvt_x vfwcvt_x_obj;
+static CONSTEXPR const vfwcvt_x_frm vfwcvt_x_frm_obj;
static CONSTEXPR const vfwcvt_x vfwcvt_xu_obj;
static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_x_obj;
static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_xu_obj;
@@ -2760,6 +2777,7 @@ BASE (vfcvt_rtz_xu)
BASE (vfcvt_f)
BASE (vfcvt_f_frm)
BASE (vfwcvt_x)
+BASE (vfwcvt_x_frm)
BASE (vfwcvt_xu)
BASE (vfwcvt_rtz_x)
BASE (vfwcvt_rtz_xu)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 08452587180..dd711846cbe 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -213,6 +213,7 @@ extern const function_base *const vfcvt_rtz_xu;
extern const function_base *const vfcvt_f;
extern const function_base *const vfcvt_f_frm;
extern const function_base *const vfwcvt_x;
+extern const function_base *const vfwcvt_x_frm;
extern const function_base *const vfwcvt_xu;
extern const function_base *const vfwcvt_rtz_x;
extern const function_base *const vfwcvt_rtz_xu;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 8dbcd946d11..4e6cc793447 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -459,6 +459,8 @@ DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds,
i_to_wf_x_v_ops)
DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, u_to_wf_xu_v_ops)
DEF_RVV_FUNCTION (vfwcvt_f, alu, full_preds, f_to_wf_f_v_ops)
+DEF_RVV_FUNCTION (vfwcvt_x_frm, alu_frm, full_preds, f_to_wi_f_v_ops)
+
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
DEF_RVV_FUNCTION (vfncvt_x, narrow_alu, full_preds, f_to_ni_f_w_ops)
DEF_RVV_FUNCTION (vfncvt_xu, narrow_alu, full_preds, f_to_nu_f_w_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c
new file mode 100644
index 000..8f67ec00966
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wcvt-x.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vint64m2_t
+test_riscv_vfwcvt_x_f_v_i64m2_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_x_f_v_i64m2_rm (op1, 0, vl);
+}
+
+vint64m2_t
+test_vfwcvt_x_f_v_i64m2_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_x_f_v_i64m2_rm_m (mask, op1, 1, vl);
+}
+
+vint64m2_t
+test_riscv_vfwcvt_x_f_v_i64m2 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_x_f_v_i64m2 (op1, vl);
+}
+
+vint64m2_t
+test_vfwcvt_x_f_v_i64m2_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfwcvt_x_f_v_i64m2_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfwcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4
} } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
[PATCH v1] RISC-V: Support RVV VFCVT.F.X.V and VFCVT.F.XU.V rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFCVT.F.X.V and VFCVT.F.XU.V as the below samples.
* __riscv_vfcvt_f_x_v_f32m1_rm
* __riscv_vfcvt_f_x_v_f32m1_rm_m
* __riscv_vfcvt_f_xu_v_f32m1_rm
* __riscv_vfcvt_f_xu_v_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfcvt_f_frm): New class for frm.
(vfcvt_f_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfcvt_f_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cvt-f.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 22
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/rvv/base/float-point-cvt-f.c| 50 +++
4 files changed, 75 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 8eb89a05580..3c2bc13b586 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -675,6 +675,26 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfcvt_f
+*/
+class vfcvt_f_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_x_v)
+ return e.use_exact_insn (code_for_pred (FLOAT, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_xu_v)
+ return e.use_exact_insn (
+ code_for_pred (UNSIGNED_FLOAT, e.vector_mode ()));
+
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2486,6 +2506,7 @@ static CONSTEXPR const vfcvt_x_frm
vfcvt_xu_frm_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj;
static CONSTEXPR const vfcvt_f vfcvt_f_obj;
+static CONSTEXPR const vfcvt_f_frm vfcvt_f_frm_obj;
static CONSTEXPR const vfwcvt_x vfwcvt_x_obj;
static CONSTEXPR const vfwcvt_x vfwcvt_xu_obj;
static CONSTEXPR const vfwcvt_rtz_x vfwcvt_rtz_x_obj;
@@ -2737,6 +2758,7 @@ BASE (vfcvt_xu_frm)
BASE (vfcvt_rtz_x)
BASE (vfcvt_rtz_xu)
BASE (vfcvt_f)
+BASE (vfcvt_f_frm)
BASE (vfwcvt_x)
BASE (vfwcvt_xu)
BASE (vfwcvt_rtz_x)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 98b61655692..08452587180 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -211,6 +211,7 @@ extern const function_base *const vfcvt_xu_frm;
extern const function_base *const vfcvt_rtz_x;
extern const function_base *const vfcvt_rtz_xu;
extern const function_base *const vfcvt_f;
+extern const function_base *const vfcvt_f_frm;
extern const function_base *const vfwcvt_x;
extern const function_base *const vfwcvt_xu;
extern const function_base *const vfwcvt_rtz_x;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 613bbe7a855..8dbcd946d11 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -447,6 +447,8 @@ DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, u_to_f_xu_v_ops)
DEF_RVV_FUNCTION (vfcvt_x_frm, alu_frm, full_preds, f_to_i_f_v_ops)
DEF_RVV_FUNCTION (vfcvt_xu_frm, alu_frm, full_preds, f_to_u_f_v_ops)
+DEF_RVV_FUNCTION (vfcvt_f_frm, alu_frm, full_preds, i_to_f_x_v_ops)
+DEF_RVV_FUNCTION (vfcvt_f_frm, alu_frm, full_preds, u_to_f_xu_v_ops)
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
DEF_RVV_FUNCTION (vfwcvt_x, alu, full_preds, f_to_wi_f_v_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
new file mode 100644
index 000..424a38ede13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+test_riscv_vfcvt_f_x_v_f32m1_rm (vint32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_f_x_v_f32m1_rm (op1, 0, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfcvt_f_x_v_f32m1_rm_m (vbool32_t mask, vint32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_f_x_v_f32m1_rm_m (mask, op1, 0, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfcvt_f_xu_v_f32m1_rm (vuint32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_f_xu_v_f32m1_rm (op1, 0, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfcvt_f_xu_v_f32m1_rm_m (vbool32_t mask, vuint32m1_t op1,
+ size_t vl) {
+
[PATCH v1] RISC-V: Support RVV VFCVT.XU.F.V rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFCVT.XU.F.V as the below samples.
* __riscv_vfcvt_xu_f_v_u32m1_rm
* __riscv_vfcvt_xu_f_v_u32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(vfcvt_xu_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfcvt_xu_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cvt-xu.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 2 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 1 +
.../riscv/rvv/base/float-point-cvt-xu.c | 29 +++
4 files changed, 33 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 754a53efd3d..8eb89a05580 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2482,6 +2482,7 @@ static CONSTEXPR const vmv_v vfmv_v_obj;
static CONSTEXPR const vfcvt_x vfcvt_x_obj;
static CONSTEXPR const vfcvt_x_frm vfcvt_x_frm_obj;
static CONSTEXPR const vfcvt_x vfcvt_xu_obj;
+static CONSTEXPR const vfcvt_x_frm vfcvt_xu_frm_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj;
static CONSTEXPR const vfcvt_f vfcvt_f_obj;
@@ -2732,6 +2733,7 @@ BASE (vfmv_v)
BASE (vfcvt_x)
BASE (vfcvt_x_frm)
BASE (vfcvt_xu)
+BASE (vfcvt_xu_frm)
BASE (vfcvt_rtz_x)
BASE (vfcvt_rtz_xu)
BASE (vfcvt_f)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 50a7d7ffb6f..98b61655692 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -207,6 +207,7 @@ extern const function_base *const vfmv_v;
extern const function_base *const vfcvt_x;
extern const function_base *const vfcvt_x_frm;
extern const function_base *const vfcvt_xu;
+extern const function_base *const vfcvt_xu_frm;
extern const function_base *const vfcvt_rtz_x;
extern const function_base *const vfcvt_rtz_xu;
extern const function_base *const vfcvt_f;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 8b6a7cc49f3..613bbe7a855 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -446,6 +446,7 @@ DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, i_to_f_x_v_ops)
DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, u_to_f_xu_v_ops)
DEF_RVV_FUNCTION (vfcvt_x_frm, alu_frm, full_preds, f_to_i_f_v_ops)
+DEF_RVV_FUNCTION (vfcvt_xu_frm, alu_frm, full_preds, f_to_u_f_v_ops)
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
DEF_RVV_FUNCTION (vfwcvt_x, alu, full_preds, f_to_wi_f_v_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
new file mode 100644
index 000..bb164b2b001
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vuint32m1_t
+test_riscv_vfcvt_xu_f_v_u32m1_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_xu_f_v_u32m1_rm (op1, 0, vl);
+}
+
+vuint32m1_t
+test_vfcvt_xu_f_v_u32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_xu_f_v_u32m1_rm_m (mask, op1, 1, vl);
+}
+
+vuint32m1_t
+test_riscv_vfcvt_xu_f_vv_u32m1 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_xu_f_v_u32m1 (op1, vl);
+}
+
+vuint32m1_t
+test_vfcvt_xu_f_v_u32m1_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_xu_f_v_u32m1_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfcvt\.xu\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4
} } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
--
2.34.1
[PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFCVT.X.F.V as the below samples.
* __riscv_vfcvt_x_f_v_i32m1_rm
* __riscv_vfcvt_x_f_v_i32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfcvt_x_frm): New class for frm.
(vfcvt_x_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfcvt_x_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cvt-x.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 17 +++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 ++
.../riscv/rvv/base/float-point-cvt-x.c| 29 +++
4 files changed, 49 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index f2124080ef9..754a53efd3d 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -660,6 +660,21 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfcvt_x
+*/
+template
+class vfcvt_x_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ rtx expand (function_expander ) const override
+ {
+return e.use_exact_insn (code_for_pred_fcvt_x_f (UNSPEC, e.arg_mode (0)));
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2465,6 +2480,7 @@ static CONSTEXPR const vfclass vfclass_obj;
static CONSTEXPR const vmerge vfmerge_obj;
static CONSTEXPR const vmv_v vfmv_v_obj;
static CONSTEXPR const vfcvt_x vfcvt_x_obj;
+static CONSTEXPR const vfcvt_x_frm vfcvt_x_frm_obj;
static CONSTEXPR const vfcvt_x vfcvt_xu_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj;
@@ -2714,6 +2730,7 @@ BASE (vfclass)
BASE (vfmerge)
BASE (vfmv_v)
BASE (vfcvt_x)
+BASE (vfcvt_x_frm)
BASE (vfcvt_xu)
BASE (vfcvt_rtz_x)
BASE (vfcvt_rtz_xu)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 2a9381eec5e..50a7d7ffb6f 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -205,6 +205,7 @@ extern const function_base *const vfclass;
extern const function_base *const vfmerge;
extern const function_base *const vfmv_v;
extern const function_base *const vfcvt_x;
+extern const function_base *const vfcvt_x_frm;
extern const function_base *const vfcvt_xu;
extern const function_base *const vfcvt_rtz_x;
extern const function_base *const vfcvt_rtz_xu;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 34def6bb82f..8b6a7cc49f3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -445,6 +445,8 @@ DEF_RVV_FUNCTION (vfcvt_rtz_xu, alu, full_preds,
f_to_u_f_v_ops)
DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, i_to_f_x_v_ops)
DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, u_to_f_xu_v_ops)
+DEF_RVV_FUNCTION (vfcvt_x_frm, alu_frm, full_preds, f_to_i_f_v_ops)
+
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
DEF_RVV_FUNCTION (vfwcvt_x, alu, full_preds, f_to_wi_f_v_ops)
DEF_RVV_FUNCTION (vfwcvt_xu, alu, full_preds, f_to_wu_f_v_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
new file mode 100644
index 000..e090f0f97e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+test_riscv_vfcvt_x_f_vv_i32m1_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1_rm (op1, 0, vl);
+}
+
+vint32m1_t
+test_vfcvt_x_f_vv_i32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1_rm_m (mask, op1, 1, vl);
+}
+
+vint32m1_t
+test_riscv_vfcvt_x_f_vv_i32m1 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1 (op1, vl);
+}
+
+vint32m1_t
+test_vfcvt_x_f_vv_i32m1_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4 }
} */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
--
2.34.1
[PATCH v2] RISC-V: Support RVV VFREC7 rounding mode intrinsic API
From: Pan Li
Update in v2:
1. Remove the template of vfrec7 frm class.
2. Update the vfrec7_frm_obj declaration.
Original logs:
This patch would like to support the rounding mode API for the
VFREC7 as the below samples.
* __riscv_vfrec7_v_f32m1_rm
* __riscv_vfrec7_v_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfrec7_frm): New class for frm.
(vfrec7_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfrec7_frm): New intrinsic function definition.
* config/riscv/vector-iterators.md
(VFMISC): Remove VFREC7.
(misc_op): Ditto.
(float_insn_type): Ditto.
(VFMISC_FRM): New int iterator.
(misc_frm_op): New op for frm.
(float_frm_insn_type): New type for frm.
* config/riscv/vector.md (@pred_):
New pattern for misc frm.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-rec7.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 16 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 ++
gcc/config/riscv/vector-iterators.md | 12 +--
gcc/config/riscv/vector.md| 23 ++
.../riscv/rvv/base/float-point-rec7.c | 31 +++
6 files changed, 82 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-rec7.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 2074dac0f16..f2124080ef9 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -646,6 +646,20 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfrec7
+*/
+class vfrec7_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ rtx expand (function_expander ) const override
+ {
+return e.use_exact_insn (code_for_pred (UNSPEC_VFREC7, e.vector_mode ()));
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2433,6 +2447,7 @@ static CONSTEXPR const unop vfsqrt_obj;
static CONSTEXPR const unop_frm vfsqrt_frm_obj;
static CONSTEXPR const float_misc vfrsqrt7_obj;
static CONSTEXPR const float_misc vfrec7_obj;
+static CONSTEXPR const vfrec7_frm vfrec7_frm_obj;
static CONSTEXPR const binop vfmin_obj;
static CONSTEXPR const binop vfmax_obj;
static CONSTEXPR const float_misc vfsgnj_obj;
@@ -2681,6 +2696,7 @@ BASE (vfsqrt)
BASE (vfsqrt_frm)
BASE (vfrsqrt7)
BASE (vfrec7)
+BASE (vfrec7_frm)
BASE (vfmin)
BASE (vfmax)
BASE (vfsgnj)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 5c91381bd4c..2a9381eec5e 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -187,6 +187,7 @@ extern const function_base *const vfsqrt;
extern const function_base *const vfsqrt_frm;
extern const function_base *const vfrsqrt7;
extern const function_base *const vfrec7;
+extern const function_base *const vfrec7_frm;
extern const function_base *const vfmin;
extern const function_base *const vfmax;
extern const function_base *const vfsgnj;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index a821aca6a4b..34def6bb82f 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -396,6 +396,8 @@ DEF_RVV_FUNCTION (vfrsqrt7, alu, full_preds, f_v_ops)
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
DEF_RVV_FUNCTION (vfrec7, alu, full_preds, f_v_ops)
+DEF_RVV_FUNCTION (vfrec7_frm, alu_frm, full_preds, f_v_ops)
+
// 13.11. Vector Floating-Point MIN/MAX Instructions
DEF_RVV_FUNCTION (vfmin, alu, full_preds, f_vvv_ops)
DEF_RVV_FUNCTION (vfmin, alu, full_preds, f_vvf_ops)
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 30808ceb241..9dd611e254b 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -1867,7 +1867,9 @@ (define_int_iterator VSAT_SHIFT_OP [UNSPEC_VSSRL
UNSPEC_VSSRA])
(define_int_iterator VMISC [UNSPEC_VMSBF UNSPEC_VMSIF UNSPEC_VMSOF])
-(define_int_iterator VFMISC [UNSPEC_VFRSQRT7 UNSPEC_VFREC7])
+(define_int_iterator VFMISC [UNSPEC_VFRSQRT7])
+
+(define_int_iterator VFMISC_FRM [UNSPEC_VFREC7])
(define_int_iterator VFCVTS [UNSPEC_VFCVT UNSPEC_UNSIGNED_VFCVT])
@@ -1890,9 +1892,13 @@ (define_int_attr sat_insn_type [(UNSPEC_VAADDU "vaalu")
(UNSPEC_VAADD "vaalu")
(UNSPEC_VNCLIPU "vnclip")])
(define_int_attr misc_op [(UNSPEC_VMSBF "sbf") (UNSPEC_VMSIF
[PATCH v1] RISC-V: Support RVV VFREC7 rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFREC7 as the below samples.
* __riscv_vfrec7_v_f32m1_rm
* __riscv_vfrec7_v_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfrec7_frm): New class for frm.
(vfrec7_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfrec7_frm): New intrinsic function definition.
* config/riscv/vector-iterators.md
(VFMISC): Remove VFREC7.
(misc_op): Ditto.
(float_insn_type): Ditto.
(VFMISC_FRM): New int iterator.
(misc_frm_op): New op for frm.
(float_frm_insn_type): New type for frm.
* config/riscv/vector.md (@pred_):
New pattern for misc frm.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-rec7.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 17 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 ++
gcc/config/riscv/vector-iterators.md | 12 +--
gcc/config/riscv/vector.md| 23 ++
.../riscv/rvv/base/float-point-rec7.c | 31 +++
6 files changed, 83 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-rec7.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 2074dac0f16..249ac4e68cd 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -646,6 +646,21 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfrec7
+*/
+template
+class vfrec7_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ rtx expand (function_expander ) const override
+ {
+return e.use_exact_insn (code_for_pred (UNSPEC, e.vector_mode ()));
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2433,6 +2448,7 @@ static CONSTEXPR const unop vfsqrt_obj;
static CONSTEXPR const unop_frm vfsqrt_frm_obj;
static CONSTEXPR const float_misc vfrsqrt7_obj;
static CONSTEXPR const float_misc vfrec7_obj;
+static CONSTEXPR const vfrec7_frm vfrec7_frm_obj;
static CONSTEXPR const binop vfmin_obj;
static CONSTEXPR const binop vfmax_obj;
static CONSTEXPR const float_misc vfsgnj_obj;
@@ -2681,6 +2697,7 @@ BASE (vfsqrt)
BASE (vfsqrt_frm)
BASE (vfrsqrt7)
BASE (vfrec7)
+BASE (vfrec7_frm)
BASE (vfmin)
BASE (vfmax)
BASE (vfsgnj)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 5c91381bd4c..2a9381eec5e 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -187,6 +187,7 @@ extern const function_base *const vfsqrt;
extern const function_base *const vfsqrt_frm;
extern const function_base *const vfrsqrt7;
extern const function_base *const vfrec7;
+extern const function_base *const vfrec7_frm;
extern const function_base *const vfmin;
extern const function_base *const vfmax;
extern const function_base *const vfsgnj;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index a821aca6a4b..34def6bb82f 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -396,6 +396,8 @@ DEF_RVV_FUNCTION (vfrsqrt7, alu, full_preds, f_v_ops)
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
DEF_RVV_FUNCTION (vfrec7, alu, full_preds, f_v_ops)
+DEF_RVV_FUNCTION (vfrec7_frm, alu_frm, full_preds, f_v_ops)
+
// 13.11. Vector Floating-Point MIN/MAX Instructions
DEF_RVV_FUNCTION (vfmin, alu, full_preds, f_vvv_ops)
DEF_RVV_FUNCTION (vfmin, alu, full_preds, f_vvf_ops)
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 30808ceb241..9dd611e254b 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -1867,7 +1867,9 @@ (define_int_iterator VSAT_SHIFT_OP [UNSPEC_VSSRL
UNSPEC_VSSRA])
(define_int_iterator VMISC [UNSPEC_VMSBF UNSPEC_VMSIF UNSPEC_VMSOF])
-(define_int_iterator VFMISC [UNSPEC_VFRSQRT7 UNSPEC_VFREC7])
+(define_int_iterator VFMISC [UNSPEC_VFRSQRT7])
+
+(define_int_iterator VFMISC_FRM [UNSPEC_VFREC7])
(define_int_iterator VFCVTS [UNSPEC_VFCVT UNSPEC_UNSIGNED_VFCVT])
@@ -1890,9 +1892,13 @@ (define_int_attr sat_insn_type [(UNSPEC_VAADDU "vaalu")
(UNSPEC_VAADD "vaalu")
(UNSPEC_VNCLIPU "vnclip")])
(define_int_attr misc_op [(UNSPEC_VMSBF "sbf") (UNSPEC_VMSIF "sif")
(UNSPEC_VMSOF "sof")
- (UNSPEC_VFRSQRT7 "rsqrt7") (UNSPEC_VFREC7 "rec7")])
+
[PATCH v1] RISC-V: Support RVV VFSQRT rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFSQRT as the below samples.
* __riscv_vfsqrt_v_f32m1_rm
* __riscv_vfsqrt_v_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class unop_frm): New class for frm.
(vfsqrt_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfsqrt_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-sqrt.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 17 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 ++
.../riscv/rvv/base/float-point-sqrt.c | 31 +++
4 files changed, 51 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-sqrt.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index b458560a040..2074dac0f16 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -631,6 +631,21 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfsqrt
+*/
+template
+class unop_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ rtx expand (function_expander ) const override
+ {
+return e.use_exact_insn (code_for_pred (CODE, e.vector_mode ()));
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2415,6 +2430,7 @@ static CONSTEXPR const vfwmsac_frm vfwmsac_frm_obj;
static CONSTEXPR const vfwnmsac vfwnmsac_obj;
static CONSTEXPR const vfwnmsac_frm vfwnmsac_frm_obj;
static CONSTEXPR const unop vfsqrt_obj;
+static CONSTEXPR const unop_frm vfsqrt_frm_obj;
static CONSTEXPR const float_misc vfrsqrt7_obj;
static CONSTEXPR const float_misc vfrec7_obj;
static CONSTEXPR const binop vfmin_obj;
@@ -2662,6 +2678,7 @@ BASE (vfwmsac_frm)
BASE (vfwnmsac)
BASE (vfwnmsac_frm)
BASE (vfsqrt)
+BASE (vfsqrt_frm)
BASE (vfrsqrt7)
BASE (vfrec7)
BASE (vfmin)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 85e8b9a3769..5c91381bd4c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -184,6 +184,7 @@ extern const function_base *const vfwmsac_frm;
extern const function_base *const vfwnmsac;
extern const function_base *const vfwnmsac_frm;
extern const function_base *const vfsqrt;
+extern const function_base *const vfsqrt_frm;
extern const function_base *const vfrsqrt7;
extern const function_base *const vfrec7;
extern const function_base *const vfmin;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 7e2a4ab2969..a821aca6a4b 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -388,6 +388,8 @@ DEF_RVV_FUNCTION (vfwnmsac_frm, alu_frm, full_preds,
f_wwfv_ops)
// 13.8. Vector Floating-Point Square-Root Instruction
DEF_RVV_FUNCTION (vfsqrt, alu, full_preds, f_v_ops)
+DEF_RVV_FUNCTION (vfsqrt_frm, alu_frm, full_preds, f_v_ops)
+
// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
DEF_RVV_FUNCTION (vfrsqrt7, alu, full_preds, f_v_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-sqrt.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-sqrt.c
new file mode 100644
index 000..afd1fb2b8f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-sqrt.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfsqrt_vv_f32m1_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfsqrt_v_f32m1_rm (op1, 0, vl);
+}
+
+vfloat32m1_t
+test_vfsqrt_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfsqrt_v_f32m1_rm_m (mask, op1, 1, vl);
+}
+
+vfloat32m1_t
+test_riscv_vfsqrt_vv_f32m1 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfsqrt_v_f32m1 (op1, vl);
+}
+
+vfloat32m1_t
+test_vfsqrt_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfsqrt_v_f32m1_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfsqrt\.v\s+v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
--
2.34.1
[PATCH v1] RISC-V: Support RVV VFWNMSAC rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFWNMSAC as the below samples.
* __riscv_vfwnmsac_vv_f64m2_rm
* __riscv_vfwnmsac_vv_f64m2_rm_m
* __riscv_vfwnmsac_vf_f64m2_rm
* __riscv_vfwnmsac_vf_f64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfwnmsac_frm): New class for frm.
(vfwnmsac_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwnmsac_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wnmsac.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 25 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/rvv/base/float-point-wnmsac.c | 47 +++
4 files changed, 75 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmsac.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 5a5da903cb2..b458560a040 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -608,6 +608,29 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfwnmsac
+*/
+class vfwnmsac_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_widen_ternop_insn (
+ code_for_pred_widen_mul_neg_scalar (PLUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_widen_ternop_insn (
+ code_for_pred_widen_mul_neg (PLUS, e.vector_mode ()));
+
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2390,6 +2413,7 @@ static CONSTEXPR const vfwnmacc_frm vfwnmacc_frm_obj;
static CONSTEXPR const vfwmsac vfwmsac_obj;
static CONSTEXPR const vfwmsac_frm vfwmsac_frm_obj;
static CONSTEXPR const vfwnmsac vfwnmsac_obj;
+static CONSTEXPR const vfwnmsac_frm vfwnmsac_frm_obj;
static CONSTEXPR const unop vfsqrt_obj;
static CONSTEXPR const float_misc vfrsqrt7_obj;
static CONSTEXPR const float_misc vfrec7_obj;
@@ -2636,6 +2660,7 @@ BASE (vfwnmacc_frm)
BASE (vfwmsac)
BASE (vfwmsac_frm)
BASE (vfwnmsac)
+BASE (vfwnmsac_frm)
BASE (vfsqrt)
BASE (vfrsqrt7)
BASE (vfrec7)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 09356dd7ac8..85e8b9a3769 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -182,6 +182,7 @@ extern const function_base *const vfwnmacc_frm;
extern const function_base *const vfwmsac;
extern const function_base *const vfwmsac_frm;
extern const function_base *const vfwnmsac;
+extern const function_base *const vfwnmsac_frm;
extern const function_base *const vfsqrt;
extern const function_base *const vfrsqrt7;
extern const function_base *const vfrec7;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index e2a79607d04..7e2a4ab2969 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -382,6 +382,8 @@ DEF_RVV_FUNCTION (vfwnmacc_frm, alu_frm, full_preds,
f_wwvv_ops)
DEF_RVV_FUNCTION (vfwnmacc_frm, alu_frm, full_preds, f_wwfv_ops)
DEF_RVV_FUNCTION (vfwmsac_frm, alu_frm, full_preds, f_wwvv_ops)
DEF_RVV_FUNCTION (vfwmsac_frm, alu_frm, full_preds, f_wwfv_ops)
+DEF_RVV_FUNCTION (vfwnmsac_frm, alu_frm, full_preds, f_wwvv_ops)
+DEF_RVV_FUNCTION (vfwnmsac_frm, alu_frm, full_preds, f_wwfv_ops)
// 13.8. Vector Floating-Point Square-Root Instruction
DEF_RVV_FUNCTION (vfsqrt, alu, full_preds, f_v_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmsac.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmsac.c
new file mode 100644
index 000..13eb306313c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmsac.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat64m2_t
+test_vfwnmsac_vv_f32m1_rm (vfloat64m2_t vd, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfwnmsac_vv_f64m2_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat64m2_t
+test_vfwnmsac_vv_f32m1_rm_m (vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t op1,
+vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfwnmsac_vv_f64m2_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat64m2_t
[PATCH v1] RISC-V: Support RVV VFWMSAC rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFWMSAC as the below samples.
* __riscv_vfwmsac_vv_f64m2_rm
* __riscv_vfwmsac_vv_f64m2_rm_m
* __riscv_vfwmsac_vf_f64m2_rm
* __riscv_vfwmsac_vf_f64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfwmsac_frm): New class for frm.
(vfwmsac_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwmsac_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wmsac.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 25 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/rvv/base/float-point-wmsac.c| 47 +++
4 files changed, 75 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wmsac.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 4a7f2b8e3e9..5a5da903cb2 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -585,6 +585,29 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfwmsac
+*/
+class vfwmsac_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_widen_ternop_insn (
+ code_for_pred_widen_mul_scalar (MINUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_widen_ternop_insn (
+ code_for_pred_widen_mul (MINUS, e.vector_mode ()));
+
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2365,6 +2388,7 @@ static CONSTEXPR const vfwmacc_frm vfwmacc_frm_obj;
static CONSTEXPR const vfwnmacc vfwnmacc_obj;
static CONSTEXPR const vfwnmacc_frm vfwnmacc_frm_obj;
static CONSTEXPR const vfwmsac vfwmsac_obj;
+static CONSTEXPR const vfwmsac_frm vfwmsac_frm_obj;
static CONSTEXPR const vfwnmsac vfwnmsac_obj;
static CONSTEXPR const unop vfsqrt_obj;
static CONSTEXPR const float_misc vfrsqrt7_obj;
@@ -2610,6 +2634,7 @@ BASE (vfwmacc_frm)
BASE (vfwnmacc)
BASE (vfwnmacc_frm)
BASE (vfwmsac)
+BASE (vfwmsac_frm)
BASE (vfwnmsac)
BASE (vfsqrt)
BASE (vfrsqrt7)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 27c7deb4ec2..09356dd7ac8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -180,6 +180,7 @@ extern const function_base *const vfwmacc_frm;
extern const function_base *const vfwnmacc;
extern const function_base *const vfwnmacc_frm;
extern const function_base *const vfwmsac;
+extern const function_base *const vfwmsac_frm;
extern const function_base *const vfwnmsac;
extern const function_base *const vfsqrt;
extern const function_base *const vfrsqrt7;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 481c3b899f2..e2a79607d04 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -380,6 +380,8 @@ DEF_RVV_FUNCTION (vfwmacc_frm, alu_frm, full_preds,
f_wwvv_ops)
DEF_RVV_FUNCTION (vfwmacc_frm, alu_frm, full_preds, f_wwfv_ops)
DEF_RVV_FUNCTION (vfwnmacc_frm, alu_frm, full_preds, f_wwvv_ops)
DEF_RVV_FUNCTION (vfwnmacc_frm, alu_frm, full_preds, f_wwfv_ops)
+DEF_RVV_FUNCTION (vfwmsac_frm, alu_frm, full_preds, f_wwvv_ops)
+DEF_RVV_FUNCTION (vfwmsac_frm, alu_frm, full_preds, f_wwfv_ops)
// 13.8. Vector Floating-Point Square-Root Instruction
DEF_RVV_FUNCTION (vfsqrt, alu, full_preds, f_v_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wmsac.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wmsac.c
new file mode 100644
index 000..886a0b13695
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wmsac.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat64m2_t
+test_vfwmsac_vv_f32m1_rm (vfloat64m2_t vd, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfwmsac_vv_f64m2_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat64m2_t
+test_vfwmsac_vv_f32m1_rm_m (vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfwmsac_vv_f64m2_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat64m2_t
+test_vfwmsac_vf_f32m1_rm
[PATCH v1] RISC-V: Support RVV VFWNMACC rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFWNMACC as the below samples.
* __riscv_vfwnmacc_vv_f64m2_rm
* __riscv_vfwnmacc_vv_f64m2_rm_m
* __riscv_vfwnmacc_vf_f64m2_rm
* __riscv_vfwnmacc_vf_f64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfwnmacc_frm): New class for frm.
(vfwnmacc_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwnmacc_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-wnmacc.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 25 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/rvv/base/float-point-wnmacc.c | 47 +++
4 files changed, 75 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index e84d6d1d047..4a7f2b8e3e9 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -562,6 +562,29 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfwnmacc
+*/
+class vfwnmacc_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_widen_ternop_insn (
+ code_for_pred_widen_mul_neg_scalar (MINUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_widen_ternop_insn (
+ code_for_pred_widen_mul_neg (MINUS, e.vector_mode ()));
+
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2340,6 +2363,7 @@ static CONSTEXPR const vfmsub_frm vfmsub_frm_obj;
static CONSTEXPR const vfwmacc vfwmacc_obj;
static CONSTEXPR const vfwmacc_frm vfwmacc_frm_obj;
static CONSTEXPR const vfwnmacc vfwnmacc_obj;
+static CONSTEXPR const vfwnmacc_frm vfwnmacc_frm_obj;
static CONSTEXPR const vfwmsac vfwmsac_obj;
static CONSTEXPR const vfwnmsac vfwnmsac_obj;
static CONSTEXPR const unop vfsqrt_obj;
@@ -2584,6 +2608,7 @@ BASE (vfmsub_frm)
BASE (vfwmacc)
BASE (vfwmacc_frm)
BASE (vfwnmacc)
+BASE (vfwnmacc_frm)
BASE (vfwmsac)
BASE (vfwnmsac)
BASE (vfsqrt)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index acbc7d42fbe..27c7deb4ec2 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -178,6 +178,7 @@ extern const function_base *const vfmsub_frm;
extern const function_base *const vfwmacc;
extern const function_base *const vfwmacc_frm;
extern const function_base *const vfwnmacc;
+extern const function_base *const vfwnmacc_frm;
extern const function_base *const vfwmsac;
extern const function_base *const vfwnmsac;
extern const function_base *const vfsqrt;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 0b73a5bcbc5..481c3b899f2 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -378,6 +378,8 @@ DEF_RVV_FUNCTION (vfwnmsac, alu, full_preds, f_wwfv_ops)
DEF_RVV_FUNCTION (vfwmacc_frm, alu_frm, full_preds, f_wwvv_ops)
DEF_RVV_FUNCTION (vfwmacc_frm, alu_frm, full_preds, f_wwfv_ops)
+DEF_RVV_FUNCTION (vfwnmacc_frm, alu_frm, full_preds, f_wwvv_ops)
+DEF_RVV_FUNCTION (vfwnmacc_frm, alu_frm, full_preds, f_wwfv_ops)
// 13.8. Vector Floating-Point Square-Root Instruction
DEF_RVV_FUNCTION (vfsqrt, alu, full_preds, f_v_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c
new file mode 100644
index 000..2602289ec88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wnmacc.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat64m2_t
+test_vfwnmacc_vv_f32m1_rm (vfloat64m2_t vd, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfwnmacc_vv_f64m2_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat64m2_t
+test_vfwnmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t op1,
+vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfwnmacc_vv_f64m2_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat64m2_t
+test_vfwnmacc_vf_f32m1_rm (vfloat64m2_t vd, float32_t op1, vfloat32m1_t op2,
+
[PATCH v1] RISC-V: Support RVV VFWMACC rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFWMACC as the below samples.
* __riscv_vfwmacc_vv_f64m2_rm
* __riscv_vfwmacc_vv_f64m2_rm_m
* __riscv_vfwmacc_vf_f64m2_rm
* __riscv_vfwmacc_vf_f64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfwmacc_frm): New class for vfwmacc frm.
(vfwmacc_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwmacc_frm): Function definition for vfwmacc.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_widen_ternop_insn): Add frm support.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-fwmacc.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 25 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 3 ++
gcc/config/riscv/riscv-vector-builtins.cc | 22 +++--
.../riscv/rvv/base/float-point-fwmacc.c | 47 +++
5 files changed, 93 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-fwmacc.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index e14e9aa7809..e84d6d1d047 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -539,6 +539,29 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfwmacc
+*/
+class vfwmacc_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_widen_ternop_insn (
+ code_for_pred_widen_mul_scalar (PLUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_widen_ternop_insn (
+ code_for_pred_widen_mul (PLUS, e.vector_mode ()));
+
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2315,6 +2338,7 @@ static CONSTEXPR const vfnmadd_frm vfnmadd_frm_obj;
static CONSTEXPR const vfmsub vfmsub_obj;
static CONSTEXPR const vfmsub_frm vfmsub_frm_obj;
static CONSTEXPR const vfwmacc vfwmacc_obj;
+static CONSTEXPR const vfwmacc_frm vfwmacc_frm_obj;
static CONSTEXPR const vfwnmacc vfwnmacc_obj;
static CONSTEXPR const vfwmsac vfwmsac_obj;
static CONSTEXPR const vfwnmsac vfwnmsac_obj;
@@ -2558,6 +2582,7 @@ BASE (vfnmadd_frm)
BASE (vfmsub)
BASE (vfmsub_frm)
BASE (vfwmacc)
+BASE (vfwmacc_frm)
BASE (vfwnmacc)
BASE (vfwmsac)
BASE (vfwnmsac)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index e60cebab4ae..acbc7d42fbe 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -176,6 +176,7 @@ extern const function_base *const vfnmadd_frm;
extern const function_base *const vfmsub;
extern const function_base *const vfmsub_frm;
extern const function_base *const vfwmacc;
+extern const function_base *const vfwmacc_frm;
extern const function_base *const vfwnmacc;
extern const function_base *const vfwmsac;
extern const function_base *const vfwnmsac;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index d75b281eebe..0b73a5bcbc5 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -376,6 +376,9 @@ DEF_RVV_FUNCTION (vfwmsac, alu, full_preds, f_wwfv_ops)
DEF_RVV_FUNCTION (vfwnmsac, alu, full_preds, f_wwvv_ops)
DEF_RVV_FUNCTION (vfwnmsac, alu, full_preds, f_wwfv_ops)
+DEF_RVV_FUNCTION (vfwmacc_frm, alu_frm, full_preds, f_wwvv_ops)
+DEF_RVV_FUNCTION (vfwmacc_frm, alu_frm, full_preds, f_wwfv_ops)
+
// 13.8. Vector Floating-Point Square-Root Instruction
DEF_RVV_FUNCTION (vfsqrt, alu, full_preds, f_v_ops)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index abab06c00ed..ad4a9098620 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3771,17 +3771,29 @@ function_expander::use_widen_ternop_insn (insn_code
icode)
add_all_one_mask_operand (mask_mode ());
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
-add_input_operand (argno);
+{
+ if (base->has_rounding_mode_operand_p ()
+ && argno == call_expr_nargs (exp) - 2)
+ {
+ /* Since the rounding mode argument position is not consistent with
+the instruction pattern, we need to skip rounding mode argument
+here. */
+ continue;
+ }
+
[PATCH v4] Mode-Switching: Fix SET_SRC ICE for create_pre_exit
From: Pan Li
In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will
be only 1 operand when SET_SRC in create_pre_exit. For example as below.
(insn 13 9 14 2 (clobber (reg/i:TI 10 a0))
"gcc/testsuite/gcc.dg/pr78148.c":24:1 -1
(expr_list:REG_UNUSED (reg/i:TI 10 a0)
(nil)))
Unfortunately, SET_SRC requires at least 2 operands and then Segment
Fault here. For SH4 part result in Segment Fault, it looks like only
valid when the return_copy_pat is load or something like that. Thus,
this patch try to fix it by restrict the SET insn for SET_SRC.
Signed-off-by: Pan Li
gcc/ChangeLog:
* mode-switching.cc (create_pre_exit): Add SET insn check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mode-switch-ice-1.c: New test.
---
gcc/mode-switching.cc | 1 +
.../gcc.target/riscv/mode-switch-ice-1.c | 22 +++
2 files changed, 23 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
diff --git a/gcc/mode-switching.cc b/gcc/mode-switching.cc
index 64ae2bc29c3..f483c831c35 100644
--- a/gcc/mode-switching.cc
+++ b/gcc/mode-switching.cc
@@ -411,6 +411,7 @@ create_pre_exit (int n_entities, int *entity_map, const int
*num_modes)
conflict with address reloads. */
if (copy_start >= ret_start
&& copy_start + copy_num <= ret_end
+ && GET_CODE (return_copy_pat) == SET
&& OBJECT_P (SET_SRC (return_copy_pat)))
forced_late_switch = true;
break;
diff --git a/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
b/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
new file mode 100644
index 000..1b34a471904
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct A { char e, f; };
+
+struct B
+{
+ int g;
+ struct A h[4];
+};
+
+extern void bar (int, int);
+
+struct B foo (void)
+{
+ bar (2, 1);
+}
+
+void baz ()
+{
+ foo ();
+}
--
2.34.1
[PATCH v1] RISC-V: Support RVV VFNMSUB rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFNMSUB as the below samples.
* __riscv_vfnmsub_vv_f32m1_rm
* __riscv_vfnmsub_vv_f32m1_rm_m
* __riscv_vfnmsub_vf_f32m1_rm
* __riscv_vfnmsub_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfnmsub_frm): New class for vfnmsub frm.
(vfnmsub_frm): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfnmsub_frm): New function declaration.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-nmsub.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 25 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/rvv/base/float-point-nmsub.c| 47 +++
4 files changed, 75 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsub.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 381bc72c784..e14e9aa7809 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -516,6 +516,29 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfnmsub
+*/
+class vfnmsub_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ false, code_for_pred_mul_neg_scalar (PLUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ false, code_for_pred_mul_neg (PLUS, e.vector_mode ()));
+
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2282,6 +2305,7 @@ static CONSTEXPR const vfnmsac_frm vfnmsac_frm_obj;
static CONSTEXPR const vfmadd vfmadd_obj;
static CONSTEXPR const vfmadd_frm vfmadd_frm_obj;
static CONSTEXPR const vfnmsub vfnmsub_obj;
+static CONSTEXPR const vfnmsub_frm vfnmsub_frm_obj;
static CONSTEXPR const vfnmacc vfnmacc_obj;
static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
static CONSTEXPR const vfmsac vfmsac_obj;
@@ -2524,6 +2548,7 @@ BASE (vfnmsac_frm)
BASE (vfmadd)
BASE (vfmadd_frm)
BASE (vfnmsub)
+BASE (vfnmsub_frm)
BASE (vfnmacc)
BASE (vfnmacc_frm)
BASE (vfmsac)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 99cfbfd78c8..e60cebab4ae 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -166,6 +166,7 @@ extern const function_base *const vfnmsac_frm;
extern const function_base *const vfmadd;
extern const function_base *const vfmadd_frm;
extern const function_base *const vfnmsub;
+extern const function_base *const vfnmsub_frm;
extern const function_base *const vfnmacc;
extern const function_base *const vfnmacc_frm;
extern const function_base *const vfmsac;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 75235ec01d3..d75b281eebe 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -363,6 +363,8 @@ DEF_RVV_FUNCTION (vfnmadd_frm, alu_frm, full_preds,
f__ops)
DEF_RVV_FUNCTION (vfnmadd_frm, alu_frm, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfmsub_frm, alu_frm, full_preds, f__ops)
DEF_RVV_FUNCTION (vfmsub_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfnmsub_frm, alu_frm, full_preds, f__ops)
+DEF_RVV_FUNCTION (vfnmsub_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsub.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsub.c
new file mode 100644
index 000..1b3e939b1e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsub.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfnmsub_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmsub_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfnmsub_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmsub_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfnmsub_vf_f32m1_rm
[PATCH v1] RISC-V: Support RVV VFMSUB rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFMSUB as the below samples.
* __riscv_vfmsub_vv_f32m1_rm
* __riscv_vfmsub_vv_f32m1_rm_m
* __riscv_vfmsub_vf_f32m1_rm
* __riscv_vfmsub_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfmsub_frm): New class for vfmsub frm.
(vfmsub_frm): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfmsub_frm): New function declaration.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-msub.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 25 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/rvv/base/float-point-msub.c | 47 +++
4 files changed, 75 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index b085ba4f52d..381bc72c784 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -493,6 +493,29 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfmsub
+*/
+class vfmsub_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ false, code_for_pred_mul_scalar (MINUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ false, code_for_pred_mul (MINUS, e.vector_mode ()));
+
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2266,6 +2289,7 @@ static CONSTEXPR const vfmsac_frm vfmsac_frm_obj;
static CONSTEXPR const vfnmadd vfnmadd_obj;
static CONSTEXPR const vfnmadd_frm vfnmadd_frm_obj;
static CONSTEXPR const vfmsub vfmsub_obj;
+static CONSTEXPR const vfmsub_frm vfmsub_frm_obj;
static CONSTEXPR const vfwmacc vfwmacc_obj;
static CONSTEXPR const vfwnmacc vfwnmacc_obj;
static CONSTEXPR const vfwmsac vfwmsac_obj;
@@ -2507,6 +2531,7 @@ BASE (vfmsac_frm)
BASE (vfnmadd)
BASE (vfnmadd_frm)
BASE (vfmsub)
+BASE (vfmsub_frm)
BASE (vfwmacc)
BASE (vfwnmacc)
BASE (vfwmsac)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 4ade0ace7b2..99cfbfd78c8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -173,6 +173,7 @@ extern const function_base *const vfmsac_frm;
extern const function_base *const vfnmadd;
extern const function_base *const vfnmadd_frm;
extern const function_base *const vfmsub;
+extern const function_base *const vfmsub_frm;
extern const function_base *const vfwmacc;
extern const function_base *const vfwnmacc;
extern const function_base *const vfwmsac;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index e9b16f99180..75235ec01d3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -361,6 +361,8 @@ DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds,
f__ops)
DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfnmadd_frm, alu_frm, full_preds, f__ops)
DEF_RVV_FUNCTION (vfnmadd_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfmsub_frm, alu_frm, full_preds, f__ops)
+DEF_RVV_FUNCTION (vfmsub_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c
new file mode 100644
index 000..e58519d0742
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msub.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfmsub_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfmsub_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfmsub_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfmsub_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfmsub_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1,
[PATCH v1] RISC-V: Support RVV VFNMADD rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFNMADD as the below samples.
* __riscv_vfnmadd_vv_f32m1_rm
* __riscv_vfnmadd_vv_f32m1_rm_m
* __riscv_vfnmadd_vf_f32m1_rm
* __riscv_vfnmadd_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfnmadd_frm): New class for vfnmadd frm.
(vfnmadd_frm): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfnmadd_frm): New function declaration.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-nmadd.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 25 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/rvv/base/float-point-nmadd.c| 47 +++
4 files changed, 75 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmadd.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 7476cdc317d..b085ba4f52d 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -470,6 +470,29 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfnmadd
+*/
+class vfnmadd_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ false, code_for_pred_mul_neg_scalar (MINUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ false, code_for_pred_mul_neg (MINUS, e.vector_mode ()));
+
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2241,6 +2264,7 @@ static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
static CONSTEXPR const vfmsac vfmsac_obj;
static CONSTEXPR const vfmsac_frm vfmsac_frm_obj;
static CONSTEXPR const vfnmadd vfnmadd_obj;
+static CONSTEXPR const vfnmadd_frm vfnmadd_frm_obj;
static CONSTEXPR const vfmsub vfmsub_obj;
static CONSTEXPR const vfwmacc vfwmacc_obj;
static CONSTEXPR const vfwnmacc vfwnmacc_obj;
@@ -2481,6 +2505,7 @@ BASE (vfnmacc_frm)
BASE (vfmsac)
BASE (vfmsac_frm)
BASE (vfnmadd)
+BASE (vfnmadd_frm)
BASE (vfmsub)
BASE (vfwmacc)
BASE (vfwnmacc)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 5850ff0cf2e..4ade0ace7b2 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -171,6 +171,7 @@ extern const function_base *const vfnmacc_frm;
extern const function_base *const vfmsac;
extern const function_base *const vfmsac_frm;
extern const function_base *const vfnmadd;
+extern const function_base *const vfnmadd_frm;
extern const function_base *const vfmsub;
extern const function_base *const vfwmacc;
extern const function_base *const vfwnmacc;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 04f3de1275c..e9b16f99180 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -359,6 +359,8 @@ DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds,
f__ops)
DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f__ops)
DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfnmadd_frm, alu_frm, full_preds, f__ops)
+DEF_RVV_FUNCTION (vfnmadd_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmadd.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmadd.c
new file mode 100644
index 000..9332617641b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmadd.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfnmadd_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmadd_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfnmadd_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmadd_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfnmadd_vf_f32m1_rm
[PATCH v1] RISC-V: Support RVV VFMADD rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFMADD as the below samples.
* __riscv_vfmadd_vv_f32m1_rm
* __riscv_vfmadd_vv_f32m1_rm_m
* __riscv_vfmadd_vf_f32m1_rm
* __riscv_vfmadd_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfmadd_frm): New class for vfmadd frm.
(vfmadd_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfmadd_frm): New function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-madd.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 25 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/rvv/base/float-point-madd.c | 47 +++
4 files changed, 75 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 60c6e16f6ae..7476cdc317d 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -447,6 +447,29 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfmadd
+*/
+class vfmadd_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ false, code_for_pred_mul_scalar (PLUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ false, code_for_pred_mul (PLUS, e.vector_mode ()));
+
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2211,6 +2234,7 @@ static CONSTEXPR const vfmacc_frm vfmacc_frm_obj;
static CONSTEXPR const vfnmsac vfnmsac_obj;
static CONSTEXPR const vfnmsac_frm vfnmsac_frm_obj;
static CONSTEXPR const vfmadd vfmadd_obj;
+static CONSTEXPR const vfmadd_frm vfmadd_frm_obj;
static CONSTEXPR const vfnmsub vfnmsub_obj;
static CONSTEXPR const vfnmacc vfnmacc_obj;
static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
@@ -2450,6 +2474,7 @@ BASE (vfmacc_frm)
BASE (vfnmsac)
BASE (vfnmsac_frm)
BASE (vfmadd)
+BASE (vfmadd_frm)
BASE (vfnmsub)
BASE (vfnmacc)
BASE (vfnmacc_frm)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 28eec2c3e99..5850ff0cf2e 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -164,6 +164,7 @@ extern const function_base *const vfmacc_frm;
extern const function_base *const vfnmsac;
extern const function_base *const vfnmsac_frm;
extern const function_base *const vfmadd;
+extern const function_base *const vfmadd_frm;
extern const function_base *const vfnmsub;
extern const function_base *const vfnmacc;
extern const function_base *const vfnmacc_frm;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index c84e052c1a9..04f3de1275c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -357,6 +357,8 @@ DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds,
f__ops)
DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f__ops)
DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f__ops)
+DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c
new file mode 100644
index 000..00c9d002998
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-madd.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfmadd_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfmadd_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfmadd_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfmadd_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfmadd_vf_f32m1_rm (vfloat32m1_t vd, float32_t
[PATCH v1] RISC-V: Support RVV VFNMSAC rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFNMSAC for the below samples.
* __riscv_vfnmsac_vv_f32m1_rm
* __riscv_vfnmsac_vv_f32m1_rm_m
* __riscv_vfnmsac_vf_f32m1_rm
* __riscv_vfnmsac_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfnmsac_frm): New class for vfnmsac frm.
(vfnmsac_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfnmsac_frm): New function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-nmsac.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 25 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/rvv/base/float-point-nmsac.c| 47 +++
4 files changed, 75 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsac.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 8d3970b28db..60c6e16f6ae 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -424,6 +424,29 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfnmsac
+*/
+class vfnmsac_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg_scalar (PLUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg (PLUS, e.vector_mode ()));
+
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2186,6 +2209,7 @@ static CONSTEXPR const widen_binop_frm
vfwmul_frm_obj;
static CONSTEXPR const vfmacc vfmacc_obj;
static CONSTEXPR const vfmacc_frm vfmacc_frm_obj;
static CONSTEXPR const vfnmsac vfnmsac_obj;
+static CONSTEXPR const vfnmsac_frm vfnmsac_frm_obj;
static CONSTEXPR const vfmadd vfmadd_obj;
static CONSTEXPR const vfnmsub vfnmsub_obj;
static CONSTEXPR const vfnmacc vfnmacc_obj;
@@ -2424,6 +2448,7 @@ BASE (vfwmul_frm)
BASE (vfmacc)
BASE (vfmacc_frm)
BASE (vfnmsac)
+BASE (vfnmsac_frm)
BASE (vfmadd)
BASE (vfnmsub)
BASE (vfnmacc)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index ca8a6dc1cc3..28eec2c3e99 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -162,6 +162,7 @@ extern const function_base *const vfwmul_frm;
extern const function_base *const vfmacc;
extern const function_base *const vfmacc_frm;
extern const function_base *const vfnmsac;
+extern const function_base *const vfnmsac_frm;
extern const function_base *const vfmadd;
extern const function_base *const vfnmsub;
extern const function_base *const vfnmacc;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 51a14e49075..c84e052c1a9 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -355,6 +355,8 @@ DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds,
f__ops)
DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f__ops)
DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f__ops)
+DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsac.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsac.c
new file mode 100644
index 000..c3089234272
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmsac.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfnmsac_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmsac_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfnmsac_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmsac_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfnmsac_vf_f32m1_rm
[PATCH v1] RISC-V: Support RVV VFMSAC rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFMSAC for the below samples.
* __riscv_vfmsac_vv_f32m1_rm
* __riscv_vfmsac_vv_f32m1_rm_m
* __riscv_vfmsac_vf_f32m1_rm
* __riscv_vfmsac_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
(class vfmsac_frm): New class for vfmsac frm.
(vfmsac_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfmsac_frm): New function definition
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-msac.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 25 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/rvv/base/float-point-msac.c | 47 +++
4 files changed, 75 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 1d4a5a18bf9..8d3970b28db 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -401,6 +401,29 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfmsac
+*/
+class vfmsac_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_scalar (MINUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul (MINUS, e.vector_mode ()));
+
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2168,6 +2191,7 @@ static CONSTEXPR const vfnmsub vfnmsub_obj;
static CONSTEXPR const vfnmacc vfnmacc_obj;
static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
static CONSTEXPR const vfmsac vfmsac_obj;
+static CONSTEXPR const vfmsac_frm vfmsac_frm_obj;
static CONSTEXPR const vfnmadd vfnmadd_obj;
static CONSTEXPR const vfmsub vfmsub_obj;
static CONSTEXPR const vfwmacc vfwmacc_obj;
@@ -2405,6 +2429,7 @@ BASE (vfnmsub)
BASE (vfnmacc)
BASE (vfnmacc_frm)
BASE (vfmsac)
+BASE (vfmsac_frm)
BASE (vfnmadd)
BASE (vfmsub)
BASE (vfwmacc)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 247074d0868..ca8a6dc1cc3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -167,6 +167,7 @@ extern const function_base *const vfnmsub;
extern const function_base *const vfnmacc;
extern const function_base *const vfnmacc_frm;
extern const function_base *const vfmsac;
+extern const function_base *const vfmsac_frm;
extern const function_base *const vfnmadd;
extern const function_base *const vfmsub;
extern const function_base *const vfwmacc;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 7aae0665520..51a14e49075 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -353,6 +353,8 @@ DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds,
f__ops)
DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f__ops)
DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f__ops)
+DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c
new file mode 100644
index 000..8fee552dd30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-msac.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfmsac_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfmsac_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfmsac_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfmsac_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfmsac_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2,
+size_t vl) {
+ return
[PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFNMACC for the below samples.
* __riscv_vfnmacc_vv_f32m1_rm
* __riscv_vfnmacc_vv_f32m1_rm_m
* __riscv_vfnmacc_vf_f32m1_rm
* __riscv_vfnmacc_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfnmacc_frm): New class for vfnmacc.
(vfnmacc_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfnmacc_frm): New function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-nmacc.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 24 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/rvv/base/float-point-nmacc.c| 47 +++
4 files changed, 74 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 1695d77e8bd..1d4a5a18bf9 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -379,6 +379,28 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfnmacc
+*/
+class vfnmacc_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg_scalar (MINUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg (MINUS, e.vector_mode ()));
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2144,6 +2166,7 @@ static CONSTEXPR const vfnmsac vfnmsac_obj;
static CONSTEXPR const vfmadd vfmadd_obj;
static CONSTEXPR const vfnmsub vfnmsub_obj;
static CONSTEXPR const vfnmacc vfnmacc_obj;
+static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
static CONSTEXPR const vfmsac vfmsac_obj;
static CONSTEXPR const vfnmadd vfnmadd_obj;
static CONSTEXPR const vfmsub vfmsub_obj;
@@ -2380,6 +2403,7 @@ BASE (vfnmsac)
BASE (vfmadd)
BASE (vfnmsub)
BASE (vfnmacc)
+BASE (vfnmacc_frm)
BASE (vfmsac)
BASE (vfnmadd)
BASE (vfmsub)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 67d18412b4c..247074d0868 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -165,6 +165,7 @@ extern const function_base *const vfnmsac;
extern const function_base *const vfmadd;
extern const function_base *const vfnmsub;
extern const function_base *const vfnmacc;
+extern const function_base *const vfnmacc_frm;
extern const function_base *const vfmsac;
extern const function_base *const vfnmadd;
extern const function_base *const vfmsub;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 92ecf8a9065..7aae0665520 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -351,6 +351,8 @@ DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f__ops)
DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f__ops)
+DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
new file mode 100644
index 000..fca378b7a8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-nmacc.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfnmacc_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vf_f32m1_rm (vfloat32m1_t vd, float32_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return
[PATCH v1] RISC-V: Support RVV VFMACC rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFMACC for the below samples.
* __riscv_vfmacc_vv_f32m1_rm
* __riscv_vfmacc_vv_f32m1_rm_m
* __riscv_vfmacc_vf_f32m1_rm
* __riscv_vfmacc_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfmacc_frm): New class for vfmacc frm.
(vfmacc_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfmacc_frm): New function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-macc.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 25 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 3 ++
.../riscv/rvv/base/float-point-macc.c | 47 +++
4 files changed, 76 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-macc.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index afe3735f5ee..1695d77e8bd 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -356,6 +356,29 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfmacc
+*/
+class vfmacc_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (true,
+ code_for_pred_mul_scalar (PLUS,
+ e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (true,
+ code_for_pred_mul (PLUS, e.vector_mode ()));
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2116,6 +2139,7 @@ static CONSTEXPR const reverse_binop_frm
vfrdiv_frm_obj;
static CONSTEXPR const widen_binop vfwmul_obj;
static CONSTEXPR const widen_binop_frm vfwmul_frm_obj;
static CONSTEXPR const vfmacc vfmacc_obj;
+static CONSTEXPR const vfmacc_frm vfmacc_frm_obj;
static CONSTEXPR const vfnmsac vfnmsac_obj;
static CONSTEXPR const vfmadd vfmadd_obj;
static CONSTEXPR const vfnmsub vfnmsub_obj;
@@ -2351,6 +2375,7 @@ BASE (vfrdiv_frm)
BASE (vfwmul)
BASE (vfwmul_frm)
BASE (vfmacc)
+BASE (vfmacc_frm)
BASE (vfnmsac)
BASE (vfmadd)
BASE (vfnmsub)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 2d2b52a312c..67d18412b4c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -160,6 +160,7 @@ extern const function_base *const vfrdiv_frm;
extern const function_base *const vfwmul;
extern const function_base *const vfwmul_frm;
extern const function_base *const vfmacc;
+extern const function_base *const vfmacc_frm;
extern const function_base *const vfnmsac;
extern const function_base *const vfmadd;
extern const function_base *const vfnmsub;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index d43b33ded17..92ecf8a9065 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -349,6 +349,9 @@ DEF_RVV_FUNCTION (vfnmadd, alu, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f__ops)
DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f__ops)
+DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
+
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwfv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-macc.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-macc.c
new file mode 100644
index 000..df29f4d240f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-macc.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfmacc_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfmacc_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfmacc_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
[PATCH v3] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
From: Pan Li
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the define insn has frm operands.
This patch would like to refactor frm and eliminate the above
assumptions, as well as unblock the underlying rounding mode intrinsic
API support.
After refactor, the default frm will be none, and the selected insn type
will be dyn. For the floating point which honors the frm, we will
set the frm_mode attr explicitly in define_insn.
Signed-off-by: Pan Li
Co-Authored-by: Kito Cheng
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_frm_mode): Remove operand
assumptions.
* config/riscv/riscv-v.cc (get_frm_mode): New function.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn):
* config/riscv/vector.md: Set frm_mode attr explicitly.
gcc/ChangeLog:
* config/riscv/riscv-protos.h
(enum floating_point_rounding_mode): Add NONE, DYN_EXIT and DYN_CALL.
(get_frm_mode): New declaration.
* config/riscv/riscv-v.cc (get_frm_mode): New function to get frm mode.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn): Take care of frm reg.
* config/riscv/riscv.cc (riscv_static_frm_mode_p): Migrate to FRM_XXX.
(riscv_emit_frm_mode_set): Ditto.
(riscv_emit_mode_set): Ditto.
(riscv_frm_adjust_mode_after_call): Ditto.
(riscv_frm_mode_needed): Ditto.
(riscv_frm_mode_after): Ditto.
(riscv_mode_entry): Ditto.
(riscv_mode_exit): Ditto.
* config/riscv/riscv.h (NUM_MODES_FOR_MODE_SWITCHING): Ditto.
* config/riscv/vector.md
(rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none): Removed
(symbol_ref): * config/riscv/vector.md: Set frm_mode attr explicitly.
---
gcc/config/riscv/riscv-protos.h | 4 +
gcc/config/riscv/riscv-v.cc | 29
gcc/config/riscv/riscv-vector-builtins.cc | 22 ++-
gcc/config/riscv/riscv.cc | 46 +++---
gcc/config/riscv/riscv.h | 2 +-
gcc/config/riscv/vector.md| 172 ++
6 files changed, 186 insertions(+), 89 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index ac9c4b02f17..2fbed04ff84 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -349,8 +349,12 @@ enum floating_point_rounding_mode
FRM_DYN = 7, /* Aka 0b111. */
FRM_STATIC_MIN = FRM_RNE,
FRM_STATIC_MAX = FRM_RMM,
+ FRM_DYN_EXIT = 8,
+ FRM_DYN_CALL = 9,
+ FRM_NONE = 10,
};
+enum floating_point_rounding_mode get_frm_mode (rtx);
opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
poly_uint64);
unsigned int autovectorize_vector_modes (vec *, bool);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 0bea04c1967..c9f0a4a9e7b 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -112,6 +112,7 @@ public:
{
m_has_fp_rounding_mode_p = true;
m_fp_rounding_mode = mode;
+gcc_assert (mode <= FRM_DYN);
}
void add_output_operand (rtx x, machine_mode mode)
@@ -1590,6 +1591,34 @@ expand_const_vector (rtx target, rtx src)
gcc_unreachable ();
}
+/* Get the frm mode with given CONST_INT rtx, the default mode is
+ FRM_DYN. */
+enum floating_point_rounding_mode
+get_frm_mode (rtx operand)
+{
+ gcc_assert (CONST_INT_P (operand));
+
+ switch (INTVAL (operand))
+{
+case FRM_RNE:
+ return FRM_RNE;
+case FRM_RTZ:
+ return FRM_RTZ;
+case FRM_RDN:
+ return FRM_RDN;
+case FRM_RUP:
+ return FRM_RUP;
+case FRM_RMM:
+ return FRM_RMM;
+case FRM_DYN:
+ return FRM_DYN;
+default:
+ gcc_unreachable ();
+}
+
+ gcc_unreachable ();
+}
+
/* Expand a pre-RA RVV data move from SRC to DEST.
It expands move for RVV fractional vector modes. */
bool
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 528dca7ae85..abab06c00ed 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p,
insn_code icode)
}
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
-add_input_operand (argno);
+{
+ if (base->has_rounding_mode_operand_p ()
+ && argno == call_expr_nargs (exp) - 2)
+ {
+ /* Since the rounding mode argument position is not consistent with
+the instruction pattern, we need to skip rounding mode argument
+here. */
+ continue;
+ }
+ add_input_operand (argno);
+
[PATCH v3] Mode-Switching: Fix SET_SRC ICE when CLOBBER insn
From: Pan Li
In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will
be only 1 operand when SET_SRC in create_pre_exit. For example as below.
(insn 13 9 14 2 (clobber (reg/i:TI 10 a0))
"gcc/testsuite/gcc.dg/pr78148.c":24:1 -1
(expr_list:REG_UNUSED (reg/i:TI 10 a0)
(nil)))
Unfortunately, SET_SRC requires at least 2 operands and then Segment
Fault here. For SH4 part result in Segment Fault, it looks like only
valid when the return_copy_pat is load or something like that. Thus,
this patch try to fix it by ingnoring the CLOBBER insn for SH4.
Signed-off-by: Pan Li
gcc/ChangeLog:
* mode-switching.cc (create_pre_exit): Add CLOBBER check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mode-switch-ice-1.c: New test.
---
gcc/mode-switching.cc | 2 +-
.../gcc.target/riscv/mode-switch-ice-1.c | 22 +++
2 files changed, 23 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
diff --git a/gcc/mode-switching.cc b/gcc/mode-switching.cc
index 64ae2bc29c3..b034cf7d437 100644
--- a/gcc/mode-switching.cc
+++ b/gcc/mode-switching.cc
@@ -392,7 +392,7 @@ create_pre_exit (int n_entities, int *entity_map, const int
*num_modes)
&& mode != targetm.mode_switching.exit (e))
break;
}
- if (j >= 0)
+ if (j >= 0 && GET_CODE (return_copy_pat) != CLOBBER)
{
/* __builtin_return emits a sequence of loads to all
return registers. One of them might require
diff --git a/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
b/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
new file mode 100644
index 000..1b34a471904
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct A { char e, f; };
+
+struct B
+{
+ int g;
+ struct A h[4];
+};
+
+extern void bar (int, int);
+
+struct B foo (void)
+{
+ bar (2, 1);
+}
+
+void baz ()
+{
+ foo ();
+}
--
2.34.1
[PATCH v2] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
From: Pan Li
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the define insn has frm operands.
This patch would like to refactor frm and eliminate the above
assumptions, as well as unblock the underlying rounding mode intrinsic
API support.
After refactor, the default frm will be none, and the selected insn type
will be dyn. For the floating point which honors the frm, we will
set the frm_mode attr explicitly in define_insn.
Signed-off-by: Pan Li
Co-Authored-by: Kito Cheng
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_frm_mode): Remove operand
assumptions.
* config/riscv/riscv-v.cc (get_frm_mode): New function.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn):
* config/riscv/vector.md: Set frm_mode attr explicitly.
gcc/ChangeLog:
* config/riscv/riscv-protos.h
(enum floating_point_rounding_mode): Add NONE, DYN_EXIT and DYN_CALL.
(get_frm_mode): New declaration.
* config/riscv/riscv-v.cc (get_frm_mode): New function to get frm mode.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn): Take care of frm reg.
* config/riscv/riscv.cc (riscv_static_frm_mode_p): Migrate to FRM_XXX.
(riscv_emit_frm_mode_set): Ditto.
(riscv_emit_mode_set): Ditto.
(riscv_frm_adjust_mode_after_call): Ditto.
(riscv_frm_mode_needed): Ditto.
(riscv_frm_mode_after): Ditto.
(riscv_mode_entry): Ditto.
(riscv_mode_exit): Ditto.
* config/riscv/riscv.h (NUM_MODES_FOR_MODE_SWITCHING): Ditto.
* config/riscv/vector.md
(rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none): Removed
(symbol_ref): * config/riscv/vector.md: Set frm_mode attr explicitly.
---
gcc/config/riscv/riscv-protos.h | 4 +
gcc/config/riscv/riscv-v.cc | 29
gcc/config/riscv/riscv-vector-builtins.cc | 22 ++-
gcc/config/riscv/riscv.cc | 46 +++---
gcc/config/riscv/riscv.h | 2 +-
gcc/config/riscv/vector.md| 172 ++
6 files changed, 186 insertions(+), 89 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 324991e2619..f45653848de 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -344,8 +344,12 @@ enum floating_point_rounding_mode
FRM_DYN = 7, /* Aka 0b111. */
FRM_STATIC_MIN = FRM_RNE,
FRM_STATIC_MAX = FRM_RMM,
+ FRM_DYN_EXIT = 8,
+ FRM_DYN_CALL = 9,
+ FRM_NONE = 10,
};
+enum floating_point_rounding_mode get_frm_mode (rtx);
opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
poly_uint64);
unsigned int autovectorize_vector_modes (vec *, bool);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 278452b9e05..9ab6ae17d33 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -112,6 +112,7 @@ public:
{
m_has_fp_rounding_mode_p = true;
m_fp_rounding_mode = mode;
+gcc_assert (mode <= FRM_DYN);
}
void add_output_operand (rtx x, machine_mode mode)
@@ -1513,6 +1514,34 @@ expand_const_vector (rtx target, rtx src)
gcc_unreachable ();
}
+/* Get the frm mode with given CONST_INT rtx, the default mode is
+ FRM_DYN. */
+enum floating_point_rounding_mode
+get_frm_mode (rtx operand)
+{
+ gcc_assert (CONST_INT_P (operand));
+
+ switch (INTVAL (operand))
+{
+case FRM_RNE:
+ return FRM_RNE;
+case FRM_RTZ:
+ return FRM_RTZ;
+case FRM_RDN:
+ return FRM_RDN;
+case FRM_RUP:
+ return FRM_RUP;
+case FRM_RMM:
+ return FRM_RMM;
+case FRM_DYN:
+ return FRM_DYN;
+default:
+ return FRM_DYN;
+}
+
+ gcc_unreachable ();
+}
+
/* Expand a pre-RA RVV data move from SRC to DEST.
It expands move for RVV fractional vector modes. */
bool
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 528dca7ae85..abab06c00ed 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p,
insn_code icode)
}
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
-add_input_operand (argno);
+{
+ if (base->has_rounding_mode_operand_p ()
+ && argno == call_expr_nargs (exp) - 2)
+ {
+ /* Since the rounding mode argument position is not consistent with
+the instruction pattern, we need to skip rounding mode argument
+here. */
+ continue;
+ }
+ add_input_operand (argno);
+}
[PATCH v2] Mode-Switching: Fix SET_SRC ICE when USE or CLOBBER
From: Pan Li
In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will
be only 1 operand when SET_SRC in create_pre_exit. For example as below.
(insn 13 9 14 2 (clobber (reg/i:TI 10 a0))
"gcc/testsuite/gcc.dg/pr78148.c":24:1 -1
(expr_list:REG_UNUSED (reg/i:TI 10 a0)
(nil)))
Unfortunately, SET_SRC requires at least 2 operands and then Segment
Fault here. This patch would like to fix this ICE by ignoring the USE
and CLOBBER insn before SET_SRC.
Signed-off-by: Pan Li
gcc/ChangeLog:
* mode-switching.cc (create_pre_exit): Add USE and CLOBBER check.
* rtl.h (CLOBBER_OR_USE_P): New macro.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mode-switch-ice-1.c: New test.
---
gcc/mode-switching.cc | 1 +
gcc/rtl.h | 4
.../gcc.target/riscv/mode-switch-ice-1.c | 22 +++
3 files changed, 27 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
diff --git a/gcc/mode-switching.cc b/gcc/mode-switching.cc
index 64ae2bc29c3..8bb016a811d 100644
--- a/gcc/mode-switching.cc
+++ b/gcc/mode-switching.cc
@@ -411,6 +411,7 @@ create_pre_exit (int n_entities, int *entity_map, const int
*num_modes)
conflict with address reloads. */
if (copy_start >= ret_start
&& copy_start + copy_num <= ret_end
+ && !CLOBBER_OR_USE_P (return_copy_pat)
&& OBJECT_P (SET_SRC (return_copy_pat)))
forced_late_switch = true;
break;
diff --git a/gcc/rtl.h b/gcc/rtl.h
index e1c51156f90..cdc2941c210 100644
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -1768,6 +1768,10 @@ extern const char * const reg_note_name[];
#define VAR_LOC_UNKNOWN_P(X) \
(GET_CODE (X) == CLOBBER && XEXP ((X), 0) == const0_rtx)
+/* Determine whether RTX is USE or CLOBBER. */
+#define CLOBBER_OR_USE_P(RTX) \
+ (GET_CODE (RTX) == USE || GET_CODE (RTX) == CLOBBER)
+
/* 1 if RTX is emitted after a call, but it should take effect before
the call returns. */
#define NOTE_DURING_CALL_P(RTX)\
diff --git a/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
b/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
new file mode 100644
index 000..1b34a471904
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct A { char e, f; };
+
+struct B
+{
+ int g;
+ struct A h[4];
+};
+
+extern void bar (int, int);
+
+struct B foo (void)
+{
+ bar (2, 1);
+}
+
+void baz ()
+{
+ foo ();
+}
--
2.34.1
[PATCH v1] Mode-Switching: Fix SET_SRC ICE when only one operand
From: Pan Li
In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will
be only 1 operand when SET_SRC in create_pre_exit. For example as below.
(insn 13 9 14 2 (clobber (reg/i:TI 10 a0))
"gcc/testsuite/gcc.dg/pr78148.c":24:1 -1
(expr_list:REG_UNUSED (reg/i:TI 10 a0)
(nil)))
Unfortunately, SET_SRC requires at least 2 operands and then Segment
Fault here. This patch would like to fix this ICE by adding operand
length check before SET_SRC.
Signed-off-by: Pan Li
gcc/ChangeLog:
* mode-switching.cc (create_pre_exit): Add operand length check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mode-switch-ice-1.c: New test.
---
gcc/mode-switching.cc | 2 ++
.../gcc.target/riscv/mode-switch-ice-1.c | 22 +++
2 files changed, 24 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
diff --git a/gcc/mode-switching.cc b/gcc/mode-switching.cc
index 64ae2bc29c3..cbf03c02159 100644
--- a/gcc/mode-switching.cc
+++ b/gcc/mode-switching.cc
@@ -411,6 +411,8 @@ create_pre_exit (int n_entities, int *entity_map, const int
*num_modes)
conflict with address reloads. */
if (copy_start >= ret_start
&& copy_start + copy_num <= ret_end
+ && GET_RTX_LENGTH (GET_CODE (return_copy_pat)) >= 2
+ /* SET_SRC requires at least 2 operands. */
&& OBJECT_P (SET_SRC (return_copy_pat)))
forced_late_switch = true;
break;
diff --git a/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
b/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
new file mode 100644
index 000..1b34a471904
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mode-switch-ice-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct A { char e, f; };
+
+struct B
+{
+ int g;
+ struct A h[4];
+};
+
+extern void bar (int, int);
+
+struct B foo (void)
+{
+ bar (2, 1);
+}
+
+void baz ()
+{
+ foo ();
+}
--
2.34.1
[PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic
From: Pan Li
The frm_mode attr has some assumptions for each define insn as below.
1. The define insn has at least 9 operands.
2. The operands[9] must be frm reg.
3. The operands[9] must be const int.
Actually, the frm operand can be operands[8], operands[9] or
operands[10], and not all the define insn has frm operands.
This patch would like to refactor frm and eliminate the above
assumptions, as well as unblock the underlying rounding mode intrinsic
API support.
After refactor, the default frm will be none, and the selected insn type
will be dyn. For the floating point which honors the frm, we will
set the frm_mode attr explicitly in define_insn.
Passed both the riscv.exp and rvv.exp for rv32/rv64 tests.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_frm_mode): Remove operand
assumptions.
* config/riscv/riscv-v.cc (get_frm_mode): New function.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn):
* config/riscv/vector.md: Set frm_mode attr explicitly.
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 28
gcc/config/riscv/riscv-vector-builtins.cc | 22 ++-
gcc/config/riscv/vector.md| 170 ++
4 files changed, 159 insertions(+), 62 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 324991e2619..33f7cb1d670 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -236,6 +236,7 @@ bool check_builtin_call (location_t, vec,
unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
bool legitimize_move (rtx, rtx);
+int get_frm_mode (rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 278452b9e05..d5fb8611d6e 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1513,6 +1513,34 @@ expand_const_vector (rtx target, rtx src)
gcc_unreachable ();
}
+/* Get the frm mode with given CONST_INT rtx, the default mode is
+ FRM_MODE_DYN. */
+int
+get_frm_mode (rtx operand)
+{
+ gcc_assert (CONST_INT_P (operand));
+
+ switch (INTVAL (operand))
+{
+case FRM_RNE:
+ return FRM_MODE_RNE;
+case FRM_RTZ:
+ return FRM_MODE_RTZ;
+case FRM_RDN:
+ return FRM_MODE_RDN;
+case FRM_RUP:
+ return FRM_MODE_RUP;
+case FRM_RMM:
+ return FRM_MODE_RMM;
+case FRM_DYN:
+ return FRM_MODE_DYN;
+default:
+ return FRM_MODE_DYN;
+}
+
+ gcc_unreachable ();
+}
+
/* Expand a pre-RA RVV data move from SRC to DEST.
It expands move for RVV fractional vector modes. */
bool
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 528dca7ae85..abab06c00ed 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p,
insn_code icode)
}
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
-add_input_operand (argno);
+{
+ if (base->has_rounding_mode_operand_p ()
+ && argno == call_expr_nargs (exp) - 2)
+ {
+ /* Since the rounding mode argument position is not consistent with
+the instruction pattern, we need to skip rounding mode argument
+here. */
+ continue;
+ }
+ add_input_operand (argno);
+}
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
- /* TODO: Currently, we don't support intrinsic that is modeling rounding
mode.
- We add default rounding mode for the intrinsics that didn't model rounding
- mode yet. */
+ if (base->has_rounding_mode_operand_p ())
+add_input_operand (call_expr_nargs (exp) - 2);
+
+ /* The RVV floating-point only support dynamic rounding mode in the
+ FRM register. */
if (opno != insn_data[icode].n_generator_args)
-add_input_operand (Pmode, const0_rtx);
+add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
return generate_insn (icode);
}
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 750b2de8df9..db3ee105ef4 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -867,26 +867,8 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
;; Defines rounding mode of an floating-point operation.
(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
- (cond
- [(match_test "INTVAL
[PATCH v1] RISC-V: Support RVV VFMADD rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFMADD as the below samples.
* __riscv_vfmadd_vv_f32m1_rm
* __riscv_vfmadd_vv_f32m1_rm_m
* __riscv_vfmadd_vf_f32m1_rm
* __riscv_vfmadd_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfmadd_frm): New class for vfmadd frm.
(vfmadd_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfmadd_frm): New function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-madd.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 24 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../riscv/rvv/base/float-point-single-madd.c | 47 +++
4 files changed, 74 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-madd.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 9c6ca8d1ddc..5b02b04aacb 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -445,6 +445,28 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfmadd
+*/
+class vfmadd_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ false, code_for_pred_mul_scalar (PLUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ false, code_for_pred_mul (PLUS, e.vector_mode ()));
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2209,6 +2231,7 @@ static CONSTEXPR const vfmacc_frm vfmacc_frm_obj;
static CONSTEXPR const vfnmsac vfnmsac_obj;
static CONSTEXPR const vfnmsac_frm vfnmsac_frm_obj;
static CONSTEXPR const vfmadd vfmadd_obj;
+static CONSTEXPR const vfmadd_frm vfmadd_frm_obj;
static CONSTEXPR const vfnmsub vfnmsub_obj;
static CONSTEXPR const vfnmacc vfnmacc_obj;
static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
@@ -2448,6 +2471,7 @@ BASE (vfmacc_frm)
BASE (vfnmsac)
BASE (vfnmsac_frm)
BASE (vfmadd)
+BASE (vfmadd_frm)
BASE (vfnmsub)
BASE (vfnmacc)
BASE (vfnmacc_frm)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 28eec2c3e99..5850ff0cf2e 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -164,6 +164,7 @@ extern const function_base *const vfmacc_frm;
extern const function_base *const vfnmsac;
extern const function_base *const vfnmsac_frm;
extern const function_base *const vfmadd;
+extern const function_base *const vfmadd_frm;
extern const function_base *const vfnmsub;
extern const function_base *const vfnmacc;
extern const function_base *const vfnmacc_frm;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 9c964ae6fcb..c9a06e6b644 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -356,6 +356,8 @@ DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds,
f__ops)
DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f__ops)
DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f__ops)
+DEF_RVV_FUNCTION (vfmadd_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-madd.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-madd.c
new file mode 100644
index 000..00c9d002998
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-madd.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfmadd_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfmadd_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfmadd_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfmadd_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
[PATCH v1] RISC-V: Support RVV VFNMSAC rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFNMSAC for the below samples.
* __riscv_vfnmsac_vv_f32m1_rm
* __riscv_vfnmsac_vv_f32m1_rm_m
* __riscv_vfnmsac_vf_f32m1_rm
* __riscv_vfnmsac_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfnmsac_frm): New class for vfnmsac frm.
(vfnmsac_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfnmsac_frm): New function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-negate-multiply-sub.c:
New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 24 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../float-point-single-negate-multiply-sub.c | 47 +++
4 files changed, 74 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-sub.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index e73051bbd89..9c6ca8d1ddc 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -423,6 +423,28 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfnmsac
+*/
+class vfnmsac_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg_scalar (PLUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg (PLUS, e.vector_mode ()));
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2185,6 +2207,7 @@ static CONSTEXPR const widen_binop_frm
vfwmul_frm_obj;
static CONSTEXPR const vfmacc vfmacc_obj;
static CONSTEXPR const vfmacc_frm vfmacc_frm_obj;
static CONSTEXPR const vfnmsac vfnmsac_obj;
+static CONSTEXPR const vfnmsac_frm vfnmsac_frm_obj;
static CONSTEXPR const vfmadd vfmadd_obj;
static CONSTEXPR const vfnmsub vfnmsub_obj;
static CONSTEXPR const vfnmacc vfnmacc_obj;
@@ -2423,6 +2446,7 @@ BASE (vfwmul_frm)
BASE (vfmacc)
BASE (vfmacc_frm)
BASE (vfnmsac)
+BASE (vfnmsac_frm)
BASE (vfmadd)
BASE (vfnmsub)
BASE (vfnmacc)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index ca8a6dc1cc3..28eec2c3e99 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -162,6 +162,7 @@ extern const function_base *const vfwmul_frm;
extern const function_base *const vfmacc;
extern const function_base *const vfmacc_frm;
extern const function_base *const vfnmsac;
+extern const function_base *const vfnmsac_frm;
extern const function_base *const vfmadd;
extern const function_base *const vfnmsub;
extern const function_base *const vfnmacc;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 8bae7e616ba..9c964ae6fcb 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -354,6 +354,8 @@ DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds,
f__ops)
DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f__ops)
DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f__ops)
+DEF_RVV_FUNCTION (vfnmsac_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-sub.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-sub.c
new file mode 100644
index 000..c3089234272
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-sub.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfnmsac_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmsac_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfnmsac_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return
[PATCH v1] RISC-V: Support RVV VFMSAC rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFMSAC for the below samples.
* __riscv_vfmsac_vv_f32m1_rm
* __riscv_vfmsac_vv_f32m1_rm_m
* __riscv_vfmsac_vf_f32m1_rm
* __riscv_vfmsac_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfmsac_frm): New class for vfmsac frm.
(vfmsac_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfmsac_frm): New function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-multiply-sub.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 24 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../base/float-point-single-multiply-sub.c| 47 +++
4 files changed, 74 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-multiply-sub.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 1d4a5a18bf9..e73051bbd89 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -401,6 +401,28 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfmsac
+*/
+class vfmsac_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_scalar (MINUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul (MINUS, e.vector_mode ()));
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2168,6 +2190,7 @@ static CONSTEXPR const vfnmsub vfnmsub_obj;
static CONSTEXPR const vfnmacc vfnmacc_obj;
static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
static CONSTEXPR const vfmsac vfmsac_obj;
+static CONSTEXPR const vfmsac_frm vfmsac_frm_obj;
static CONSTEXPR const vfnmadd vfnmadd_obj;
static CONSTEXPR const vfmsub vfmsub_obj;
static CONSTEXPR const vfwmacc vfwmacc_obj;
@@ -2405,6 +2428,7 @@ BASE (vfnmsub)
BASE (vfnmacc)
BASE (vfnmacc_frm)
BASE (vfmsac)
+BASE (vfmsac_frm)
BASE (vfnmadd)
BASE (vfmsub)
BASE (vfwmacc)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 247074d0868..ca8a6dc1cc3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -167,6 +167,7 @@ extern const function_base *const vfnmsub;
extern const function_base *const vfnmacc;
extern const function_base *const vfnmacc_frm;
extern const function_base *const vfmsac;
+extern const function_base *const vfmsac_frm;
extern const function_base *const vfnmadd;
extern const function_base *const vfmsub;
extern const function_base *const vfwmacc;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 223e8346cd8..8bae7e616ba 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -352,6 +352,8 @@ DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds,
f__ops)
DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f__ops)
DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f__ops)
+DEF_RVV_FUNCTION (vfmsac_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-multiply-sub.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-multiply-sub.c
new file mode 100644
index 000..8fee552dd30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-multiply-sub.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfmsac_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfmsac_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfmsac_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfmsac_vv_f32m1_rm_m (mask, vd, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
[PATCH v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFNMACC for the below samples.
* __riscv_vfnmacc_vv_f32m1_rm
* __riscv_vfnmacc_vv_f32m1_rm_m
* __riscv_vfnmacc_vf_f32m1_rm
* __riscv_vfnmacc_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfnmacc_frm): New class for vfnmacc.
(vfnmacc_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfnmacc_frm): New function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c:
New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 24 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
.../float-point-single-negate-multiply-add.c | 47 +++
4 files changed, 74 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 1695d77e8bd..1d4a5a18bf9 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -379,6 +379,28 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfnmacc
+*/
+class vfnmacc_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg_scalar (MINUS, e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (
+ true, code_for_pred_mul_neg (MINUS, e.vector_mode ()));
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2144,6 +2166,7 @@ static CONSTEXPR const vfnmsac vfnmsac_obj;
static CONSTEXPR const vfmadd vfmadd_obj;
static CONSTEXPR const vfnmsub vfnmsub_obj;
static CONSTEXPR const vfnmacc vfnmacc_obj;
+static CONSTEXPR const vfnmacc_frm vfnmacc_frm_obj;
static CONSTEXPR const vfmsac vfmsac_obj;
static CONSTEXPR const vfnmadd vfnmadd_obj;
static CONSTEXPR const vfmsub vfmsub_obj;
@@ -2380,6 +2403,7 @@ BASE (vfnmsac)
BASE (vfmadd)
BASE (vfnmsub)
BASE (vfnmacc)
+BASE (vfnmacc_frm)
BASE (vfmsac)
BASE (vfnmadd)
BASE (vfmsub)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 67d18412b4c..247074d0868 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -165,6 +165,7 @@ extern const function_base *const vfnmsac;
extern const function_base *const vfmadd;
extern const function_base *const vfnmsub;
extern const function_base *const vfnmacc;
+extern const function_base *const vfnmacc_frm;
extern const function_base *const vfmsac;
extern const function_base *const vfnmadd;
extern const function_base *const vfmsub;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 3906f2e6248..223e8346cd8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -350,6 +350,8 @@ DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f__ops)
DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f__ops)
DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f__ops)
+DEF_RVV_FUNCTION (vfnmacc_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c
new file mode 100644
index 000..fca378b7a8f
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-negate-multiply-add.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfnmacc_vv_f32m1_rm (vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_rm (vd, op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfnmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t op1,
+ vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfnmacc_vv_f32m1_rm_m (mask, vd, op1, op2, 1,
[PATCH v1] RISC-V: Support RVV VFMACC rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFMACC for the below samples.
* __riscv_vfmacc_vv_f32m1_rm
* __riscv_vfmacc_vv_f32m1_rm_m
* __riscv_vfmacc_vf_f32m1_rm
* __riscv_vfmacc_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfmacc_frm): New class for vfmacc frm.
(vfmacc_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfmacc_frm): New function definition.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn): Add frm operand support.
* config/riscv/vector.md: Add vfmuladd to frm_mode.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-multiply-add.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 25 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
gcc/config/riscv/riscv-vector-builtins.cc | 22 +++--
gcc/config/riscv/vector.md| 2 +-
.../base/float-point-single-multiply-add.c| 47 +++
6 files changed, 93 insertions(+), 6 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-multiply-add.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 8d689f0c935..204ea77c372 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -355,6 +355,29 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfmacc
+*/
+class vfmacc_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ bool has_merge_operand_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+if (e.op_info->op == OP_TYPE_vf)
+ return e.use_ternop_insn (true,
+ code_for_pred_mul_scalar (PLUS,
+ e.vector_mode ()));
+if (e.op_info->op == OP_TYPE_vv)
+ return e.use_ternop_insn (true,
+ code_for_pred_mul (PLUS, e.vector_mode ()));
+gcc_unreachable ();
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2115,6 +2138,7 @@ static CONSTEXPR const reverse_binop_frm
vfrdiv_frm_obj;
static CONSTEXPR const widen_binop vfwmul_obj;
static CONSTEXPR const widen_binop_frm vfwmul_frm_obj;
static CONSTEXPR const vfmacc vfmacc_obj;
+static CONSTEXPR const vfmacc_frm vfmacc_frm_obj;
static CONSTEXPR const vfnmsac vfnmsac_obj;
static CONSTEXPR const vfmadd vfmadd_obj;
static CONSTEXPR const vfnmsub vfnmsub_obj;
@@ -2350,6 +2374,7 @@ BASE (vfrdiv_frm)
BASE (vfwmul)
BASE (vfwmul_frm)
BASE (vfmacc)
+BASE (vfmacc_frm)
BASE (vfnmsac)
BASE (vfmadd)
BASE (vfnmsub)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 2d2b52a312c..67d18412b4c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -160,6 +160,7 @@ extern const function_base *const vfrdiv_frm;
extern const function_base *const vfwmul;
extern const function_base *const vfwmul_frm;
extern const function_base *const vfmacc;
+extern const function_base *const vfmacc_frm;
extern const function_base *const vfnmsac;
extern const function_base *const vfmadd;
extern const function_base *const vfnmsub;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index d43b33ded17..3906f2e6248 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -348,6 +348,8 @@ DEF_RVV_FUNCTION (vfnmadd, alu, full_preds, f__ops)
DEF_RVV_FUNCTION (vfnmadd, alu, full_preds, f_vvfv_ops)
DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f__ops)
DEF_RVV_FUNCTION (vfmsub, alu, full_preds, f_vvfv_ops)
+DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f__ops)
+DEF_RVV_FUNCTION (vfmacc_frm, alu_frm, full_preds, f_vvfv_ops)
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfwmacc, alu, full_preds, f_wwvv_ops)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 528dca7ae85..abab06c00ed 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p,
insn_code icode)
}
for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
-add_input_operand (argno);
+{
+ if (base->has_rounding_mode_operand_p ()
+ && argno ==
[PATCH v1] RISC-V: Fix one comment for binop_frm insn
From: Pan Li The previous patch missed the vfsub comment for binop_frm, this patch would like to fix this. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Add vfsub. --- gcc/config/riscv/riscv-vector-builtins-bases.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 3adc11138a3..36c9aadd19c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -277,6 +277,7 @@ public: /* Implements below instructions for now. - vfadd + - vfsub - vfmul */ template -- 2.34.1
[PATCH v1] RISC-V: Support RVV VFWMUL rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFWMUL for the below samples.
* __riscv_vfwmul_vv_f64m2_rm
* __riscv_vfwmul_vv_f64m2_rm_m
* __riscv_vfwmul_vf_f64m2_rm
* __riscv_vfwmul_vf_f64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(vfwmul_frm_obj): New declaration.
(vfwmul_frm): Ditto.
* config/riscv/riscv-vector-builtins-bases.h:
(vfwmul_frm): Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfwmul_frm): New function definition.
* config/riscv/vector.md: (frm_mode) Add vfwmul to frm_mode.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-widening-mul.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 3 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
gcc/config/riscv/vector.md| 2 +-
.../riscv/rvv/base/float-point-widening-mul.c | 44 +++
5 files changed, 51 insertions(+), 1 deletion(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 95ec9ccb481..8d689f0c935 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -321,6 +321,7 @@ public:
/* Implements below instructions for frm
- vfwadd
- vfwsub
+ - vfwmul
*/
template
class widen_binop_frm : public function_base
@@ -2112,6 +2113,7 @@ static CONSTEXPR const binop_frm vfdiv_frm_obj;
static CONSTEXPR const reverse_binop vfrdiv_obj;
static CONSTEXPR const reverse_binop_frm vfrdiv_frm_obj;
static CONSTEXPR const widen_binop vfwmul_obj;
+static CONSTEXPR const widen_binop_frm vfwmul_frm_obj;
static CONSTEXPR const vfmacc vfmacc_obj;
static CONSTEXPR const vfnmsac vfnmsac_obj;
static CONSTEXPR const vfmadd vfmadd_obj;
@@ -2346,6 +2348,7 @@ BASE (vfdiv_frm)
BASE (vfrdiv)
BASE (vfrdiv_frm)
BASE (vfwmul)
+BASE (vfwmul_frm)
BASE (vfmacc)
BASE (vfnmsac)
BASE (vfmadd)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index f35fd3d27cf..2d2b52a312c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -158,6 +158,7 @@ extern const function_base *const vfdiv_frm;
extern const function_base *const vfrdiv;
extern const function_base *const vfrdiv_frm;
extern const function_base *const vfwmul;
+extern const function_base *const vfwmul_frm;
extern const function_base *const vfmacc;
extern const function_base *const vfnmsac;
extern const function_base *const vfmadd;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index e7e6c7d8ed8..d43b33ded17 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -328,6 +328,8 @@ DEF_RVV_FUNCTION (vfrdiv_frm, alu_frm, full_preds,
f_vvf_ops)
// 13.5. Vector Widening Floating-Point Multiply
DEF_RVV_FUNCTION (vfwmul, alu, full_preds, f_wvv_ops)
DEF_RVV_FUNCTION (vfwmul, alu, full_preds, f_wvf_ops)
+DEF_RVV_FUNCTION (vfwmul_frm, alu_frm, full_preds, f_wvv_ops)
+DEF_RVV_FUNCTION (vfwmul_frm, alu_frm, full_preds, f_wvf_ops)
// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
DEF_RVV_FUNCTION (vfmacc, alu, full_preds, f__ops)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 4b6c3859947..750b2de8df9 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -866,7 +866,7 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
;; Defines rounding mode of an floating-point operation.
(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
- (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv")
+ (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
(cond
[(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
(const_string "rne")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c
new file mode 100644
index 000..893fa866a31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-mul.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat64m2_t
+test_vfwmul_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfwmul_vv_f64m2_rm (op1, op2, 0, vl);
+}
+
+vfloat64m2_t
+test_vfwmul_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfwmul_vv_f64m2_rm_m (mask, op1, op2,
[PATCH v1] RISC-V: Support RVV VFDIV and VFRDIV rounding mode intrinsic API
From: Pan Li This patch would like to support the rounding mode API for the VFDIV and VFRDIV for the below samples. * __riscv_vfdiv_vv_f32m1_rm * __riscv_vfdiv_vv_f32m1_rm_m * __riscv_vfdiv_vf_f32m1_rm * __riscv_vfdiv_vf_f32m1_rm_m * __riscv_vfrdiv_vf_f32m1_rm * __riscv_vfrdiv_vf_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (binop_frm): New declaration. (reverse_binop_frm): Likewise. (BASE): Likewise. * config/riscv/riscv-vector-builtins-bases.h: (vfdiv_frm): New extern declaration. (vfrdiv_frm): Likewise. * config/riscv/riscv-vector-builtins-functions.def (vfdiv_frm): New function definition. (vfrdiv_frm): Likewise. * config/riscv/vector.md: Add vfdiv to frm_mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-single-div.c: New test. * gcc.target/riscv/rvv/base/float-point-single-rdiv.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 6 +++ .../riscv/riscv-vector-builtins-bases.h | 2 + .../riscv/riscv-vector-builtins-functions.def | 3 ++ gcc/config/riscv/vector.md| 2 +- .../riscv/rvv/base/float-point-single-div.c | 44 +++ .../riscv/rvv/base/float-point-single-rdiv.c | 33 ++ 6 files changed, 89 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-div.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rdiv.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 3adc11138a3..95ec9ccb481 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -278,6 +278,7 @@ public: /* Implements below instructions for now. - vfadd - vfmul + - vfdiv */ template class binop_frm : public function_base @@ -301,6 +302,7 @@ public: /* Implements below instructions for frm - vfrsub + - vfrdiv */ template class reverse_binop_frm : public function_base @@ -2106,7 +2108,9 @@ static CONSTEXPR const widen_binop_frm vfwsub_frm_obj; static CONSTEXPR const binop vfmul_obj; static CONSTEXPR const binop_frm vfmul_frm_obj; static CONSTEXPR const binop vfdiv_obj; +static CONSTEXPR const binop_frm vfdiv_frm_obj; static CONSTEXPR const reverse_binop vfrdiv_obj; +static CONSTEXPR const reverse_binop_frm vfrdiv_frm_obj; static CONSTEXPR const widen_binop vfwmul_obj; static CONSTEXPR const vfmacc vfmacc_obj; static CONSTEXPR const vfnmsac vfnmsac_obj; @@ -2338,7 +2342,9 @@ BASE (vfwsub_frm) BASE (vfmul) BASE (vfmul_frm) BASE (vfdiv) +BASE (vfdiv_frm) BASE (vfrdiv) +BASE (vfrdiv_frm) BASE (vfwmul) BASE (vfmacc) BASE (vfnmsac) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 9c12a6b4e8f..f35fd3d27cf 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -154,7 +154,9 @@ extern const function_base *const vfwsub_frm; extern const function_base *const vfmul; extern const function_base *const vfmul_frm; extern const function_base *const vfdiv; +extern const function_base *const vfdiv_frm; extern const function_base *const vfrdiv; +extern const function_base *const vfrdiv_frm; extern const function_base *const vfwmul; extern const function_base *const vfmacc; extern const function_base *const vfnmsac; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 35a83ef239c..e7e6c7d8ed8 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -321,6 +321,9 @@ DEF_RVV_FUNCTION (vfdiv, alu, full_preds, f_vvf_ops) DEF_RVV_FUNCTION (vfrdiv, alu, full_preds, f_vvf_ops) DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvv_ops) DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvf_ops) +DEF_RVV_FUNCTION (vfdiv_frm, alu_frm, full_preds, f_vvv_ops) +DEF_RVV_FUNCTION (vfdiv_frm, alu_frm, full_preds, f_vvf_ops) +DEF_RVV_FUNCTION (vfrdiv_frm, alu_frm, full_preds, f_vvf_ops) // 13.5. Vector Widening Floating-Point Multiply DEF_RVV_FUNCTION (vfwmul, alu, full_preds, f_wvv_ops) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 5d3e4256cd5..4b6c3859947 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -866,7 +866,7 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none" ;; Defines rounding mode of an floating-point operation. (define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none" - (cond [(eq_attr "type" "vfalu,vfwalu,vfmul") + (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv") (cond [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE") (const_string "rne") diff --git
[PATCH v2] RISC-V: Support RVV VFMUL rounding mode intrinsic API
From: Pan Li
Update in v2:
* Sync with upstream for the vfmul duplicated declaration.
Original log:
This patch would like to support the rounding mode API for the VFMUL
for the below samples.
* __riscv_vfmul_vv_f32m1_rm
* __riscv_vfmul_vv_f32m1_rm_m
* __riscv_vfmul_vf_f32m1_rm
* __riscv_vfmul_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(vfmul_frm_obj): New declaration.
(Base): Likewise.
* config/riscv/riscv-vector-builtins-bases.h: Likewise.
* config/riscv/riscv-vector-builtins-functions.def
(vfmul_frm): New function definition.
* config/riscv/vector.md: Add vfmul to frm_mode.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-mul.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 3 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 +
gcc/config/riscv/vector.md| 2 +-
.../riscv/rvv/base/float-point-single-mul.c | 44 +++
5 files changed, 51 insertions(+), 1 deletion(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index ddf694c771c..3adc11138a3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -277,6 +277,7 @@ public:
/* Implements below instructions for now.
- vfadd
+ - vfmul
*/
template
class binop_frm : public function_base
@@ -2103,6 +2104,7 @@ static CONSTEXPR const widen_binop_frm
vfwadd_frm_obj;
static CONSTEXPR const widen_binop vfwsub_obj;
static CONSTEXPR const widen_binop_frm vfwsub_frm_obj;
static CONSTEXPR const binop vfmul_obj;
+static CONSTEXPR const binop_frm vfmul_frm_obj;
static CONSTEXPR const binop vfdiv_obj;
static CONSTEXPR const reverse_binop vfrdiv_obj;
static CONSTEXPR const widen_binop vfwmul_obj;
@@ -2334,6 +2336,7 @@ BASE (vfwadd_frm)
BASE (vfwsub)
BASE (vfwsub_frm)
BASE (vfmul)
+BASE (vfmul_frm)
BASE (vfdiv)
BASE (vfrdiv)
BASE (vfwmul)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index f40b022239d..9c12a6b4e8f 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -152,6 +152,7 @@ extern const function_base *const vfwadd_frm;
extern const function_base *const vfwsub;
extern const function_base *const vfwsub_frm;
extern const function_base *const vfmul;
+extern const function_base *const vfmul_frm;
extern const function_base *const vfdiv;
extern const function_base *const vfrdiv;
extern const function_base *const vfwmul;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 58a7224fe0c..35a83ef239c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -319,6 +319,8 @@ DEF_RVV_FUNCTION (vfmul, alu, full_preds, f_vvf_ops)
DEF_RVV_FUNCTION (vfdiv, alu, full_preds, f_vvv_ops)
DEF_RVV_FUNCTION (vfdiv, alu, full_preds, f_vvf_ops)
DEF_RVV_FUNCTION (vfrdiv, alu, full_preds, f_vvf_ops)
+DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvv_ops)
+DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvf_ops)
// 13.5. Vector Widening Floating-Point Multiply
DEF_RVV_FUNCTION (vfwmul, alu, full_preds, f_wvv_ops)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 65f36744f54..5d3e4256cd5 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -866,7 +866,7 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
;; Defines rounding mode of an floating-point operation.
(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
- (cond [(eq_attr "type" "vfalu,vfwalu")
+ (cond [(eq_attr "type" "vfalu,vfwalu,vfmul")
(cond
[(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
(const_string "rne")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c
new file mode 100644
index 000..e6410ea3a37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfmul_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfmul_vv_f32m1_rm (op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfmul_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfmul_vv_f32m1_rm_m (mask, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
[PATCH v1] RISC-V: Remove redudant extern declaration in function base
From: Pan Li This patch would like to remove the redudant declaration. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.h: Remove redudant declaration. --- gcc/config/riscv/riscv-vector-builtins-bases.h | 1 - 1 file changed, 1 deletion(-) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 5800fca0169..f40b022239d 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -152,7 +152,6 @@ extern const function_base *const vfwadd_frm; extern const function_base *const vfwsub; extern const function_base *const vfwsub_frm; extern const function_base *const vfmul; -extern const function_base *const vfmul; extern const function_base *const vfdiv; extern const function_base *const vfrdiv; extern const function_base *const vfwmul; -- 2.34.1
[PATCH v1] RISC-V: Support RVV VFMUL rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the VFMUL
for the below samples.
* __riscv_vfmul_vv_f32m1_rm
* __riscv_vfmul_vv_f32m1_rm_m
* __riscv_vfmul_vf_f32m1_rm
* __riscv_vfmul_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(vfmul_frm_obj): New declaration.
(Base): Likewise.
* config/riscv/riscv-vector-builtins-bases.h: Likewise.
* config/riscv/riscv-vector-builtins-functions.def
(vfmul_frm): New function definition.
* config/riscv/vector.md: Add vfmul to frm_mode.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-mul.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 3 ++
.../riscv/riscv-vector-builtins-bases.h | 2 +-
.../riscv/riscv-vector-builtins-functions.def | 2 +
gcc/config/riscv/vector.md| 2 +-
.../riscv/rvv/base/float-point-single-mul.c | 44 +++
5 files changed, 51 insertions(+), 2 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index ddf694c771c..3adc11138a3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -277,6 +277,7 @@ public:
/* Implements below instructions for now.
- vfadd
+ - vfmul
*/
template
class binop_frm : public function_base
@@ -2103,6 +2104,7 @@ static CONSTEXPR const widen_binop_frm
vfwadd_frm_obj;
static CONSTEXPR const widen_binop vfwsub_obj;
static CONSTEXPR const widen_binop_frm vfwsub_frm_obj;
static CONSTEXPR const binop vfmul_obj;
+static CONSTEXPR const binop_frm vfmul_frm_obj;
static CONSTEXPR const binop vfdiv_obj;
static CONSTEXPR const reverse_binop vfrdiv_obj;
static CONSTEXPR const widen_binop vfwmul_obj;
@@ -2334,6 +2336,7 @@ BASE (vfwadd_frm)
BASE (vfwsub)
BASE (vfwsub_frm)
BASE (vfmul)
+BASE (vfmul_frm)
BASE (vfdiv)
BASE (vfrdiv)
BASE (vfwmul)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 5800fca0169..9c12a6b4e8f 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -152,7 +152,7 @@ extern const function_base *const vfwadd_frm;
extern const function_base *const vfwsub;
extern const function_base *const vfwsub_frm;
extern const function_base *const vfmul;
-extern const function_base *const vfmul;
+extern const function_base *const vfmul_frm;
extern const function_base *const vfdiv;
extern const function_base *const vfrdiv;
extern const function_base *const vfwmul;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 58a7224fe0c..35a83ef239c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -319,6 +319,8 @@ DEF_RVV_FUNCTION (vfmul, alu, full_preds, f_vvf_ops)
DEF_RVV_FUNCTION (vfdiv, alu, full_preds, f_vvv_ops)
DEF_RVV_FUNCTION (vfdiv, alu, full_preds, f_vvf_ops)
DEF_RVV_FUNCTION (vfrdiv, alu, full_preds, f_vvf_ops)
+DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvv_ops)
+DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvf_ops)
// 13.5. Vector Widening Floating-Point Multiply
DEF_RVV_FUNCTION (vfwmul, alu, full_preds, f_wvv_ops)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 65f36744f54..5d3e4256cd5 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -866,7 +866,7 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
;; Defines rounding mode of an floating-point operation.
(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
- (cond [(eq_attr "type" "vfalu,vfwalu")
+ (cond [(eq_attr "type" "vfalu,vfwalu,vfmul")
(cond
[(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE")
(const_string "rne")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c
new file mode 100644
index 000..e6410ea3a37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfmul_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfmul_vv_f32m1_rm (op1, op2, 0, vl);
+}
+
+vfloat32m1_t
+test_vfmul_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfmul_vv_f32m1_rm_m (mask, op1, op2, 1, vl);
+}
+
+vfloat32m1_t
+test_vfmul_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t
[PATCH v1] RISC-V: Support RVV VFWSUB rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the VFWSUB
for the below samples.
* __riscv_vfwsub_vv_f64m2_rm
* __riscv_vfwsub_vv_f64m2_rm_m
* __riscv_vfwsub_vf_f64m2_rm
* __riscv_vfwsub_vf_f64m2_rm_m
* __riscv_vfwsub_wv_f64m2_rm
* __riscv_vfwsub_wv_f64m2_rm_m
* __riscv_vfwsub_wf_f64m2_rm
* __riscv_vfwsub_wf_f64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (BASE): Add
vfwsub frm.
* config/riscv/riscv-vector-builtins-bases.h: Add declaration.
* config/riscv/riscv-vector-builtins-functions.def (vfwsub_frm):
Add vfwsub function definitions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-widening-sub.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 3 +
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 4 ++
.../riscv/rvv/base/float-point-widening-sub.c | 66 +++
4 files changed, 74 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 981a4a7ede8..ddf694c771c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -317,6 +317,7 @@ public:
/* Implements below instructions for frm
- vfwadd
+ - vfwsub
*/
template
class widen_binop_frm : public function_base
@@ -2100,6 +2101,7 @@ static CONSTEXPR const reverse_binop_frm
vfrsub_frm_obj;
static CONSTEXPR const widen_binop vfwadd_obj;
static CONSTEXPR const widen_binop_frm vfwadd_frm_obj;
static CONSTEXPR const widen_binop vfwsub_obj;
+static CONSTEXPR const widen_binop_frm vfwsub_frm_obj;
static CONSTEXPR const binop vfmul_obj;
static CONSTEXPR const binop vfdiv_obj;
static CONSTEXPR const reverse_binop vfrdiv_obj;
@@ -2330,6 +2332,7 @@ BASE (vfrsub_frm)
BASE (vfwadd)
BASE (vfwadd_frm)
BASE (vfwsub)
+BASE (vfwsub_frm)
BASE (vfmul)
BASE (vfdiv)
BASE (vfrdiv)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index f9e1df5fe75..5800fca0169 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -150,6 +150,7 @@ extern const function_base *const vfrsub_frm;
extern const function_base *const vfwadd;
extern const function_base *const vfwadd_frm;
extern const function_base *const vfwsub;
+extern const function_base *const vfwsub_frm;
extern const function_base *const vfmul;
extern const function_base *const vfmul;
extern const function_base *const vfdiv;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 743205a9b97..58a7224fe0c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -306,8 +306,12 @@ DEF_RVV_FUNCTION (vfwsub, widen_alu, full_preds, f_wwv_ops)
DEF_RVV_FUNCTION (vfwsub, widen_alu, full_preds, f_wwf_ops)
DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wvv_ops)
DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wvf_ops)
+DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wvv_ops)
+DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wvf_ops)
DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wwv_ops)
DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wwf_ops)
+DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wwv_ops)
+DEF_RVV_FUNCTION (vfwsub_frm, widen_alu_frm, full_preds, f_wwf_ops)
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
DEF_RVV_FUNCTION (vfmul, alu, full_preds, f_vvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c
new file mode 100644
index 000..4325cc510a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-sub.c
@@ -0,0 +1,66 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat64m2_t
+test_vfwsub_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfwsub_vv_f64m2_rm (op1, op2, 0, vl);
+}
+
+vfloat64m2_t
+test_vfwsub_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfwsub_vv_f64m2_rm_m (mask, op1, op2, 1, vl);
+}
+
+vfloat64m2_t
+test_vfwsub_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) {
+ return __riscv_vfwsub_vf_f64m2_rm (op1, op2, 2, vl);
+}
+
+vfloat64m2_t
+test_vfwsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+ size_t vl) {
+ return __riscv_vfwsub_vf_f64m2_rm_m
[PATCH v1] RISC-V: Enhance the test case for RVV vfsub/vfrsub rounding
From: Pan Li
This patch would like to enhance the vfsub/vfrsub rounding API test for
below 2 purposes.
* The non-rm API has no frm related insn generated.
* The rm API has the frm backup/restore/set insn generated.
Signed-off-by: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-rsub.c: Enhance
cases.
* gcc.target/riscv/rvv/base/float-point-single-sub.c: Ditto.
---
.../riscv/rvv/base/float-point-single-rsub.c | 16 +++-
.../riscv/rvv/base/float-point-single-sub.c | 16 +++-
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
index 1d770adc32c..86c56b7c6cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
@@ -16,4 +16,18 @@ test_vfrsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1,
float32_t op2,
return __riscv_vfrsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl);
}
-/* { dg-final { scan-assembler-times
{vfrsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
+vfloat32m1_t
+test_vfrsub_vf_f32m1 (vfloat32m1_t op1, float32_t op2, size_t vl) {
+ return __riscv_vfrsub_vf_f32m1 (op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfrsub_vf_f32m1_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+ size_t vl) {
+ return __riscv_vfrsub_vf_f32m1_m (mask, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times
{vfrsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
index 34ed03a31d9..8075dced0b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
@@ -27,4 +27,18 @@ test_vfsub_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1,
float32_t op2,
return __riscv_vfsub_vf_f32m1_rm_m (mask, op1, op2, 3, vl);
}
-/* { dg-final { scan-assembler-times
{vfsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+vfloat32m1_t
+test_riscv_vfsub_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+ return __riscv_vfsub_vv_f32m1 (op1, op2, vl);
+}
+
+vfloat32m1_t
+test_vfsub_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfsub_vv_f32m1_m (mask, op1, op2, vl);
+}
+
+/* { dg-final { scan-assembler-times
{vfsub\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */
--
2.34.1
[PATCH v2] RISC-V: Support RVV VFWADD rounding mode intrinsic API
From: Pan Li
Update in v2:
1. Add vfwalu type to frm_mode.
2. Enhance the test cases for frm.
Original log:
This patch would like to support the rounding mode API for the VFWADD
VFSUB and VFRSUB as below samples.
* __riscv_vfwadd_vv_f64m2_rm
* __riscv_vfwadd_vv_f64m2_rm_m
* __riscv_vfwadd_vf_f64m2_rm
* __riscv_vfwadd_vf_f64m2_rm_m
* __riscv_vfwadd_wv_f64m2_rm
* __riscv_vfwadd_wv_f64m2_rm_m
* __riscv_vfwadd_wf_f64m2_rm
* __riscv_vfwadd_wf_f64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class widen_binop_frm): New class for binop frm.
(BASE): Add vfwadd_frm.
* config/riscv/riscv-vector-builtins-bases.h: New declaration.
* config/riscv/riscv-vector-builtins-functions.def
(vfwadd_frm): New function definition.
* config/riscv/riscv-vector-builtins-shapes.cc
(BASE_NAME_MAX_LEN): New macro.
(struct alu_frm_def): Leverage new base class.
(struct build_frm_base): New build base for frm.
(struct widen_alu_frm_def): New struct for widen alu frm.
(SHAPE): Add widen_alu_frm shape.
* config/riscv/riscv-vector-builtins-shapes.h: New declaration.
* config/riscv/vector.md (frm_mode): Add vfwalu type.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-widening-add.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 37 +++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 4 ++
.../riscv/riscv-vector-builtins-shapes.cc | 66 +++
.../riscv/riscv-vector-builtins-shapes.h | 1 +
gcc/config/riscv/vector.md| 2 +-
.../riscv/rvv/base/float-point-widening-add.c | 66 +++
7 files changed, 164 insertions(+), 13 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-add.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 035cafc43b3..981a4a7ede8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -315,6 +315,41 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfwadd
+*/
+template
+class widen_binop_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+ {
+ case OP_TYPE_vv:
+ return e.use_exact_insn (
+ code_for_pred_dual_widen (CODE, e.vector_mode ()));
+ case OP_TYPE_vf:
+ return e.use_exact_insn (
+ code_for_pred_dual_widen_scalar (CODE, e.vector_mode ()));
+ case OP_TYPE_wv:
+ if (CODE == PLUS)
+ return e.use_exact_insn (
+ code_for_pred_single_widen_add (e.vector_mode ()));
+ else
+ return e.use_exact_insn (
+ code_for_pred_single_widen_sub (e.vector_mode ()));
+ case OP_TYPE_wf:
+ return e.use_exact_insn (
+ code_for_pred_single_widen_scalar (CODE, e.vector_mode ()));
+ default:
+ gcc_unreachable ();
+ }
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2063,6 +2098,7 @@ static CONSTEXPR const binop_frm vfsub_frm_obj;
static CONSTEXPR const reverse_binop vfrsub_obj;
static CONSTEXPR const reverse_binop_frm vfrsub_frm_obj;
static CONSTEXPR const widen_binop vfwadd_obj;
+static CONSTEXPR const widen_binop_frm vfwadd_frm_obj;
static CONSTEXPR const widen_binop vfwsub_obj;
static CONSTEXPR const binop vfmul_obj;
static CONSTEXPR const binop vfdiv_obj;
@@ -2292,6 +2328,7 @@ BASE (vfsub_frm)
BASE (vfrsub)
BASE (vfrsub_frm)
BASE (vfwadd)
+BASE (vfwadd_frm)
BASE (vfwsub)
BASE (vfmul)
BASE (vfdiv)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 5c6b239c274..f9e1df5fe75 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -148,6 +148,7 @@ extern const function_base *const vfsub_frm;
extern const function_base *const vfrsub;
extern const function_base *const vfrsub_frm;
extern const function_base *const vfwadd;
+extern const function_base *const vfwadd_frm;
extern const function_base *const vfwsub;
extern const function_base *const vfmul;
extern const function_base *const vfmul;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index fa1c2cef970..743205a9b97 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -304,6 +304,10 @@ DEF_RVV_FUNCTION (vfwadd, widen_alu, full_preds, f_wwv_ops)
DEF_RVV_FUNCTION (vfwadd, widen_alu, full_preds, f_wwf_ops)
DEF_RVV_FUNCTION (vfwsub, widen_alu, full_preds, f_wwv_ops)
DEF_RVV_FUNCTION (vfwsub,
[PATCH v1] RISC-V: Support RVV VFWADD rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the VFWADD
VFSUB and VFRSUB as below samples.
* __riscv_vfwadd_vv_f64m2_rm
* __riscv_vfwadd_vv_f64m2_rm_m
* __riscv_vfwadd_vf_f64m2_rm
* __riscv_vfwadd_vf_f64m2_rm_m
* __riscv_vfwadd_wv_f64m2_rm
* __riscv_vfwadd_wv_f64m2_rm_m
* __riscv_vfwadd_wf_f64m2_rm
* __riscv_vfwadd_wf_f64m2_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class widen_binop_frm): New class for binop frm.
(BASE): Add vfwadd_frm.
* config/riscv/riscv-vector-builtins-bases.h: New declaration.
* config/riscv/riscv-vector-builtins-functions.def
(vfwadd_frm): New function definition.
* config/riscv/riscv-vector-builtins-shapes.cc
(BASE_NAME_MAX_LEN): New macro.
(struct alu_frm_def): Leverage new base class.
(struct build_frm_base): New build base for frm.
(struct widen_alu_frm_def): New struct for widen alu frm.
(SHAPE): Add widen_alu_frm shape.
* config/riscv/riscv-vector-builtins-shapes.h: New declaration.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-widening-add.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 37 +++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 4 ++
.../riscv/riscv-vector-builtins-shapes.cc | 66 +++
.../riscv/riscv-vector-builtins-shapes.h | 1 +
.../riscv/rvv/base/float-point-widening-add.c | 52 +++
6 files changed, 149 insertions(+), 12 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-widening-add.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 035cafc43b3..981a4a7ede8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -315,6 +315,41 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfwadd
+*/
+template
+class widen_binop_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+ {
+ case OP_TYPE_vv:
+ return e.use_exact_insn (
+ code_for_pred_dual_widen (CODE, e.vector_mode ()));
+ case OP_TYPE_vf:
+ return e.use_exact_insn (
+ code_for_pred_dual_widen_scalar (CODE, e.vector_mode ()));
+ case OP_TYPE_wv:
+ if (CODE == PLUS)
+ return e.use_exact_insn (
+ code_for_pred_single_widen_add (e.vector_mode ()));
+ else
+ return e.use_exact_insn (
+ code_for_pred_single_widen_sub (e.vector_mode ()));
+ case OP_TYPE_wf:
+ return e.use_exact_insn (
+ code_for_pred_single_widen_scalar (CODE, e.vector_mode ()));
+ default:
+ gcc_unreachable ();
+ }
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2063,6 +2098,7 @@ static CONSTEXPR const binop_frm vfsub_frm_obj;
static CONSTEXPR const reverse_binop vfrsub_obj;
static CONSTEXPR const reverse_binop_frm vfrsub_frm_obj;
static CONSTEXPR const widen_binop vfwadd_obj;
+static CONSTEXPR const widen_binop_frm vfwadd_frm_obj;
static CONSTEXPR const widen_binop vfwsub_obj;
static CONSTEXPR const binop vfmul_obj;
static CONSTEXPR const binop vfdiv_obj;
@@ -2292,6 +2328,7 @@ BASE (vfsub_frm)
BASE (vfrsub)
BASE (vfrsub_frm)
BASE (vfwadd)
+BASE (vfwadd_frm)
BASE (vfwsub)
BASE (vfmul)
BASE (vfdiv)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 5c6b239c274..f9e1df5fe75 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -148,6 +148,7 @@ extern const function_base *const vfsub_frm;
extern const function_base *const vfrsub;
extern const function_base *const vfrsub_frm;
extern const function_base *const vfwadd;
+extern const function_base *const vfwadd_frm;
extern const function_base *const vfwsub;
extern const function_base *const vfmul;
extern const function_base *const vfmul;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index fa1c2cef970..743205a9b97 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -304,6 +304,10 @@ DEF_RVV_FUNCTION (vfwadd, widen_alu, full_preds, f_wwv_ops)
DEF_RVV_FUNCTION (vfwadd, widen_alu, full_preds, f_wwf_ops)
DEF_RVV_FUNCTION (vfwsub, widen_alu, full_preds, f_wwv_ops)
DEF_RVV_FUNCTION (vfwsub, widen_alu, full_preds, f_wwf_ops)
+DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wvv_ops)
+DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm, full_preds, f_wvf_ops)
+DEF_RVV_FUNCTION (vfwadd_frm, widen_alu_frm,
[PATCH v1] RISC-V: Support RVV VFSUB and VFRSUB rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for both the
VFSUB and VFRSUB as below samples.
* __riscv_vfsub_vv_f32m1_rm
* __riscv_vfsub_vv_f32m1_rm_m
* __riscv_vfsub_vf_f32m1_rm
* __riscv_vfsub_vf_f32m1_rm_m
* __riscv_vfrsub_vf_f32m1_rm
* __riscv_vfrsub_vf_f32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class reverse_binop_frm): Add new template for reversed frm.
(vfsub_frm_obj): New obj.
(vfrsub_frm_obj): Likewise.
* config/riscv/riscv-vector-builtins-bases.h:
(vfsub_frm): New declaration.
(vfrsub_frm): Likewise.
* config/riscv/riscv-vector-builtins-functions.def
(vfsub_frm): New function define.
(vfrsub_frm): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-single-rsub.c: New test.
* gcc.target/riscv/rvv/base/float-point-single-sub.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 21 +
.../riscv/riscv-vector-builtins-bases.h | 2 ++
.../riscv/riscv-vector-builtins-functions.def | 3 ++
.../riscv/rvv/base/float-point-single-rsub.c | 19
.../riscv/rvv/base/float-point-single-sub.c | 30 +++
5 files changed, 75 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-sub.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 316b35b57c8..035cafc43b3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -298,6 +298,23 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfrsub
+*/
+template
+class reverse_binop_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+public:
+ rtx expand (function_expander ) const override
+ {
+return e.use_exact_insn (
+ code_for_pred_reverse_scalar (CODE, e.vector_mode ()));
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2042,7 +2059,9 @@ static CONSTEXPR const vid vid_obj;
static CONSTEXPR const binop vfadd_obj;
static CONSTEXPR const binop vfsub_obj;
static CONSTEXPR const binop_frm vfadd_frm_obj;
+static CONSTEXPR const binop_frm vfsub_frm_obj;
static CONSTEXPR const reverse_binop vfrsub_obj;
+static CONSTEXPR const reverse_binop_frm vfrsub_frm_obj;
static CONSTEXPR const widen_binop vfwadd_obj;
static CONSTEXPR const widen_binop vfwsub_obj;
static CONSTEXPR const binop vfmul_obj;
@@ -2269,7 +2288,9 @@ BASE (vid)
BASE (vfadd)
BASE (vfadd_frm)
BASE (vfsub)
+BASE (vfsub_frm)
BASE (vfrsub)
+BASE (vfrsub_frm)
BASE (vfwadd)
BASE (vfwsub)
BASE (vfmul)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index e771a36adc8..5c6b239c274 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -144,7 +144,9 @@ extern const function_base *const vid;
extern const function_base *const vfadd;
extern const function_base *const vfadd_frm;
extern const function_base *const vfsub;
+extern const function_base *const vfsub_frm;
extern const function_base *const vfrsub;
+extern const function_base *const vfrsub_frm;
extern const function_base *const vfwadd;
extern const function_base *const vfwsub;
extern const function_base *const vfmul;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 035c9e4252f..fa1c2cef970 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -291,6 +291,9 @@ DEF_RVV_FUNCTION (vfsub, alu, full_preds, f_vvf_ops)
DEF_RVV_FUNCTION (vfrsub, alu, full_preds, f_vvf_ops)
DEF_RVV_FUNCTION (vfadd_frm, alu_frm, full_preds, f_vvv_ops)
DEF_RVV_FUNCTION (vfadd_frm, alu_frm, full_preds, f_vvf_ops)
+DEF_RVV_FUNCTION (vfsub_frm, alu_frm, full_preds, f_vvv_ops)
+DEF_RVV_FUNCTION (vfsub_frm, alu_frm, full_preds, f_vvf_ops)
+DEF_RVV_FUNCTION (vfrsub_frm, alu_frm, full_preds, f_vvf_ops)
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
DEF_RVV_FUNCTION (vfwadd, widen_alu, full_preds, f_wvv_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
new file mode 100644
index 000..1d770adc32c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-rsub.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_vfrsub_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) {
+ return
[PATCH v1] RISC-V: Bugfix for RVV floating-point rm suffix sequence
From: Pan Li
According to below RVV intrinsic doc, the RVV floating-point intrinsic name
with rounding mode should be:
_rm_m
instead of:
_m_rm
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
This patch fix this naming sequence issue and adjust the test cases.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_frm_def):
Move rm suffix before mask.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-insert-1.c: Adjust
test cases.
* gcc.target/riscv/rvv/base/float-point-frm.c: Ditto.
---
gcc/config/riscv/riscv-vector-builtins-shapes.cc | 10 +-
.../riscv/rvv/base/float-point-frm-insert-1.c| 14 +++---
.../gcc.target/riscv/rvv/base/float-point-frm.c | 16
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 22b5fe256df..6af57c22bfb 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -261,6 +261,11 @@ struct alu_frm_def : public build_base
b.append_name (type_suffixes[instance.type.index].vector);
}
+/* According to rvv-intrinsic-doc, it does not add "_rm" suffix
+ for vop_rm C++ overloaded API. */
+if (!overloaded_p)
+ b.append_name ("_rm");
+
/* According to rvv-intrinsic-doc, it does not add "_m" suffix
for vop_m C++ overloaded API. */
if (overloaded_p && instance.pred == PRED_TYPE_m)
@@ -268,11 +273,6 @@ struct alu_frm_def : public build_base
b.append_name (predication_suffixes[instance.pred]);
-/* According to rvv-intrinsic-doc, it does not add "_rm" suffix
- for vop_rm C++ overloaded API. */
-if (!overloaded_p)
- b.append_name ("_rm");
-
return b.finish_name ();
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c
index 608b3883dd0..d6c5e1bddd6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-1.c
@@ -11,20 +11,20 @@ test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1,
vfloat32m1_t op2, size_t vl) {
}
vfloat32m1_t
-test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+test_vfadd_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
size_t vl) {
- return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 1, vl);
+ return __riscv_vfadd_vv_f32m1_rm_m (mask, op1, op2, 1, vl);
}
vfloat32m1_t
-test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) {
- return __riscv_vfadd_vf_f32m1_rm(op1, op2, 2, vl);
+test_vfadd_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) {
+ return __riscv_vfadd_vf_f32m1_rm (op1, op2, 2, vl);
}
vfloat32m1_t
-test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
-size_t vl) {
- return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 3, vl);
+test_vfadd_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+ size_t vl) {
+ return __riscv_vfadd_vf_f32m1_rm_m (mask, op1, op2, 3, vl);
}
/* { dg-final { scan-assembler-times
{vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm.c
index 95271b2c822..1f142605cc3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm.c
@@ -11,20 +11,20 @@ test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1,
vfloat32m1_t op2, size_t vl) {
}
vfloat32m1_t
-test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
-size_t vl) {
- return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 0, vl);
+test_vfadd_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+ return __riscv_vfadd_vv_f32m1_rm_m (mask, op1, op2, 0, vl);
}
vfloat32m1_t
-test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) {
- return __riscv_vfadd_vf_f32m1_rm(op1, op2, 0, vl);
+test_vfadd_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) {
+ return __riscv_vfadd_vf_f32m1_rm (op1, op2, 0, vl);
}
vfloat32m1_t
-test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
-size_t vl) {
- return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 0, vl);
+test_vfadd_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+ size_t vl) {
+ return __riscv_vfadd_vf_f32m1_rm_m (mask, op1, op2, 0, vl);
}
/* { dg-final { scan-assembler-times
{vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
--
2.34.1
[PATCH v8] RISC-V: Support CALL for RVV floating-point dynamic rounding
From: Pan Li Update in PATCH v8: 1. Emit non-abnormal backup insn to edge. 2. Fix _after return when call. 3. Refine some run tests. 4. Cleanup code. Original commit logs: In basic dynamic rounding mode, we simply ignore call instructions and we would like to take care of call in this PATCH. During the call, the frm may be updated or keep as is. Thus, we must make sure at least 2 things. 1. The static frm before call should not pollute the frm value in call. 2. The updated frm value in call should be sticky after call completed. We will perfrom some steps to make above happen. 1. Mark call instruction with new mode DYN_CALL. 2. Mark the instruction after CALL from NONE to DYN. 3. When emit for a DYN_CALL, we will restore the frm value. 4. When emit from a DYN_CALL, we will backup the frm value. Let's take a flow for this. +-+ | Entry (DYN) | <- frrm a5 +-+ / \ +---+ +---+ | VFADD | | VFADD RTZ | <- fsrmi 1(RTZ) +---+ +---+ || +---+ +---+ | CALL | | CALL | <- fsrm a5 +---+ +---+ | | +---+ +---+ | SHIFT | <- frrm a5 | VFADD | <- frrm a5 +---+ +---+ | / +---+ / | VFADD RUP | <- fsrm1 3(RUP) +---+ / \ / +-+ | Exit (DYN_EXIT) | <- fsrm a5 +-+ When call is the last insn of one bb, we take care of it when needed for each insn by inserting one frm backup (frrm) insn to the end of the current bb. Signed-off-by: Pan Li Co-Authored-By: Juzhe-Zhong gcc/ChangeLog: * config/riscv/riscv.cc (DYNAMIC_FRM_RTL): New macro. (STATIC_FRM_P): Ditto. (struct mode_switching_info): New struct for mode switching. (struct machine_function): Add new field mode switching. (riscv_emit_frm_mode_set): Add DYN_CALL emit. (riscv_frm_adjust_mode_after_call): New function for call mode. (riscv_frm_emit_after_call_in_bb_end): New function for emit insn when call as the end of bb. (riscv_frm_mode_needed): New function for frm mode needed. (frm_unknown_dynamic_p): Remove call check. (riscv_mode_needed): Extrac function for frm. (riscv_frm_mode_after): Add DYN_CALL after. (riscv_mode_entry): Remove backup rtl initialization. * config/riscv/vector.md (frm_mode): Add dyn_call. (fsrmsi_restore_exit): Rename to _volatile. (fsrmsi_restore_volatile): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: Adjust test cases. * gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-run-2.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-run-3.c: Ditto. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-38.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-40.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-42.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-43.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-44.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-47.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-51.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-53.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-54.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-55.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c: New test. *
[PATCH v1] RISC-V: Remove unnecessary vread_csr/vwrite_csr intrinsic.
From: Pan Li
According to below RVV doc, the related intrinsic is not longer needed.
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/249
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv_vector.h (enum RVV_CSR): Removed.
(vread_csr): Ditto.
(vwrite_csr): Ditto.
---
gcc/config/riscv/riscv_vector.h | 51 -
1 file changed, 51 deletions(-)
diff --git a/gcc/config/riscv/riscv_vector.h b/gcc/config/riscv/riscv_vector.h
index ff54b6be863..3366fd972b5 100644
--- a/gcc/config/riscv/riscv_vector.h
+++ b/gcc/config/riscv/riscv_vector.h
@@ -35,57 +35,6 @@
extern "C" {
#endif
-enum RVV_CSR {
- RVV_VSTART = 0,
- RVV_VXSAT,
- RVV_VXRM,
- RVV_VCSR,
-};
-
-__extension__ extern __inline unsigned long
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vread_csr(enum RVV_CSR csr)
-{
- unsigned long rv = 0;
- switch (csr)
-{
-case RVV_VSTART:
- __asm__ __volatile__ ("csrr\t%0,vstart" : "=r"(rv) : : "memory");
- break;
-case RVV_VXSAT:
- __asm__ __volatile__ ("csrr\t%0,vxsat" : "=r"(rv) : : "memory");
- break;
-case RVV_VXRM:
- __asm__ __volatile__ ("csrr\t%0,vxrm" : "=r"(rv) : : "memory");
- break;
-case RVV_VCSR:
- __asm__ __volatile__ ("csrr\t%0,vcsr" : "=r"(rv) : : "memory");
- break;
-}
- return rv;
-}
-
-__extension__ extern __inline void
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vwrite_csr(enum RVV_CSR csr, unsigned long value)
-{
- switch (csr)
-{
-case RVV_VSTART:
- __asm__ __volatile__ ("csrw\tvstart,%z0" : : "rJ"(value) : "memory");
- break;
-case RVV_VXSAT:
- __asm__ __volatile__ ("csrw\tvxsat,%z0" : : "rJ"(value) : "memory");
- break;
-case RVV_VXRM:
- __asm__ __volatile__ ("csrw\tvxrm,%z0" : : "rJ"(value) : "memory");
- break;
-case RVV_VCSR:
- __asm__ __volatile__ ("csrw\tvcsr,%z0" : : "rJ"(value) : "memory");
- break;
-}
-}
-
/* NOTE: This implementation of riscv_vector.h is intentionally short. It does
not define the RVV types and intrinsic functions directly in C and C++
code, but instead uses the following pragma to tell GCC to insert the
--
2.34.1
[PATCH v7] RISC-V: Support CALL for RVV floating-point dynamic rounding
From: Pan Li Update in PATCH v7: 1. Take previous/next_nonnote_nondebug_insn_bb for seeking the insn. 2. Splitting the function in detection and emit when needed. Original commit logs: In basic dynamic rounding mode, we simply ignore call instructions and we would like to take care of call in this PATCH. During the call, the frm may be updated or keep as is. Thus, we must make sure at least 2 things. 1. The static frm before call should not pollute the frm value in call. 2. The updated frm value in call should be sticky after call completed. We will perfrom some steps to make above happen. 1. Mark call instruction with new mode DYN_CALL. 2. Mark the instruction after CALL from NONE to DYN. 3. When emit for a DYN_CALL, we will restore the frm value. 4. When emit from a DYN_CALL, we will backup the frm value. Let's take a flow for this. +-+ | Entry (DYN) | <- frrm a5 +-+ / \ +---+ +---+ | VFADD | | VFADD RTZ | <- fsrmi 1(RTZ) +---+ +---+ || +---+ +---+ | CALL | | CALL | <- fsrm a5 +---+ +---+ | | +---+ +---+ | SHIFT | <- frrm a5 | VFADD | <- frrm a5 +---+ +---+ | / +---+ / | VFADD RUP | <- fsrm1 3(RUP) +---+ / \ / +-+ | Exit (DYN_EXIT) | <- fsrm a5 +-+ When call is the last insn of one bb, we take care of it when needed for each insn by inserting one frm backup (frrm) insn to the end of the current bb. Signed-off-by: Pan Li Co-Authored-By: Juzhe-Zhong gcc/ChangeLog: * config/riscv/riscv.cc (DYNAMIC_FRM_RTL): New macro. (STATIC_FRM_P): Ditto. (struct mode_switching_info): New struct for mode switching. (struct machine_function): Add new field mode switching. (riscv_emit_frm_mode_set): Add DYN_CALL emit. (riscv_frm_adjust_mode_after_call): New function for call mode. (riscv_frm_emit_after_call_in_bb_end): New function for emit insn when call as the end of bb. (riscv_frm_mode_needed): New function for frm mode needed. (riscv_mode_needed): Extrac function for frm. (riscv_frm_mode_after): Add DYN_CALL after. (riscv_mode_entry): Remove backup rtl initialization. * config/riscv/vector.md (frm_mode): Add dyn_call. (fsrmsi_restore_exit): Rename to _volatile. (fsrmsi_restore_volatile): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: Adjust test cases. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-38.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-40.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-42.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-43.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-44.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-47.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-51.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-53.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-54.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-55.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-57.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-58.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c: New test. *
[PATCH v6] RISC-V: Support CALL for RVV floating-point dynamic rounding
From: Pan Li In basic dynamic rounding mode, we simply ignore call instructions and we would like to take care of call in this PATCH. During the call, the frm may be updated or keep as is. Thus, we must make sure at least 2 things. 1. The static frm before call should not pollute the frm value in call. 2. The updated frm value in call should be sticky after call completed. We will perfrom some steps to make above happen. 1. Mark call instruction with new mode DYN_CALL. 2. Mark the instruction after CALL from NONE to DYN. 3. When emit for a DYN_CALL, we will restore the frm value. 4. When emit from a DYN_CALL, we will backup the frm value. Let's take a flow for this. +-+ | Entry (DYN) | <- frrm a5 +-+ / \ +---+ +---+ | VFADD | | VFADD RTZ | <- fsrmi 1(RTZ) +---+ +---+ || +---+ +---+ | CALL | | CALL | <- fsrm a5 +---+ +---+ | | +---+ +---+ | SHIFT | <- frrm a5 | VFADD | <- frrm a5 +---+ +---+ | / +---+ / | VFADD RUP | <- fsrm1 3(RUP) +---+ / \ / +-+ | Exit (DYN_EXIT) | <- fsrm a5 +-+ When call is the last insn of one bb, we take care of it when needed for each insn by inserting one frm backup (frrm) insn to the end of the current bb. Signed-off-by: Pan Li Co-Authored-By: Juzhe-Zhong gcc/ChangeLog: * config/riscv/riscv.cc (DYNAMIC_FRM_RTL): New macro. (STATIC_FRM_P): Ditto. (struct mode_switching_info): New struct for mode switching. (struct machine_function): Add new field mode switching. (riscv_emit_frm_mode_set): Add DYN_CALL emit. (riscv_frm_adjust_mode_after_call): New function for call mode. (riscv_frm_reconcile_call_as_bb_end): New function for call as the last insn of bb. (riscv_frm_mode_needed): New function for frm mode needed. (riscv_mode_needed): Extrac function for frm. (riscv_frm_mode_after): Add DYN_CALL after. (riscv_mode_entry): Remove backup rtl initialization. * config/riscv/vector.md (frm_mode): Add dyn_call. (fsrmsi_restore_exit): Rename to _volatile. (fsrmsi_restore_volatile): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: Adjust test cases. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-38.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-40.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-42.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-43.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-44.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-47.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-51.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-53.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-54.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-55.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-57.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-58.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c: New test.
[PATCH v1] RISC-V: Bugfix for allowing incorrect dyn for static rounding
From: Pan Li
According to the spec, dyn rounding mode is invalid for RVV
floating-point, this patch would like to fix this.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-shapes.cc
(struct alu_frm_def): Take range check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-error.c: Update cases.
* gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: Removed.
---
.../riscv/riscv-vector-builtins-shapes.cc | 3 +-
.../riscv/rvv/base/float-point-frm-error.c| 6 ++--
.../riscv/rvv/base/float-point-frm-insert-6.c | 33 ---
3 files changed, 4 insertions(+), 38 deletions(-)
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
index 69a67106418..22b5fe256df 100644
--- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc
@@ -285,8 +285,7 @@ struct alu_frm_def : public build_base
{
unsigned int frm_num = c.arg_num () - 2;
- return c.require_immediate_range_or (frm_num, FRM_STATIC_MIN,
-FRM_STATIC_MAX, FRM_DYN);
+ return c.require_immediate (frm_num, FRM_STATIC_MIN, FRM_STATIC_MAX);
}
return true;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c
index 4ebaa15ab0b..01d82d4e661 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-error.c
@@ -7,9 +7,9 @@ typedef float float32_t;
void test_float_point_frm_error (float32_t *out, vfloat32m1_t op1,
vfloat32m1_t op2, size_t vl)
{
- vfloat32m1_t v1 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 5, vl); /* { dg-error
{passing 5 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value
in the range \[0, 4\] or 7} } */
- vfloat32m1_t v2 = __riscv_vfadd_vv_f32m1_rm (v1, v1, 6, vl); /* { dg-error
{passing 6 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value
in the range \[0, 4\] or 7} } */
- vfloat32m1_t v3 = __riscv_vfadd_vv_f32m1_rm (v2, v2, 8, vl); /* { dg-error
{passing 8 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value
in the range \[0, 4\] or 7} } */
+ vfloat32m1_t v1 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 5, vl); /* { dg-error
{passing 5 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value
in the range \[0, 4\]} } */
+ vfloat32m1_t v2 = __riscv_vfadd_vv_f32m1_rm (v1, v1, 6, vl); /* { dg-error
{passing 6 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value
in the range \[0, 4\]} } */
+ vfloat32m1_t v3 = __riscv_vfadd_vv_f32m1_rm (v2, v2, 8, vl); /* { dg-error
{passing 8 to argument 3 of '__riscv_vfadd_vv_f32m1_rm', which expects a value
in the range \[0, 4\]} } */
__riscv_vse32_v_f32m1 (out, v3, vl);
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
deleted file mode 100644
index 1ef0e015d8f..000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
-
-#include "riscv_vector.h"
-
-typedef float float32_t;
-
-vfloat32m1_t
-test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
- return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl);
-}
-
-vfloat32m1_t
-test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
-size_t vl) {
- return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl);
-}
-
-vfloat32m1_t
-test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) {
- return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl);
-}
-
-vfloat32m1_t
-test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
-size_t vl) {
- return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl);
-}
-
-/* { dg-final { scan-assembler-times
{vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
-/* { dg-final { scan-assembler-not {fsrm\s+[axs][0-9]+} } } */
-/* { dg-final { scan-assembler-not {frrm\s+[axs][0-9]+} } } */
-/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */
--
2.34.1
[PATCH v5] RISC-V: Support CALL for RVV floating-point dynamic rounding
From: Pan Li In basic dynamic rounding mode, we simply ignore call instructions and we would like to take care of call in this PATCH. During the call, the frm may be updated or keep as is. Thus, we must make sure at least 2 things. 1. The static frm before call should not pollute the frm value in call. 2. The updated frm value in call should be sticky after call completed. We will perfrom some steps to make above happen. 1. Mark call instruction with new mode DYN_CALL. 2. Mark the instruction after CALL from NONE to DYN. 3. When emit for a DYN_CALL, we will restore the frm value. 4. When emit from a DYN_CALL, we will backup the frm value. Let's take a flow for this. +-+ | Entry (DYN) | <- frrm a5 +-+ / \ +---+ +---+ | VFADD | | VFADD RTZ | <- fsrmi 1(RTZ) +---+ +---+ || +---+ +---+ | CALL | | CALL | <- fsrm a5 +---+ +---+ | | +---+ +---+ | SHIFT | <- frrm a5 | VFADD | <- frrm a5 +---+ +---+ | / +---+ / | VFADD RUP | <- fsrm1 3(RUP) +---+ / \ / +-+ | Exit (DYN_EXIT) | <- fsrm a5 +-+ When call is the last insn of one bb, we take care of it when needed for each insn by inserting one frm backup (frrm) insn to the end of the current bb. Signed-off-by: Pan Li Co-Authored-By: Juzhe-Zhong gcc/ChangeLog: * config/riscv/riscv.cc (DYNAMIC_FRM_RTL): New macro. (STATIC_FRM_P): Ditto. (struct mode_switching_info): New struct for mode switching. (struct machine_function): Add new field mode switching. (riscv_emit_frm_mode_set): Add DYN_CALL emit. (riscv_frm_adjust_mode_after_call): New function for call mode. (riscv_frm_reconcile_call_as_bb_end): New function for call as the last insn of bb. (riscv_frm_mode_needed): New function for frm mode needed. (riscv_mode_needed): Extrac function for frm. (riscv_frm_mode_after): Add DYN_CALL after. (riscv_mode_entry): Remove backup rtl initialization. * config/riscv/vector.md (frm_mode): Add dyn_call. (fsrmsi_restore_exit): Rename to _volatile. (fsrmsi_restore_volatile): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: Adjust test cases. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-38.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-40.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-42.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-43.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-44.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-47.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-51.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-53.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-54.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-55.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-57.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-58.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c: New test.
[PATCH v1] RISC-V: Fix one incorrect match operand for RVV reduction
From: Pan Li
There are 2 of the RVV reduction pattern mask operand takes
vector_merge_operand instead of vector_mask_operand by mistake. This
patch would like to fix this.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/vector.md: Fix incorrect match_operand.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr110299-1.c: Adjust tests.
* gcc.target/riscv/rvv/base/pr110299-2.c: Ditto.
---
gcc/config/riscv/vector.md | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index fcff3ee3a17..f745888127c 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7915,7 +7915,7 @@ (define_insn
"@pred_widen_reduc_plus"
(unspec:VSF_LMUL1
[(unspec:VSF_LMUL1
[(unspec:
- [(match_operand: 1 "vector_merge_operand" "vmWc1,vmWc1")
+ [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1")
(match_operand 5 "vector_length_operand" " rK, rK")
(match_operand 6 "const_int_operand" "i,i")
(match_operand 7 "const_int_operand" "i,i")
@@ -7937,7 +7937,7 @@ (define_insn
"@pred_widen_reduc_plus"
(unspec:VDF_LMUL1
[(unspec:VDF_LMUL1
[(unspec:
- [(match_operand: 1 "vector_merge_operand" "vmWc1,vmWc1")
+ [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1")
(match_operand 5 "vector_length_operand" " rK, rK")
(match_operand 6 "const_int_operand" "i,i")
(match_operand 7 "const_int_operand" "i,i")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
index d83eea925a7..a903dde34d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
@@ -3,5 +3,5 @@
#include "pr110299-1.h"
-/* { dg-final { scan-assembler-times
{vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
-/* { dg-final { scan-assembler-times
{vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times
{vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times
{vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
index cdcde1b89a4..1254ace58eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
@@ -4,5 +4,5 @@
#include "pr110299-1.h"
#include "pr110299-2.h"
-/* { dg-final { scan-assembler-times
{vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 3 } } */
-/* { dg-final { scan-assembler-times
{vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 3 } } */
+/* { dg-final { scan-assembler-times
{vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times
{vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */
--
2.34.1
[PATCH v4] RISC-V: Support CALL for RVV floating-point dynamic rounding
From: Pan Li In basic dynamic rounding mode, we simply ignore call instructions and we would like to take care of call in this PATCH. During the call, the frm may be updated or keep as is. Thus, we must make sure at least 2 things. 1. The static frm before call should not pollute the frm value in call. 2. The updated frm value in call should be sticky after call completed. We will perfrom some steps to make above happen. 1. Mark call instruction with new mode DYN_CALL. 2. Mark the instruction after CALL from NONE to DYN. 3. When emit for a DYN_CALL, we will restore the frm value. 4. When emit from a DYN_CALL, we will backup the frm value. Let's take a flow for this. +-+ | Entry (DYN) | <- frrm a5 +-+ / \ +---+ +---+ | VFADD | | VFADD RTZ | <- fsrmi 1(RTZ) +---+ +---+ || +---+ +---+ | CALL | | CALL | <- fsrm a5 +---+ +---+ | | +---+ +---+ | SHIFT | <- frrm a5 | VFADD | <- frrm a5 +---+ +---+ | / +---+ / | VFADD RUP | <- fsrm1 3(RUP) +---+ / \ / +-+ | Exit (DYN_EXIT) | <- fsrm a5 +-+ Please *NOTE* some corn cases like no instruction after a call is not well handled, and will be coverred in another PATCH(s) soon. Signed-off-by: Pan Li Co-Authored-By: Juzhe-Zhong gcc/ChangeLog: * config/riscv/riscv.cc (DYNAMIC_FRM_RTL): New macro. (STATIC_FRM_P): Ditto. (struct mode_switching_info): New struct for mode switching. (struct machine_function): Add new field mode switching. (riscv_emit_frm_mode_set): Add DYN_CALL emit. (riscv_frm_mode_needed): New function for frm mode needed. (riscv_mode_needed): Extrac function for frm. (riscv_frm_mode_after): Add DYN_CALL after. * config/riscv/vector.md (frm_mode): Add dyn_call. (fsrmsi_restore_exit): Rename to _volatile. (fsrmsi_restore_volatile): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: Adjust test cases. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-38.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-40.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-42.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-43.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-44.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-47.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-51.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-53.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-54.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-55.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-57.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-58.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-63.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c: New test. *
[PATCH v1] RISC-V: Align the pattern format in vector.md
From: Pan Li There are some format-unaligned pattern in vector.md, this patch would like to align the format for these patterns. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/vector.md: Align pattern format. --- gcc/config/riscv/vector.md | 850 + 1 file changed, 297 insertions(+), 553 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 69680de2600..fcff3ee3a17 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -669,61 +669,45 @@ (define_attr "avl_type" "" ;; Defines rounding mode of an fixed-point operation. (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none" - (cond -[ - (eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip") - (cond - [ - (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNU") - (const_string "rnu") - - (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNE") - (const_string "rne") - - (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RDN") - (const_string "rdn") - - (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_ROD") - (const_string "rod") - ] - (const_string "none") - ) -] -(const_string "none") - ) -) + (cond [(eq_attr "type" "vsalu,vaalu,vsmul,vsshift,vnclip") +(cond + [(match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNU") + (const_string "rnu") + + (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNE") + (const_string "rne") + + (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RDN") + (const_string "rdn") + + (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_ROD") + (const_string "rod")] + (const_string "none"))] +(const_string "none"))) ;; Defines rounding mode of an floating-point operation. (define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,none" - (cond -[ - (eq_attr "type" "vfalu") - (cond - [ - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE") - (const_string "rne") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ") - (const_string "rtz") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN") - (const_string "rdn") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP") - (const_string "rup") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM") - (const_string "rmm") - - (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN") - (const_string "dyn") - ] - (const_string "none") - ) -] -(const_string "none") - ) -) + (cond [(eq_attr "type" "vfalu") + (cond + [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE") + (const_string "rne") + + (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RTZ") + (const_string "rtz") + + (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RDN") + (const_string "rdn") + + (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RUP") + (const_string "rup") + + (match_test "INTVAL (operands[9]) == riscv_vector::FRM_RMM") + (const_string "rmm") + + (match_test "INTVAL (operands[9]) == riscv_vector::FRM_DYN") + (const_string "dyn")] + (const_string "none"))] +(const_string "none"))) ;; - ;; Miscellaneous Operations @@ -7631,583 +7615,343 @@ (define_insn "@pred_rod_trunc" ;; Integer Reduction for QI (define_insn "@pred_reduc_" - [ -(set - (match_operand:VQI_LMUL1 0 "register_operand" "=vr, vr") - (unspec:VQI_LMUL1 - [ - (unspec: - [ - (match_operand:1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK") - (match_operand 6 "const_int_operand" "i, i") - (match_operand 7 "const_int_operand" "i, i") - (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - ] UNSPEC_VPREDICATE - ) - (any_reduc:VQI - (vec_duplicate:VQI - (vec_select: - (match_operand:VQI_LMUL1 4 "register_operand" " vr, vr") - (parallel [(const_int 0)]) - ) - ) - (match_operand:VQI 3 "register_operand" " vr, vr") - ) - (match_operand:VQI_LMUL1 2 "vector_merge_operand" " vu, 0") - ] UNSPEC_REDUC - ) -) - ] + [(set (match_operand:VQI_LMUL1 0 "register_operand" "=vr, vr") + (unspec:VQI_LMUL1 + [(unspec: + [(match_operand:
[PATCH v3] RISC-V: Support CALL for RVV floating-point dynamic rounding
From: Pan Li In basic dynamic rounding mode, we simply ignore call instructions and we would like to take care of call in this PATCH. During the call, the frm may be updated or keep as is. Thus, we must make sure at least 2 things. 1. The static frm before call should not pollute the frm value in call. 2. The updated frm value in call should be sticky after call completed. We will perfrom some steps to make above happen. 1. Mark call instruction with new mode DYN_CALL. 2. Mark the instruction after CALL from NONE to DYN. 3. When emit for a DYN_CALL, we will restore the frm value. 4. When emit from a DYN_CALL, we will backup the frm value. Let's take a flow for this. +-+ | Entry (DYN) | <- frrm a5 +-+ / \ +---+ +---+ | VFADD | | VFADD RTZ | <- fsrmi 1(RTZ) +---+ +---+ || +---+ +---+ | CALL | | CALL | <- fsrm a5 +---+ +---+ | | +---+ +---+ | SHIFT | <- frrm a5 | VFADD | <- frrm a5 +---+ +---+ | / +---+ / | VFADD RUP | <- fsrm1 3(RUP) +---+ / \ / +-+ | Exit (DYN_EXIT) | <- fsrm a5 +-+ Please *NOTE* some corn cases like no instruction after a call is not well handled, and will be coverred in another PATCH(s) soon. Signed-off-by: Pan Li Co-Authored-By: Juzhe-Zhong gcc/ChangeLog: * config/riscv/riscv.cc (DYNAMIC_FRM_RTL): New macro. (STATIC_FRM_P): Ditto. (struct mode_switching_info): New struct for mode switching. (struct machine_function): Add new field mode switching. (riscv_emit_frm_mode_set): Add DYN_CALL emit. (riscv_frm_mode_needed): New function for frm mode needed. (riscv_mode_needed): Extrac function for frm. (riscv_frm_mode_after): Add DYN_CALL after. * config/riscv/vector.md (frm_mode): Add dyn_call. (fsrmsi_restore_exit): Rename to _volatile. (fsrmsi_restore_volatile): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: Adjust test cases. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-38.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-40.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-42.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-43.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-44.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-45.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-46.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-47.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-48.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-51.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-53.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-54.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-55.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-56.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-57.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-58.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-59.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-60.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-61.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-62.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-63.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-64.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-65.c: New test. *
[PATCH v2] RISC-V: Support CALL for RVV floating-point dynamic rounding
From: Pan Li In basic dynamic rounding mode, we simply ignore call instructions and we would like to take care of call in this PATCH. During the call, the frm may be updated or keep as is. Thus, we must make sure at least 2 things. 1. The static frm before call should not pollute the frm value in call. 2. The updated frm value in call should be sticky after call completed. We will perfrom some steps to make above happen. 1. Mark call instruction with new mode DYN_CALL. 2. Mark the instruction after CALL from NONE to DYN. 3. When emit for a DYN_CALL, we will restore the frm value. 4. When emit from a DYN_CALL, we will backup the frm value. Let's take a flow for this. +-+ | Entry (DYN) | <- frrm a5 +-+ / \ +---+ +---+ | VFADD | | VFADD RTZ | <- fsrmi 1(RTZ) +---+ +---+ || +---+ +---+ | CALL | | CALL | <- fsrm a5 +---+ +---+ | | +---+ +---+ | SHIFT | <- frrm a5 | VFADD | <- frrm a5 +---+ +---+ | / +---+ / | VFADD RUP | <- fsrm1 3(RUP) +---+ / \ / +-+ | Exit (DYN_EXIT) | <- fsrm a5 +-+ Please *NOTE* some corn cases like no instruction after a call is not well handled, and will be coverred in another PATCH(s) soon. Signed-off-by: Pan Li Co-Authored-By: Juzhe-Zhong gcc/ChangeLog: * config/riscv/riscv.cc (DYNAMIC_FRM_RTL): New macro. (STATIC_FRM_P): Ditto. (struct mode_switching_info): New struct for mode switching. (struct machine_function): Add new field mode switching. (riscv_emit_frm_mode_set): Add DYN_CALL emit. (riscv_frm_mode_needed): New function for frm mode needed. (riscv_mode_needed): Extrac function for frm. (riscv_frm_mode_after): Add DYN_CALL after. * config/riscv/vector.md (frm_mode): Add dyn_call. (fsrmsi_restore_exit): Rename to _volatile. (fsrmsi_restore_volatile): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: Adjust test cases. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-38.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-40.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-42.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-43.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-44.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-run-4.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-run-5.c: New test. --- gcc/config/riscv/riscv.cc | 100 -- gcc/config/riscv/vector.md| 4 +- .../rvv/base/float-point-dynamic-frm-33.c | 31 ++ .../rvv/base/float-point-dynamic-frm-34.c | 32 ++ .../rvv/base/float-point-dynamic-frm-35.c | 32 ++ .../rvv/base/float-point-dynamic-frm-36.c | 29 + .../rvv/base/float-point-dynamic-frm-37.c | 36 +++ .../rvv/base/float-point-dynamic-frm-38.c | 34 ++ .../rvv/base/float-point-dynamic-frm-39.c | 36 +++ .../rvv/base/float-point-dynamic-frm-40.c | 34 ++ .../rvv/base/float-point-dynamic-frm-41.c | 37 +++ .../rvv/base/float-point-dynamic-frm-42.c | 37 +++ .../rvv/base/float-point-dynamic-frm-43.c | 38 +++ .../rvv/base/float-point-dynamic-frm-44.c | 40 +++ .../riscv/rvv/base/float-point-frm-insert-7.c | 5 +- .../riscv/rvv/base/float-point-frm-run-4.c| 82 ++ .../riscv/rvv/base/float-point-frm-run-5.c| 83 +++ 17 files changed, 676 insertions(+), 14 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c create mode 100644
[PATCH v1] RISC-V: Support CALL for RVV floating-point dynamic rounding
From: Pan Li In basic dynamic rounding mode, we simply ignore call instructions and we would like to take care of call in this PATCH. During the call, the frm may be updated or keep as is. Thus, we must make sure at least 2 things. 1. The static frm before call should not pollute the frm value in call. 2. The updated frm value in call should be sticky after call completed. We will perfrom some steps to make above happen. 1. Mark call instruction with new mode DYN_CALL. 2. Mark the instruction after CALL from NONE to DYN. 3. When emit for a DYN_CALL, we will restore the frm value. 4. When emit from a DYN_CALL, we will backup the frm value. Let's take a flow for this. +-+ | Entry (DYN) | <- frrm a5 +-+ / \ +---+ +---+ | VFADD | | VFADD RTZ | <- fsrmi 1(RTZ) +---+ +---+ || +---+ +---+ | CALL | | CALL | <- fsrm a5 +---+ +---+ | | +---+ +---+ | SHIFT | <- frrm a5 | VFADD | <- frrm a5 +---+ +---+ | / +---+ / | VFADD RUP | <- fsrm1 3(RUP) +---+ / \ / +-+ | Exit (DYN_EXIT) | <- fsrm a5 +-+ Please *NOTE* some corn cases like no instruction after a call is not well handled, and will be coverred in another PATCH(s) soon. Signed-off-by: Pan Li Co-Authored-By: Juzhe-Zhong gcc/ChangeLog: * config/riscv/riscv.cc (struct machine_function): Add new field static_frm_p. (riscv_emit_frm_mode_set): Add DYN_CALL emit. (riscv_frm_mode_needed): New function for frm mode needed. (riscv_mode_needed): Extrac function for frm. (riscv_frm_mode_after): Add DYN_CALL after. * config/riscv/vector.md (frm_mode): Add dyn_call. (fsrmsi_restore_exit): Rename to _volatile. (fsrmsi_restore_volatile): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: Fix tests cases. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-38.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-39.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-40.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-41.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-42.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-43.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-44.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-run-4.c: New test. * gcc.target/riscv/rvv/base/float-point-frm-run-5.c: New test. --- gcc/config/riscv/riscv.cc | 73 +++- gcc/config/riscv/vector.md| 4 +- .../rvv/base/float-point-dynamic-frm-33.c | 31 +++ .../rvv/base/float-point-dynamic-frm-34.c | 32 +++ .../rvv/base/float-point-dynamic-frm-35.c | 32 +++ .../rvv/base/float-point-dynamic-frm-36.c | 29 +++ .../rvv/base/float-point-dynamic-frm-37.c | 36 .../rvv/base/float-point-dynamic-frm-38.c | 34 .../rvv/base/float-point-dynamic-frm-39.c | 36 .../rvv/base/float-point-dynamic-frm-40.c | 34 .../rvv/base/float-point-dynamic-frm-41.c | 37 + .../rvv/base/float-point-dynamic-frm-42.c | 37 + .../rvv/base/float-point-dynamic-frm-43.c | 38 + .../rvv/base/float-point-dynamic-frm-44.c | 40 + .../riscv/rvv/base/float-point-frm-insert-7.c | 5 +- .../riscv/rvv/base/float-point-frm-run-4.c| 82 ++ .../riscv/rvv/base/float-point-frm-run-5.c| 83 +++ 17 files changed, 655 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-33.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-34.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-35.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-36.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-37.c create mode 100644
[PATCH v2] RISC-V: Fix RVV frm run test failure on RV32
From: Pan Li
Refine the run test case to avoid interactive checking in RV32, by
separating each checks in different functions.
Signed-off-by: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Fix run failure.
---
.../riscv/rvv/base/float-point-frm-run-1.c| 59 +++
1 file changed, 36 insertions(+), 23 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
index 245ce7d1fc0..1b2789a924b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
@@ -5,6 +5,24 @@
#include
#include
+#define DEFINE_TEST_FUNC(FRM) \
+vfloat32m1_t __attribute__ ((noinline)) \
+test_float_point_frm_run_##FRM (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl)
\
+{
\
+ vfloat32m1_t result;
\
+
\
+ set_frm (0);
\
+
\
+ result = __riscv_vfadd_vv_f32m1_rm (op1, result, FRM, vl);
\
+
\
+ assert_equal (FRM, get_frm (), "The value of frm should be " #FRM ".");
\
+
\
+ return result;
\
+}
+
+#define RUN_TEST_FUNC(FRM, op1, op2, vl) \
+ test_float_point_frm_run_##FRM (op1, op2, vl)
+
static int
get_frm ()
{
@@ -41,28 +59,11 @@ assert_equal (int a, int b, char *message)
}
}
-vfloat32m1_t __attribute__ ((noinline))
-test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl)
-{
- vfloat32m1_t result;
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl);
- assert_equal (1, get_frm (), "The value of frm register should be 1.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl);
- assert_equal (2, get_frm (), "The value of frm register should be 2.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl);
- assert_equal (3, get_frm (), "The value of frm register should be 3.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl);
- assert_equal (4, get_frm (), "The value of frm register should be 4.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 0, vl);
- assert_equal (0, get_frm (), "The value of frm register should be 0.");
-
- return result;
-}
+DEFINE_TEST_FUNC (0)
+DEFINE_TEST_FUNC (1)
+DEFINE_TEST_FUNC (2)
+DEFINE_TEST_FUNC (3)
+DEFINE_TEST_FUNC (4)
int
main ()
@@ -72,8 +73,20 @@ main ()
vfloat32m1_t op2;
set_frm (4);
- test_float_point_frm_run (op1, op2, vl);
+ RUN_TEST_FUNC (0, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (1, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (2, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (3, op1, op2, vl);
+ assert_equal (4, get_frm (), "The value of frm register should be 4.");
+
+ RUN_TEST_FUNC (4, op1, op2, vl);
assert_equal (4, get_frm (), "The value of frm register should be 4.");
return 0;
--
2.34.1
[PATCH v1|GCC-13] RISC-V: Bugfix for riscv-vsetvl pass.
From: Ju-Zhe Zhong
This patch comes from part of below change, which locate one bug of rvv
vsetvel pass when auto-vectorization.
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624523.html
Unforunately, It is not easy to reproduce this bug by intrinsic APIs
but it is worth to backport to GCC 13.
Signed-off-by: Ju-Zhe Zhong
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Add vl parameter.
(change_vsetvl_insn): Ditto.
(change_insn): Add validate change as well as assert.
(pass_vsetvl::backward_demand_fusion): Allow forward.
---
gcc/config/riscv/riscv-vsetvl.cc | 29 +++--
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 3355ca4e3fb..fbd26988106 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -633,7 +633,8 @@ gen_vsetvl_pat (enum vsetvl_type insn_type, const
vl_vtype_info , rtx vl)
}
static rtx
-gen_vsetvl_pat (rtx_insn *rinsn, const vector_insn_info )
+gen_vsetvl_pat (rtx_insn *rinsn, const vector_insn_info ,
+ rtx vl = NULL_RTX)
{
rtx new_pat;
vl_vtype_info new_info = info;
@@ -644,7 +645,7 @@ gen_vsetvl_pat (rtx_insn *rinsn, const vector_insn_info
)
if (vsetvl_insn_p (rinsn) || vlmax_avl_p (info.get_avl ()))
{
rtx dest = get_vl (rinsn);
- new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, dest);
+ new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, vl ? vl : dest);
}
else if (INSN_CODE (rinsn) == CODE_FOR_vsetvl_vtype_change_only)
new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, new_info, NULL_RTX);
@@ -926,7 +927,8 @@ change_insn (rtx_insn *rinsn, rtx new_pat)
print_rtl_single (dump_file, PATTERN (rinsn));
}
- validate_change (rinsn, (rinsn), new_pat, false);
+ bool change_p = validate_change (rinsn, (rinsn), new_pat, false);
+ gcc_assert (change_p);
if (dump_file)
{
@@ -1039,7 +1041,8 @@ change_insn (function_info *ssa, insn_change change,
insn_info *insn,
}
static void
-change_vsetvl_insn (const insn_info *insn, const vector_insn_info )
+change_vsetvl_insn (const insn_info *insn, const vector_insn_info ,
+ rtx vl = NULL_RTX)
{
rtx_insn *rinsn;
if (vector_config_insn_p (insn->rtl ()))
@@ -1053,7 +1056,7 @@ change_vsetvl_insn (const insn_info *insn, const
vector_insn_info )
rinsn = PREV_INSN (insn->rtl ());
gcc_assert (vector_config_insn_p (rinsn));
}
- rtx new_pat = gen_vsetvl_pat (rinsn, info);
+ rtx new_pat = gen_vsetvl_pat (rinsn, info, vl);
change_insn (rinsn, new_pat);
}
@@ -3331,7 +3334,21 @@ pass_vsetvl::backward_demand_fusion (void)
new_info))
continue;
- change_vsetvl_insn (new_info.get_insn (), new_info);
+ rtx vl = NULL_RTX;
+ /* Backward VLMAX VL:
+ bb 3:
+vsetivli zero, 1 ... -> vsetvli t1, zero
+vmv.s.x
+ bb 5:
+vsetvli t1, zero ... -> to be elided.
+vlse16.v
+
+ We should forward "t1". */
+ if (!block_info.reaching_out.has_avl_reg ()
+ && vlmax_avl_p (new_info.get_avl ()))
+ vl = get_vl (prop.get_insn ()->rtl ());
+change_vsetvl_insn (new_info.get_insn (), new_info, vl);
+
if (block_info.local_dem == block_info.reaching_out)
block_info.local_dem = new_info;
block_info.reaching_out = new_info;
--
2.34.1
[PATCH v1] RISC-V: Fix RVV frm run test failure on RV32
From: Pan Li
Refine the run test case to avoid interactive checking in RV32, by
separating each checks in different functions.
Signed-off-by: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Fix failure
on RV32.
---
.../riscv/rvv/base/float-point-frm-run-1.c| 58 ++-
1 file changed, 31 insertions(+), 27 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
index 210c49c5e8d..1d90b4f50d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
@@ -5,6 +5,24 @@
#include
#include
+#define DEFINE_TEST_FRM_FUNC(FRM) \
+vfloat32m1_t __attribute__ ((noinline)) \
+test_float_point_frm_run_##FRM (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl)
\
+{
\
+ vfloat32m1_t result;
\
+
\
+ set_frm (0);
\
+
\
+ result = __riscv_vfadd_vv_f32m1_rm (op1, result, FRM, vl);
\
+
\
+ assert_equal (FRM, get_frm (), "The value of frm should be " #FRM ".");
\
+
\
+ return result;
\
+}
+
+#define CALL_TEST_FUNC(FRM, op1, op2, vl) \
+ test_float_point_frm_run_##FRM (op1, op2, vl)
+
static int
get_frm ()
{
@@ -31,40 +49,22 @@ set_frm (int frm)
);
}
-static inline void
+void __attribute__ ((noinline)) \
assert_equal (int a, int b, char *message)
{
if (a != b)
{
- printf (message);
+ fprintf (stdout, message);
+ fflush (stdout);
__builtin_abort ();
}
}
-vfloat32m1_t __attribute__ ((noinline))
-test_float_point_frm_run (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl)
-{
- set_frm (0);
-
- vfloat32m1_t result;
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 1, vl);
- assert_equal (1, get_frm (), "The value of frm register should be 1.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 2, vl);
- assert_equal (2, get_frm (), "The value of frm register should be 2.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl);
- assert_equal (3, get_frm (), "The value of frm register should be 3.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 4, vl);
- assert_equal (4, get_frm (), "The value of frm register should be 4.");
-
- result = __riscv_vfadd_vv_f32m1_rm (op1, result, 0, vl);
- assert_equal (0, get_frm (), "The value of frm register should be 0.");
-
- return result;
-}
+DEFINE_TEST_FRM_FUNC (0)
+DEFINE_TEST_FRM_FUNC (1)
+DEFINE_TEST_FRM_FUNC (2)
+DEFINE_TEST_FRM_FUNC (3)
+DEFINE_TEST_FRM_FUNC (4)
int
main ()
@@ -73,7 +73,11 @@ main ()
vfloat32m1_t op1;
vfloat32m1_t op2;
- test_float_point_frm_run (op1, op2, vl);
+ CALL_TEST_FUNC (0, op1, op2, vl);
+ CALL_TEST_FUNC (1, op1, op2, vl);
+ CALL_TEST_FUNC (2, op1, op2, vl);
+ CALL_TEST_FUNC (3, op1, op2, vl);
+ CALL_TEST_FUNC (4, op1, op2, vl);
return 0;
}
--
2.34.1
[PATCH v1] RISC-V: Support basic floating-point dynamic rounding mode
From: Pan Li This patch would like to support the basic floating-point dynamic rounding modes for the RVV. We implement the dynamic rounding mode by below steps. 1. Set entry to DYN and exit to DYN_EXIT. 2. Add one rtl variable into machine_function for backup/restore. 3. Backup frm value when entry. 4. Restore frm value when exit and prev mode is not DYN. 5. Restore frm when mode switching to DYN. 6. Set frm when mode switching to STATIC. Take one flow to describe the scenarios. +-+ | Entry (DYN) | <- frrm a5 +-+ / \ +---++---+ | VFADD | <- fsrm a5 | VFADD RTZ | <- fsrmi 1(RTZ) +---++---+ || +---++---+ | VFADD || VFADD RTZ | +---++---+ | | +---+ +---+ | VFADD RUP | <- fsrmi 3(RUP) | VFADD | <- fsrm a5 +---+ +---+ | / +---+ / | VFADD RUP | / +---+ / \ / +-+ | Exit (DYN_EXIT) | <- fsrm a5 +-+ Please *NOTE* inline asm and call during the cfun will be implemented in another PATCH(s). Signed-off-by: Pan Li Co-Authored-By: Juzhe-Zhong gcc/ChangeLog: * config/riscv/riscv.cc (struct machine_function): Add new field. (riscv_static_frm_mode_p): New function. (riscv_emit_frm_mode_set): New function for emit FRM. (riscv_emit_mode_set): Extract function for FRM. (riscv_mode_needed): Fix the TODO. (riscv_mode_entry): Initial dynamic frm RTL. (riscv_mode_exit): Return DYN_EXIT. * config/riscv/riscv.md: Add rdfrm. * config/riscv/vector-iterators.md (unspecv): Add DYN_EXIT unspecv. * config/riscv/vector.md (frm_modee): Add new mode dyn_exit. (fsrm): Removed. (fsrmsi_backup): New pattern for swap. (fsrmsi_restore): New pattern for restore. (fsrmsi_restore_exit): New pattern for restore exit. (frrmsi): New pattern for backup. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-frm-insert-1.c: Adjust test cases. * gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-insert-2.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-insert-3.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-insert-4.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-insert-5.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-insert-8.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-insert-9.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-run-1.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-run-2.c: Ditto. * gcc.target/riscv/rvv/base/float-point-frm-run-3.c: Ditto. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-1.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-10.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-11.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-12.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-13.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-14.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-15.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-16.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-17.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-18.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-19.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-2.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-20.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-21.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-22.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-23.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-24.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-25.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-26.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-27.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-28.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-29.c: New test. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-3.c: New test. *
[PATCH v2] RISC-V: Add more tests for RVV floating-point FRM.
From: Pan Li
Add more test cases include both the asm check and run for RVV FRM.
Signed-off-by: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: New test.
* gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: New test.
* gcc.target/riscv/rvv/base/float-point-frm-insert-8.c: New test.
* gcc.target/riscv/rvv/base/float-point-frm-insert-9.c: New test.
* gcc.target/riscv/rvv/base/float-point-frm-run-1.c: New test.
* gcc.target/riscv/rvv/base/float-point-frm-run-2.c: New test.
* gcc.target/riscv/rvv/base/float-point-frm-run-3.c: New test.
---
.../rvv/base/float-point-frm-insert-10.c | 23 ++
.../riscv/rvv/base/float-point-frm-insert-7.c | 29 +++
.../riscv/rvv/base/float-point-frm-insert-8.c | 27 +++
.../riscv/rvv/base/float-point-frm-insert-9.c | 24 ++
.../riscv/rvv/base/float-point-frm-run-1.c| 79 +++
.../riscv/rvv/base/float-point-frm-run-2.c| 70
.../riscv/rvv/base/float-point-frm-run-3.c| 71 +
7 files changed, 323 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c
new file mode 100644
index 000..c46910b878c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+void
+test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2,
+size_t vl)
+{
+ asm volatile (
+"addi %0, %0, 0x12"
+:"+r"(vl)
+:
+:
+ );
+
+ vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl);
+ result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl);
+ *(vfloat32m1_t *)out = result;
+}
+
+/* { dg-final { scan-assembler-times
{vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c
new file mode 100644
index 000..7b1602fd509
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+size_t __attribute__ ((noinline))
+normalize_vl (size_t vl)
+{
+ if (vl % 4 == 0)
+return vl;
+
+ return ((vl / 4) + 1) * 4;
+}
+
+void
+test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2,
+size_t vl)
+{
+ vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl);
+
+ vl = normalize_vl (vl);
+
+ result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl);
+
+ *(vfloat32m1_t *)out = result;
+}
+
+/* { dg-final { scan-assembler-times
{vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c
new file mode 100644
index 000..37481ddac38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+size_t __attribute__ ((noinline))
+normalize_vl (size_t vl)
+{
+ if (vl % 4 == 0)
+return vl;
+
+ return ((vl / 4) + 1) * 4;
+}
+
+void
+test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2,
+size_t vl)
+{
+ vl = normalize_vl (vl);
+
+ vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl);
+
+ *(vfloat32m1_t *)out = result;
+}
+
+/* { dg-final { scan-assembler-times
{vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c
new file mode 100644
index
[PATCH v3] RISC-V: Refactor riscv mode after for VXRM and FRM
From: Pan Li
When investigate the FRM dynmaic rounding mode, we find the global
unknown status is quite different between the fixed-point and
floating-point. Thus, we separate the unknown function with extracting
some inner common functions.
We will also prepare more test cases in another PATCH.
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv.cc (vxrm_rtx): New static var.
(frm_rtx): Ditto.
(global_state_unknown_p): Removed.
(riscv_entity_mode_after): Removed.
(asm_insn_p): New function.
(vxrm_unknown_p): New function for fixed-point.
(riscv_vxrm_mode_after): Ditto.
(frm_unknown_dynamic_p): New function for floating-point.
(riscv_frm_mode_after): Ditto.
(riscv_mode_after): Leverage new functions.
---
gcc/config/riscv/riscv.cc | 85 ---
1 file changed, 62 insertions(+), 23 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 706c18416db..6ed735d6983 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7701,17 +7701,24 @@ riscv_mode_needed (int entity, rtx_insn *insn)
}
}
-/* Return true if the VXRM/FRM status of the INSN is unknown. */
+/* Return TRUE that an insn is asm. */
+
static bool
-global_state_unknown_p (rtx_insn *insn, unsigned int regno)
+asm_insn_p (rtx_insn *insn)
{
- struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn);
- df_ref ref;
+ extract_insn (insn);
+
+ return recog_data.is_asm;
+}
+
+/* Return TRUE that an insn is unknown for VXRM. */
+static bool
+vxrm_unknown_p (rtx_insn *insn)
+{
/* Return true if there is a definition of VXRM. */
- for (ref = DF_INSN_INFO_DEFS (insn_info); ref; ref = DF_REF_NEXT_LOC (ref))
-if (DF_REF_REGNO (ref) == regno)
- return true;
+ if (reg_set_p (gen_rtx_REG (SImode, VXRM_REGNUM), insn))
+return true;
/* A CALL function may contain an instruction that modifies the VXRM,
return true in this situation. */
@@ -7720,25 +7727,61 @@ global_state_unknown_p (rtx_insn *insn, unsigned int
regno)
/* Return true for all assembly since users may hardcode a assembly
like this: asm volatile ("csrwi vxrm, 0"). */
- extract_insn (insn);
- if (recog_data.is_asm)
+ if (asm_insn_p (insn))
+return true;
+
+ return false;
+}
+
+/* Return TRUE that an insn is unknown dynamic for FRM. */
+
+static bool
+frm_unknown_dynamic_p (rtx_insn *insn)
+{
+ /* Return true if there is a definition of FRM. */
+ if (reg_set_p (gen_rtx_REG (SImode, FRM_REGNUM), insn))
return true;
+
+ /* A CALL function may contain an instruction that modifies the FRM,
+ return true in this situation. */
+ if (CALL_P (insn))
+return true;
+
return false;
}
+/* Return the mode that an insn results in for VXRM. */
+
static int
-riscv_entity_mode_after (int regnum, rtx_insn *insn, int mode,
-int (*get_attr_mode) (rtx_insn *), int default_mode)
+riscv_vxrm_mode_after (rtx_insn *insn, int mode)
{
- if (global_state_unknown_p (insn, regnum))
-return default_mode;
- else if (recog_memoized (insn) < 0)
+ if (vxrm_unknown_p (insn))
+return VXRM_MODE_NONE;
+
+ if (recog_memoized (insn) < 0)
+return mode;
+
+ if (reg_mentioned_p (gen_rtx_REG (SImode, VXRM_REGNUM), PATTERN (insn)))
+return get_attr_vxrm_mode (insn);
+ else
return mode;
+}
+
+/* Return the mode that an insn results in for FRM. */
- rtx reg = gen_rtx_REG (SImode, regnum);
- bool mentioned_p = reg_mentioned_p (reg, PATTERN (insn));
+static int
+riscv_frm_mode_after (rtx_insn *insn, int mode)
+{
+ if (frm_unknown_dynamic_p (insn))
+return FRM_MODE_DYN;
- return mentioned_p ? get_attr_mode (insn): mode;
+ if (recog_memoized (insn) < 0)
+return mode;
+
+ if (reg_mentioned_p (gen_rtx_REG (SImode, FRM_REGNUM), PATTERN (insn)))
+return get_attr_frm_mode (insn);
+ else
+return mode;
}
/* Return the mode that an insn results in. */
@@ -7749,13 +7792,9 @@ riscv_mode_after (int entity, int mode, rtx_insn *insn)
switch (entity)
{
case RISCV_VXRM:
- return riscv_entity_mode_after (VXRM_REGNUM, insn, mode,
- (int (*)(rtx_insn *)) get_attr_vxrm_mode,
- VXRM_MODE_NONE);
+ return riscv_vxrm_mode_after (insn, mode);
case RISCV_FRM:
- return riscv_entity_mode_after (FRM_REGNUM, insn, mode,
- (int (*)(rtx_insn *)) get_attr_frm_mode,
- FRM_MODE_DYN);
+ return riscv_frm_mode_after (insn, mode);
default:
gcc_unreachable ();
}
--
2.34.1
[PATCH v1] RISC-V: Add more tests for RVV floating-point FRM.
From: Pan Li
Add more test cases include both the asm check and run for RVV FRM.
Signed-off-by: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-insert-10.c: New test.
* gcc.target/riscv/rvv/base/float-point-frm-insert-7.c: New test.
* gcc.target/riscv/rvv/base/float-point-frm-insert-8.c: New test.
* gcc.target/riscv/rvv/base/float-point-frm-insert-9.c: New test.
* gcc.target/riscv/rvv/base/float-point-frm-run-1.c: New test.
* gcc.target/riscv/rvv/base/float-point-frm-run-2.c: New test.
* gcc.target/riscv/rvv/base/float-point-frm-run-3.c: New test.
---
.../rvv/base/float-point-frm-insert-10.c | 23 ++
.../riscv/rvv/base/float-point-frm-insert-7.c | 29 +++
.../riscv/rvv/base/float-point-frm-insert-8.c | 27 +++
.../riscv/rvv/base/float-point-frm-insert-9.c | 24 ++
.../riscv/rvv/base/float-point-frm-run-1.c| 79 +++
.../riscv/rvv/base/float-point-frm-run-2.c| 71 +
.../riscv/rvv/base/float-point-frm-run-3.c| 73 +
7 files changed, 326 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-run-3.c
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c
new file mode 100644
index 000..d35ee6d2131
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-10.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+void
+test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2,
+size_t vl)
+{
+ asm volatile (
+"addi %0, %0, 0x12"
+:"=r"(vl)
+:
+:
+ );
+
+ vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl);
+ result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl);
+ *(vfloat32m1_t *)out = result;
+}
+
+/* { dg-final { scan-assembler-times
{vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c
new file mode 100644
index 000..7b1602fd509
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-7.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+size_t __attribute__ ((noinline))
+normalize_vl (size_t vl)
+{
+ if (vl % 4 == 0)
+return vl;
+
+ return ((vl / 4) + 1) * 4;
+}
+
+void
+test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2,
+size_t vl)
+{
+ vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl);
+
+ vl = normalize_vl (vl);
+
+ result = __riscv_vfadd_vv_f32m1_rm (op1, result, 3, vl);
+
+ *(vfloat32m1_t *)out = result;
+}
+
+/* { dg-final { scan-assembler-times
{vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c
new file mode 100644
index 000..37481ddac38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-8.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+size_t __attribute__ ((noinline))
+normalize_vl (size_t vl)
+{
+ if (vl % 4 == 0)
+return vl;
+
+ return ((vl / 4) + 1) * 4;
+}
+
+void
+test_float_point_frm_static (float *out, vfloat32m1_t op1, vfloat32m1_t op2,
+size_t vl)
+{
+ vl = normalize_vl (vl);
+
+ vfloat32m1_t result = __riscv_vfadd_vv_f32m1_rm (op1, op2, 2, vl);
+
+ *(vfloat32m1_t *)out = result;
+}
+
+/* { dg-final { scan-assembler-times
{vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-9.c
new file mode 100644
index
