RE: PING [PATCH] RX new builtin function

[Sebastian Perta]

PING

> -Original Message-
> From: Sebastian Perta 
> Sent: 24 October 2018 18:19
> To: 'gcc-patches@gcc.gnu.org' 
> Cc: 'Nick Clifton' 
> Subject: [PATCH] RX new builtin function
> 
> Hi,
> 
> The following patch adds a new builtin function for rx (
__builtin_rx_bset) to
> make it possible for the user to use BSET whenever necessary.
> Please note this builtin function is dedicated only for the variant 32 bit
variant
> of BSET (when destination is a register).
> For the 8 bit variant (when destination is a memory location) another
builtin
> function is necessary.
> 
> The patch contains also a test case which I added in
testsuite/gcc.target/rx.
> 
> The patch also modifies extend.texi as necessary.
> 
> Regression test is OK, tested with the following command:
> make -k check-gcc RUNTESTFLAGS=--target_board=rx-sim
> 
> Please find below the changelog entries and patch.
> 
> Best Regards,
> Sebastian
> 
> --- ChangeLog
> 2018-10-23  Sebastian Perta  
> 
>   * config/rx/rx.c (RX_BUILTIN_BSET): New enum.
>   * config/rx/rx.c (rx_init_builtins): Added new builtin for BSET.
>   * config/rx/rx.c (rx_expand_builtin_bit_manip): New function.
>   * config/rx/rx.c (rx_expand_builtin): Added new case for BSET.
>   * doc/extend.texi (RX Built-in Functions): Added declaration for
>   __builtin_rx_bset.
> 
> testsuite/ChangeLog
> 2018-10-23  Sebastian Perta  
> 
>   * gcc.target/rx/testbset.c: New test.
> 
> 
> 
> 
> 
> Index: config/rx/rx.c
> ==
> =
> --- config/rx/rx.c(revision 265425)
> +++ config/rx/rx.c(working copy)
> @@ -2374,6 +2374,7 @@
>RX_BUILTIN_ROUND,
>RX_BUILTIN_SETPSW,
>RX_BUILTIN_WAIT,
> +  RX_BUILTIN_BSET,
>RX_BUILTIN_max
>  };
> 
> @@ -2440,6 +2441,7 @@
>ADD_RX_BUILTIN1 (ROUND,   "round",   intSI, float);
>ADD_RX_BUILTIN1 (REVW,"revw",intSI, intSI);
>ADD_RX_BUILTIN0 (WAIT,"wait",void);
> +  ADD_RX_BUILTIN2 (BSET,"bset",intSI, intSI, intSI);
>  }
> 
>  /* Return the RX builtin for CODE.  */
> @@ -2576,6 +2578,26 @@
>return target;
>  }
> 
> +static rtx
> +rx_expand_builtin_bit_manip(tree exp, rtx target, rtx (* gen_func)(rtx,
rtx,
> rtx))
> +{
> +  rtx arg1 = expand_normal (CALL_EXPR_ARG (exp, 0));
> +  rtx arg2 = expand_normal (CALL_EXPR_ARG (exp, 1));
> +
> +  if (! REG_P (arg1))
> +arg1 = force_reg (SImode, arg1);
> +
> +  if (! REG_P (arg2))
> +arg2 = force_reg (SImode, arg2);
> +
> +  if (target == NULL_RTX || ! REG_P (target))
> + target = gen_reg_rtx (SImode);
> +
> +  emit_insn(gen_func(target, arg2, arg1));
> +
> +  return target;
> +}
> +
>  static int
>  valid_psw_flag (rtx op, const char *which)
>  {
> @@ -2653,6 +2675,7 @@
>  case RX_BUILTIN_REVW:return rx_expand_int_builtin_1_arg
>   (op, target, gen_revw, false);
>  case RX_BUILTIN_WAIT:emit_insn (gen_wait ()); return NULL_RTX;
> + case RX_BUILTIN_BSET:   return
> rx_expand_builtin_bit_manip(exp, target, gen_bitset);
> 
>  default:
>internal_error ("bad builtin code");
> Index: doc/extend.texi
> ==
> =
> --- doc/extend.texi   (revision 265425)
> +++ doc/extend.texi   (working copy)
> @@ -19635,6 +19635,10 @@
>  Generates the @code{wait} machine instruction.
>  @end deftypefn
> 
> +@deftypefn {Built-in Function}  int __builtin_rx_bset (int, int)
> +Generates the @code{bset} machine instruction.
> +@end deftypefn
> +
>  @node S/390 System z Built-in Functions
>  @subsection S/390 System z Built-in Functions
>  @deftypefn {Built-in Function} int __builtin_tbegin (void*)
> Index: testsuite/ChangeLog
> Index: testsuite/gcc.target/rx/testbset.c
> ==
> =
> --- testsuite/gcc.target/rx/testbset.c(nonexistent)
> +++ testsuite/gcc.target/rx/testbset.c(working copy)
> @@ -0,0 +1,53 @@
> +/* { dg-do run } */
> +
> +#include 
> +
> +int f1(int a, int b) __attribute((noinline));
> +int f1(int a, int b)
> +{
> + return __builtin_rx_bset (a, b);
> +}
> +
> +int f2(int a) __attribute((noinline));
> +int f2(int a)
> +{
> + return __builtin_rx_bset (a, 1);
> +}
> +
> +int x, y;
> +
> +int f3() __attribute((noinline));
> +int f3()
> +{
> + return __builtin_rx_bset (x, 4);
> +}
> +
> +int f4() __attribute((noinline));
> +int f4()
> +{
> + return __builtin_rx_bset (x, y);
> +}
> +
> +void f5() __attribute((noinline));
> +void f5()
> +{
> + x = __builtin_rx_bset (x, 6);
> +}
> +
> +int main()
> +{
> + if(f1(0xF, 8) != 0x10F)
> + abort();
> + if(f2(0xC) != 0xE)
> + abort();
> + x = 0xF;
> + if(f3() != 0x1F)
> + abort();
> + y = 5;
> + if(f4() != 0x2F)
> + abort();
> + f5();
> + if(x != 0x4F)
> + abort();
> + exit(0);
> +}

[PATCH] RX new builtin function

[Sebastian Perta]

Hi,

The following patch adds a new builtin function for rx ( __builtin_rx_bset)
to make it possible for the user to use BSET whenever necessary.
Please note this builtin function is dedicated only for the variant 32 bit
variant of BSET (when destination is a register). 
For the 8 bit variant (when destination is a memory location) another
builtin function is necessary.

The patch contains also a test case which I added in
testsuite/gcc.target/rx.

The patch also modifies extend.texi as necessary.

Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rx-sim

Please find below the changelog entries and patch.

Best Regards,
Sebastian

--- ChangeLog
2018-10-23  Sebastian Perta  

* config/rx/rx.c (RX_BUILTIN_BSET): New enum.
* config/rx/rx.c (rx_init_builtins): Added new builtin for BSET.
* config/rx/rx.c (rx_expand_builtin_bit_manip): New function.
* config/rx/rx.c (rx_expand_builtin): Added new case for BSET.
* doc/extend.texi (RX Built-in Functions): Added declaration for
__builtin_rx_bset.

testsuite/ChangeLog
2018-10-23  Sebastian Perta  

* gcc.target/rx/testbset.c: New test.





Index: config/rx/rx.c
===
--- config/rx/rx.c  (revision 265425)
+++ config/rx/rx.c  (working copy)
@@ -2374,6 +2374,7 @@
   RX_BUILTIN_ROUND,
   RX_BUILTIN_SETPSW,
   RX_BUILTIN_WAIT,
+  RX_BUILTIN_BSET,
   RX_BUILTIN_max
 };
 
@@ -2440,6 +2441,7 @@
   ADD_RX_BUILTIN1 (ROUND,   "round",   intSI, float);
   ADD_RX_BUILTIN1 (REVW,"revw",intSI, intSI);
   ADD_RX_BUILTIN0 (WAIT,"wait",void);
+  ADD_RX_BUILTIN2 (BSET,"bset",intSI, intSI, intSI);
 }
 
 /* Return the RX builtin for CODE.  */
@@ -2576,6 +2578,26 @@
   return target;
 }
 
+static rtx
+rx_expand_builtin_bit_manip(tree exp, rtx target, rtx (* gen_func)(rtx,
rtx, rtx))
+{
+  rtx arg1 = expand_normal (CALL_EXPR_ARG (exp, 0));
+  rtx arg2 = expand_normal (CALL_EXPR_ARG (exp, 1));
+
+  if (! REG_P (arg1))
+arg1 = force_reg (SImode, arg1);
+
+  if (! REG_P (arg2))
+arg2 = force_reg (SImode, arg2);
+
+  if (target == NULL_RTX || ! REG_P (target))
+ target = gen_reg_rtx (SImode);
+
+  emit_insn(gen_func(target, arg2, arg1));
+
+  return target;
+}
+
 static int
 valid_psw_flag (rtx op, const char *which)
 {
@@ -2653,6 +2675,7 @@
 case RX_BUILTIN_REVW:return rx_expand_int_builtin_1_arg
(op, target, gen_revw, false);
 case RX_BUILTIN_WAIT:emit_insn (gen_wait ()); return NULL_RTX;
+   case RX_BUILTIN_BSET:   return rx_expand_builtin_bit_manip(exp,
target, gen_bitset);
 
 default:
   internal_error ("bad builtin code");
Index: doc/extend.texi
===
--- doc/extend.texi (revision 265425)
+++ doc/extend.texi (working copy)
@@ -19635,6 +19635,10 @@
 Generates the @code{wait} machine instruction.
 @end deftypefn
 
+@deftypefn {Built-in Function}  int __builtin_rx_bset (int, int)
+Generates the @code{bset} machine instruction.
+@end deftypefn
+
 @node S/390 System z Built-in Functions
 @subsection S/390 System z Built-in Functions
 @deftypefn {Built-in Function} int __builtin_tbegin (void*)
Index: testsuite/ChangeLog
Index: testsuite/gcc.target/rx/testbset.c
===
--- testsuite/gcc.target/rx/testbset.c  (nonexistent)
+++ testsuite/gcc.target/rx/testbset.c  (working copy)
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+
+#include 
+
+int f1(int a, int b) __attribute((noinline));
+int f1(int a, int b)
+{
+   return __builtin_rx_bset (a, b);
+}
+
+int f2(int a) __attribute((noinline));
+int f2(int a)
+{
+   return __builtin_rx_bset (a, 1);
+}
+
+int x, y;
+
+int f3() __attribute((noinline));
+int f3()
+{
+   return __builtin_rx_bset (x, 4);
+}
+
+int f4() __attribute((noinline));
+int f4()
+{
+   return __builtin_rx_bset (x, y);
+}
+
+void f5() __attribute((noinline));
+void f5()
+{
+   x = __builtin_rx_bset (x, 6);
+}
+
+int main()
+{
+   if(f1(0xF, 8) != 0x10F)
+   abort();
+   if(f2(0xC) != 0xE)
+   abort();
+   x = 0xF;
+   if(f3() != 0x1F)
+   abort();
+   y = 5;
+   if(f4() != 0x2F)
+   abort();
+   f5();
+   if(x != 0x4F)
+   abort();
+   exit(0);
+}

RE: [PATCH] RL78 one_cmplhi2 improvement

[Sebastian Perta]

HI DJ,

> One thing to try is to use (subreg:QI in a define_expand, so that
> there's a one_cmplhi2 pattern that expands to two QImode insns that
> operate on HImode input/outputs via SUBREGs.

Thank you for the suggestion! After several attempts the following is the
only successful one, however the code produced is identical with and without
the patch:

(define_expand "one_cmplhi2"
 [(set (subreg:QI (match_operand:HI 0 "nonimmediate_operand") 0)
  (xor:HI (subreg:QI (match_operand:HI 1 "general_operand") 0)
(const_int -1)))
  (set (subreg:QI (match_dup 0) 1)
  (xor:HI (subreg:QI (match_dup 1) 1)
(const_int -1)))
  ]
  ""
  "DONE;"
)

Is this similar to what you had in mind?

Output code (same as before the patch ... the patch makes no difference):
_test_one_cmplhi:
mov a, [sp+4]
xor a, #-1
mov r8, a
mov a, [sp+5]
xor a, #-1
mov r9, a
ret

I also explored other options including define_split without any success.

> If it doesn't work out, consider this patch approved, though.
Can I checkin now?

Best Regards,
Sebastian


> -Original Message-
> From: DJ Delorie [mailto:d...@redhat.com]
> Sent: 20 February 2018 19:39
> To: Sebastian Perta <sebastian.pe...@renesas.com>
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] RL78 one_cmplhi2 improvement
> 
> 
> Const type promotion is the bane of embedded developers...
> 
> One thing to try is to use (subreg:QI in a define_expand, so that
> there's a one_cmplhi2 pattern that expands to two QImode insns that
> operate on HImode input/outputs via SUBREGs.
> 
> I don't have high hopes of gcc optimizing this properly in all cases,
> but it's worth trying.
> 
> If it doesn't work out, consider this patch approved, though.
> 
> Thanks!

RE: [PATCH] RX TARGET_RTX_COSTS function

[Sebastian Perta]

Hi Oleg,

Sorry, for some reason your emails did not ended up in Inbox, I was quite 
surprized when Nick's email started with Hi Oleg.

>>Do you happen to have any other numbers on the resulting code
>>size/speed?  
The original patch from DJ was present in my local sources since 4.7 so all the 
benchmarks (CSIBE etc.) were done on that version (when the patch was initially 
applied)
Of course I re-tested the patch when I applied it to the trunk (but I didn't 
re-tested CSIBE) the only problem I spotted was the multiplication with the 
reciprocal.

Best Regards,
Sebastian

> -Original Message-
> From: Nick Clifton [mailto:ni...@redhat.com]
> Sent: 22 February 2018 15:41
> To: Oleg Endo <oleg.e...@t-online.de>; gcc-patches@gcc.gnu.org
> Cc: Sebastian Perta <sebastian.pe...@renesas.com>; 'DJ Delorie'
> <d...@redhat.com>
> Subject: Re: [PATCH] RX TARGET_RTX_COSTS function
> 
> Hi Oleg,
> 
> > Ping.
> 
> Sorry - I am not very good at spotting RX bugs on the gcc-patches list. :-(
> 
> >> gcc/ChangeLog:
> >>* config/rx/rx.c (rx_rtx_costs): New function.
> >>(TARGET_RTX_COSTS): Override to use rx_rtx_costs.
> 
> Approved - please apply.
> 
> Cheers
>   Nick
> 

[PATCH] RL78 one_cmplhi2 improvement

[Sebastian Perta]

Hello,

The following patch defines one_cmplhi2 pattern.  The improvement does not
come from the two xor instructions used 
(in fact for the second xor the pattern uses xor saddr , #byte is used which
is 1 bytes longer than xor a, #byte) it comes 
from the fact that that the number of move instructions is reduced (16 bit
movw is used instead of 8 bit mov).

This can be seen on a very simple test case:

uint16_t test_one_cmplhi(uint16_t x) 
{
 return ~x; 
}

_test_one_cmplhi:
mov a, [sp+4]
xor a, #-1
mov r8, a
mov a, [sp+5]
xor a, #-1
mov r9, a
ret

_test_one_cmplhi:
movwax, [sp+4]
xor a, #-1 
xor 0xFFEF8, #-1 ;one_cmplhi2 ax, ax
movwr8, ax
ret

In "gcc.c-torture/execute/" I have seen the patch being effective in 18
cases with the biggest improvement is occurring in
gcc.c-torture/execute/pr68376-2 where this patch reduces the code size from
792 bytes to 704.

Unfortunately there's also a downside to this patch. In cases when the
second xor is redundant GCC never gets the chance to remove the second xor. 
This can be seen in gcc.c-torture/execute/pr42833.c for example line 57: 
vdest.v1 = (vsrc1.v1 + (1 << (-1 - tmp))) >> -tmp;
This is because all variables are 8 bit while the operation is being
promoted to 16 bit (because of the constants being of type int by default)
this is why the one_cmplhi2 is used in this case.

The relevant insns for this case are:

(insn 35 257 260 14 (set (reg:HI 0 x)
(xor:HI (reg:HI 0 x)
(const_int -1 [0x])))
"./xgcc_rw_trunk2/gcc/testsuite/gcc.c-torture/execute/pr42833.c":57 59
{*one_cmplhi2_real}
 (nil))
(insn 260 35 261 14 (set (reg:QI 1 a)
(reg:QI 0 x [8]))
"./xgcc_rw_trunk2/gcc/testsuite/gcc.c-torture/execute/pr42833.c":57 44
{*movqi_real}
 (expr_list:REG_DEAD (reg:QI 8 r8)
(nil)))

As it can be seen it is quite obvious that reg "a" is dead after insn 35.
I think I can write a simple rtl_opt_pass (similar to pass_rl78_move_elim)
to look for such cases and replace the one_cmplhi2 with one_cmplqi2.

Even without this new pass (which I plan to do in the near future) I still
think (based on testing) the advantages of this patch outweigh the
disadvantage described above.
Is OK to check-in? Or do I need to add the new pass as well for this to be
considered? Thank you!

Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim


Best Regards,
Sebastian

2018-02-20  Sebastian Perta  <sebastian.pe...@renesas.com>

* config/rl78/rl78-expand.md (one_cmplhi2): New define expand.
* config/rl78/rl78-virt.md (one_cmplhi2_virt): New define insn.
* config/rl78/rl78-real.md (one_cmplhi2_real): New define insn.


Index: rl78-expand.md
===
--- rl78-expand.md  (revision 257806)
+++ rl78-expand.md  (working copy)
@@ -211,6 +211,16 @@
  DONE;"
 )
 
+(define_expand "one_cmplhi2"
+ [(set (match_operand:HI 0 "nonimmediate_operand")
+  (xor:HI (match_operand:HI 1 "general_operand")
+   (const_int -1)))
+  ]
+  ""
+  "if (rl78_force_nonfar_2 (operands, gen_one_cmplhi2))
+ DONE;"
+)
+
 ;;-- Shifts 
 
 (define_expand "ashl3"
Index: rl78-real.md
===
--- rl78-real.md(revision 257806)
+++ rl78-real.md(working copy)
@@ -240,6 +240,16 @@
   [(set (attr "update_Z") (const_string "update_Z"))]
 )
 
+(define_insn "*one_cmplhi2_real"
+ [(set (match_operand:HI 0 "register_operand" "=A")
+   (xor:HI (match_operand:HI 1 "general_operand" "0")
+   (const_int -1)))
+ ]
+ "rl78_real_insns_ok ()"
+ "xor a, #-1 \;xor 0xFFEF8, #-1 ;one_cmplhi2 %0, %1"
+ [(set_attr "update_Z" "clobber")]
+)
+
 ;;-- Shifts 
 
 (define_insn "*ashlqi3_real"
Index: rl78-virt.md
===
--- rl78-virt.md(revision 257806)
+++ rl78-virt.md(working copy)
@@ -165,6 +165,16 @@
   "v.xor\t%0, %1, %2"
 )
 
+(define_insn "*one_cmplhi2_virt"
+ [(set (match_operand:HI 0 "rl78_nonfar_nonimm_operand" "=v")
+  (xor:HI (match_operand:HI 1 "general_operand"  "ivU")
+   (const_int -1)))
+  ]
+  "rl78_virt_insns_ok ()"
+  "v.one_cmplhi2\t%0, %1"
+ [(set_attr "valloc" "op1")]
+)
+
 ;;-- Shifts 
 
 (define_insn "*ashl3_virt"

{PATCH] RL78 movdf define expand

[Sebastian Perta]

Hello,

The following patch defines a new expand movdf, it is similar to the movdi
expand which I implemented a while ago.
The usefulness of the patch can be seen easily even on the following test
case where it reduces the code size from 199 bytes to 109 bytes:

long double long_double_add(long double a, long double b)
{
return a + b;
}

Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

Best Regards,
Sebastian

Index: ChangeLog
===
--- ChangeLog   (revision 257733)
+++ ChangeLog   (working copy)
@@ -1,3 +1,7 @@
+2018-02-16  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/rl78.md (movdf): New define expand.
+
 2018-02-16  Richard Biener  <rguent...@suse.de>
 
PR tree-optimization/84417




Index: rl78.md
===
--- rl78.md (revision 257733)
+++ rl78.md (working copy)
@@ -727,6 +727,14 @@
   DONE;"
 )
 
+(define_expand "movdf"
+  [(set (match_operand:DF 0 "nonimmediate_operand" "")
+(match_operand:DF 1 "general_operand" ""))]
+  ""
+  "rl78_split_movdi(operands, DFmode);
+  DONE;"
+)
+
 (define_expand "umindi3"
  [(set (match_operand:DI  0 "nonimmediate_operand" "")
(umin:DI (match_operand:DI 1 "general_operand"  "")

[PATCH] RX TARGET_RTX_COSTS function

[Sebastian Perta]

Hello,

DJ has posted a patch a few years ago which implements TARGET_RTX_COSTS for
RX:
https://gcc.gnu.org/ml/gcc-patches/2012-05/msg8.html

Nick has accepted the patch:
https://gcc.gnu.org/ml/gcc-patches/2012-05/msg00012.html

But it was never made it into the trunk.

The patch required some changes (the prototype, second param more exactly,
has changed) in order to compile in the trunk.
So I updated this and I also same a further change to the patch: I disabled
the replacement of the division with multiplication of reciprocals on -Os
because it increases code size for example for the following division:
int a;
void foo()
{
  a = a / 24;
}

The output code without this patch or with my updated patch it looks like:
_foo:
mov.L   #_a, r4
mov.L   [r4], r14
div #24, r14
mov.L   r14, [r4]
rts

While with DJ's original patch:

_foo:
pushm   r7-r8
mov.L   #_a, r3
mov.L   [r3], r14
mov.L   #0x2aab, r7
emulr14, r7
shar#2, r8, r4
shar#31, r14
sub r14, r4, r14
mov.L   r14, [r3]
rtsd#8, r7-r8

Regression test is OK, I tested with the following command:
"make -k check-gcc RUNTESTFLAGS=--target_board=rx-sim"

Please let me know if this OK to check-in.

Best Regards,
Sebastian

Index: ChangeLog
===
--- ChangeLog   (revision 257628)
+++ ChangeLog   (working copy)
@@ -1,3 +1,8 @@
+2018-02-13  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rx/rx.c (TARGET_RTX_COSTS): Define.
+   * config/rx/rx.c (rx_rtx_costs): New function.
+
 2018-02-13  Paolo Bonzini <bonz...@gnu.org>
 
PR sanitizer/84340



Index: rx.c
===
--- rx.c(revision 257412)
+++ rx.c(working copy)
@@ -2975,7 +2975,73 @@
   return COSTS_N_INSNS (1);
 }
 
+#undef  TARGET_RTX_COSTS
+#define TARGET_RTX_COSTS rx_rtx_costs
+
 static bool
+rx_rtx_costs (rtx  x,
+   machine_mode mode,
+   int  outer_code ATTRIBUTE_UNUSED,
+   int  opno ATTRIBUTE_UNUSED,
+   int *total,
+   bool speed)
+{
+  int code = GET_CODE (x);
+
+  if((GET_CODE (x) == CONST_INT) && (INTVAL (x) == 0))
+   {
+   *total = 0;
+   return true;
+   }
+  switch (code)
+{
+case MULT:
+  if (mode == DImode)
+   {
+ *total = COSTS_N_INSNS (2);
+ return true;
+   }
+  /* fall through */
+case PLUS:
+case MINUS:
+case AND:
+case COMPARE:
+case IOR:
+case XOR:
+  if (GET_CODE (XEXP (x, 0)) == MEM
+ || GET_CODE (XEXP (x, 1)) == MEM)
+   *total = COSTS_N_INSNS (3);
+  else
+   *total = COSTS_N_INSNS (1);
+  return true;
+
+case DIV:
+  if(speed)
+ /* This is worst case.  */
+ *total = COSTS_N_INSNS (20);
+  else
+ *total = COSTS_N_INSNS (3);
+  return true;
+
+case UDIV:
+  if(speed)
+ /* This is worst case.  */
+ *total = COSTS_N_INSNS (18);
+  else
+ *total = COSTS_N_INSNS (3);
+  return true;
+
+case IF_THEN_ELSE:
+  *total = COSTS_N_INSNS (3);
+  return true;
+
+default:
+  break;
+}
+  return false;
+}
+
+static bool
 rx_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
 {
   /* We can always eliminate to the frame pointer.

RE: [PATCH] RL78 new "vector" function attribute

[Sebastian Perta]

Hi DJ,

>>Looks OK to me, but wait a day or two for a docs person to comment on...
6 days no comments so far, can I check in now?

>>if the new line is too long
There are many other lines which have the same length or are even longer
this is why I let it as it is.

Also based on comments from Jakub (on a different patch) I corrected the
Changelog entry for this patch (see below). Is this OK?

Best Regards,
Sebastian

Index: ChangeLog
===
--- ChangeLog   (revision 257588)
+++ ChangeLog   (working copy)
@@ -1,3 +1,13 @@
+2018-02-12  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/rl78.c (add_vector_labels): New function.
+   * config/rl78/rl78.c (rl78_handle_vector_attribute): New function.
+   * config/rl78/rl78.c (rl78_start_function): Call add_vector_labels.
+   * config/rl78/rl78.c (rl78_handle_func_attribute): Removed the
assert 
+   which checks that no arguments are passed.
+   * config/rl78/rl78.c (rl78_attribute_table): Add "vector" attribute.
+   * doc/extend.texi: Documentation for the new attribute.
+
 2018-02-12  Richard Biener  <rguent...@suse.de>
 
PR tree-optimization/84037
Index: testsuite/ChangeLog
===
--- testsuite/ChangeLog (revision 257588)
+++ testsuite/ChangeLog (working copy)
@@ -1,3 +1,7 @@
+2018-02-12  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * gcc.target/rl78/test_auto_vector.c: New test.
+
 2018-02-12  Tamar Christina  <tamar.christ...@arm.com>
 
PR target/82641



> -Original Message-
> From: DJ Delorie [mailto:d...@redhat.com]
> Sent: 06 February 2018 22:57
> To: Sebastian Perta <sebastian.pe...@renesas.com>
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] RL78 new "vector" function attribute
> 
> 
> Sebastian Perta <sebastian.pe...@renesas.com> writes:
> > I've updated the patch (extend.texi) as you suggested.
> > Please let me know if this is OK to check-in, thank you!
> 
> Looks OK to me, but wait a day or two for a docs person to comment on...
> 
> > -On RX targets, you may specify one or more vector numbers as arguments
> > +On RX and RL78 targets, you may specify one or more vector numbers as
> arguments
> 
> ...if the new line is too long and if a paragraph reformat is warranted.
> 
> Thanks!

RE: PING [PATCH] RX movsicc degrade fix

[Sebastian Perta]

Hi Jakub,

>>Still missing . at the end of the above line.

The sentence continues on the next line (so the "." is there):

+* config/rx/constraints.md (CALL_OP_SYMBOL_REF): Added new constraint
+to allow or block "symbol_ref" depending on the value of TARGET_JSR.

 I think this is OK, please confirm.

Best Regards,
Sebastian

> -Original Message-
> From: Jakub Jelinek [mailto:ja...@redhat.com]
> Sent: 12 February 2018 13:30
> To: Sebastian Perta <sebastian.pe...@renesas.com>
> Cc: Nick Clifton <ni...@redhat.com>; gcc-patches  patc...@gcc.gnu.org>
> Subject: Re: PING [PATCH] RX movsicc degrade fix
>
> On Mon, Feb 12, 2018 at 01:27:24PM -, Sebastian Perta wrote:
> > --- ChangeLog(revision 257583)
> > +++ ChangeLog(working copy)
> > @@ -129,8 +129,7 @@
> >
> >  2018-02-09  Sebastian Perta  <sebastian.pe...@renesas.com>
> >
> > -* config/rx.md: updated "movsicc" expand to be matched by GCC
> > -* testsuite/gcc.target/rx/movsicc.c: new test case
> > +* config/rx/rx.md (movsicc): Update expander to be matched by
> GCC.
> >
> >  2018-02-09  Peter Bergner  <berg...@vnet.ibm.com>
> >
> > @@ -143,10 +142,10 @@
> >
> >  2018-02-09  Sebastian Perta  <sebastian.pe...@renesas.com>
> >
> > -* config/rx/constraints.md: added new constraint
> CALL_OP_SYMBOL_REF
> > -to allow or block "symbol_ref" depending on value of TARGET_JSR
> > -* config/rx/rx.md: use CALL_OP_SYMBOL_REF in call_internal and
> > -call_value_internal insns
> > +* config/rx/constraints.md (CALL_OP_SYMBOL_REF): Added new
> constraint
>
> Still missing . at the end of the above line.
>
> Otherwise LGTM.
>
> Jakub



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, 
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered 
No. 04586709.

RE: PING [PATCH] RX movsicc degrade fix

[Sebastian Perta]

HI Jakub,

I have updated the changelog entries as per your suggestion.
Is this OK? Thank you!

Best Regards,
Sebastian

Index: ChangeLog
===
--- ChangeLog   (revision 257583)
+++ ChangeLog   (working copy)
@@ -129,8 +129,7 @@
 
 2018-02-09  Sebastian Perta  <sebastian.pe...@renesas.com>
 
-   * config/rx.md: updated "movsicc" expand to be matched by GCC
-   * testsuite/gcc.target/rx/movsicc.c: new test case
+   * config/rx/rx.md (movsicc): Update expander to be matched by GCC.
 
 2018-02-09  Peter Bergner  <berg...@vnet.ibm.com>
 
@@ -143,10 +142,10 @@
 
 2018-02-09  Sebastian Perta  <sebastian.pe...@renesas.com>
 
-   * config/rx/constraints.md: added new constraint CALL_OP_SYMBOL_REF 
-   to allow or block "symbol_ref" depending on value of TARGET_JSR
-   * config/rx/rx.md: use CALL_OP_SYMBOL_REF in call_internal and 
-   call_value_internal insns
+   * config/rx/constraints.md (CALL_OP_SYMBOL_REF): Added new
constraint 
+   to allow or block "symbol_ref" depending on the value of TARGET_JSR.
+   * config/rx/rx.md (call_internal): Use CALL_OP_SYMBOL_REF.
+   * config/rx/rx.md (call_value_internal): Use CALL_OP_SYMBOL_REF.
 
 2018-02-09  Pierre-Marie de Rodat  <dero...@adacore.com>
 
@@ -1342,9 +1341,8 @@
 
 2018-01-26  Sebastian Perta  <sebastian.pe...@renesas.com>
 
-   * config/rl78/rl78.c: if operand 2 is const avoid addition with 0
-   and use incw and decw where possible
-   * testsuite/gcc.target/rl78/test_addsi3_internal.c: new file
+   * config/rl78/rl78.c (rl78_addsi3_internal): If operand 2 is const 
+   avoid addition with 0 and use incw and decw where possible.
 
 2018-01-26  Richard Biener  <rguent...@suse.de>
 
@@ -1675,15 +1673,15 @@
 
 2018-01-22  Sebastian Perta  <sebastian.pe...@renesas.com>
 
-   * config/rl78/rl78-expand.md: New define_expand "bswaphi2"
-   * config/rl78/rl78-virt.md: New define_insn "*bswaphi2_virt"
-   * config/rl78/rl78-real.md: New define_insn "*bswaphi2_real"
+   * config/rl78/rl78-expand.md (bswaphi2): New define_expand.
+   * config/rl78/rl78-virt.md (*bswaphi2_virt): New define_insn.
+   * config/rl78/rl78-real.md (*bswaphi2_real): New define_insn.
 
 2018-01-22  Sebastian Perta  <sebastian.pe...@renesas.com>
 
-   * config/rl78/rl78-protos.h: New function declaration
rl78_split_movdi
-   * config/rl78/rl78.md: New define_expand "movdi"
-   * config/rl78/rl78.c: New function definition rl78_split_movdi
+   * config/rl78/rl78-protos.h (rl78_split_movdi): New function
declaration.
+   * config/rl78/rl78.md (movdi): New define_expand.
+   * config/rl78/rl78.c (rl78_split_movdi): New function.
 
 2018-01-22  Michael Meissner  <meiss...@linux.vnet.ibm.com>
 
@@ -1706,19 +1704,19 @@
 
 2018-01-22  Sebastian Perta  <sebastian.pe...@renesas.com>
 
-   * config/rl78/rl78.md: New define_expand "anddi3".
+   * config/rl78/rl78.md (anddi3): New define_expand.
 
 2018-01-22  Sebastian Perta  <sebastian.pe...@renesas.com>
 
-   * config/rl78/rl78.md: New define_expand "umindi3".
+   * config/rl78/rl78.md (umindi3): New define_expand.
 
 2018-01-22  Sebastian Perta  <sebastian.pe...@renesas.com>
 
-   * config/rl78/rl78.md: New define_expand "smindi3".
+   * config/rl78/rl78.md (smindi3): New define_expand.
 
 2018-01-22  Sebastian Perta  <sebastian.pe...@renesas.com>
 
-   * config/rl78/rl78.md: New define_expand "smaxdi3".
+   * config/rl78/rl78.md (smaxdi3): New define_expand.
 
 2018-01-22 Carl Love <c...@us.ibm.com>
 
@@ -1738,12 +1736,12 @@
 
 2018-01-22  Sebastian Perta  <sebastian.pe...@renesas.com>
 
-   * config/rl78/rl78.md: New define_expand "umaxdi3".
+   * config/rl78/rl78.md (umaxdi3): New define_expand.
 
 2018-01-22  Sebastian Perta  <sebastian.pe...@renesas.com>
 
-   * config/rl78/rl78.c (rl78_note_reg_set): fixed dead reg check
-   for non-QImode registers
+   * config/rl78/rl78.c (rl78_note_reg_set): Fixed dead reg check
+   for non-QImode registers.
 
 2018-01-22  Richard Biener  <rguent...@suse.de>
 
Index: testsuite/ChangeLog
=======
--- testsuite/ChangeLog (revision 257583)
+++ testsuite/ChangeLog (working copy)
@@ -80,7 +80,11 @@
 
PR sanitizer/83987
* g++.dg/ubsan/pr83987-2.C: New test.
+   
+2018-02-09  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * gcc.target/rx/movsicc.c: New test.
+
 2018-02-09  Peter Bergner  <berg...@vnet.ibm.com>
 
PR target/83926
@@ -945,6 +949,10 @@
PR c++/83924
* g++.dg/warn/Wduplicated-branches5.C: New.
 
+2018-01-26  Sebastian Pert

RE: PING [PATCH] RX movsicc degrade fix

[Sebastian Perta]

Hi Jakub,

Thank you for pointing this out, I'm sorry!
Can I create a patch to correct the changelog entries?

Best Regards,
Sebastian
 
>>1) there should be a space between * and the filename
The spaces are there (see the changelog), the renesas mail server removes
them sometimes

> -Original Message-
> From: Jakub Jelinek [mailto:ja...@redhat.com]
> Sent: 09 February 2018 18:24
> To: Sebastian Perta <sebastian.pe...@renesas.com>; Nick Clifton
> <ni...@redhat.com>
> Cc: gcc-patches <gcc-patches@gcc.gnu.org>
> Subject: Re: PING [PATCH] RX movsicc degrade fix
> 
> On Wed, Feb 07, 2018 at 02:10:21PM +, Nick Clifton wrote:
> > Hi Sebastian,
> >
> >   Sorry for missing this one.  If it helps in the future, feel free to
ping me
> directly.
> >
> > > +2018-01-09  Sebastian Perta  <sebastian.pe...@renesas.com>
> > > +
> > > + *config/rx.md: updated "movsicc" expand to be matched by GCC
> > > + *testsuite/gcc.target/rx/movsicc.c: new test case
> >
> > Approved - please apply.
> 
> Note the ChangeLog is incorrect:
> 1) there should be a space between * and the filename
> 2) testsuite/ has its own ChangeLog, so changes for testsuite/ should
>go there and filenames be relative to the testsuite/ directory
> 3) there is no config/rx.md file, you've changed config/rx/rx.md instead
> 4) the format is * filename (what): Description. , so it should be
>   * config/rx/rx.md (movsicc): Update expander to be matched by
> GCC.
> 5) note capital letter after : and full stop at the end.
>   * gcc.target/rx/movsicc.c: New test.
>goes into testsuite/ChangeLog
> 
> Many other of your ChangeLog entries suffer from similar issues.
> 
>   Jakub

PING [PATCH] -mjsr option bug fix

[Sebastian Perta]

PING

> -Original Message-
> From: Sebastian Perta [mailto:sebastian.pe...@renesas.com]
> Sent: 08 January 2018 10:57
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH] -mjsr option bug fix
> 
> Hi,
> 
> The -mjsr option in RX should ensure the that BSR instruction is not
> generated, only JSR instruction should be generated.
> However this does not work as expected: BSR instruction still gets
generated
> even if -mjsr is passed in the command line.
> This is reproducible even if test cases from the gcc testsuite, for
example:
> gcc.c-torture\compile\920625-1.c
> gcc.c-torture\compile\20051216-1.c
> gcc.dg\torture\builtin-explog-1.c
> 
> The following patch fixes this issue by adding a new constraint to
call_internal
> and call_value_internal.
> The patch also contains a test case which I created as follows:
> 1. I copied gcc.c-torture\compile\20051216-1.c  to gcc.target\rx and
renamed
> to mjsr.c
> 2. added the following lines to scan the assembly files for BSR. If BSR is
> present the test fails.
> /* { dg-do compile } */
> /* { dg-options "-O2 -mjsr" } */
> /* { dg-final { scan-assembler-not "bsr" } } */
> 
> Regression test is OK, tested with the following command:
> make -k check-gcc RUNTESTFLAGS=--target_board=rx-sim
> 
> Please let me know if this is OK. Thank you!
> 
> Best Regards,
> Sebastian
> 
> Index: ChangeLog
> ======
> =
> --- ChangeLog (revision 256278)
> +++ ChangeLog (working copy)
> @@ -1,3 +1,10 @@
> +2018-01-05  Sebastian Perta  <sebastian.pe...@renesas.com>
> +
> + * config/rx/constraints.md: added new constraint
> CALL_OP_SYMBOL_REF
> + to allow or block "symbol_ref" depending on value of TARGET_JSR
> + * config/rx/rx.md: use CALL_OP_SYMBOL_REF in call_internal and
> + call_value_internal insns
> +
>  2018-01-05  Richard Sandiford  <richard.sandif...@linaro.org>
> 
>   * tree-vect-data-refs.c (vect_compute_data_ref_alignment): Don't
> Index: config/rx/constraints.md
> ==
> =
> --- config/rx/constraints.md  (revision 256278)
> +++ config/rx/constraints.md  (working copy)
> @@ -106,3 +106,9 @@
> )
>)
>  )
> +
> +(define_constraint "CALL_OP_SYMBOL_REF"
> +"constraint for call instructions using symbol ref"
> +(and (match_test "!TARGET_JSR")
> + (match_code "symbol_ref"))
> +)
> Index: config/rx/rx.md
> ==
> =
> --- config/rx/rx.md   (revision 256278)
> +++ config/rx/rx.md   (working copy)
> @@ -438,7 +438,7 @@
>  )
> 
>  (define_insn "call_internal"
> -  [(call (mem:QI (match_operand:SI 0 "rx_call_operand" "r,Symbol"))
> +  [(call (mem:QI (match_operand:SI 0 "rx_call_operand"
> "r,CALL_OP_SYMBOL_REF"))
>(const_int 0))
> (clobber (reg:CC CC_REG))]
>""
> @@ -466,7 +466,7 @@
> 
>  (define_insn "call_value_internal"
>[(set (match_operand  0 "register_operand" "=r,r")
> - (call (mem:QI (match_operand:SI 1 "rx_call_operand"   "r,Symbol"))
> + (call (mem:QI (match_operand:SI 1 "rx_call_operand"
> "r,CALL_OP_SYMBOL_REF"))
> (const_int 0)))
> (clobber (reg:CC CC_REG))]
>""
> Index: testsuite/gcc.target/rx/mjsr.c
> ==
> =
> --- testsuite/gcc.target/rx/mjsr.c(nonexistent)
> +++ testsuite/gcc.target/rx/mjsr.c(working copy)
> @@ -0,0 +1,134 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -mjsr" } */
> +
> +void *malloc (__SIZE_TYPE__);
> +void *realloc (void *, __SIZE_TYPE__);
> +
> +struct A { double x, y; };
> +struct B { double x0, y0, x1, y1; };
> +struct C { int n_points; int dir; struct B bbox; struct A *points; };
> +struct D { int n_segs; struct C segs[1]; };
> +
> +void foo (int, int, int *, int, int *, struct A **, int *, int *,
> +   struct D *, int *, struct D **, int *, int **);
> +int baz (struct A, struct A, struct A, struct A);
> +
> +static void
> +bar (struct D *svp, int *n_points_max,
> + struct A p, int *seg_map, int *active_segs, int i)
> +{
> +  int asi, n_points;
> +  struct C *seg;
> +
> +  asi = seg_map[active_segs[i]];
> +  seg = >segs[asi];
> +  n_points = seg->n_points;
> +  seg->points = ((struct A *)
> + realloc (seg->points, (n_points_max[asi] <<= 1) * s

PING [PATCH] RX movsicc degrade fix

[Sebastian Perta]

PING

> -Original Message-
> From: Sebastian Perta [mailto:sebastian.pe...@renesas.com]
> Sent: 09 January 2018 14:46
> To: 'gcc-patches@gcc.gnu.org' <gcc-patches@gcc.gnu.org>
> Subject: [PATCH] RX movsicc degrade fix
> 
> Hello,
> 
> In recent versions of GCC the define_expand "movsicc" has stopped being
> used by GCC (approx. 4.7.x/4.8.x onwards)
> The reason for this is that the first operand of if_then_else has SI mode
and
> it shouldn't have. If we take a look at movsicc for all other targets we
see this
> is true.
> The fix in rx.md is basically a copy paste from v850.md
> 
> The patch also adds a testcase in gcc.target/rx to make sure this degrade
> does not occur again.
> 
> 
> Regression test is OK with one observation (see below), tested with the
> following command:
> make -k check-gcc RUNTESTFLAGS=--target_board=rx-sim
> 
> 
> I have the following fail (which was not present before):
> FAIL: gcc.dg/loop-8.c scan-rtl-dump-times loop2_invariant "Decided" 1
> (found 0 times)
> 
> This is because the patch is effective in this test case and the dump is
not the
> same, I checked the asm code manually and it is OK.
> Is it possible to disable parts of a test case, not the whole test case (*
{ dg-
> final { scan-rtl-dump-times "Decided" 1 "loop2_invariant" } } */  from
loop-8.c
> in this example) for a particular target?
> 
> The total numbers of failures remains the same because the following FAIL
is
> not present anymore with this patch:
> FAIL: gcc.dg/ifcvt-4.c scan-rtl-dump ce1 "2 true changes made"
> 
> 
> Please let me know if this is OK. Thank you!
> 
> Best Regards,
> Sebastian
> 
> 
> Index: ChangeLog
> ==
> =
> --- ChangeLog (revision 256382)
> +++ ChangeLog (working copy)
> @@ -1,3 +1,8 @@
> +2018-01-09  Sebastian Perta  <sebastian.pe...@renesas.com>
> +
> + *config/rx.md: updated "movsicc" expand to be matched by GCC
> + *testsuite/gcc.target/rx/movsicc.c: new test case
> +
>  2018-01-09  Richard Biener  <rguent...@suse.de>
> 
>   PR tree-optimization/83668
> Index: config/rx/rx.md
> ==
> =
> --- config/rx/rx.md   (revision 256382)
> +++ config/rx/rx.md   (working copy)
> @@ -733,12 +733,17 @@
>  (define_expand "movsicc"
>[(parallel
>  [(set (match_operand:SI  0 "register_operand")
> -   (if_then_else:SI (match_operand:SI 1 "comparison_operator")
> +   (if_then_else:SI (match_operand 1 "comparison_operator")
>  (match_operand:SI 2 "nonmemory_operand")
>  (match_operand:SI 3 "nonmemory_operand")))
>   (clobber (reg:CC CC_REG))])]
>""
>  {
> +  /* Make sure that we have an integer comparison...  */
> +  if (GET_MODE (XEXP (operands[1], 0)) != CCmode
> +  && GET_MODE (XEXP (operands[1], 0)) != SImode)
> +FAIL;
> +
>/* One operand must be a constant or a register, the other must be a
> register.  */
>if (   ! CONSTANT_P (operands[2])
>&& ! CONSTANT_P (operands[3])
> Index: testsuite/gcc.target/rx/movsicc.c
> ==
> =
> --- testsuite/gcc.target/rx/movsicc.c (nonexistent)
> +++ testsuite/gcc.target/rx/movsicc.c (working copy)
> @@ -0,0 +1,94 @@
> +/* { dg-do compile } */
> +/* { dg-options "-Os" } */
> +
> +typedef unsigned char u8;
> +typedef unsigned short u16;
> +signed int Xa, Xb;
> +
> +signed int stzreg_beq(int i, int a, int b)
> +{
> +  signed int x;
> +  x = a;
> +  if (i)
> +x = b;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "bne 1f" } } */
> +
> +signed int stzreg_bge(int i, int a, int b, int c)
> +{
> +  signed int x;
> +  x = a;
> +  if (i<c)
> +x = b;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "blt 1f" } } */
> +
> +signed int stzreg_bgt(int i, int a, int b)
> +{
> +  signed int x;
> +  x = a;
> +  if (i<10)
> +x = b;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "ble 1f" } } */
> +
> +signed int stzreg_ble(int i, int a, int b)
> +{
> +  signed int x;
> +  x = a;
> +  if (i>0)
> +x = b;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "bgt 1f" } } */
> +
> +signed int stzreg_blt(int i, int a, int b)
> +{
> +  signed int x;
> +  x = a;
> +  if (i<0)
> +x = b;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "blt 1f" } } */
> +
> +signed int stzreg_bne(int i, int a, int b)
> +{
> +  signed int x;
> +  x = a;
> +  if (!i)
> +x = b;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "beq 1f" } } */
> +
> +signed int stzimm_le( int i, int a )
> +{
> +  signed int x;
> +  x = a;
> +  if (i>0)
> +x = 5;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "ble 1f" } } */
> +
> +signed int stzimm_le_r( int i, int a )
> +{
> +  signed int x;
> +  x = a;
> +  if (i<0)
> +x = 5;
> +  return x;
> +}
> +
> +/* { dg-final { scan-assembler "bge 1f" } } */

RE: [PATCH] RL78 new "vector" function attribute

[Sebastian Perta]

Hi DJ,

I've updated the patch (extend.texi) as you suggested.
Please let me know if this is OK to check-in, thank you!

Best Regards,
Sebastian

Index: config/rl78/rl78.c
===
--- config/rl78/rl78.c(revision 257142)
+++ config/rl78/rl78.c(working copy)
@@ -809,7 +809,6 @@
 bool * no_add_attrs)
 {
   gcc_assert (DECL_P (* node));
-  gcc_assert (args == NULL_TREE);

   if (TREE_CODE (* node) != FUNCTION_DECL)
 {
@@ -868,6 +867,28 @@
   return NULL_TREE;
 }

+/* Check "vector" attribute.  */
+
+static tree
+rl78_handle_vector_attribute (tree * node,
+tree   name,
+tree   args,
+intflags ATTRIBUTE_UNUSED,
+bool * no_add_attrs)
+{
+  gcc_assert (DECL_P (* node));
+  gcc_assert (args != NULL_TREE);
+
+  if (TREE_CODE (* node) != FUNCTION_DECL)
+{
+  warning (OPT_Wattributes, "%qE attribute only applies to functions",
+   name);
+  * no_add_attrs = true;
+}
+
+  return NULL_TREE;
+}
+
 #undef  TARGET_ATTRIBUTE_TABLE
 #define TARGET_ATTRIBUTE_TABLErl78_attribute_table

@@ -876,7 +897,7 @@
 {
   /* Name, min_len, max_len, decl_req, type_req, fn_type_req,
  affects_type_identity, handler, exclude.  */
-  { "interrupt",  0, 0, true, false, false, false,
+  { "interrupt",  0, -1, true, false, false, false,
 rl78_handle_func_attribute, NULL },
   { "brk_interrupt",  0, 0, true, false, false, false,
 rl78_handle_func_attribute, NULL },
@@ -884,6 +905,8 @@
 rl78_handle_naked_attribute, NULL },
   { "saddr",  0, 0, true, false, false, false,
 rl78_handle_saddr_attribute, NULL },
+  { "vector", 1, -1, true, false, false,
+rl78_handle_vector_attribute, false },
   { NULL, 0, 0, false, false, false, false, NULL, NULL }
 };

@@ -1583,6 +1606,62 @@
 #undef  TARGET_ASM_FUNCTION_PROLOGUE
 #define TARGET_ASM_FUNCTION_PROLOGUErl78_start_function

+static void
+add_vector_labels (FILE *file, const char *aname)
+{
+  tree vec_attr;
+  tree val_attr;
+  const char *vname = "vect";
+  const char *s;
+  int vnum;
+
+  /* This node is for the vector/interrupt tag itself */
+  vec_attr = lookup_attribute (aname, DECL_ATTRIBUTES (current_function_decl));
+  if (!vec_attr)
+return;
+
+  /* Now point it at the first argument */
+  vec_attr = TREE_VALUE (vec_attr);
+
+  /* Iterate through the arguments.  */
+  while (vec_attr)
+{
+  val_attr = TREE_VALUE (vec_attr);
+  switch (TREE_CODE (val_attr))
+{
+case STRING_CST:
+  s = TREE_STRING_POINTER (val_attr);
+  goto string_id_common;
+
+case IDENTIFIER_NODE:
+  s = IDENTIFIER_POINTER (val_attr);
+
+string_id_common:
+  if (strcmp (s, "$default") == 0)
+{
+  fprintf (file, "\t.global\t$tableentry$default$%s\n", vname);
+  fprintf (file, "$tableentry$default$%s:\n", vname);
+}
+  else
+vname = s;
+  break;
+
+case INTEGER_CST:
+  vnum = TREE_INT_CST_LOW (val_attr);
+
+  fprintf (file, "\t.global\t$tableentry$%d$%s\n", vnum, vname);
+  fprintf (file, "$tableentry$%d$%s:\n", vnum, vname);
+  break;
+
+default:
+  ;
+}
+
+  vec_attr = TREE_CHAIN (vec_attr);
+}
+
+}
+
 /* We don't use this to actually emit the function prologue.  We use
this to insert a comment in the asm file describing the
function.  */
@@ -1590,6 +1669,9 @@
 rl78_start_function (FILE *file)
 {
   int i;
+
+  add_vector_labels (file, "interrupt");
+  add_vector_labels (file, "vector");

   if (cfun->machine->framesize == 0)
 return;
Index: doc/extend.texi
===
--- doc/extend.texi(revision 257142)
+++ doc/extend.texi(working copy)
@@ -5182,7 +5182,7 @@
 function entry and exit sequences suitable for use in an interrupt handler
 when this attribute is present.

-On RX targets, you may specify one or more vector numbers as arguments
+On RX and RL78 targets, you may specify one or more vector numbers as arguments
 to the attribute, as well as naming an alternate table name.
 Parameters are handled sequentially, so one handler can be assigned to
 multiple entries in multiple tables.  One may also pass the magic
Index: testsuite/gcc.target/rl78/test_auto_vector.c
===
--- testsuite/gcc.target/rl78/test_auto_vector.c(nonexistent)
+++ testsuite/gcc.target/rl78/test_auto_vector.c(working copy)
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+
+void __attribute__ ((interrupt (5))) interrupt_5_handler ();
+
+void interrupt_5_handler ()
+{
+}
+
+void __attribute__ ((vector (4))) interrupt_4_handler ();
+
+void interrupt_4_handler ()
+{
+}
+
+void __attribute__ ((interrupt)) interrupt_handler ();
+
+void interrupt_handler ()
+{
+}
+
+/* { dg-final { scan-assembler "tableentry" } } */

> -Original Message-
> From: DJ Delo

RE: [PATCH] RL78 new "vector" function attribute

[Sebastian Perta]

Hello,

The below patch adds a new vector attribute for RL78, it is basically a copy
past of what DJ has done for RX a while ago:
https://gcc.gnu.org/ml/gcc-patches/2014-05/msg02387.html

The patch adds also a test case and updates extend.texi with the new
attribute.

Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

As you can see I had to duplicate some of the code from RX for this on the
other hand if I try to make this attribute generic 
It will become available for all targets which I'm not sure if it is
desirable. Please let me know if this is OK to checkin or should I 
look further into avoiding the code duplication.

Best Regards,
Sebastian

Index: ChangeLog
===
--- ChangeLog   (revision 257142)
+++ ChangeLog   (working copy)
@@ -1,3 +1,14 @@
+2018-01-29  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/rl78.c (add_vector_labels): New function.
+   * config/rl78/rl78.c (rl78_handle_vector_attribute): New function.
+   * config/rl78/rl78.c (rl78_start_function): Call add_vector_labels.
+   * config/rl78/rl78.c (rl78_handle_func_attribute): Removed the
assert 
+   which checks that no arguments are passed.
+   * config/rl78/rl78.c (rl78_attribute_table): Add "vector" attribute.
+   * testsuite/gcc.target/rl78/test_auto_vector.c: New file.
+   * doc/extend.texi: documentation for the new attribute
+   
 2018-01-29  Richard Biener  <rguent...@suse.de>
 
PR tree-optimization/84057




Index: config/rl78/rl78.c
===
--- config/rl78/rl78.c  (revision 257142)
+++ config/rl78/rl78.c  (working copy)
@@ -809,7 +809,6 @@
bool * no_add_attrs)
 {
   gcc_assert (DECL_P (* node));
-  gcc_assert (args == NULL_TREE);
 
   if (TREE_CODE (* node) != FUNCTION_DECL)
 {
@@ -868,6 +867,28 @@
   return NULL_TREE;
 }
 
+/* Check "vector" attribute.  */
+
+static tree
+rl78_handle_vector_attribute (tree * node,
+   tree   name,
+   tree   args,
+   intflags ATTRIBUTE_UNUSED,
+   bool * no_add_attrs)
+{
+  gcc_assert (DECL_P (* node));
+  gcc_assert (args != NULL_TREE);
+
+  if (TREE_CODE (* node) != FUNCTION_DECL)
+{
+  warning (OPT_Wattributes, "%qE attribute only applies to functions",
+  name);
+  * no_add_attrs = true;
+}
+
+  return NULL_TREE;
+}
+
 #undef  TARGET_ATTRIBUTE_TABLE
 #define TARGET_ATTRIBUTE_TABLE rl78_attribute_table
 
@@ -876,7 +897,7 @@
 {
   /* Name, min_len, max_len, decl_req, type_req, fn_type_req,
  affects_type_identity, handler, exclude.  */
-  { "interrupt",  0, 0, true, false, false, false,
+  { "interrupt",  0, -1, true, false, false, false,
 rl78_handle_func_attribute, NULL },
   { "brk_interrupt",  0, 0, true, false, false, false,
 rl78_handle_func_attribute, NULL },
@@ -884,6 +905,8 @@
 rl78_handle_naked_attribute, NULL },
   { "saddr",  0, 0, true, false, false, false,
 rl78_handle_saddr_attribute, NULL },
+  { "vector", 1, -1, true, false, false, 
+   rl78_handle_vector_attribute, false },
   { NULL, 0, 0, false, false, false, false, NULL, NULL }
 };
 
@@ -1583,6 +1606,62 @@
 #undef  TARGET_ASM_FUNCTION_PROLOGUE
 #define TARGET_ASM_FUNCTION_PROLOGUE   rl78_start_function
 
+static void
+add_vector_labels (FILE *file, const char *aname)
+{
+  tree vec_attr;
+  tree val_attr;
+  const char *vname = "vect";
+  const char *s;
+  int vnum;
+
+  /* This node is for the vector/interrupt tag itself */
+  vec_attr = lookup_attribute (aname, DECL_ATTRIBUTES
(current_function_decl));
+  if (!vec_attr)
+return;
+
+  /* Now point it at the first argument */
+  vec_attr = TREE_VALUE (vec_attr);
+
+  /* Iterate through the arguments.  */
+  while (vec_attr)
+{
+  val_attr = TREE_VALUE (vec_attr);
+  switch (TREE_CODE (val_attr))
+   {
+   case STRING_CST:
+ s = TREE_STRING_POINTER (val_attr);
+ goto string_id_common;
+
+   case IDENTIFIER_NODE:
+ s = IDENTIFIER_POINTER (val_attr);
+
+   string_id_common:
+ if (strcmp (s, "$default") == 0)
+   {
+ fprintf (file, "\t.global\t$tableentry$default$%s\n", vname);
+ fprintf (file, "$tableentry$default$%s:\n", vname);
+   }
+ else
+   vname = s;
+ break;
+
+   case INTEGER_CST:
+ vnum = TREE_INT_CST_LOW (val_attr);
+
+ fprintf (file, "\t.global\t$tableentry$%d$%s\n", vnum, vname);
+ fprintf (file, "$tableentry$%d$%s:\n", vnum, vname);
+ break;
+
+   default:
+ ;
+  

RE: [PATCH] RL78 addsi3 improvement

[Sebastian Perta]

HI DJ,

Thank you!

>> I wonder if these types of optimizations should be added to the
assembler too?  
Thank you for the suggestion, I will take a look into it.

Best Regards,
Sebastian


> -Original Message-
> From: DJ Delorie [mailto:d...@redhat.com]
> Sent: 25 January 2018 19:38
> To: Sebastian Perta <sebastian.pe...@renesas.com>
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] RL78 addsi3 improvement
> 
> 
> This is OK.
> 
> I wonder if these types of optimizations should be added to the
> assembler too?  At least, if relaxation is enabled...

[PATCH] RL78 addsi3 improvement

[Sebastian Perta]

Hello,
 
The following patch improves addsi3 by eliminating addw ax, #0 and replacing
addw ax, #-1 with decw ax where possible (if operand 2 is const)

The patch adds also a test case to check this.

Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim
 
 Please let me know if this is OK to check-in, Thank you!

Best Regards,
 Sebastian

Index: ChangeLog
===
--- ChangeLog   (revision 257055)
+++ ChangeLog   (working copy)
@@ -1,3 +1,9 @@
+2018-01-25  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/rl78.c: if operand 2 is const avoid addition with 0
+   and use incw and decw where possible
+   * testsuite/gcc.target/rl78/test_addsi3_internal.c: new file
+
 2018-01-25  Jakub Jelinek  <ja...@redhat.com>
 
PR middle-end/83977




Index: config/rl78/rl78.c
===
--- config/rl78/rl78.c  (revision 257055)
+++ config/rl78/rl78.c  (working copy)
@@ -80,6 +80,9 @@
   "sp", "ap", "psw", "es", "cs"
 };
 
+/* used by rl78_addsi3_internal for formatting insns output */
+static char fmt_buffer[1024];
+
 /* Structure for G13 MDUC registers.  */
 struct mduc_reg_type
 {
@@ -4788,6 +4791,8 @@
 const char *
 rl78_addsi3_internal (rtx * operands, unsigned int alternative)
 {
+  const char *addH2 = "addw ax, %H2\n\t";
+
   /* If we are adding in a constant symbolic address when -mes0
  is active then we know that the address must be <64K and
  that it is invalid to access anything above 64K relative to
@@ -4799,16 +4804,38 @@
   && ! TREE_SIDE_EFFECTS (SYMBOL_REF_DECL (operands[2])))
 return "movw ax, %h1\n\taddw ax, %h2\n\tmovw %h0, ax";
 
+  if(CONST_INT_P(operands[2]))
+  {
+if((INTVAL(operands[2]) & 0x) == 0)
+{
+addH2 = "";
+}
+else if((INTVAL(operands[2]) & 0x) == 0x0001)
+{
+addH2 = "incw ax\n\t";
+}
+else if((INTVAL(operands[2]) & 0x) == 0x)
+{
+addH2 = "decw ax\n\t";
+}
+  }
+
   switch (alternative)
 {
 case 0:
 case 1:
-  return "movw ax, %h1\n\taddw ax, %h2\n\tmovw %h0, ax\n\tmovw ax,
%H1\n\tsknc\n\tincw ax\n\taddw ax, %H2\n\tmovw %H0, ax";
+ snprintf(fmt_buffer, sizeof(fmt_buffer),
+   "movw ax, %%h1\n\taddw ax, %%h2\n\tmovw %%h0, ax\n\tmovw ax,
%%H1\n\tsknc\n\tincw ax\n\t%smovw %%H0,ax", addH2);
+ break;
 case 2:
-  return "movw ax, %h1\n\taddw ax,%h2\n\tmovw bc, ax\n\tmovw ax,
%H1\n\tsknc\n\tincw ax\n\taddw ax, %H2\n\tmovw %H0, ax\n\tmovw ax,
bc\n\tmovw %h0, ax";
+ snprintf(fmt_buffer, sizeof(fmt_buffer),
+   "movw ax, %%h1\n\taddw ax, %%h2\n\tmovw bc, ax\n\tmovw ax,
%%H1\n\tsknc\n\tincw ax\n\t%smovw %%H0, ax\n\tmovw ax, bc\n\tmovw %%h0, ax",
addH2);
+ break;
 default:
   gcc_unreachable ();
 }
+
+  return fmt_buffer;
 }
 
 rtx
Index: testsuite/gcc.target/rl78/test_addsi3_internal.c
===
--- testsuite/gcc.target/rl78/test_addsi3_internal.c(nonexistent)
+++ testsuite/gcc.target/rl78/test_addsi3_internal.c(working copy)
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+long l, v;
+
+void test1()
+{
+   l++;
+}
+
+void test2()
+{
+   l--;
+}
+
+void test3()
+{
+   l += 10;
+}
+
+long test4()
+{
+   return l + v;
+}
+
+/* { dg-final { scan-assembler-not "addw ax, #0" } } */
+/* { dg-final { scan-assembler-not "addw ax, #-1" } } */
+/* { dg-final { scan-assembler "decw ax" } } */

RE: [PATCH] RL78 UNUSED note setting bug fix in rl78_note_reg_set

[Sebastian Perta]

HI DJ,

>>Do you have checkin privs yet?
>> This is ok aside from.. ... + /* Do not mark the reg unused unless all
QImode parts of it are dead.  */
Can I checkin this patch? Thank you!

Best Regards,
Sebastian


> -Original Message-
> From: Sebastian Perta
> Sent: 12 January 2018 18:42
> To: 'DJ Delorie' <d...@redhat.com>
> Cc: gcc-patches@gcc.gnu.org
> Subject: RE: [PATCH] RL78 UNUSED note setting bug fix in rl78_note_reg_set
> 
> Hi DJ,
> 
> >>Do you have checkin privs yet?
> I have filled out the form. "Thanks for your request. It must be approved
by
> the person you named as approver ...
> 
> >> This is ok aside from..
> Sorry about this. I will keep this in mind in future.
> I corrected the patch with your second suggestion.
> 
> Best Regards,
> Sebastian
> 
> Index: ChangeLog
> ==
> =
> --- ChangeLog (revision 256590)
> +++ ChangeLog (working copy)
> @@ -1,3 +1,8 @@
> +2018-01-12  Sebastian Perta  <sebastian.pe...@renesas.com>
> +
> + * config/rl78/rl78.c (rl78_note_reg_set): fixed dead reg check
> + for non-QImode registers
> +
>  2018-01-12  Vladimir Makarov  <vmaka...@redhat.com>
> 
>   PR rtl-optimization/80481
> Index: config/rl78/rl78.c
> ==
> =
> --- config/rl78/rl78.c(revision 256590)
> +++ config/rl78/rl78.c(working copy)
> @@ -3792,7 +3792,7 @@
>  rl78_note_reg_set (char *dead, rtx d, rtx insn)
>  {
>int r, i;
> -
> +  bool is_dead;
>if (GET_CODE (d) == MEM)
>  rl78_note_reg_uses (dead, XEXP (d, 0), insn);
> 
> @@ -3799,9 +3799,15 @@
>if (GET_CODE (d) != REG)
>  return;
> 
> + /* Do not mark the reg unused unless all QImode parts of it are dead.
*/
>r = REGNO (d);
> -  if (dead [r])
> -add_reg_note (insn, REG_UNUSED, gen_rtx_REG (GET_MODE (d), r));
> +  is_dead = true;
> +  for (i = 0; i < GET_MODE_SIZE (GET_MODE (d)); i ++)
> +   if (!dead [r + i])
> +   is_dead = false;
> +  if(is_dead)
> + add_reg_note (insn, REG_UNUSED, gen_rtx_REG (GET_MODE (d),
> r));
>if (dump_file)
>  fprintf (dump_file, "note set reg %d size %d\n", r, GET_MODE_SIZE
> (GET_MODE (d)));
>for (i = 0; i < GET_MODE_SIZE (GET_MODE (d)); i ++)
> 
> > -Original Message-
> > From: DJ Delorie [mailto:d...@redhat.com]
> > Sent: 12 January 2018 18:12
> > To: Sebastian Perta <sebastian.pe...@renesas.com>
> > Cc: gcc-patches@gcc.gnu.org
> > Subject: Re: [PATCH] RL78 UNUSED note setting bug fix in
> rl78_note_reg_set
> >
> >
> > "Sebastian Perta" <sebastian.pe...@renesas.com> writes:
> > > Please let me know if this is OK. Thank you!
> >
> > Do you have checkin privs yet?
> >
> > This is ok aside from..
> >
> > > +  /* 'dead' keeps track of the QImode registers if r is of different
size
> > > +  we need to check the other subparts as well  */
> >
> > Missing period at the end of a sentence; should capitalize first word
> > but it's a variable, which should be block caps anyway, and it reads
> > better as two sentences:
> >
> > > +  /* DEAD keeps track of the QImode registers.  If R is of different
size
> > > +  we need to check the other subparts as well.  */
> >
> > Or rewrite to not mention variables?
> >
> > > + /* Do not mark the reg unused unless all QImode parts of it are
dead.
> */

RE: New code merge optimization?

[Sebastian Perta]

Hi,

Thank you very much!
I tried with and without -fcode-hoisting the file I mentioned earlier 
gcc/testsuite/gcc.c-torture/execute/pr58574.c but it remains the same.
But I can certainly extend on this.

Sorry I didn't found out this myself! I'll do more research next time before I 
start asking questions.

Best Regards,
Sebastian



> -Original Message-
> From: Andrew Pinski [mailto:pins...@gmail.com]
> Sent: 18 January 2018 16:19
> To: Sebastian Perta <sebastian.pe...@renesas.com>
> Cc: Martin Jambor <mjam...@suse.cz>; gcc-patches@gcc.gnu.org;
> l...@gcc.gnu.org
> Subject: Re: New code merge optimization?
>
> On Thu, Jan 18, 2018 at 8:03 AM, Sebastian Perta
> <sebastian.pe...@renesas.com> wrote:
> > Hi,
> >
> > Thank you!
> > As the description says this finds equivalent functions, I would like to 
> > find
> identical sequences inside
> > functions but at least this will provide all the up to date tools to compare
> code sequences, thank you again!
>
> There is already some identical sequence finding (code hoisting) in
> GCC 7 (and above), see
> https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00360.html
> for the patch.
>
> Thanks,
> Andrew
>
> >
> > Best Regards,
> > Sebastian
> >
> >
> >> -Original Message-
> >> From: Martin Jambor [mailto:mjam...@suse.cz]
> >> Sent: 18 January 2018 15:18
> >> To: Sebastian Perta <sebastian.pe...@renesas.com>; gcc-
> >> patc...@gcc.gnu.org
> >> Cc: l...@gcc.gnu.org
> >> Subject: Re: New code merge optimization?
> >>
> >> Hi,
> >>
> >> On Thu, Jan 18 2018, Sebastian Perta wrote:
> >> > Hello,
> >> >
> >> > I am interested in implementing a new pass in gcc to merge identical
> >> > sequences of code in GCC to be used mainly for RL78.
> >> > The commercial RL78 compilers have such algorithms implemented and
> >> they make
> >> > quite good use of it.
> >> > Opportunities arise from the limited capabilities of RL78, for other
> targets
> >> > this might be a lot less useful.
> >> >
> >> > A while ago I found the following:
> >> > https://www.gnu.org/software/gcc/projects/cfo.html
> >> > And I ported all algorithms to gcc 4.9.2 and tried it on RL78 and RX and
> >> > this is what I found out:
> >> > For RX: no visible improvements with any of them
> >> > For RL78: some minor improvements only with -frtl-seqbastr:
> >> > Compiling all the C files from gcc/testsuite/gcc.c-torture/execute/*c
> with
> >> > "-Os" and "-Os  -frtl-seqabstr" (using the modified gcc 4.9.2)
> >> > The algorithm was effective only in 60 files(out of 1643 files, that's 
> >> > only
> >> > 0.03% of the files currently present in gcc/testsuite/gcc.c-
> torture/execute)
> >> > On those 60 files I got an average of 6.5% improvement with the best
> >> > improvement for pr58574.c (36.4%).
> >> >
> >> > What do you think: is it worthwhile porting this to the trunk or I will 
> >> > just
> >> > waste my time?
> >> > Or should I start fresh? Maybe start from here:
> >> > http://llvm.org/docs/MergeFunctions.html?
> >>
> >> Martin Liška contributed identical code folding to GCC quite a few years
> >> ago now.  Look up the -fipa-icf option.  If that is not enough for you,
> >> starting from that seems more natural.
> >>
> >> Martin
> >>
> >> >
> >> > Gimple or rtl?
> >> > I suppose the preferred way will be to do this in gimple; however based
> on
> >> > what I did so far,  it's more likely to find identical sequences in rtl 
> >> > (for
> >> > RL78).
> >> >
> >> > Any thoughts? Thank you!
> >> >
> >> > Best Regards,
> >> > Sebastian
> >
> >
> >
> > Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne
> End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under
> Registered No. 04586709.



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, 
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered 
No. 04586709.

RE: New code merge optimization?

[Sebastian Perta]

Hi,

Thank you!
As the description says this finds equivalent functions, I would like to find 
identical sequences inside
functions but at least this will provide all the up to date tools to compare 
code sequences, thank you again!

Best Regards,
Sebastian


> -Original Message-
> From: Martin Jambor [mailto:mjam...@suse.cz]
> Sent: 18 January 2018 15:18
> To: Sebastian Perta <sebastian.pe...@renesas.com>; gcc-
> patc...@gcc.gnu.org
> Cc: l...@gcc.gnu.org
> Subject: Re: New code merge optimization?
>
> Hi,
>
> On Thu, Jan 18 2018, Sebastian Perta wrote:
> > Hello,
> >
> > I am interested in implementing a new pass in gcc to merge identical
> > sequences of code in GCC to be used mainly for RL78.
> > The commercial RL78 compilers have such algorithms implemented and
> they make
> > quite good use of it.
> > Opportunities arise from the limited capabilities of RL78, for other targets
> > this might be a lot less useful.
> >
> > A while ago I found the following:
> > https://www.gnu.org/software/gcc/projects/cfo.html
> > And I ported all algorithms to gcc 4.9.2 and tried it on RL78 and RX and
> > this is what I found out:
> > For RX: no visible improvements with any of them
> > For RL78: some minor improvements only with -frtl-seqbastr:
> > Compiling all the C files from gcc/testsuite/gcc.c-torture/execute/*c  with
> > "-Os" and "-Os  -frtl-seqabstr" (using the modified gcc 4.9.2)
> > The algorithm was effective only in 60 files(out of 1643 files, that's only
> > 0.03% of the files currently present in gcc/testsuite/gcc.c-torture/execute)
> > On those 60 files I got an average of 6.5% improvement with the best
> > improvement for pr58574.c (36.4%).
> >
> > What do you think: is it worthwhile porting this to the trunk or I will just
> > waste my time?
> > Or should I start fresh? Maybe start from here:
> > http://llvm.org/docs/MergeFunctions.html?
>
> Martin Liška contributed identical code folding to GCC quite a few years
> ago now.  Look up the -fipa-icf option.  If that is not enough for you,
> starting from that seems more natural.
>
> Martin
>
> >
> > Gimple or rtl?
> > I suppose the preferred way will be to do this in gimple; however based on
> > what I did so far,  it's more likely to find identical sequences in rtl (for
> > RL78).
> >
> > Any thoughts? Thank you!
> >
> > Best Regards,
> > Sebastian



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, 
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered 
No. 04586709.

New code merge optimization?

[Sebastian Perta]

Hello,

I am interested in implementing a new pass in gcc to merge identical
sequences of code in GCC to be used mainly for RL78. 
The commercial RL78 compilers have such algorithms implemented and they make
quite good use of it.
Opportunities arise from the limited capabilities of RL78, for other targets
this might be a lot less useful.

A while ago I found the following:
https://www.gnu.org/software/gcc/projects/cfo.html
And I ported all algorithms to gcc 4.9.2 and tried it on RL78 and RX and
this is what I found out:
For RX: no visible improvements with any of them 
For RL78: some minor improvements only with -frtl-seqbastr:
Compiling all the C files from gcc/testsuite/gcc.c-torture/execute/*c  with
"-Os" and "-Os  -frtl-seqabstr" (using the modified gcc 4.9.2)
The algorithm was effective only in 60 files(out of 1643 files, that's only
0.03% of the files currently present in gcc/testsuite/gcc.c-torture/execute)
On those 60 files I got an average of 6.5% improvement with the best
improvement for pr58574.c (36.4%).

What do you think: is it worthwhile porting this to the trunk or I will just
waste my time?
Or should I start fresh? Maybe start from here:
http://llvm.org/docs/MergeFunctions.html?

Gimple or rtl?
I suppose the preferred way will be to do this in gimple; however based on
what I did so far,  it's more likely to find identical sequences in rtl (for
RL78).

Any thoughts? Thank you!

Best Regards,
Sebastian

[PATCH, committed] Add myself to MAINTAINERS

[Sebastian Perta]

Hi,

Just added myself to MAINTAINERS (write after approval)

Best Regards,
Sebastian

Index: ChangeLog
===
--- ChangeLog(revision 256737)
+++ ChangeLog(working copy)
@@ -1,3 +1,7 @@
+2018-01-16  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+* MAINTAINERS (write after approval): Add myself.
+
 2018-01-03  Jakub Jelinek  <ja...@redhat.com>

 Update copyright years.
Index: MAINTAINERS
===
--- MAINTAINERS(revision 256737)
+++ MAINTAINERS(working copy)
@@ -535,6 +535,7 @@
 Devang Patel<dpa...@apple.com>
 Andris Pavenis<andris.pave...@iki.fi>
 Fernando Pereira<prone...@gmail.com>
+Sebastian Perta<sebastian.pe...@renesas.com>
 Sebastian Peryt<sebastian.pe...@intel.com>
 Kaushik Phatak<kaushik.pha...@kpitcummins.com>
 Nicolas Pitre<n...@cam.org>



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, 
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered 
No. 04586709.

RE: [PATCH] RL78 UNUSED note setting bug fix in rl78_note_reg_set

[Sebastian Perta]

Hi DJ,

>>Do you have checkin privs yet?
I have filled out the form. "Thanks for your request. It must be approved by 
the person you named as approver ...

>> This is ok aside from..
Sorry about this. I will keep this in mind in future.
I corrected the patch with your second suggestion.

Best Regards,
Sebastian

Index: ChangeLog
===
--- ChangeLog(revision 256590)
+++ ChangeLog(working copy)
@@ -1,3 +1,8 @@
+2018-01-12  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+* config/rl78/rl78.c (rl78_note_reg_set): fixed dead reg check
+for non-QImode registers
+
 2018-01-12  Vladimir Makarov  <vmaka...@redhat.com>

 PR rtl-optimization/80481
Index: config/rl78/rl78.c
===
--- config/rl78/rl78.c(revision 256590)
+++ config/rl78/rl78.c(working copy)
@@ -3792,7 +3792,7 @@
 rl78_note_reg_set (char *dead, rtx d, rtx insn)
 {
   int r, i;
-
+  bool is_dead;
   if (GET_CODE (d) == MEM)
 rl78_note_reg_uses (dead, XEXP (d, 0), insn);

@@ -3799,9 +3799,15 @@
   if (GET_CODE (d) != REG)
 return;

+ /* Do not mark the reg unused unless all QImode parts of it are dead.  */
   r = REGNO (d);
-  if (dead [r])
-add_reg_note (insn, REG_UNUSED, gen_rtx_REG (GET_MODE (d), r));
+  is_dead = true;
+  for (i = 0; i < GET_MODE_SIZE (GET_MODE (d)); i ++)
+  if (!dead [r + i])
+  is_dead = false;
+  if(is_dead)
+add_reg_note (insn, REG_UNUSED, gen_rtx_REG (GET_MODE (d), r));
   if (dump_file)
 fprintf (dump_file, "note set reg %d size %d\n", r, GET_MODE_SIZE 
(GET_MODE (d)));
   for (i = 0; i < GET_MODE_SIZE (GET_MODE (d)); i ++)

> -Original Message-
> From: DJ Delorie [mailto:d...@redhat.com]
> Sent: 12 January 2018 18:12
> To: Sebastian Perta <sebastian.pe...@renesas.com>
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] RL78 UNUSED note setting bug fix in rl78_note_reg_set
>
>
> "Sebastian Perta" <sebastian.pe...@renesas.com> writes:
> > Please let me know if this is OK. Thank you!
>
> Do you have checkin privs yet?
>
> This is ok aside from..
>
> > +  /* 'dead' keeps track of the QImode registers if r is of different size
> > +  we need to check the other subparts as well  */
>
> Missing period at the end of a sentence; should capitalize first word
> but it's a variable, which should be block caps anyway, and it reads
> better as two sentences:
>
> > +  /* DEAD keeps track of the QImode registers.  If R is of different size
> > +  we need to check the other subparts as well.  */
>
> Or rewrite to not mention variables?
>
> > + /* Do not mark the reg unused unless all QImode parts of it are dead.  */



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, 
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered 
No. 04586709.

[PATCH] RL78 UNUSED note setting bug fix in rl78_note_reg_set

[Sebastian Perta]

Hello,

The below patch fixes 31 regression failures (28 for C and 3 for C++, see
below) plus the problem discovered here
https://gcc.gnu.org/ml/gcc-patches/2018-01/msg00688.html by DJ.
Tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

List of previous fails which get fixed by this patch:
FAIL: gcc.c-torture/execute/pr42512.c   -O3 -fomit-frame-pointer
-funroll-loops -fpeel-loops -ftracer -finline-functions  execution test
FAIL: gcc.c-torture/execute/pr53645-2.c   -O1  execution test
FAIL: gcc.c-torture/execute/pr53645-2.c   -O2  execution test
FAIL: gcc.c-torture/execute/pr53645-2.c   -O3 -fomit-frame-pointer
-funroll-loops -fpeel-loops -ftracer -finline-functions  execution test
FAIL: gcc.c-torture/execute/pr53645-2.c   -O3 -g  execution test
FAIL: gcc.c-torture/execute/pr53645-2.c   -Os  execution test
FAIL: gcc.c-torture/execute/pr53645-2.c   -O2 -flto -fno-use-linker-plugin
-flto-partition=none  execution test
FAIL: gcc.c-torture/execute/pr53645-2.c   -O2 -flto -fuse-linker-plugin
-fno-fat-lto-objects  execution test
FAIL: gcc.c-torture/execute/pr53645.c   -O1  execution test
FAIL: gcc.c-torture/execute/pr53645.c   -O2  execution test
FAIL: gcc.c-torture/execute/pr53645.c   -O3 -fomit-frame-pointer
-funroll-loops -fpeel-loops -ftracer -finline-functions  execution test
FAIL: gcc.c-torture/execute/pr53645.c   -O3 -g  execution test
FAIL: gcc.c-torture/execute/pr53645.c   -Os  execution test
FAIL: gcc.c-torture/execute/pr53645.c   -O2 -flto -fno-use-linker-plugin
-flto-partition=none  execution test
FAIL: gcc.c-torture/execute/pr53645.c   -O2 -flto -fuse-linker-plugin
-fno-fat-lto-objects  execution test
FAIL: gcc.c-torture/execute/pr61306-2.c   -O1  execution test
FAIL: gcc.c-torture/execute/pr61306-2.c   -O2  execution test
FAIL: gcc.c-torture/execute/pr61306-2.c   -O3 -g  execution test
FAIL: gcc.c-torture/execute/pr61306-2.c   -Os  execution test
FAIL: gcc.c-torture/execute/pr61306-2.c   -O2 -flto -fno-use-linker-plugin
-flto-partition=none  execution test
FAIL: gcc.c-torture/execute/pr65401.c   -O3 -fomit-frame-pointer
-funroll-loops -fpeel-loops -ftracer -finline-functions  execution test
FAIL: gcc.dg/compat/struct-by-value-13 c_compat_x_tst.o-c_compat_y_tst.o
link
FAIL: gcc.dg/builtin-arith-overflow-1.c execution test
FAIL: gcc.dg/builtin-bswap-4.c execution test
FAIL: gcc.dg/pr26719.c execution test
FAIL: c-c++-common/torture/builtin-arith-overflow-14.c   -O0  (test for
excess errors)
FAIL: c-c++-common/torture/builtin-arith-overflow-3.c   -O0  (test for
excess errors)
FAIL: gcc.dg/torture/pr57569.c   -Os  execution test
FAIL: tmpdir-g++.dg-struct-layout-1/t005 cp_compat_x_tst.o-cp_compat_y_tst.o
link
FAIL: c-c++-common/torture/builtin-arith-overflow-14.c   -O0  (test for
excess errors)
FAIL: c-c++-common/torture/builtin-arith-overflow-3.c   -O0  (test for
excess errors)

Please let me know if this is OK. Thank you!

Best Regards,
Sebastian

Index: ChangeLog
===
--- ChangeLog   (revision 256590)
+++ ChangeLog   (working copy)
@@ -1,3 +1,8 @@
+2018-01-12  Sebastian Perta  <sebastian.pe...@renesas.com>
+   
+   * config/rl78/rl78.c (rl78_note_reg_set): fixed dead reg check 
+   for non-QImode registers
+
 2018-01-12  Vladimir Makarov  <vmaka...@redhat.com>
 
PR rtl-optimization/80481
Index: config/rl78/rl78.c
===
--- config/rl78/rl78.c  (revision 256590)
+++ config/rl78/rl78.c  (working copy)
@@ -3792,7 +3792,7 @@
 rl78_note_reg_set (char *dead, rtx d, rtx insn)
 {
   int r, i;
-
+  bool is_dead;
   if (GET_CODE (d) == MEM)
 rl78_note_reg_uses (dead, XEXP (d, 0), insn);
 
@@ -3799,9 +3799,15 @@
   if (GET_CODE (d) != REG)
 return;
 
+  /* 'dead' keeps track of the QImode registers if r is of different size
+  we need to check the other subparts as well  */
   r = REGNO (d);
-  if (dead [r])
-add_reg_note (insn, REG_UNUSED, gen_rtx_REG (GET_MODE (d), r));
+  is_dead = true;
+  for (i = 0; i < GET_MODE_SIZE (GET_MODE (d)); i ++)
+ if (!dead [r + i])
+ is_dead = false;
+  if(is_dead)
+   add_reg_note (insn, REG_UNUSED, gen_rtx_REG (GET_MODE (d), r));
   if (dump_file)
 fprintf (dump_file, "note set reg %d size %d\n", r, GET_MODE_SIZE
(GET_MODE (d)));
   for (i = 0; i < GET_MODE_SIZE (GET_MODE (d)); i ++)

RE: [PATCH] RL78 movdi improvement

[Sebastian Perta]

Hi DJ,

I managed to reproduce the issue, it is in function test_7,  sorry I'm not
sure how I missed it I always compare the logs carefully with and without
the patch.
After investigating this I found the problem is caused by a removal of 1
instruction due to wrong UNUSED note being
added(rl78_calculate_death_notes), more exactly in rl78_note_reg_set :

  r = REGNO (d);
  if (dead [r])
add_reg_note (insn, REG_UNUSED, gen_rtx_REG (GET_MODE (d), r));

For example if the reg is HImode and the high part is not dead (dead[r + 1])
the register should NOT be marked as UNUSED but it is.
After I corrected the problem the code was generated correctly; I will
prepare another patch with this fix.

Below you can see the relevant parts from the rtl dump(.314r.devirt) which
show this:

(insn 41 91 92 2 (set (reg:HI 0 x)
(mem/c:HI (reg:HI 6 l) [0  S2 A16])) "../test_movdi.c":20 43
{*movhi_real}
 (nil))
(insn 92 41 42 2 (set (reg:HI 8 r8 [orig:44 a.0_3 ] [44])
(reg:HI 0 x)) "../test_movdi.c":20 -1
 (nil))
...
(insn 17 105 106 2 (set (reg:QI 1 a)
(reg:QI 9 r9 [ a.0_3+1 ])) "../test_movdi.c":20 42 {*movqi_real}
 (nil))
...
(insn 19 107 108 2 (set (reg:QI 1 a)
(reg:QI 9 r9 [ a.0_3+1 ])) "../test_movdi.c":20 42 {*movqi_real}
 (nil))
...
(insn 22 110 23 2 (set (reg/f:HI 8 r8 [53])
(symbol_ref:HI ("c") )) "../test_movdi.c":20
43 {*movhi_real}
 (expr_list:REG_EQUIV (symbol_ref:HI ("c") )
(nil)))


When the death notes are calculated we have the following
(rl78_calculate_death_notes):
Because this parse the functions backwards insn 22 is processed first.

note set reg 8 size 2
(insn 22 110 23 2 (set (reg/f:HI 8 r8 [53])
(symbol_ref:HI ("c") )) "../test_movdi.c":20
43 {*movhi_real}
 (expr_list:REG_EQUIV (symbol_ref:HI ("c") )
(nil)))

--
Dead: x a c b r8 r9 r10 r11 r12 r13 r16 r17 <---As you can see R8
and R9 are marked as dead which is correct



note set reg 1 size 1
note use reg 9 size 1 on insn 19
(reg:QI 9 r9 [ a.0_3+1 ])
(insn 19 107 108 2 (set (reg:QI 1 a)
(reg:QI 9 r9 [ a.0_3+1 ])) "../test_movdi.c":20 42 {*movqi_real}
 (expr_list:REG_DEAD (reg:QI 9 r9)
(nil)))

--
Dead: x a c b r8 r10 r13 r16 r17 <---As you can see R9 is not dead
anymore

Now we get to insn 92 and we can see that r8 is wrongfully marked as unused
because the code check only R8 (and it should check R9 as well).
As a consequence insn 92 get removed later on.
--
Dead: x a c b r8 r10 r11 r12 r13 r14 r15 r16 r17
(insn 92 41 42 2 (set (reg:HI 8 r8 [orig:44 a.0_3 ] [44])
(reg:HI 0 x)) "../test_movdi.c":20 43 {*movhi_real}
 (nil))
note set reg 8 size 2
note use reg 0 size 2 on insn 92
(reg:HI 0 x)
(insn 92 41 42 2 (set (reg:HI 8 r8 [orig:44 a.0_3 ] [44])
(reg:HI 0 x)) "../test_movdi.c":20 43 {*movhi_real}
 (expr_list:REG_DEAD (reg:HI 0 x)
(expr_list:REG_UNUSED (reg:HI 8
r8)<here is the problem
(nil

Also later on (in 290r.peephole2) we see that instruction 41 is eliminated
as well:
DCE: Deleting insn 41
deleting insn with uid = 41.

Best Regards,
Sebastian

> -Original Message-
> From: DJ Delorie [mailto:d...@redhat.com]
> Sent: 09 January 2018 22:55
> To: Sebastian Perta <sebastian.pe...@renesas.com>
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] RL78 movdi improvement
> 
> 
> I saw one regression with this patch:
> 
> PASS-FAIL: gcc.dg/torture/vshuf-v8qi.c   -O2  execution test
> 
> Could you confirm this?  Note: I'm testing with your other (pre-2018 at
> least) patches applied at the same time (smax etc, anddi, bswaphi) so it
> might be an interaction, but the code looks like a movdi bug.  The other
> patches look OK otherwise.

[PATCH] RX movsicc degrade fix

[Sebastian Perta]

Hello,

In recent versions of GCC the define_expand "movsicc" has stopped being used
by GCC (approx. 4.7.x/4.8.x onwards)
The reason for this is that the first operand of if_then_else has SI mode
and it shouldn't have. If we take a look at movsicc for all other targets we
see this is true.
The fix in rx.md is basically a copy paste from v850.md

The patch also adds a testcase in gcc.target/rx to make sure this degrade
does not occur again. 


Regression test is OK with one observation (see below), tested with the
following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rx-sim


I have the following fail (which was not present before):
FAIL: gcc.dg/loop-8.c scan-rtl-dump-times loop2_invariant "Decided" 1 (found
0 times)

This is because the patch is effective in this test case and the dump is not
the same, I checked the asm code manually and it is OK.
Is it possible to disable parts of a test case, not the whole test case (* {
dg-final { scan-rtl-dump-times "Decided" 1 "loop2_invariant" } } */  from
loop-8.c in this example) for a particular target?

The total numbers of failures remains the same because the following FAIL is
not present anymore with this patch:
FAIL: gcc.dg/ifcvt-4.c scan-rtl-dump ce1 "2 true changes made"


Please let me know if this is OK. Thank you!

Best Regards,
Sebastian


Index: ChangeLog
===
--- ChangeLog   (revision 256382)
+++ ChangeLog   (working copy)
@@ -1,3 +1,8 @@
+2018-01-09  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   *config/rx.md: updated "movsicc" expand to be matched by GCC
+   *testsuite/gcc.target/rx/movsicc.c: new test case
+
 2018-01-09  Richard Biener  <rguent...@suse.de>
 
PR tree-optimization/83668
Index: config/rx/rx.md
===
--- config/rx/rx.md (revision 256382)
+++ config/rx/rx.md (working copy)
@@ -733,12 +733,17 @@
 (define_expand "movsicc"
   [(parallel
 [(set (match_operand:SI  0 "register_operand")
- (if_then_else:SI (match_operand:SI 1 "comparison_operator")
+ (if_then_else:SI (match_operand 1 "comparison_operator")
   (match_operand:SI 2 "nonmemory_operand")
   (match_operand:SI 3 "nonmemory_operand")))
  (clobber (reg:CC CC_REG))])]
   ""
 {
+  /* Make sure that we have an integer comparison...  */
+  if (GET_MODE (XEXP (operands[1], 0)) != CCmode
+  && GET_MODE (XEXP (operands[1], 0)) != SImode)
+FAIL;
+
   /* One operand must be a constant or a register, the other must be a
register.  */
   if (   ! CONSTANT_P (operands[2])
   && ! CONSTANT_P (operands[3])
Index: testsuite/gcc.target/rx/movsicc.c
===
--- testsuite/gcc.target/rx/movsicc.c   (nonexistent)
+++ testsuite/gcc.target/rx/movsicc.c   (working copy)
@@ -0,0 +1,94 @@
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+signed int Xa, Xb;
+
+signed int stzreg_beq(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (i)
+x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "bne 1f" } } */
+
+signed int stzreg_bge(int i, int a, int b, int c)
+{
+  signed int x;
+  x = a;
+  if (i<c)
+x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "blt 1f" } } */
+
+signed int stzreg_bgt(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (i<10)
+x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "ble 1f" } } */
+
+signed int stzreg_ble(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (i>0)
+x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "bgt 1f" } } */
+
+signed int stzreg_blt(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (i<0)
+x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "blt 1f" } } */
+
+signed int stzreg_bne(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (!i)
+x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "beq 1f" } } */
+
+signed int stzimm_le( int i, int a )
+{
+  signed int x;
+  x = a;
+  if (i>0)
+x = 5;
+  return x;
+}
+
+/* { dg-final { scan-assembler "ble 1f" } } */
+
+signed int stzimm_le_r( int i, int a )
+{
+  signed int x;
+  x = a;
+  if (i<0)
+x = 5;
+  return x;
+}
+
+/* { dg-final { scan-assembler "bge 1f" } } */

RE: [PATCH] RL78 pragma address

[Sebastian Perta]

Hello,

So I would like to drop this patch.
Oleg Endo has proposed a better solution:
https://gcc.gnu.org/ml/gcc-patches/2018-01/msg00305.html

Best Regards,
Sebastian

-Original Message-
From: Sebastian Perta [mailto:sebastian.pe...@renesas.com] 
Sent: 15 December 2017 09:25
To: 'gcc-patches@gcc.gnu.org' <gcc-patches@gcc.gnu.org>
Subject: [PATCH] RL78 pragma address

Hello 

The following patch adds a new pragma, "pragma address" for RL78.
The patch updates extend.texi and add a test case to the regression as well.
For the test case I checked than test is getting picked up in gcc.log
unfortunately 
for the .texi part I don't know where to look/what to do to get the
documentation generated.

This is similar to the pragma address implemented for M32C.

Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

Please let me know if this is OK, Thank you!
Sebastian

Index: ChangeLog
===
--- ChangeLog   (revision 255643)
+++ ChangeLog   (working copy)
@@ -1,3 +1,19 @@
+2017-12-14  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/rl78.c (rl78_get_pragma_address): New function
+   * config/rl78/rl78.c (rl78_note_pragma_address): New function 
+   * config/rl78/rl78.c (rl78_output_aligned_common): use .set instead 
+   of .comm for pragma address variables
+   * config/rl78/rl78.c (rl78_insert_attributes): make pragma address 
+   variables volatile
+   * config/rl78/rl78-c.c (rl78_pragma_address): New function
+   * config/rl78/rl78-c.c (rl78_register_pragmas): registered the new 
+   pragma address
+   * config/rl78/rl78-protos.h: New declaration
rl78_note_pragma_address
+   * doc/entend.texi: Added documenation for RL78 pragmas
+   * testsuite/gcc.target/rl78/test_pragma_address.c: New file
+   
+   
 2017-12-14  Andreas Schwab  <sch...@linux-m68k.org>
 
PR bootstrap/83396
Index: config/rl78/rl78-c.c
===
--- config/rl78/rl78-c.c(revision 255643)
+++ config/rl78/rl78-c.c(working copy)
@@ -23,7 +23,42 @@
 #include "coretypes.h"
 #include "tm.h"
 #include "c-family/c-common.h"
+#include "c-family/c-pragma.h"
+#include "rl78-protos.h"
 
+/* Implements the "pragma ADDRESS" pragma.  This pragma takes a
+   variable name and an address, and arranges for that variable to be
+   "at" that address.  The variable is also made volatile.  */
+static void
+rl78_pragma_address (cpp_reader * reader ATTRIBUTE_UNUSED)
+{
+  /* on off */
+  tree var, addr;
+  enum cpp_ttype type;
+
+  type = pragma_lex ();
+  if (type == CPP_NAME)
+{
+  type = pragma_lex ();
+  if (type == CPP_NUMBER)
+   {
+ if (var != error_mark_node)
+   {
+ unsigned uaddr = tree_to_uhwi (addr);
+ rl78_note_pragma_address (IDENTIFIER_POINTER (var), uaddr);
+   }
+
+ type = pragma_lex ();
+ if (type != CPP_EOF)
+   {
+ error ("junk at end of #pragma ADDRESS");
+   }
+ return;
+   }
+}
+  error ("malformed #pragma ADDRESS variable address");
+}
+
 /* Implements REGISTER_TARGET_PRAGMAS.  */
 void
 rl78_register_pragmas (void)
@@ -30,4 +65,7 @@
 {
   c_register_addr_space ("__near", ADDR_SPACE_NEAR);
   c_register_addr_space ("__far", ADDR_SPACE_FAR);
+  
+  c_register_pragma (NULL, "ADDRESS", rl78_pragma_address);
+  c_register_pragma (NULL, "address", rl78_pragma_address);
 }
Index: config/rl78/rl78-protos.h
===
--- config/rl78/rl78-protos.h   (revision 255643)
+++ config/rl78/rl78-protos.h   (working copy)
@@ -52,6 +52,7 @@
 intrl78_sfr_p (rtx x);
 void   rl78_output_aligned_common (FILE *, tree, const char *,
int, int, int);
+void   rl78_note_pragma_address (const char *varname, unsigned
address);
 
 intrl78_one_far_p (rtx *operands, int num_operands);
 
Index: config/rl78/rl78.c
===
--- config/rl78/rl78.c  (revision 255643)
+++ config/rl78/rl78.c  (working copy)
@@ -4565,6 +4565,30 @@
   fputs (str2, file);
 }
 
+struct GTY(()) pragma_entry {
+  const char *varname;
+  unsigned address;
+};
+typedef struct pragma_entry pragma_entry;
+
+/* Hash table of pragma info.  */
+static GTY(()) hash_map<nofree_string_hash, unsigned> *pragma_htab;
+
+static bool
+rl78_get_pragma_address (const char *varname, unsigned *address)
+{
+  if (!pragma_htab)
+return false;
+
+  unsigned int *slot = pragma_htab->get (varname);
+  if (slot)
+{
+  *address = *slot;
+

RE: [PATCH] RX pragma address

[Sebastian Perta]

Hello,

The AP4 tool team have agreed with this change and are willing to update their 
tool.
So I would like to drop this patch.

Best Regards,
Sebastian


-Original Message-
From: Sebastian Perta [mailto:sebastian.pe...@renesas.com] 
Sent: 05 January 2018 13:46
To: 'Oleg Endo' <oleg.e...@t-online.de>; gcc-patches@gcc.gnu.org
Subject: RE: [PATCH] RX pragma address

Hi Oleg,

Thank you very much for those suggestions, they are definitely the better way 
to go.
>From my point of view I would like drop both patches(RX and RL78) however I 
>contacted the AP4 tool team to see if they agree with this change and are 
>willing to update their tool.
If not I will follow your suggestion and move it out from the M32C target and 
make it available for every target.

Best Regards,
Sebastian

-Original Message-
From: Oleg Endo [mailto:oleg.e...@t-online.de] 
Sent: 05 January 2018 12:50
To: Sebastian Perta <sebastian.pe...@renesas.com>; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] RX pragma address

On Fri, 2018-01-05 at 12:12 +, Sebastian Perta wrote:
> 
> > > 
> > > Is this for some kind of legacy backwards compatibility of
> > > something?

> Sort of, this is required by the following tool
> https://www.renesas.com/en-eu/products/software-tools/tools/code-
> generator/ap4-application-leading-tool-applilet.html

> There are not many plans to improve this tool and other solutions
> (which might be more complex) might not be possible to implement in
> this tool.

I see.

> 
> The only way I can think of is to put the variable in a separate
> section (using section attribute) and then in the linker script put
> that section at the desired address.
> The problem is AP4 does not touch the linker script it only generates
> source code.
> 
> Do you have any other ideas/suggestions? I'm very happy to listen.

If you can compile the code only as plain C, for example

#define const_addr_var(addr, type) (*(volatile type*)addr)

#define DTCCR const_addr_var (0x00082400, uint8_t)
#define DTCSTS const_addr_var (0x0008240E, uint16_t)


If you can compile the code as C++11 there are certainly more options,
albeit probably not useful for generated code.  For example I do those
things this way:

// read-write hardware register with constant address
static constexpr hw_reg_rw<uint8_t, const_addr<0x00082400>> DTCCR = { };

// ready-only hardware register with constant address
static constexpr hw_reg_r<uint16_t, const_addr<0x0008240E>> DTCSTS = { };


In both cases (C and C++) the following will compile to the same code:

void test_wr (void)
{
  DTCCR = 123;
}

int test_rd (void)
{
  return DTCSTS;
}

volatile void* get_reg_addr (void)
{
  return 
}

For a possible implementation of the hw_reg thingy see
https://github.com/shared-ptr/bits/blob/master/hw_reg.hpp

But really, if that is just for some code generator, why not simply
adjust the code generator to spit out normal C code instead of
cluttering the compiler with non-portable pragmas?  You have also
posted a similar thing for RL78 a while ago, so in the end the same
pragma thing would be re-implemented in the compiler three times (M32C,
RL78, RX)?  In that case, maybe better move it out from the M32C target
and make it available for every target?

Cheers,
Oleg

[PATCH] -mjsr option bug fix

[Sebastian Perta]

Hi,

The -mjsr option in RX should ensure the that BSR instruction is not
generated, only JSR instruction should be generated.
However this does not work as expected: BSR instruction still gets generated
even if -mjsr is passed in the command line.
This is reproducible even if test cases from the gcc testsuite, for example:
gcc.c-torture\compile\920625-1.c
gcc.c-torture\compile\20051216-1.c
gcc.dg\torture\builtin-explog-1.c

The following patch fixes this issue by adding a new constraint to
call_internal and call_value_internal.
The patch also contains a test case which I created as follows:
1. I copied gcc.c-torture\compile\20051216-1.c  to gcc.target\rx and renamed
to mjsr.c
2. added the following lines to scan the assembly files for BSR. If BSR is
present the test fails.
/* { dg-do compile } */
/* { dg-options "-O2 -mjsr" } */
/* { dg-final { scan-assembler-not "bsr" } } */

Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rx-sim

Please let me know if this is OK. Thank you!

Best Regards,
Sebastian

Index: ChangeLog
===
--- ChangeLog   (revision 256278)
+++ ChangeLog   (working copy)
@@ -1,3 +1,10 @@
+2018-01-05  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rx/constraints.md: added new constraint CALL_OP_SYMBOL_REF 
+   to allow or block "symbol_ref" depending on value of TARGET_JSR
+   * config/rx/rx.md: use CALL_OP_SYMBOL_REF in call_internal and 
+   call_value_internal insns
+
 2018-01-05  Richard Sandiford  <richard.sandif...@linaro.org>
 
* tree-vect-data-refs.c (vect_compute_data_ref_alignment): Don't
Index: config/rx/constraints.md
===
--- config/rx/constraints.md(revision 256278)
+++ config/rx/constraints.md(working copy)
@@ -106,3 +106,9 @@
)
   )
 )
+
+(define_constraint "CALL_OP_SYMBOL_REF"
+"constraint for call instructions using symbol ref"
+(and (match_test "!TARGET_JSR")
+ (match_code "symbol_ref"))
+)
Index: config/rx/rx.md
===
--- config/rx/rx.md (revision 256278)
+++ config/rx/rx.md (working copy)
@@ -438,7 +438,7 @@
 )
 
 (define_insn "call_internal"
-  [(call (mem:QI (match_operand:SI 0 "rx_call_operand" "r,Symbol"))
+  [(call (mem:QI (match_operand:SI 0 "rx_call_operand"
"r,CALL_OP_SYMBOL_REF"))
 (const_int 0))
(clobber (reg:CC CC_REG))]
   ""
@@ -466,7 +466,7 @@
 
 (define_insn "call_value_internal"
   [(set (match_operand  0 "register_operand" "=r,r")
-   (call (mem:QI (match_operand:SI 1 "rx_call_operand"   "r,Symbol"))
+   (call (mem:QI (match_operand:SI 1 "rx_call_operand"
"r,CALL_OP_SYMBOL_REF"))
  (const_int 0)))
(clobber (reg:CC CC_REG))]
   ""
Index: testsuite/gcc.target/rx/mjsr.c
===
--- testsuite/gcc.target/rx/mjsr.c  (nonexistent)
+++ testsuite/gcc.target/rx/mjsr.c  (working copy)
@@ -0,0 +1,134 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mjsr" } */
+
+void *malloc (__SIZE_TYPE__);
+void *realloc (void *, __SIZE_TYPE__);
+
+struct A { double x, y; };
+struct B { double x0, y0, x1, y1; };
+struct C { int n_points; int dir; struct B bbox; struct A *points; };
+struct D { int n_segs; struct C segs[1]; };
+
+void foo (int, int, int *, int, int *, struct A **, int *, int *,
+ struct D *, int *, struct D **, int *, int **);
+int baz (struct A, struct A, struct A, struct A);
+
+static void
+bar (struct D *svp, int *n_points_max,
+ struct A p, int *seg_map, int *active_segs, int i)
+{
+  int asi, n_points;
+  struct C *seg;
+
+  asi = seg_map[active_segs[i]];
+  seg = >segs[asi];
+  n_points = seg->n_points;
+  seg->points = ((struct A *)
+   realloc (seg->points, (n_points_max[asi] <<= 1) * sizeof
(struct A)));
+  seg->points[n_points] = p;
+  seg->bbox.y1 = p.y;
+  seg->n_points++;
+}
+
+struct D *
+test (struct D *vp)
+{
+  int *active_segs, n_active_segs, *cursor, seg_idx;
+  double y, share_x;
+  int tmp1, tmp2, asi, i, j, *n_ips, *n_ips_max, n_segs_max;
+  struct A **ips, p_curs, *pts;
+  struct D *new_vp;
+  int *n_points_max, *seg_map, first_share;
+
+  n_segs_max = 16;
+  new_vp = (struct D *) malloc (sizeof (struct D) +
+   (n_segs_max - 1) * sizeof (struct C));
+  new_vp->n_segs = 0;
+
+  if (vp->n_segs == 0)
+return new_vp;
+
+  active_segs = ((int *) malloc ((vp->n_segs) * sizeof (int)));
+  cursor = ((int *) malloc ((vp->n_segs) * sizeof (int)));
+
+  seg_map = ((int *) malloc ((vp->n_segs) 

RE: [PATCH] RX pragma address

[Sebastian Perta]

Hi Oleg,

Thank you very much for those suggestions, they are definitely the better way 
to go.
>From my point of view I would like drop both patches(RX and RL78) however I 
>contacted the AP4 tool team to see if they agree with this change and are 
>willing to update their tool.
If not I will follow your suggestion and move it out from the M32C target and 
make it available for every target.

Best Regards,
Sebastian

-Original Message-
From: Oleg Endo [mailto:oleg.e...@t-online.de] 
Sent: 05 January 2018 12:50
To: Sebastian Perta <sebastian.pe...@renesas.com>; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] RX pragma address

On Fri, 2018-01-05 at 12:12 +0000, Sebastian Perta wrote:
> 
> > > 
> > > Is this for some kind of legacy backwards compatibility of
> > > something?

> Sort of, this is required by the following tool
> https://www.renesas.com/en-eu/products/software-tools/tools/code-
> generator/ap4-application-leading-tool-applilet.html

> There are not many plans to improve this tool and other solutions
> (which might be more complex) might not be possible to implement in
> this tool.

I see.

> 
> The only way I can think of is to put the variable in a separate
> section (using section attribute) and then in the linker script put
> that section at the desired address.
> The problem is AP4 does not touch the linker script it only generates
> source code.
> 
> Do you have any other ideas/suggestions? I'm very happy to listen.

If you can compile the code only as plain C, for example

#define const_addr_var(addr, type) (*(volatile type*)addr)

#define DTCCR const_addr_var (0x00082400, uint8_t)
#define DTCSTS const_addr_var (0x0008240E, uint16_t)


If you can compile the code as C++11 there are certainly more options,
albeit probably not useful for generated code.  For example I do those
things this way:

// read-write hardware register with constant address
static constexpr hw_reg_rw<uint8_t, const_addr<0x00082400>> DTCCR = { };

// ready-only hardware register with constant address
static constexpr hw_reg_r<uint16_t, const_addr<0x0008240E>> DTCSTS = { };


In both cases (C and C++) the following will compile to the same code:

void test_wr (void)
{
  DTCCR = 123;
}

int test_rd (void)
{
  return DTCSTS;
}

volatile void* get_reg_addr (void)
{
  return 
}

For a possible implementation of the hw_reg thingy see
https://github.com/shared-ptr/bits/blob/master/hw_reg.hpp

But really, if that is just for some code generator, why not simply
adjust the code generator to spit out normal C code instead of
cluttering the compiler with non-portable pragmas?  You have also
posted a similar thing for RL78 a while ago, so in the end the same
pragma thing would be re-implemented in the compiler three times (M32C,
RL78, RX)?  In that case, maybe better move it out from the M32C target
and make it available for every target?

Cheers,
Oleg

RE: [PATCH] RX pragma address

[Sebastian Perta]

Hi,

Thank you for your comment.

>>Is this for some kind of legacy backwards compatibility of something?
Sort of, this is required by the following tool
https://www.renesas.com/en-eu/products/software-tools/tools/code-generator/ap4-application-leading-tool-applilet.html
There are not many plans to improve this tool and other solutions (which might 
be more complex) might not be possible to implement in this tool.

>>There are ways how to achieve the same with standard C and C++ language
The only way I can think of is to put the variable in a separate section (using 
section attribute) and then in the linker script put that section at the 
desired address.
The problem is AP4 does not touch the linker script it only generates source 
code.

Do you have any other ideas/suggestions? I'm very happy to listen.

Best Regards,
Sebastian

-Original Message-
From: Oleg Endo [mailto:oleg.e...@t-online.de] 
Sent: 05 January 2018 11:59
To: Sebastian Perta <sebastian.pe...@renesas.com>; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] RX pragma address

Hi,

On Fri, 2018-01-05 at 11:03 +0000, Sebastian Perta wrote:
> 
> Hello, 
> 
> The following patch adds a new pragma, "pragma address" for RX.
> The patch updates extend.texi and add a test case to the regression
> as well.
> For the test case I checked than test is getting picked up in gcc.log
> unfortunately for the .texi part I don't know where to look/what to
> do to
> get the
> documentation generated.
> 
> This is similar to the pragma address implemented for M32C.

Is this for some kind of legacy backwards compatibility of something?
There are ways how to achieve the same with standard C and C++ language
features ... so I was wondering what's the purpose of this?

Cheers,
Oleg

RE: [PATCH] RX pragma address

[Sebastian Perta]

Sorry the spaces got removed from previous email.

-Original Message-
From: Sebastian Perta 
Sent: 05 January 2018 10:59
To: 'gcc-patches@gcc.gnu.org' <gcc-patches@gcc.gnu.org>
Subject: [PATCH] RX pragma address

Hello, 

The following patch adds a new pragma, "pragma address" for RX.
The patch updates extend.texi and add a test case to the regression as well.
For the test case I checked than test is getting picked up in gcc.log
unfortunately for the .texi part I don't know where to look/what to do to
get the
documentation generated.

This is similar to the pragma address implemented for M32C.

Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rx-sim

Please let me know if this is OK, Thank you!
Sebastian

Index: ChangeLog
===
--- ChangeLog   (revision 256076)
+++ ChangeLog   (working copy)
@@ -1,3 +1,21 @@
+2018-01-03  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rx/rx.c (rx_get_pragma_address): New function
+   * config/rx/rx.c (rx_note_pragma_address): New function 
+   * config/rx/rx.c (rx_output_aligned_common): New function use .set
instead 
+   of .comm for pragma address variables
+   * config/rx/rx.c (rx_insert_attributes): New function which makes
pragma address 
+   variables volatile
+   * config/rx/rx-pragma.c: New file with 2 functions rx_pragma_address
and 
+   rx_register_pragmas to implement and register the new pragma
+   * config/rx/rx-protos.h: New declarations rl78_note_pragma_address, 
+   rx_register_pragmas, rx_output_aligned_common
+   * config/rx/t-rx: added rx-pragma.o
+   * config/rx/rx.h: defined ASM_OUTPUT_ALIGNED_DECL_COMMON and
REGISTER_TARGET_PRAGMAS
+   * doc/entend.texi: Added documenation for RX pragmas
+   * testsuite/gcc.target/rx/test_pragma_address.c: New file
+   * config.gcc: added "rx-pragma.o" to c_target_objs and
cxx_target_objs
+   
 2018-01-02  Richard Biener  <rguent...@suse.de>
 
* ipa-inline.c (big_speedup_p): Fix expression.
Index: config.gcc
===
--- config.gcc  (revision 256076)
+++ config.gcc  (working copy)
@@ -2661,6 +2661,8 @@
 rx-*-elf*)
tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
tmake_file="${tmake_file} rx/t-rx"
+   c_target_objs="rx-pragma.o"
+   cxx_target_objs="rx-pragma.o"
;;
 s390-*-linux*)
tm_file="s390/s390.h dbxelf.h elfos.h gnu-user.h linux.h
glibc-stdint.h s390/linux.h"
Index: config/rx/rx-pragma.c
===
--- config/rx/rx-pragma.c   (nonexistent)
+++ config/rx/rx-pragma.c   (working copy)
@@ -0,0 +1,67 @@
+/* Subroutines used for code generation on Renesas RX processors.
+   Copyright (C) 2018 Free Software Foundation, Inc.
+   Contributed by Sebastian Perta.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+   
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "c-family/c-common.h"
+#include "c-family/c-pragma.h"
+#include "rx-protos.h"
+
+/* Implements the "pragma ADDRESS" pragma.  This pragma takes a
+ *variable name and an address, and arranges for that variable to be
+ *   "at" that address.  The variable is also made volatile.  */
+static void
+rx_pragma_address (cpp_reader * reader ATTRIBUTE_UNUSED)
+{
+  tree var, addr;
+  enum cpp_ttype type;
+  type = pragma_lex ();
+  if (type == CPP_NAME)
+{
+  type = pragma_lex ();
+  if (type == CPP_NUMBER)
+   {
+ if (var != error_mark_node)
+   {
+  unsigned uaddr = tree_to_uhwi (addr);
+  rx_note_pragma_address (IDENTIFIER_POINTER (var),
uaddr);
+   }
+
+ type = pragma_lex ();
+ if (type != CPP_EOF)
+   {
+  error ("junk at end of #pragma ADDRESS");
+   }
+ return;
+

[PATCH] RX pragma address

[Sebastian Perta]

Hello,

The following patch adds a new pragma, "pragma address" for RX.
The patch updates extend.texi and add a test case to the regression as well.
For the test case I checked than test is getting picked up in gcc.log
unfortunately for the .texi part I don't know where to look/what to do to get 
the
documentation generated.

This is similar to the pragma address implemented for M32C.

Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rx-sim

Please let me know if this is OK, Thank you!
Sebastian

Index: ChangeLog
===
--- ChangeLog(revision 256076)
+++ ChangeLog(working copy)
@@ -1,3 +1,21 @@
+2018-01-03  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+* config/rx/rx.c (rx_get_pragma_address): New function
+* config/rx/rx.c (rx_note_pragma_address): New function
+* config/rx/rx.c (rx_output_aligned_common): New function use .set instead
+of .comm for pragma address variables
+* config/rx/rx.c (rx_insert_attributes): New function which makes pragma 
address
+variables volatile
+* config/rx/rx-pragma.c: New file with 2 functions rx_pragma_address and
+rx_register_pragmas to implement and register the new pragma
+* config/rx/rx-protos.h: New declarations rl78_note_pragma_address,
+rx_register_pragmas, rx_output_aligned_common
+* config/rx/t-rx: added rx-pragma.o
+* config/rx/rx.h: defined ASM_OUTPUT_ALIGNED_DECL_COMMON and 
REGISTER_TARGET_PRAGMAS
+* doc/entend.texi: Added documenation for RX pragmas
+* testsuite/gcc.target/rx/test_pragma_address.c: New file
+* config.gcc: added "rx-pragma.o" to c_target_objs and cxx_target_objs
+
 2018-01-02  Richard Biener  <rguent...@suse.de>

 * ipa-inline.c (big_speedup_p): Fix expression.
Index: config.gcc
===
--- config.gcc(revision 256076)
+++ config.gcc(working copy)
@@ -2661,6 +2661,8 @@
 rx-*-elf*)
 tm_file="dbxelf.h elfos.h newlib-stdint.h ${tm_file}"
 tmake_file="${tmake_file} rx/t-rx"
+c_target_objs="rx-pragma.o"
+cxx_target_objs="rx-pragma.o"
 ;;
 s390-*-linux*)
 tm_file="s390/s390.h dbxelf.h elfos.h gnu-user.h linux.h glibc-stdint.h 
s390/linux.h"
Index: config/rx/rx-pragma.c
===
--- config/rx/rx-pragma.c(nonexistent)
+++ config/rx/rx-pragma.c(working copy)
@@ -0,0 +1,67 @@
+/* Subroutines used for code generation on Renesas RX processors.
+   Copyright (C) 2018 Free Software Foundation, Inc.
+   Contributed by Sebastian Perta.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tree.h"
+#include "c-family/c-common.h"
+#include "c-family/c-pragma.h"
+#include "rx-protos.h"
+
+/* Implements the "pragma ADDRESS" pragma.  This pragma takes a
+ *variable name and an address, and arranges for that variable to be
+ *   "at" that address.  The variable is also made volatile.  */
+static void
+rx_pragma_address (cpp_reader * reader ATTRIBUTE_UNUSED)
+{
+  tree var, addr;
+  enum cpp_ttype type;
+  type = pragma_lex ();
+  if (type == CPP_NAME)
+{
+  type = pragma_lex ();
+  if (type == CPP_NUMBER)
+{
+  if (var != error_mark_node)
+{
+   unsigned uaddr = tree_to_uhwi (addr);
+   rx_note_pragma_address (IDENTIFIER_POINTER (var), uaddr);
+}
+
+  type = pragma_lex ();
+  if (type != CPP_EOF)
+{
+   error ("junk at end of #pragma ADDRESS");
+}
+  return;
+}
+}
+  error ("malformed #pragma ADDRESS variable address");
+}
+
+void
+rx_register_pragmas (void)
+{
+  c_register_pragma (NULL, "ADDRESS", rx_pragma_address);
+  c_register_pragma (NULL, "address", rx_pragma_address);
+}
+
Index: config/rx/rx-protos.h
===
--- config/rx/rx-protos.h(revision 256076)
+++ config/rx/rx-protos.h(working copy)
@@ -25,7 +25,11 @@
 extern voidrx_expand_epilogue (bool);
 extern voidrx_expand_prologue (void);
 extern intrx_initial_elimination_offset (int, int);
+extern void rx_register_pragmas (void);

+extern void rx_note

[PATCH] RL78 pragma address

[Sebastian Perta]

Hello 

The following patch adds a new pragma, "pragma address" for RL78.
The patch updates extend.texi and add a test case to the regression as well.
For the test case I checked than test is getting picked up in gcc.log
unfortunately 
for the .texi part I don't know where to look/what to do to get the
documentation generated.

This is similar to the pragma address implemented for M32C.

Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

Please let me know if this is OK, Thank you!
Sebastian

Index: ChangeLog
===
--- ChangeLog   (revision 255643)
+++ ChangeLog   (working copy)
@@ -1,3 +1,19 @@
+2017-12-14  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/rl78.c (rl78_get_pragma_address): New function
+   * config/rl78/rl78.c (rl78_note_pragma_address): New function 
+   * config/rl78/rl78.c (rl78_output_aligned_common): use .set instead 
+   of .comm for pragma address variables
+   * config/rl78/rl78.c (rl78_insert_attributes): make pragma address 
+   variables volatile
+   * config/rl78/rl78-c.c (rl78_pragma_address): New function
+   * config/rl78/rl78-c.c (rl78_register_pragmas): registered the new 
+   pragma address
+   * config/rl78/rl78-protos.h: New declaration
rl78_note_pragma_address
+   * doc/entend.texi: Added documenation for RL78 pragmas
+   * testsuite/gcc.target/rl78/test_pragma_address.c: New file
+   
+   
 2017-12-14  Andreas Schwab  <sch...@linux-m68k.org>
 
PR bootstrap/83396
Index: config/rl78/rl78-c.c
===
--- config/rl78/rl78-c.c(revision 255643)
+++ config/rl78/rl78-c.c(working copy)
@@ -23,7 +23,42 @@
 #include "coretypes.h"
 #include "tm.h"
 #include "c-family/c-common.h"
+#include "c-family/c-pragma.h"
+#include "rl78-protos.h"
 
+/* Implements the "pragma ADDRESS" pragma.  This pragma takes a
+   variable name and an address, and arranges for that variable to be
+   "at" that address.  The variable is also made volatile.  */
+static void
+rl78_pragma_address (cpp_reader * reader ATTRIBUTE_UNUSED)
+{
+  /* on off */
+  tree var, addr;
+  enum cpp_ttype type;
+
+  type = pragma_lex ();
+  if (type == CPP_NAME)
+{
+  type = pragma_lex ();
+  if (type == CPP_NUMBER)
+   {
+ if (var != error_mark_node)
+   {
+ unsigned uaddr = tree_to_uhwi (addr);
+ rl78_note_pragma_address (IDENTIFIER_POINTER (var), uaddr);
+   }
+
+ type = pragma_lex ();
+ if (type != CPP_EOF)
+   {
+ error ("junk at end of #pragma ADDRESS");
+   }
+ return;
+   }
+}
+  error ("malformed #pragma ADDRESS variable address");
+}
+
 /* Implements REGISTER_TARGET_PRAGMAS.  */
 void
 rl78_register_pragmas (void)
@@ -30,4 +65,7 @@
 {
   c_register_addr_space ("__near", ADDR_SPACE_NEAR);
   c_register_addr_space ("__far", ADDR_SPACE_FAR);
+  
+  c_register_pragma (NULL, "ADDRESS", rl78_pragma_address);
+  c_register_pragma (NULL, "address", rl78_pragma_address);
 }
Index: config/rl78/rl78-protos.h
===
--- config/rl78/rl78-protos.h   (revision 255643)
+++ config/rl78/rl78-protos.h   (working copy)
@@ -52,6 +52,7 @@
 intrl78_sfr_p (rtx x);
 void   rl78_output_aligned_common (FILE *, tree, const char *,
int, int, int);
+void   rl78_note_pragma_address (const char *varname, unsigned
address);
 
 intrl78_one_far_p (rtx *operands, int num_operands);
 
Index: config/rl78/rl78.c
===
--- config/rl78/rl78.c  (revision 255643)
+++ config/rl78/rl78.c  (working copy)
@@ -4565,6 +4565,30 @@
   fputs (str2, file);
 }
 
+struct GTY(()) pragma_entry {
+  const char *varname;
+  unsigned address;
+};
+typedef struct pragma_entry pragma_entry;
+
+/* Hash table of pragma info.  */
+static GTY(()) hash_map<nofree_string_hash, unsigned> *pragma_htab;
+
+static bool
+rl78_get_pragma_address (const char *varname, unsigned *address)
+{
+  if (!pragma_htab)
+return false;
+
+  unsigned int *slot = pragma_htab->get (varname);
+  if (slot)
+{
+  *address = *slot;
+  return true;
+}
+  return false;
+}
+
 void
 rl78_output_aligned_common (FILE *stream,
tree decl ATTRIBUTE_UNUSED,
@@ -4571,6 +4595,7 @@
const char *name,
int size, int align, int global)
 {
+  unsigned int address;
   /* We intentionally don't use rl78_section_tag() here.  */
   if (name[0] == '@' && nam

[PATCH] RL78 bswaphi improvement

[Sebastian Perta]

Hello,

The following patch helps GCC to generate xch instruction.

The patch is being useful in many test cases from c-torture, for example in
gcc.c-torture/execute/pr52760.c 
xch is being generated 4 times in foo and the code size for foo is being
reduced from 94 to 58 bytes.

Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

Please let me know if this is OK, Thank you!
Sebastian

Index: ChangeLog
===
--- ChangeLog   (revision 255581)
+++ ChangeLog   (working copy)
@@ -1,3 +1,9 @@
+2017-12-12  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/rl78-expand.md: New define_expand "bswaphi2"
+   * config/rl78/rl78-virt.md: New define_insn "*bswaphi2_virt"
+   * config/rl78/rl78-real.md: New define_insn "*bswaphi2_real"
+   
 2017-12-12  Richard Biener  <rguent...@suse.de>
 
PR tree-optimization/83385
Index: config/rl78/rl78-expand.md
===
--- config/rl78/rl78-expand.md  (revision 255581)
+++ config/rl78/rl78-expand.md  (working copy)
@@ -105,6 +105,14 @@
   [(set_attr "valloc" "op1")]
 )
 
+(define_expand "bswaphi2"
+  [(set (match_operand:HI   0 "nonimmediate_operand")
+(bswap:HI (match_operand:HI 1 "general_operand")))]
+  ""
+  "if (rl78_force_nonfar_2 (operands, gen_bswaphi2))
+ DONE;"
+)
+
 ;;-- Conversions 
 
 (define_expand "zero_extendqihi2"
Index: config/rl78/rl78-real.md
===
--- config/rl78/rl78-real.md(revision 255581)
+++ config/rl78/rl78-real.md(working copy)
@@ -90,6 +90,15 @@
movw\t%0, %1"
 )
 
+(define_insn "*bswaphi2_real"
+  [(set (match_operand:HI   0 "rl78_nonfar_nonimm_operand" "=A,A")
+(bswap:HI (match_operand:HI 1 "general_operand"  "0,viU")))]
+  "rl78_real_insns_ok ()"
+  "@
+   xch\ta, x
+   movw\tax, %1\n\txch\ta, x"
+)
+
 ;;-- Conversions 
 
 (define_insn "*zero_extendqihi2_real"
Index: config/rl78/rl78-virt.md
===
--- config/rl78/rl78-virt.md(revision 255581)
+++ config/rl78/rl78-virt.md(working copy)
@@ -65,6 +65,14 @@
   [(set_attr "valloc" "op1")]
 )
 
+(define_insn "*bswaphi2_virt"
+  [(set (match_operand:HI   0 "rl78_nonfar_nonimm_operand" "=vm")
+(bswap:HI (match_operand:HI 1 "general_operand"  "vim")))]
+  "rl78_virt_insns_ok ()"
+  "v.bswaphi\t%0, %1"
+  [(set_attr "valloc" "op1")]
+)
+
 ;;-- Conversions 
 
 (define_insn "*zero_extendqihi2_virt"

[PATCH] RL78 movdi improvement

[Sebastian Perta]

Hello,

The following patch improves 64 bit operations by instructing GCC to use 16
bit movw instead of 8 bit mov.
On the following test case the patch reduces the code size from 323 bytes to
245 bytes.
unsigned long long my_anddi3(unsigned long long x, unsigned long long y){ 
return x & y;
}
I did not add this to the regression as it very simple and there many test
cases in the regression especially c-torture which use this patch.
Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

Please let me know if this is OK, Thank you!
Sebastian

Index: ChangeLog
===
--- ChangeLog   (revision 255538)
+++ ChangeLog   (working copy)
@@ -1,3 +1,9 @@
+2017-12-12  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/rl78-protos.h: New function declaration
rl78_split_movdi
+   * config/rl78/rl78.md: New define_expand "movdi"
+   * config/rl78/rl78.c: New function definition rl78_split_movdi
+   
 2017-12-10  Gerald Pfeifer  <ger...@pfeifer.com>
 
* doc/install.texi (Specific): Tweak link to mkssoftware.com.
Index: config/rl78/rl78-protos.h
===
--- config/rl78/rl78-protos.h   (revision 255538)
+++ config/rl78/rl78-protos.h   (working copy)
@@ -23,6 +23,7 @@
 void   rl78_expand_compare (rtx *);
 void   rl78_expand_movsi (rtx *);
 void   rl78_split_movsi (rtx *, machine_mode);
+void   rl78_split_movdi (rtx *, enum machine_mode);
 intrl78_force_nonfar_2 (rtx *, rtx (*gen)(rtx,rtx));
 intrl78_force_nonfar_3 (rtx *, rtx (*gen)(rtx,rtx,rtx));
 void   rl78_expand_eh_epilogue (rtx);
Index: config/rl78/rl78.c
===
--- config/rl78/rl78.c  (revision 255538)
+++ config/rl78/rl78.c  (working copy)
@@ -596,6 +596,18 @@
 }
 }
 
+void
+rl78_split_movdi (rtx *operands, enum machine_mode omode)
+{
+rtx op00, op04, op10, op14;
+op00 = rl78_subreg (SImode, operands[0], omode, 0);
+op04 = rl78_subreg (SImode, operands[0], omode, 4);
+op10 = rl78_subreg (SImode, operands[1], omode, 0);
+op14 = rl78_subreg (SImode, operands[1], omode, 4);
+emit_insn (gen_movsi (op00, op10));
+emit_insn (gen_movsi (op04, op14));
+}
+
 /* Used by various two-operand expanders which cannot accept all
operands in the "far" namespace.  Force some such operands into
registers so that each pattern has at most one far operand.  */
Index: config/rl78/rl78.md
===
--- config/rl78/rl78.md (revision 255538)
+++ config/rl78/rl78.md (working copy)
@@ -718,3 +718,11 @@
   [(set_attr "valloc" "macax")
(set_attr "is_g13_muldiv_insn" "yes")]
 )
+
+(define_expand "movdi"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "")
+(match_operand:DI 1 "general_operand"  ""))]
+  ""
+  "rl78_split_movdi(operands, DImode);
+  DONE;"
+)

RE: [PATCH] rl78 anddi3 improvement

[Sebastian Perta]

Hello Jeff,

Thank you for your comments.

>>So I think you're ultimately far better off determining why GCC does not
>>generate efficient code for 64bit logicals on the rl78 target.
I totally agree with you, this is why:
1. I have another patch: I define_expand movdi in which I instruct GCC to use 
16 bit movw instead of movw, with this patch applied on the latest revision I 
reduce the code size of this function (my_anddi3) from 323 bytes to 245 bytes. 
I'm just waiting on the regression to finish I will post this patch.
2. I am working very hard for quite some time to improve/replace the 
"devirtualization" pass (see pass_rl78_devirt in rl78.c). I am working on a 
solution which will generate very similar code what I wrote in ___adddi3 and 
will also allow me to also change the calling convention to be efficient 
(similar to what the RL78 commercial compilers use) but unfortunately I still a 
long way from being finished (as it is quite difficult). I think DJ can explain 
much better why he needed to do things this way (add this pass and the *_virt 
and *_real variants for the instructions) in the first place.

However if you look closely at the patch you will see the that I put the 
following condition for the availability of the expand:
+  "optimize_size"
The idea behind this is the following:
Compared to the commercial RL78 compilers GCC is quite far behind (even 2x-3x 
bigger). When comparing the output code I observed the commercial compilers I 
saw they use quite extensively code merging techniques.
For GCC I found some work on this on a branch which didn't make to master 
(https://www.gnu.org/software/gcc/projects/cfo.html). I have ported this a 
while back to 4.9.2 but I didn't get significant code size improvement (I think 
I will give this another try after I finish point 2 above)
So I decided then to continue doing things this way which finally gave me some 
really good results (improved the code size by 30% on average, even more than 
50% in some cases).
So even if/when I finish with point 2 above I think I will still like to have 
things done this way as they improve code size significantly.

I hope this explanation is satisfactory to you  as I have other patches (not 
only for 64 bit operations) which make use of the same idea.

Best Regards,
Sebastian


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No. 04586709.

[PATCH] rl78 anddi3 improvement

[Sebastian Perta]

Hello,

The following patch improves code size for 64 bit and for RL78:
it emits a library function call instead of emitting code for  the 64 bit
min for every single time.
The and function which was added in libgcc is hand written, so more optimal
than what GCC generates.

The change can easily be seen on the following test case:
unsigned long long my_anddi3(unsigned long long x, unsigned long long y){ 
return x & y;
}
I did not add this to the regression as it very simple and there are test
cases in the regression which test this, for example
gcc.dg/torture/stackalign/alloca-1.c  and
gcc.dg/torture/stackalign/vararg-2.c.
Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

Please let me know if this is OK, Thank you!
Sebastian

Index: gcc/ChangeLog
===
--- gcc/ChangeLog   (revision 255511)
+++ gcc/ChangeLog   (working copy)
@@ -1,3 +1,7 @@
+2017-12-08  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/rl78.md: New define_expand "anddi3".
+   
 2017-12-08  Martin Jambor  <mjam...@suse.cz>
 
PR tree-optimization/83141
Index: gcc/config/rl78/rl78.md
===
--- gcc/config/rl78/rl78.md (revision 255511)
+++ gcc/config/rl78/rl78.md (working copy)
@@ -718,3 +718,13 @@
   [(set_attr "valloc" "macax")
(set_attr "is_g13_muldiv_insn" "yes")]
 )
+
+(define_expand "anddi3"
+ [(set (match_operand:DI  0 "nonimmediate_operand" "")
+   (and:DI (match_operand:DI 1 "general_operand"  "")
+(match_operand:DI2 "general_operand"  "")))
+   ]
+  "optimize_size"
+  "rl78_emit_libcall (\"__anddi3\", AND, DImode, DImode, 3, operands);
+   DONE;"
+)
Index: libgcc/ChangeLog
===
--- libgcc/ChangeLog(revision 255511)
+++ libgcc/ChangeLog(working copy)
@@ -1,3 +1,8 @@
+2017-12-08  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/anddi3.S: New assembly file.
+   * config/rl78/t-rl78: Added anddi3.S to LIB2ADD.
+   
 2017-11-30  Michael Meissner  <meiss...@linux.vnet.ibm.com>
 
* config/rs6000/_mulkc3.c (__mulkc3): Add forward declaration.
Index: libgcc/config/rl78/anddi3.S
===
--- libgcc/config/rl78/anddi3.S (nonexistent)
+++ libgcc/config/rl78/anddi3.S (working copy)
@@ -0,0 +1,66 @@
+;   Copyright (C) 2017 Free Software Foundation, Inc.
+;   Contributed by Sebastian Perta.
+; 
+; This file is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published by the
+; Free Software Foundation; either version 3, or (at your option) any
+; later version.
+; 
+; This file is distributed in the hope that it will be useful, but
+; WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+; General Public License for more details.
+; 
+; Under Section 7 of GPL version 3, you are granted additional
+; permissions described in the GCC Runtime Library Exception, version
+; 3.1, as published by the Free Software Foundation.
+;
+; You should have received a copy of the GNU General Public License and
+; a copy of the GCC Runtime Library Exception along with this program;
+; see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+; <http://www.gnu.org/licenses/>.
+
+
+#include "vregs.h"
+
+.text
+
+START_FUNC ___anddi3
+
+movw  hl, sp
+
+mov   a, [hl+4]
+and   a, [hl+12]
+mov   r8, a
+
+mov   a, [hl+5]
+and   a, [hl+13]
+mov   r9, a
+
+mov   a, [hl+6]
+and   a, [hl+14]
+mov   r10, a
+
+mov   a, [hl+7]
+and   a, [hl+15]
+mov   r11, a
+
+mov   a, [hl+8]
+and   a, [hl+16]
+mov   r12, a
+
+mov   a, [hl+9]
+and   a, [hl+17]
+mov   r13, a
+
+mov   a, [hl+10]
+and   a, [hl+18]
+mov   r14, a
+
+mov   a, [hl+11]
+and   a, [hl+19]
+mov   r15, a
+
+ret
+
+END_FUNC ___anddi3
Index: libgcc/config/rl78/t-rl78
===
--- libgcc/config/rl78/t-rl78   (revision 255511)
+++ libgcc/config/rl78/t-rl78   (working copy)
@@ -32,7 +32,8 @@
$(srcdir)/config/rl78/fpmath-sf.S \
$(srcdir)/config/rl78/cmpsi2.S \
$(srcdir)/config/rl78/adddi3.S \
-   $(srcdir)/config/rl78/subdi3.S
+   $(srcdir)/config/rl78/subdi3.S \
+   $(srcdir)/config/rl78/anddi3.S
 
 LIB2FUNCS_EXCLUDE = _clzhi2 _clzsi2 _ctzhi2 _ctzsi2 \
   _popcounthi2 _popcountsi2 \

[PATCH] rl78 umindi3 improvement

[Sebastian Perta]

Hello,

The following patch improves both the speed and code size for 64 bit
unsigned min for RL78:
it emits a library function call instead of emitting code for  the 64 bit
min for every single time.
The unsigned min function which was added in libgcc is hand written, so more
optimal than what GCC generates.

The change can easily be seen on the following test case:
unsigned long long my_smaxdi3(unsigned long long x, unsigned long long y){ 
return (x < y)? x : y;
}
I did not add this to the regression as it very simple and there are test
cases in the regression which test this, for example
gcc.c-torture/execute/pr49039.c and gcc.dg/torture/pr25718-1.c.
Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

Please let me know if this is OK, Thank you!
Sebastian

Index: gcc/ChangeLog
===
--- gcc/ChangeLog   (revision 255471)
+++ gcc/ChangeLog   (working copy)
@@ -1,3 +1,7 @@
+2017-12-07  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/rl78.md: New define_expand "umindi3".
+   
 2017-12-07  Vladimir Makarov  <vmaka...@redhat.com>
 
PR target/83252
Index: gcc/config/rl78/rl78.md
===
--- gcc/config/rl78/rl78.md (revision 255471)
+++ gcc/config/rl78/rl78.md (working copy)
@@ -234,6 +234,16 @@
DONE;"
 )
 
+(define_expand "umindi3"
+ [(set (match_operand:DI  0 "nonimmediate_operand" "")
+   (umin:DI (match_operand:DI 1 "general_operand"  "")
+(match_operand:DI2 "general_operand"  "")))
+   ]
+  "optimize_size"
+  "rl78_emit_libcall (\"__umindi3\", UMIN, DImode, DImode, 3, operands);
+   DONE;"
+)
+
 (define_insn "addsi3_internal_virt"
   [(set (match_operand:SI  0 "nonimmediate_operand" "=v,, vm")
(plus:SI (match_operand:SI 1 "general_operand"  "0, vim, vim")
Index: libgcc/ChangeLog
=======
--- libgcc/ChangeLog(revision 255471)
+++ libgcc/ChangeLog(working copy)
@@ -1,3 +1,8 @@
+2017-12-07  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/umindi3.S: New assembly file.
+   * config/rl78/t-rl78: Added umindi3.S to LIB2ADD.
+   
 2017-11-30  Michael Meissner  <meiss...@linux.vnet.ibm.com>
 
* config/rs6000/_mulkc3.c (__mulkc3): Add forward declaration.
Index: libgcc/config/rl78/t-rl78
===
--- libgcc/config/rl78/t-rl78   (revision 255471)
+++ libgcc/config/rl78/t-rl78   (working copy)
@@ -32,7 +32,8 @@
$(srcdir)/config/rl78/fpmath-sf.S \
$(srcdir)/config/rl78/cmpsi2.S \
$(srcdir)/config/rl78/adddi3.S \
-   $(srcdir)/config/rl78/subdi3.S
+   $(srcdir)/config/rl78/subdi3.S \
+   $(srcdir)/config/rl78/umindi3.S
 
 LIB2FUNCS_EXCLUDE = _clzhi2 _clzsi2 _ctzhi2 _ctzsi2 \
   _popcounthi2 _popcountsi2 \
Index: libgcc/config/rl78/umindi3.S
===
--- libgcc/config/rl78/umindi3.S(nonexistent)
+++ libgcc/config/rl78/umindi3.S(working copy)
@@ -0,0 +1,74 @@
+;   Copyright (C) 2017 Free Software Foundation, Inc.
+;   Contributed by Sebastian Perta.
+; 
+; This file is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published by the
+; Free Software Foundation; either version 3, or (at your option) any
+; later version.
+; 
+; This file is distributed in the hope that it will be useful, but
+; WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+; General Public License for more details.
+; 
+; Under Section 7 of GPL version 3, you are granted additional
+; permissions described in the GCC Runtime Library Exception, version
+; 3.1, as published by the Free Software Foundation.
+;
+; You should have received a copy of the GNU General Public License and
+; a copy of the GCC Runtime Library Exception along with this program;
+; see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+; <http://www.gnu.org/licenses/>.
+
+
+#include "vregs.h"
+
+.text
+
+START_FUNC ___umindi3
+
+; copy first argument/operand to the output registers
+movw   ax, [sp+4]
+movw   r8, ax
+movw   ax, [sp+6]
+movw   r10, ax
+movw   ax, [sp+8]
+movw   r12, ax
+movw   ax, [sp+10]
+movw   r14, ax
+
+; use 16-bit compares from the most significant words downto the least
significant ones
+movw   ax, [sp+18]
+cmpw   ax, r14
+bc $.L1
+bnz$.L2
+
+movw   ax, [sp+16]
+  

[PATCH] rl78 smindi3 improvement

[Sebastian Perta]

Hello,

The following patch improves both the speed and code size for 64 bit signed
min for RL78:
it emits a library function call instead of emitting code for  the 64 bit
min for every single time.
The signed min function which was added in libgcc is hand written, so more
optimal than what GCC generates.

The change can easily be seen on the following test case:
long long my_smaxdi3(long long x, long long y){ 
return (x < y)? x : y;
}
I did not add this to the regression as it very simple and there are test
cases in the regression which test this, for example
gcc.c-torture/execute/mode-dependent-address.c and
gcc.c-torture/execute/pr68249.c
Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

Please let me know if this is OK, Thank you!
Sebastian

Index: gcc/ChangeLog
===
--- gcc/ChangeLog   (revision 255468)
+++ gcc/ChangeLog   (working copy)
@@ -1,3 +1,8 @@
+2017-12-07  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/rl78.md: New define_expand "smindi3".
+   
+
 2017-12-07  Tamar Christina  <tamar.christ...@arm.com>
 
PR target/82641
Index: gcc/config/rl78/rl78.md
===
--- gcc/config/rl78/rl78.md (revision 255468)
+++ gcc/config/rl78/rl78.md (working copy)
@@ -718,3 +718,13 @@
   [(set_attr "valloc" "macax")
(set_attr "is_g13_muldiv_insn" "yes")]
 )
+
+(define_expand "smindi3"
+ [(set (match_operand:DI  0 "nonimmediate_operand" "")
+   (smin:DI (match_operand:DI 1 "general_operand"  "")
+(match_operand:DI2 "general_operand"  "")))
+   ]
+  "optimize_size"
+  "rl78_emit_libcall (\"__smindi3\", SMIN, DImode, DImode, 3, operands);
+   DONE;"
+)
Index: libgcc/ChangeLog
=======
--- libgcc/ChangeLog(revision 255468)
+++ libgcc/ChangeLog(working copy)
@@ -1,3 +1,8 @@
+2017-12-07  Sebastian Perta  <sebastian.pe...@renesas.com>
+ 
+   * config/rl78/smindi3.S: New assembly file.
+   * config/rl78/t-rl78: Added smindi3.S to LIB2ADD.
+
 2017-11-30  Michael Meissner  <meiss...@linux.vnet.ibm.com>
 
* config/rs6000/_mulkc3.c (__mulkc3): Add forward declaration.
Index: libgcc/config/rl78/t-rl78
===
--- libgcc/config/rl78/t-rl78   (revision 255468)
+++ libgcc/config/rl78/t-rl78   (working copy)
@@ -32,7 +32,8 @@
$(srcdir)/config/rl78/fpmath-sf.S \
$(srcdir)/config/rl78/cmpsi2.S \
$(srcdir)/config/rl78/adddi3.S \
-   $(srcdir)/config/rl78/subdi3.S
+   $(srcdir)/config/rl78/subdi3.S \
+   $(srcdir)/config/rl78/smindi3.S
 
 LIB2FUNCS_EXCLUDE = _clzhi2 _clzsi2 _ctzhi2 _ctzsi2 \
   _popcounthi2 _popcountsi2 \
Index: libgcc/config/rl78/smindi3.S
===
--- libgcc/config/rl78/smindi3.S    (nonexistent)
+++ libgcc/config/rl78/smindi3.S(working copy)
@@ -0,0 +1,76 @@
+;   Copyright (C) 2017 Free Software Foundation, Inc.
+;   Contributed by Sebastian Perta.
+; 
+; This file is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published by the
+; Free Software Foundation; either version 3, or (at your option) any
+; later version.
+; 
+; This file is distributed in the hope that it will be useful, but
+; WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+; General Public License for more details.
+; 
+; Under Section 7 of GPL version 3, you are granted additional
+; permissions described in the GCC Runtime Library Exception, version
+; 3.1, as published by the Free Software Foundation.
+;
+; You should have received a copy of the GNU General Public License and
+; a copy of the GCC Runtime Library Exception along with this program;
+; see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+; <http://www.gnu.org/licenses/>.
+
+
+#include "vregs.h"
+
+.text
+
+START_FUNC ___smindi3
+
+; copy first argument/operand to the output registers
+movw   ax, [sp+4]
+movw   r8, ax
+movw   ax, [sp+6]
+movw   r10, ax
+movw   ax, [sp+8]
+movw   r12, ax
+movw   ax, [sp+10]
+movw   r14, ax
+
+; use 16-bit compares from the most significant words downto the least
significant ones
+movw   ax, [sp+18]
+cmpw   ax, r14
+xor1   CY, a.7   ; first compare accounts for the
+xor1   CY, r15.7 ; sign bits of the two operands
+bc $.L1
+bnz$.L2
+
+movw   ax, [sp+16]
+cmpw   ax, r12
+bc $.L1
+

[PATCH] rl78 smaxdi3 improvement

[Sebastian Perta]

Hello,

The following patch improves both the speed and code size for 64 bit signed
max for RL78:
it emits a library function call instead of emitting code for  the 64 bit
max for every single time.
The signed max function which was added in libgcc is hand written, so more
optimal than what GCC generates.

The change can easily be seen on the following test case:
long long my_smaxdi3(long long x, long long y){ 
return (x > y)? x : y;
}
I did not add this to the regression as it very simple and there are test
cases in the regression which test this, for example
gcc.c-torture/execute/2224-1.c and gcc.c-torture/execute/20021010-2.c
Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

Please let me know if this is OK, Thank you!
Sebastian

Index: gcc/ChangeLog
===
--- gcc/ChangeLog   (revision 255467)
+++ gcc/ChangeLog   (working copy)
@@ -1,3 +1,7 @@
+2017-12-07  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/rl78.md: New define_expand "smaxdi3".
+   
 2017-12-07  Michael Matz  <m...@suse.de>
 
Add unroll and jam pass
Index: gcc/config/rl78/rl78.md
===
--- gcc/config/rl78/rl78.md (revision 255467)
+++ gcc/config/rl78/rl78.md (working copy)
@@ -718,3 +718,13 @@
   [(set_attr "valloc" "macax")
(set_attr "is_g13_muldiv_insn" "yes")]
 )
+
+(define_expand "smaxdi3"
+ [(set (match_operand:DI  0 "nonimmediate_operand" "")
+   (smax:DI (match_operand:DI 1 "general_operand"  "")
+(match_operand:DI2 "general_operand"  "")))
+   ]
+  "optimize_size"
+  "rl78_emit_libcall (\"__smaxdi3\", SMAX, DImode, DImode, 3, operands);
+   DONE;"
+)
Index: libgcc/ChangeLog
=======
--- libgcc/ChangeLog(revision 255467)
+++ libgcc/ChangeLog(working copy)
@@ -1,3 +1,9 @@
+2017-12-07  Sebastian Perta  <sebastian.pe...@renesas.com>
+ 
+   * config/rl78/smaxdi3.S: New assembly file.
+   * config/rl78/t-rl78: Added smaxdi3.S to LIB2ADD.
+
+
 2017-11-30  Michael Meissner  <meiss...@linux.vnet.ibm.com>
 
* config/rs6000/_mulkc3.c (__mulkc3): Add forward declaration.
Index: libgcc/config/rl78/t-rl78
===
--- libgcc/config/rl78/t-rl78   (revision 255467)
+++ libgcc/config/rl78/t-rl78   (working copy)
@@ -32,7 +32,8 @@
$(srcdir)/config/rl78/fpmath-sf.S \
$(srcdir)/config/rl78/cmpsi2.S \
$(srcdir)/config/rl78/adddi3.S \
-   $(srcdir)/config/rl78/subdi3.S
+   $(srcdir)/config/rl78/subdi3.S \
+   $(srcdir)/config/rl78/smaxdi3.S
 
 LIB2FUNCS_EXCLUDE = _clzhi2 _clzsi2 _ctzhi2 _ctzsi2 \
   _popcounthi2 _popcountsi2 \
Index: libgcc/config/rl78/smaxdi3.S
===
--- libgcc/config/rl78/smaxdi3.S    (nonexistent)
+++ libgcc/config/rl78/smaxdi3.S(working copy)
@@ -0,0 +1,76 @@
+;   Copyright (C) 2017 Free Software Foundation, Inc.
+;   Contributed by Sebastian Perta.
+; 
+; This file is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published by the
+; Free Software Foundation; either version 3, or (at your option) any
+; later version.
+; 
+; This file is distributed in the hope that it will be useful, but
+; WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+; General Public License for more details.
+; 
+; Under Section 7 of GPL version 3, you are granted additional
+; permissions described in the GCC Runtime Library Exception, version
+; 3.1, as published by the Free Software Foundation.
+;
+; You should have received a copy of the GNU General Public License and
+; a copy of the GCC Runtime Library Exception along with this program;
+; see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+; <http://www.gnu.org/licenses/>.
+
+
+#include "vregs.h"
+
+.text
+
+START_FUNC ___smaxdi3
+
+; copy first argument/operand to the output registers
+movw   ax, [sp+4]
+movw   r8, ax
+movw   ax, [sp+6]
+movw   r10, ax
+movw   ax, [sp+8]
+movw   r12, ax
+movw   ax, [sp+10]
+movw   r14, ax
+
+; use 16-bit compares from the most significant words downto the least
significant ones
+movw   ax, [sp+18]
+cmpw   ax, r14
+xor1   CY, a.7   ; first compare accounts for the
+xor1   CY, r15.7 ; sign bits of the two operands
+bh $.L1
+bnz$.L2
+
+movw   ax, [sp+16]
+cmpw   ax, r12
+bh $.L1
+bnz$.L2
+

FW: [PATCH] rl78 umaxdi3 improvement

[Sebastian Perta]

Hello,

The following patch improves both the speed and code size for 64 bit
unsigned max for RL78:
it emits a library function call instead of emitting code for  the 64 bit
max for every single time.
The unsigned max function which was added in libgcc is hand written, so more
optimal than what GCC generates.

The change can easily be seen on the following test case:
unsigned long long my_umaxdi3(unsigned long long x, unsigned long long y){ 
return (x > y)? x : y;
}
I did not add this to the regression as it very simple and there are test
cases in the regression which test this, for example
gcc/testsuite/gcc.c-torture/execute/pr49039.c
Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

Please let me know if this is OK, Thank you!
Sebastian

Index: gcc/ChangeLog
===
--- gcc/ChangeLog   (revision 255466)
+++ gcc/ChangeLog   (working copy)
@@ -1,3 +1,7 @@
+2017-12-07  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+   * config/rl78/rl78.md: New define_expand "umaxdi3".
+   
 2017-12-07  Richard Biener  <rguent...@suse.de>
 
PR tree-optimization/83296
Index: gcc/config/rl78/rl78.md
===
--- gcc/config/rl78/rl78.md (revision 255466)
+++ gcc/config/rl78/rl78.md (working copy)
@@ -718,3 +718,13 @@
   [(set_attr "valloc" "macax")
(set_attr "is_g13_muldiv_insn" "yes")]
 )
+
+(define_expand "umaxdi3"
+ [(set (match_operand:DI  0 "nonimmediate_operand" "")
+   (umax:DI (match_operand:DI 1 "general_operand"  "")
+(match_operand:DI2 "general_operand"  "")))
+   ]
+  "optimize_size"
+  "rl78_emit_libcall (\"__umaxdi3\", UMAX, DImode, DImode, 3, operands);
+   DONE;"
+)
Index: libgcc/ChangeLog
=======
--- libgcc/ChangeLog(revision 255466)
+++ libgcc/ChangeLog(working copy)
@@ -1,3 +1,8 @@
+2017-12-07  Sebastian Perta  <sebastian.pe...@renesas.com>
+ 
+   * config/rl78/umaxdi3.S: New assembly file.
+   * config/rl78/t-rl78: Added umaxdi3.S to LIB2ADD.
+
 2017-11-30  Michael Meissner  <meiss...@linux.vnet.ibm.com>
 
* config/rs6000/_mulkc3.c (__mulkc3): Add forward declaration.
Index: libgcc/config/rl78/t-rl78
===
--- libgcc/config/rl78/t-rl78   (revision 255466)
+++ libgcc/config/rl78/t-rl78   (working copy)
@@ -32,7 +32,8 @@
$(srcdir)/config/rl78/fpmath-sf.S \
$(srcdir)/config/rl78/cmpsi2.S \
$(srcdir)/config/rl78/adddi3.S \
-   $(srcdir)/config/rl78/subdi3.S
+   $(srcdir)/config/rl78/subdi3.S \
+   $(srcdir)/config/rl78/umaxdi3.S
 
 LIB2FUNCS_EXCLUDE = _clzhi2 _clzsi2 _ctzhi2 _ctzsi2 \
   _popcounthi2 _popcountsi2 \
Index: libgcc/config/rl78/umaxdi3.S
===
--- libgcc/config/rl78/umaxdi3.S    (nonexistent)
+++ libgcc/config/rl78/umaxdi3.S(working copy)
@@ -0,0 +1,74 @@
+;   Copyright (C) 2017 Free Software Foundation, Inc.
+;   Contributed by Sebastian Perta.
+; 
+; This file is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published by the
+; Free Software Foundation; either version 3, or (at your option) any
+; later version.
+; 
+; This file is distributed in the hope that it will be useful, but
+; WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+; General Public License for more details.
+; 
+; Under Section 7 of GPL version 3, you are granted additional
+; permissions described in the GCC Runtime Library Exception, version
+; 3.1, as published by the Free Software Foundation.
+;
+; You should have received a copy of the GNU General Public License and
+; a copy of the GCC Runtime Library Exception along with this program;
+; see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+; <http://www.gnu.org/licenses/>.
+
+
+#include "vregs.h"
+
+.text
+
+START_FUNC ___umaxdi3
+
+; copy first argument/operand to the output registers
+movw   ax, [sp+4]
+movw   r8, ax
+movw   ax, [sp+6]
+movw   r10, ax
+movw   ax, [sp+8]
+movw   r12, ax
+movw   ax, [sp+10]
+movw   r14, ax
+
+; use 16-bit compares from the most significant words downto the least
significant ones
+movw   ax, [sp+18]
+cmpw   ax, r14
+bh $.L1
+bnz$.L2
+
+movw   ax, [sp+16]
+cmpw   ax, r12
+bh $.L1
+bnz$.L2
+
+movw   ax, [sp+14]
+cmpw   ax, r10
+bh $.L1
+bnz$.L2
+
+movw   ax, [sp+

[PATCH] rl78 subdi3 improvement

[Sebastian Perta]

Hello,

The following patch improves both the speed and code size for 64 bit 
subtraction for RL78:
it emits a library function call instead of emitting code for  the 64 bit add 
for every single subtraction.
The subtraction function which was added in libgcc is hand written, so more 
optimal than what GCC generates.

The change can easily be seen on the following test case.
long long my_subdi3(long long a, long long b) {
return a - b;
}
I did not add this to the regression as it very simple and there are many test 
cases in the regression which test this, for example 
gcc.c-torture/execute/20041011-1.c and  gcc.c-torture/execute/arith-rand-ll.c  
and so on.

Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

Please let me know if this is OK, Thank you!
Sebastian

Index: gcc/ChangeLog
===
--- gcc/ChangeLog(revision 253893)
+++ gcc/ChangeLog(working copy)
@@ -1,3 +1,7 @@
+2017-10-13  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+* config/rl78/rl78.md: New define_expand "subdi3".
+
 2017-10-19  Eric Botcazou  <ebotca...@adacore.com>

 PR debug/82509
Index: gcc/config/rl78/rl78.md
===
--- gcc/config/rl78/rl78.md(revision 253893)
+++ gcc/config/rl78/rl78.md(working copy)
@@ -268,6 +268,16 @@
   DONE;"
 )

+(define_expand "subdi3"
+ [(set (match_operand:DI  0 "nonimmediate_operand" "")
+(minus:DI (match_operand:DI 1 "general_operand"  "")
+ (match_operand:DI2 "general_operand"  "")))
+   ]
+  ""
+  "rl78_emit_libcall (\"__subdi3\", MINUS, DImode, DImode, 3, operands);
+   DONE;"
+)
+
 (define_insn "subsi3_internal_virt"
   [(set (match_operand:SI   0 "nonimmediate_operand" "=v,, vm")
 (minus:SI (match_operand:SI 1 "general_operand"  "0, vim, vim")
Index: libgcc/ChangeLog
=======
--- libgcc/ChangeLog(revision 253893)
+++ libgcc/ChangeLog(working copy)
@@ -1,5 +1,10 @@
 2017-10-13  Sebastian Perta  <sebastian.pe...@renesas.com>

+* config/rl78/subdi3.S: New assembly file.
+* config/rl78/t-rl78: Added subdi3.S to LIB2ADD.
+
+2017-10-13  Sebastian Perta  <sebastian.pe...@renesas.com>
+
 * config/rl78/adddi3.S: New assembly file.
 * config/rl78/t-rl78: Added adddi3.S to LIB2ADD.

Index: libgcc/config/rl78/t-rl78
===
--- libgcc/config/rl78/t-rl78(revision 253893)
+++ libgcc/config/rl78/t-rl78(working copy)
@@ -31,7 +31,8 @@
 $(srcdir)/config/rl78/fpbit-sf.S \
 $(srcdir)/config/rl78/fpmath-sf.S \
 $(srcdir)/config/rl78/cmpsi2.S \
-$(srcdir)/config/rl78/adddi3.S
+$(srcdir)/config/rl78/adddi3.S \
+$(srcdir)/config/rl78/subdi3.S

 LIB2FUNCS_EXCLUDE = _clzhi2 _clzsi2 _ctzhi2 _ctzsi2 \
   _popcounthi2 _popcountsi2 \
Index: libgcc/config/rl78/subdi3.S
===
--- libgcc/config/rl78/subdi3.S(nonexistent)
+++ libgcc/config/rl78/subdi3.S(working copy)
@@ -0,0 +1,58 @@
+;   Copyright (C) 2017 Free Software Foundation, Inc.
+;   Contributed by Sebastian Perta.
+;
+; This file is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published by the
+; Free Software Foundation; either version 3, or (at your option) any
+; later version.
+;
+; This file is distributed in the hope that it will be useful, but
+; WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+; General Public License for more details.
+;
+; Under Section 7 of GPL version 3, you are granted additional
+; permissions described in the GCC Runtime Library Exception, version
+; 3.1, as published by the Free Software Foundation.
+;
+; You should have received a copy of the GNU General Public License and
+; a copy of the GCC Runtime Library Exception along with this program;
+; see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+; <http://www.gnu.org/licenses/>.
+
+
+#include "vregs.h"
+
+.text
+
+START_FUNC ___subdi3
+
+movw  hl, sp   ; use HL-based addressing (allows for direct subw)
+
+movw  ax, [hl+4]
+subw  ax, [hl+12]
+movw  r8, ax
+
+mov   a, [hl+6]; middle bytes of the result are determined using 8-bit
+subc  a, [hl+14]   ; SUBC insns which both account for and update the 
carry bit
+mov   r10, a   ; (no SUBWC instruction is available)
+mov   a, [hl+7]
+subc  a, [hl+15]
+mov   r11, a
+
+mov   a, [hl+8]
+subc  a, [hl+16]
+mov   r12, a
+mov   a, [hl+9]
+subc  a, [hl+17]
+mov   r13, a
+
+movw  ax, [hl+1

[PING] [PATCH] rl78 adddi3 improvement

[Sebastian Perta]

Hi,

I would like to ping the below patch posted on 14th of august.

Thank you!

Sebastian


-Original Message-
From: Sebastian Perta
Sent: 14 August 2017 15:26
To: 'gcc-patches@gcc.gnu.org' <gcc-patches@gcc.gnu.org>
Subject: [PATCH] rl78 adddi3 improvement

The following patch improves both the speed and code size for 64 bit addition 
for RL78:
it emits a library function call instead of emitting code for  the 64 bit add 
for every single addition.
The addition function which was added in libgcc is hand written, so more 
optimal than what GCC generates.

The change can easily be seen on the following test case.
long long my_adddi3(long long a, long long b) {
return a + b;
}
I did not add this to the regression as it very simple and there are many test 
cases in the regression which test this, for example 
gcc.c-torture/execute/20090711-1.c and  gcc.c-torture/execute/20091229-1.c and 
so on.

Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

Please let me know if this is OK, Thank you!
Sebastian



Index: gcc/ChangeLog
===
--- gcc/ChangeLog(revision 251091)
+++ gcc/ChangeLog(working copy)
@@ -1,3 +1,12 @@
+2017-08-14  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+changed long long addition for RL78
+* gcc/config/rl78/rl78.c (rl78_emit_libcall): new function.
+* gcc/config/rl78/rl78-protos.h (rl78_emit_libcall): new function.
+* gcc/config/rl78/rl78.md: new define_expand "adddi3".
+* libgcc/config/rl78/adddi3.S: new assembly file.
+* libgcc/config/rl78/t-rl78: added adddi3.S to LIB2ADD.
+
 2017-08-14  Bin Cheng  <bin.ch...@arm.com>

 PR tree-optimization/81799
Index: gcc/config/rl78/rl78-protos.h
===
--- gcc/config/rl78/rl78-protos.h(revision 251091)
+++ gcc/config/rl78/rl78-protos.h(working copy)
@@ -56,3 +56,13 @@
 int, int, int);

 intrl78_one_far_p (rtx *operands, int num_operands);
+
+#ifdef RTX_CODE
+#ifdef HAVE_MACHINE_MODES
+
+rtx rl78_emit_libcall (const char*, enum rtx_code,
+   enum machine_mode, enum machine_mode,
+   int, rtx*);
+
+#endif
+#endif
Index: gcc/config/rl78/rl78.c
===
--- gcc/config/rl78/rl78.c(revision 251091)
+++ gcc/config/rl78/rl78.c(working copy)
@@ -4791,4 +4791,43 @@


 struct gcc_target targetm = TARGET_INITIALIZER;

+rtx
+rl78_emit_libcall (const char *name, enum rtx_code code,
+   enum machine_mode dmode, enum machine_mode smode,
+   int noperands, rtx *operands) {
+  rtx ret;
+  rtx_insn *insns;
+  rtx libcall;
+  rtx equiv;
+
+  start_sequence ();
+  libcall = gen_rtx_SYMBOL_REF (Pmode, name);
+
+  switch (noperands)
+{
+case 2:
+  ret = emit_library_call_value (libcall, NULL_RTX, LCT_CONST,
+ dmode, 1, operands[1], smode);
+  equiv = gen_rtx_fmt_e (code, dmode, operands[1]);
+  break;
+
+case 3:
+  ret = emit_library_call_value (libcall, NULL_RTX,
+ LCT_CONST, dmode, 2,
+ operands[1], smode, operands[2],
+ smode);
+  equiv = gen_rtx_fmt_ee (code, dmode, operands[1], operands[2]);
+  break;
+
+default:
+  gcc_unreachable ();
+}
+
+  insns = get_insns ();
+  end_sequence ();
+  emit_libcall_block (insns, operands[0], ret, equiv);
+  return ret;
+}
+
 #include "gt-rl78.h"
Index: gcc/config/rl78/rl78.md
===
--- gcc/config/rl78/rl78.md(revision 251091)
+++ gcc/config/rl78/rl78.md(working copy)
@@ -224,6 +224,16 @@
DONE;"
 )

+(define_expand "adddi3"
+ [(set (match_operand:DI  0 "nonimmediate_operand" "")
+(plus:DI (match_operand:DI 1 "general_operand"  "")
+ (match_operand:DI2 "general_operand"  "")))
+   ]
+  ""
+  "rl78_emit_libcall (\"__adddi3\", PLUS, DImode, DImode, 3, operands);
+   DONE;"
+)
+
 (define_insn "addsi3_internal_virt"
   [(set (match_operand:SI  0 "nonimmediate_operand" "=v,, vm")
 (plus:SI (match_operand:SI 1 "general_operand"  "0, vim, vim")
Index: libgcc/config/rl78/adddi3.S
===
--- libgcc/config/rl78/adddi3.S(nonexistent)
+++ libgcc/config/rl78/adddi3.S(working copy)
@@ -0,0 +1,58 @@
+;   Copyright (C) 2017 Free Software Foundation, Inc.
+;   Contributed by Sebastian Perta.
+;
+; This file is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published by the
+; Free Software Foundati

[PATCH] rl78 adddi3 improvement

[Sebastian Perta]

The following patch improves both the speed and code size for 64 bit addition 
for RL78:
it emits a library function call instead of emitting code for  the 64 bit add 
for every single addition.
The addition function which was added in libgcc is hand written, so more 
optimal than what GCC generates.

The change can easily be seen on the following test case.
long long my_adddi3(long long a, long long b)
{
return a + b;
}
I did not add this to the regression as it very simple and there are many test 
cases in the regression which test this, for example
gcc.c-torture/execute/20090711-1.c and  gcc.c-torture/execute/20091229-1.c and 
so on.

Regression test is OK, tested with the following command:
make -k check-gcc RUNTESTFLAGS=--target_board=rl78-sim

Please let me know if this is OK, Thank you!
Sebastian



Index: gcc/ChangeLog
===
--- gcc/ChangeLog(revision 251091)
+++ gcc/ChangeLog(working copy)
@@ -1,3 +1,12 @@
+2017-08-14  Sebastian Perta  <sebastian.pe...@renesas.com>
+
+changed long long addition for RL78
+* gcc/config/rl78/rl78.c (rl78_emit_libcall): new function.
+* gcc/config/rl78/rl78-protos.h (rl78_emit_libcall): new function.
+* gcc/config/rl78/rl78.md: new define_expand "adddi3".
+* libgcc/config/rl78/adddi3.S: new assembly file.
+* libgcc/config/rl78/t-rl78: added adddi3.S to LIB2ADD.
+
 2017-08-14  Bin Cheng  <bin.ch...@arm.com>

 PR tree-optimization/81799
Index: gcc/config/rl78/rl78-protos.h
===
--- gcc/config/rl78/rl78-protos.h(revision 251091)
+++ gcc/config/rl78/rl78-protos.h(working copy)
@@ -56,3 +56,13 @@
 int, int, int);

 intrl78_one_far_p (rtx *operands, int num_operands);
+
+#ifdef RTX_CODE
+#ifdef HAVE_MACHINE_MODES
+
+rtx rl78_emit_libcall (const char*, enum rtx_code,
+   enum machine_mode, enum machine_mode,
+   int, rtx*);
+
+#endif
+#endif
Index: gcc/config/rl78/rl78.c
===
--- gcc/config/rl78/rl78.c(revision 251091)
+++ gcc/config/rl78/rl78.c(working copy)
@@ -4791,4 +4791,43 @@


 struct gcc_target targetm = TARGET_INITIALIZER;

+rtx
+rl78_emit_libcall (const char *name, enum rtx_code code,
+   enum machine_mode dmode, enum machine_mode smode,
+   int noperands, rtx *operands)
+{
+  rtx ret;
+  rtx_insn *insns;
+  rtx libcall;
+  rtx equiv;
+
+  start_sequence ();
+  libcall = gen_rtx_SYMBOL_REF (Pmode, name);
+
+  switch (noperands)
+{
+case 2:
+  ret = emit_library_call_value (libcall, NULL_RTX, LCT_CONST,
+ dmode, 1, operands[1], smode);
+  equiv = gen_rtx_fmt_e (code, dmode, operands[1]);
+  break;
+
+case 3:
+  ret = emit_library_call_value (libcall, NULL_RTX,
+ LCT_CONST, dmode, 2,
+ operands[1], smode, operands[2],
+ smode);
+  equiv = gen_rtx_fmt_ee (code, dmode, operands[1], operands[2]);
+  break;
+
+default:
+  gcc_unreachable ();
+}
+
+  insns = get_insns ();
+  end_sequence ();
+  emit_libcall_block (insns, operands[0], ret, equiv);
+  return ret;
+}
+
 #include "gt-rl78.h"
Index: gcc/config/rl78/rl78.md
===
--- gcc/config/rl78/rl78.md(revision 251091)
+++ gcc/config/rl78/rl78.md(working copy)
@@ -224,6 +224,16 @@
DONE;"
 )

+(define_expand "adddi3"
+ [(set (match_operand:DI  0 "nonimmediate_operand" "")
+(plus:DI (match_operand:DI 1 "general_operand"  "")
+ (match_operand:DI2 "general_operand"  "")))
+   ]
+  ""
+  "rl78_emit_libcall (\"__adddi3\", PLUS, DImode, DImode, 3, operands);
+   DONE;"
+)
+
 (define_insn "addsi3_internal_virt"
   [(set (match_operand:SI  0 "nonimmediate_operand" "=v,, vm")
 (plus:SI (match_operand:SI 1 "general_operand"  "0, vim, vim")
Index: libgcc/config/rl78/adddi3.S
===
--- libgcc/config/rl78/adddi3.S(nonexistent)
+++ libgcc/config/rl78/adddi3.S(working copy)
@@ -0,0 +1,58 @@
+;   Copyright (C) 2017 Free Software Foundation, Inc.
+;   Contributed by Sebastian Perta.
+;
+; This file is free software; you can redistribute it and/or modify it
+; under the terms of the GNU General Public License as published by the
+; Free Software Foundation; either version 3, or (at your option) any
+; later version.
+;
+; This file is distributed in the hope that it will be useful, but
+; WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+; General Public License f