[COMMITTED] Re: Re: [PATCH] RISC-V: Add an implicit dependency for Zawrs

[Xiao Zeng]

2024-09-30 14:32  Kito Cheng  wrote:
>
>LGTM, and let me know if you need my help to commit that :) 
Thank you, Kito. Recently, I received permission from Jeff.

>
>On Mon, Sep 30, 2024 at 9:37 AM Xiao Zeng  wrote:
>>
>> There is a description in 
>> <https://github.com/riscv/riscv-isa-manual/blob/main/src/zawrs.adoc>:
>>
>> "The instructions in the Zawrs extension are only useful in conjunction
>> with the LR instruction, which is provided by the Zalrsc component
>> of the A extension."
>>
>> It can be concluded that: zawrs -> zalrsc.
>>
>> gcc/ChangeLog:
>>
>> * common/config/riscv/riscv-common.cc: zawrs -> zalrsc.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/predef-38.c: New test.
>> * gcc.target/riscv/predef-39.c: New test.
>>
>> Signed-off-by: Xiao Zeng 
>> ---
>>  gcc/common/config/riscv/riscv-common.cc    |  1 +
>>  gcc/testsuite/gcc.target/riscv/predef-38.c | 31 ++
>>  gcc/testsuite/gcc.target/riscv/predef-39.c | 31 ++
>>  3 files changed, 63 insertions(+)
>>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-38.c
>>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-39.c
>>
>> diff --git a/gcc/common/config/riscv/riscv-common.cc 
>> b/gcc/common/config/riscv/riscv-common.cc
>> index bd42fd01532..a6abd903b98 100644
>> --- a/gcc/common/config/riscv/riscv-common.cc
>> +++ b/gcc/common/config/riscv/riscv-common.cc
>> @@ -96,6 +96,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
>>
>>    {"zabha", "zaamo"},
>>    {"zacas", "zaamo"},
>> +  {"zawrs", "zalrsc"},
>>
>>    {"zcmop", "zca"},
>>
>> diff --git a/gcc/testsuite/gcc.target/riscv/predef-38.c 
>> b/gcc/testsuite/gcc.target/riscv/predef-38.c
>> new file mode 100644
>> index 000..986c02b451a
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/predef-38.c
>> @@ -0,0 +1,31 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-O2 -march=rv32i_zawrs -mabi=ilp32 -mcmodel=medlow 
>> -misa-spec=20191213" } */
>> +
>> +int main () {
>> +
>> +#ifndef __riscv_arch_test
>> +#error "__riscv_arch_test"
>> +#endif
>> +
>> +#if __riscv_xlen != 32
>> +#error "__riscv_xlen"
>> +#endif
>> +
>> +#if !defined(__riscv_i)
>> +#error "__riscv_i"
>> +#endif
>> +
>> +#if !defined(__riscv_zawrs)
>> +#error "__riscv_zawrs"
>> +#endif
>> +
>> +#if !defined(__riscv_zalrsc)
>> +#error "__riscv_zalrsc"
>> +#endif
>> +
>> +#if defined(__riscv_a)
>> +#error "__riscv_a"
>> +#endif
>> +
>> +  return 0;
>> +}
>> diff --git a/gcc/testsuite/gcc.target/riscv/predef-39.c 
>> b/gcc/testsuite/gcc.target/riscv/predef-39.c
>> new file mode 100644
>> index 000..558164de8c4
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/predef-39.c
>> @@ -0,0 +1,31 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-O2 -march=rv64i_zawrs -mabi=lp64 -mcmodel=medlow 
>> -misa-spec=20191213" } */
>> +
>> +int main () {
>> +
>> +#ifndef __riscv_arch_test
>> +#error "__riscv_arch_test"
>> +#endif
>> +
>> +#if __riscv_xlen != 64
>> +#error "__riscv_xlen"
>> +#endif
>> +
>> +#if !defined(__riscv_i)
>> +#error "__riscv_i"
>> +#endif
>> +
>> +#if !defined(__riscv_zawrs)
>> +#error "__riscv_zawrs"
>> +#endif
>> +
>> +#if !defined(__riscv_zalrsc)
>> +#error "__riscv_zalrsc"
>> +#endif
>> +
>> +#if defined(__riscv_a)
>> +#error "__riscv_a"
>> +#endif
>> +
>> +  return 0;
>> +}
>> --
>> 2.17.1
>>
Thanks
Xiao Zeng

[PATCH] RISC-V: Add an implicit dependency for Zawrs

[Xiao Zeng]

There is a description in 
<https://github.com/riscv/riscv-isa-manual/blob/main/src/zawrs.adoc>:

"The instructions in the Zawrs extension are only useful in conjunction
with the LR instruction, which is provided by the Zalrsc component
of the A extension."

It can be concluded that: zawrs -> zalrsc.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: zawrs -> zalrsc.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-38.c: New test.
* gcc.target/riscv/predef-39.c: New test.

Signed-off-by: Xiao Zeng 
---
 gcc/common/config/riscv/riscv-common.cc|  1 +
 gcc/testsuite/gcc.target/riscv/predef-38.c | 31 ++
 gcc/testsuite/gcc.target/riscv/predef-39.c | 31 ++
 3 files changed, 63 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-38.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-39.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index bd42fd01532..a6abd903b98 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -96,6 +96,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
 
   {"zabha", "zaamo"},
   {"zacas", "zaamo"},
+  {"zawrs", "zalrsc"},
 
   {"zcmop", "zca"},
 
diff --git a/gcc/testsuite/gcc.target/riscv/predef-38.c 
b/gcc/testsuite/gcc.target/riscv/predef-38.c
new file mode 100644
index 000..986c02b451a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-38.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32i_zawrs -mabi=ilp32 -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 32
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_zawrs)
+#error "__riscv_zawrs"
+#endif
+
+#if !defined(__riscv_zalrsc)
+#error "__riscv_zalrsc"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-39.c 
b/gcc/testsuite/gcc.target/riscv/predef-39.c
new file mode 100644
index 000..558164de8c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-39.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64i_zawrs -mabi=lp64 -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_zawrs)
+#error "__riscv_zawrs"
+#endif
+
+#if !defined(__riscv_zalrsc)
+#error "__riscv_zalrsc"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+  return 0;
+}
-- 
2.17.1

Re: Re: [PATCH v2 1/1] RISC-V: Support BF16 interfaces in libgcc

[Xiao Zeng]

2024-08-13 15:53  Jakub Jelinek  wrote:
>
>On Tue, Aug 13, 2024 at 11:14:47AM +0800, Xiao Zeng wrote:
>> Thank you very much for the in-depth discussion between Jakub Jelinek and 
>> jeff.
>> My knowledge is narrow, and I am not familiar with architectures other than 
>> RISCV.
>> At the same time, my understanding of libraries such as libc and libm is 
>> also shallow.
>>
>> I spent some time sorting out my thoughts, which resulted in slow email 
>> replies. I am very sorry.
>
>The important thing is that the current state of BF16 support on other
>architectures is what we want there, not more.  So any changes done for
>RISCV shouldn't affect the other architectures, that wasn't the case of
>the patch you've posted.
>E.g. on x86_64, for FP16 we have:
>__divhc3@@GCC_12.0.0
>__eqhf2@@GCC_12.0.0
>__extendhfdf2@@GCC_12.0.0
>__extendhfsf2@@GCC_12.0.0
>__extendhftf2@@GCC_12.0.0
>__extendhfxf2@@GCC_12.0.0
>__fixhfti@@GCC_12.0.0
>__fixunshfti@@GCC_12.0.0
>__floatbitinthf@@GCC_14.0.0
>__floattihf@@GCC_12.0.0
>__floatuntihf@@GCC_12.0.0
>__mulhc3@@GCC_12.0.0
>__nehf2@@GCC_12.0.0
>__truncdfhf2@@GCC_12.0.0
>__trunchfbf2@@GCC_13.0.0
>__truncsfhf2@@GCC_12.0.0
>__trunctfhf2@@GCC_12.0.0
>__truncxfhf2@@GCC_12.0.0
>exported from libgcc, while for BF16 just:
>__extendbfsf2@@GCC_13.0.0
>__floatbitintbf@@GCC_14.0.0
>__floattibf@@GCC_13.0.0
>__floatuntibf@@GCC_13.0.0
>__truncdfbf2@@GCC_13.0.0
>__trunchfbf2@@GCC_13.0.0
>__truncsfbf2@@GCC_13.0.0
>__trunctfbf2@@GCC_13.0.0
>__truncxfbf2@@GCC_13.0.0
>More attention has been paid to what we actually need there, which is
>primarily conversions to/from other types (but even not to all of them, with
>some changes on the RTL expression lowering side to make sure we use the
>SFmode arithmetics as much as possible and only have the really required
>stuff on the libgcc side.
>We don't want to change that, if you really need __mulbc3/__divbc3 on RISCV,
>then it should be added for that arch only.  And similarly, the choice
>of the builtins on the compiler side, the two builtins we have right now is
>all we want on the other arches.  So, further builtins would be either a
>matter of RISCV specific builtins, or in generic code but guarded by some
>target hook so that they aren't enabled on arches which don't want them.
>On the libstdc++ side, the current headers provide for std::bfloat16_t and
>std::float16_t an implementation which uses SFmode calculations where
>possible, so stuff like:
>  constexpr _Float16
>  acos(_Float16 __x)
>  { return _Float16(__builtin_acosf(__x)); }
>or
>  constexpr __gnu_cxx::__bfloat16_t
>  acos(__gnu_cxx::__bfloat16_t __x)
>  { return __gnu_cxx::__bfloat16_t(__builtin_acosf(__x)); }
>And for printing, note there is
>_ZSt20__to_chars_float16_tPcS_fSt12chars_format@@GLIBCXX_3.4.31
>_ZSt21__to_chars_bfloat16_tPcS_fSt12chars_format@@GLIBCXX_3.4.31
>_ZSt22__from_chars_float16_tPKcS0_RfSt12chars_format@@GLIBCXX_3.4.31
>_ZSt23__from_chars_bfloat16_tPKcS0_RfSt12chars_format@@GLIBCXX_3.4.31
>which input and output _Float16 and __bf16, but in the parameter passing
>they expect those types to be promoted to float, so that the ABIs aren't
>dependent on when a particular arch enables those types.
>
>For RISCV, the things to consider are, what is the _Float16 and __bf16
>function argument passing/returning ABI?  Is the type enabled on all
>variants of RISCV, or just some (e.g. regarding _Float16 and __bf16
>on i686-linux, there is support for it only if the SSE2 ISA is available,
>so e.g. the *[hb][fc]* functions in libgcc need to be compiled with
>-msse2 extra flag)?  If it can be passed/returned the same in all ABIs,
>what excess precision mode do you want to use on them?  I mean e.g. the
>TARGET_C_EXCESS_PRECISION target hook.  On e.g. x86_64, the default
>is to promote all _Float16 and __bf16 calculations to float, so if you have
>__bf16 a, b, c, d, e;
>...
>a = b * c + d - e + c * d;
>all variables are converted to SFmode temporaries and all the arithmetics
>is done in SFmode and only then at the end finally converted to HFmode
>or BFmode.  One can request a different mode, -fexcess-precision=16
>in which such promotion isn't done, but as there is no hw support for
>most of the operations, the actual multiplication, addition or subtraction
>is still done in SFmode, just there is a conversion to BFmode after each
>operation (so slower, but more precise).
>If you still want to export __divbc3 and __mulbc3, do you want to export
>those just on some RISCV ABI variants or all of them?  Depending on that,
>arrange for those to be compiled just for those; and, if it is exported
>from libgcc_s.so.1, you also need to add a sy

Re: Re: [PATCH v2 1/1] RISC-V: Support BF16 interfaces in libgcc

[Xiao Zeng]

2024-08-07 23:15  Jeff Law  wrote:
>
>
>
>On 8/7/24 8:55 AM, Jakub Jelinek wrote:
>> On Wed, Aug 07, 2024 at 08:46:11AM -0600, Jeff Law wrote:
>>>
>>>
>>> On 8/7/24 1:16 AM, Jakub Jelinek wrote:
>>>
>>>>
>>>> This looks all wrong to me.
>>>>
>>>> On all the other targets that already do support __bf16 type it is a 
>>>> storage
>>>> only type, so all arithmetics on it is expected to be done on float, not in
>>>> __bf16.
>>> RISC-V has (via extensions) degrees of arithmetic/conversion support, so for
>>> example it can do a multiply-add of bf16 operands widening to float.
>>
>> Even the __builtin_*f16 _Float16 builtins are mostly unused (at least on
>> other targets), but there those functions are at least part of C23, even
>> when they are really not implemented yet in libm (at least talking about
>> glibc, but I doubt other C libraries are any further than that).
>> For __bf16, the only standard required stuff is in C++23 and the provided
>> builtins are whatever was necessary for that.
>>
>> I understand RISC-V has via extensions more full _Float16 and __bf16
>> support, but if it needs further builtins, the questions are:
>> 1) should they be enabled on all arches or just on those that need them?
>I'd tend to take a wait and see approach, meaning start when them as
>target builtins and promote them to generic builtins if we see other
>targets implementing a richer set of bf16 operations.
>
>> 2) is there plan to add libm support for __bf16, even when it is
>> non-standard in C (especially if we don't know if C2y or newer will or won't
>> add support for it and if it will use the chosen suffixes or some others)?
> > 3) is there plan to add variants for C++23  and 
>etc.> to handle _Float16 and __bf16 differently?  Currently those types
>are just
>> handled by doing as much as possible on float, using its builtins
>I have no idea on either of these questions.
>
>jeff

Thank you very much for the in-depth discussion between Jakub Jelinek and jeff.
My knowledge is narrow, and I am not familiar with architectures other than 
RISCV.
At the same time, my understanding of libraries such as libc and libm is also 
shallow.

I spent some time sorting out my thoughts, which resulted in slow email 
replies. I am very sorry.

1 BF16 is a 16 bit floating-point data type that differs only in encoding from 
FP16, but is otherwise the same.

2 BF16 can be used by any architecture, just like FP16.

3 libgcc provides interface functions related to floating-point types, such as 
__mulsc3/__divsc3.

4 There is test case:

typedef _Complex float __cbf16 __attribute__((__mode__(__BC__)));
__cbf16 cbf16;
__cbf16 cbf16_1;
__cbf16 cbf16_2;
__cbf16 cbf16_mul_cbf16() { cbf16 = cbf16_1 * cbf16_2; }
__cbf16 cbf16_div_cbf16() { cbf16 = cbf16_1 / cbf16_2; }


4.1 Riscv architecture, -march=rv64imafdcv_zvfh -mabi=lp64d -O2. After 
compilation, the resulting assembly will include:

call__mulbc3
call__divbc3

Due to the absence of the __mulbc3/__divbc3 interface in libgcc, this can 
result in link errors.

4.2 Riscv architecture, -march=rv64imafdcv -mabi=lp64d -O2 After compilation, 
the resulting assembly will include:

call__mulsc3
call__divsc3

Due to the presence of the __mulsc3/__divsc3 interface in libgcc, it can be 
linked normally.

4.3 x86_64 architecture, the results obtained after testing are the same as the 
Riscv architecture in 4.2, that is:

a) bf16 -> fp32
b) calls the corresponding complex interfaces __mulsc3/__divsc3


At the beginning, I had planned to only add the __mulbc3/__divbc3 interface in 
libgcc.
After exploration, it was found that libgcc already has a complete 
infrastructure, and adding
only the __mulbc3/__divbc3 interfaces would cause a lot of trouble.
In this context, it was decided to add a new data type BF16 to the 
infrastructure of libgcc, similar to FP16.

Perhaps I can get some suggestions to complete the addition of 
__mulbc3/__divbc3 and eliminate errors when linking.

Thanks
Xiao Zeng

Re: [PATCH v2 1/1] RISC-V: Support BF16 interfaces in libgcc

[Xiao Zeng]

2024-08-07 11:13  Xiao Zeng  wrote: 

The existing test cases 'gcc.dg/portal/float16 complex.c' for gcc are
already good, so no new test cases were added.

Of course, more test cases are always good, and if necessary, I will
supplement the test cases.
>
>gcc/ChangeLog:
>
>   * builtin-types.def (BT_COMPLEX_BFLOAT16): Support BF16 node.
>   (BT_BFLOAT16_PTR): Ditto.
>   (BT_FN_BFLOAT16): New.
>   (BT_FN_BFLOAT16_BFLOAT16): Ditto.
>   (BT_FN_COMPLEX_BFLOAT16_COMPLEX_BFLOAT16): Ditto.
>   (BT_FN_BFLOAT16_COMPLEX_BFLOAT16): Ditto.
>   (BT_FN_INT_BFLOAT16): Ditto.
>   (BT_FN_LONG_BFLOAT16): Ditto.
>   (BT_FN_LONGLONG_BFLOAT16): Ditto.
>   (BT_FN_BFLOAT16_BFLOAT16_BFLOAT16PTR): Ditto.
>   (BT_FN_BFLOAT16_BFLOAT16_INT): Ditto.
>   (BT_FN_BFLOAT16_BFLOAT16_INTPTR): Ditto.
>   (BT_FN_BFLOAT16_BFLOAT16_LONG): Ditto.
>   (BT_FN_COMPLEX_BFLOAT16_COMPLEX_BFLOAT16_COMPLEX_BFLOAT16): Ditto.
>   (BT_FN_BFLOAT16_BFLOAT16_BFLOAT16_BFLOAT16): Ditto.
>   (BT_FN_BFLOAT16_BFLOAT16_BFLOAT16_INTPTR): Ditto.
>   * builtins.cc (expand_builtin_classify_type): Support BF16.
>   (mathfn_built_in_2): Ditto.
>   (CASE_MATHFN_FLOATN): Ditto.
>   * builtins.def (DEF_GCC_FLOATN_NX_BUILTINS): Ditto.
>   (DEF_EXT_LIB_FLOATN_NX_BUILTINS): Ditto.
>   (BUILT_IN_NANSF16B): Added in general processing, redundant
>   is removed here.
>   (BUILT_IN_NEXTAFTERF16B): Ditto.
>   * fold-const-call.cc (fold_const_call): Ditto.
>   (fold_const_call_sss): Ditto.
>   * gencfn-macros.cc: Support BF16.
>   * match.pd: Like FP16, add optimization for BF16.
>   * tree.h (CASE_FLT_FN_FLOATN_NX): Support BF16.
>
>gcc/c-family/ChangeLog:
>
>   * c-cppbuiltin.cc (c_cpp_builtins): Modify suffix names to avoid
>   conflicts.
>
>libgcc/ChangeLog:
>
>   * Makefile.in: Add _mulbc3 and _divbc3.
>   * libgcc2.c (if): Ditto.
>   (defined): Ditto.
>   (MTYPE): Macros defined for BF16.
>   (CTYPE): Ditto.
>   (AMTYPE): Ditto.
>   (MODE): Ditto.
>   (CEXT): Ditto.
>   (NOTRUNC): Ditto.
>   * libgcc2.h (LIBGCC2_HAS_BF_MODE): Support BF16.
>   (__attribute__): Ditto.
>   (__divbc3): Add __divbc3 declaration.
>   (__mulbc3): Add __mulbc3 declaration.
>
>Signed-off-by: Xiao Zeng 
>---
> gcc/builtin-types.def    | 30 ++
> gcc/builtins.cc  |  6 ++
> gcc/builtins.def | 22 +++---
> gcc/c-family/c-cppbuiltin.cc |  2 +-
> gcc/fold-const-call.cc   |  2 --
> gcc/gencfn-macros.cc |  5 +++--
> gcc/match.pd |  9 ++---
> gcc/tree.h   |  2 +-
> libgcc/Makefile.in   |  6 +++---
> libgcc/libgcc2.c | 20 ++--
> libgcc/libgcc2.h | 14 ++
> 11 files changed, 89 insertions(+), 29 deletions(-)
>
>diff --git a/gcc/builtin-types.def b/gcc/builtin-types.def
>index c97d6bad1de..6980873f2f1 100644
>--- a/gcc/builtin-types.def
>+++ b/gcc/builtin-types.def
>@@ -109,6 +109,10 @@ DEF_PRIMITIVE_TYPE (BT_FLOAT128X, (float128x_type_node
> DEF_PRIMITIVE_TYPE (BT_COMPLEX_FLOAT, complex_float_type_node)
> DEF_PRIMITIVE_TYPE (BT_COMPLEX_DOUBLE, complex_double_type_node)
> DEF_PRIMITIVE_TYPE (BT_COMPLEX_LONGDOUBLE, complex_long_double_type_node)
>+DEF_PRIMITIVE_TYPE (BT_COMPLEX_BFLOAT16, (bfloat16_type_node
>+  ? build_complex_type
>+  (bfloat16_type_node)
>+  : error_mark_node))
> DEF_PRIMITIVE_TYPE (BT_COMPLEX_FLOAT16, (float16_type_node
> ? build_complex_type
> (float16_type_node)
>@@ -163,6 +167,9 @@ DEF_PRIMITIVE_TYPE (BT_CONST_DOUBLE_PTR,
>  (build_qualified_type (double_type_node,
>      TYPE_QUAL_CONST)))
> DEF_PRIMITIVE_TYPE (BT_LONGDOUBLE_PTR, long_double_ptr_type_node)
>+DEF_PRIMITIVE_TYPE (BT_BFLOAT16_PTR, (bfloat16_type_node
>+    ? build_pointer_type (bfloat16_type_node)
>+    : error_mark_node))
> DEF_PRIMITIVE_TYPE (BT_FLOAT16_PTR, (float16_type_node
>   ? build_pointer_type (float16_type_node)
>   : error_mark_node))
>@@ -239,6 +246,7 @@ DEF_FUNCTION_TYPE_0 (BT_FN_DOUBLE, BT_DOUBLE)
>    distinguish it from two types in sequence, "long" followed by
>    "double".  */
> DEF_FUNCTION_TYPE_0 (BT_FN_LONGDOUBLE, BT_LONGDOUBLE)
>+DEF_FUNCTION_TYPE_0 (BT_FN_BFLOAT16, BT_BFLOAT16)
> DEF_FUNCTION_TYPE_0 (BT_FN_FLOAT16, BT_FLOAT16)
> DEF_FUNCTION_TYPE_0 (BT_FN_FLOAT32, BT_FLOAT32)
> DEF_FUNCTION_TYPE_0 (BT_FN_FLOAT64, BT_FLOAT64)
>@@ -257,6 +265,7 @@ DEF_FUNCTION_TYPE_1 (BT_FN_FLOAT_FLOAT, BT_FLOAT, BT_FLOAT)
> DEF_FUNCTION_TYPE_1 (BT_FN_DOUBLE_DOUBLE, BT_D

[PATCH v2 1/1] RISC-V: Support BF16 interfaces in libgcc

[Xiao Zeng]

gcc/ChangeLog:

* builtin-types.def (BT_COMPLEX_BFLOAT16): Support BF16 node.
(BT_BFLOAT16_PTR): Ditto.
(BT_FN_BFLOAT16): New.
(BT_FN_BFLOAT16_BFLOAT16): Ditto.
(BT_FN_COMPLEX_BFLOAT16_COMPLEX_BFLOAT16): Ditto.
(BT_FN_BFLOAT16_COMPLEX_BFLOAT16): Ditto.
(BT_FN_INT_BFLOAT16): Ditto.
(BT_FN_LONG_BFLOAT16): Ditto.
(BT_FN_LONGLONG_BFLOAT16): Ditto.
(BT_FN_BFLOAT16_BFLOAT16_BFLOAT16PTR): Ditto.
(BT_FN_BFLOAT16_BFLOAT16_INT): Ditto.
(BT_FN_BFLOAT16_BFLOAT16_INTPTR): Ditto.
(BT_FN_BFLOAT16_BFLOAT16_LONG): Ditto.
(BT_FN_COMPLEX_BFLOAT16_COMPLEX_BFLOAT16_COMPLEX_BFLOAT16): Ditto.
(BT_FN_BFLOAT16_BFLOAT16_BFLOAT16_BFLOAT16): Ditto.
(BT_FN_BFLOAT16_BFLOAT16_BFLOAT16_INTPTR): Ditto.
* builtins.cc (expand_builtin_classify_type): Support BF16.
(mathfn_built_in_2): Ditto.
(CASE_MATHFN_FLOATN): Ditto.
* builtins.def (DEF_GCC_FLOATN_NX_BUILTINS): Ditto.
(DEF_EXT_LIB_FLOATN_NX_BUILTINS): Ditto.
(BUILT_IN_NANSF16B): Added in general processing, redundant
is removed here.
(BUILT_IN_NEXTAFTERF16B): Ditto.
* fold-const-call.cc (fold_const_call): Ditto.
(fold_const_call_sss): Ditto.
* gencfn-macros.cc: Support BF16.
* match.pd: Like FP16, add optimization for BF16.
* tree.h (CASE_FLT_FN_FLOATN_NX): Support BF16.

gcc/c-family/ChangeLog:

* c-cppbuiltin.cc (c_cpp_builtins): Modify suffix names to avoid
conflicts.

libgcc/ChangeLog:

* Makefile.in: Add _mulbc3 and _divbc3.
* libgcc2.c (if): Ditto.
(defined): Ditto.
(MTYPE): Macros defined for BF16.
(CTYPE): Ditto.
(AMTYPE): Ditto.
(MODE): Ditto.
(CEXT): Ditto.
(NOTRUNC): Ditto.
* libgcc2.h (LIBGCC2_HAS_BF_MODE): Support BF16.
(__attribute__): Ditto.
(__divbc3): Add __divbc3 declaration.
(__mulbc3): Add __mulbc3 declaration.

Signed-off-by: Xiao Zeng 
---
 gcc/builtin-types.def| 30 ++
 gcc/builtins.cc  |  6 ++
 gcc/builtins.def | 22 +++---
 gcc/c-family/c-cppbuiltin.cc |  2 +-
 gcc/fold-const-call.cc   |  2 --
 gcc/gencfn-macros.cc |  5 +++--
 gcc/match.pd |  9 ++---
 gcc/tree.h   |  2 +-
 libgcc/Makefile.in   |  6 +++---
 libgcc/libgcc2.c | 20 ++--
 libgcc/libgcc2.h | 14 ++
 11 files changed, 89 insertions(+), 29 deletions(-)

diff --git a/gcc/builtin-types.def b/gcc/builtin-types.def
index c97d6bad1de..6980873f2f1 100644
--- a/gcc/builtin-types.def
+++ b/gcc/builtin-types.def
@@ -109,6 +109,10 @@ DEF_PRIMITIVE_TYPE (BT_FLOAT128X, (float128x_type_node
 DEF_PRIMITIVE_TYPE (BT_COMPLEX_FLOAT, complex_float_type_node)
 DEF_PRIMITIVE_TYPE (BT_COMPLEX_DOUBLE, complex_double_type_node)
 DEF_PRIMITIVE_TYPE (BT_COMPLEX_LONGDOUBLE, complex_long_double_type_node)
+DEF_PRIMITIVE_TYPE (BT_COMPLEX_BFLOAT16, (bfloat16_type_node
+? build_complex_type
+   (bfloat16_type_node)
+: error_mark_node))
 DEF_PRIMITIVE_TYPE (BT_COMPLEX_FLOAT16, (float16_type_node
 ? build_complex_type
(float16_type_node)
@@ -163,6 +167,9 @@ DEF_PRIMITIVE_TYPE (BT_CONST_DOUBLE_PTR,
 (build_qualified_type (double_type_node,
TYPE_QUAL_CONST)))
 DEF_PRIMITIVE_TYPE (BT_LONGDOUBLE_PTR, long_double_ptr_type_node)
+DEF_PRIMITIVE_TYPE (BT_BFLOAT16_PTR, (bfloat16_type_node
+ ? build_pointer_type (bfloat16_type_node)
+ : error_mark_node))
 DEF_PRIMITIVE_TYPE (BT_FLOAT16_PTR, (float16_type_node
  ? build_pointer_type (float16_type_node)
  : error_mark_node))
@@ -239,6 +246,7 @@ DEF_FUNCTION_TYPE_0 (BT_FN_DOUBLE, BT_DOUBLE)
distinguish it from two types in sequence, "long" followed by
"double".  */
 DEF_FUNCTION_TYPE_0 (BT_FN_LONGDOUBLE, BT_LONGDOUBLE)
+DEF_FUNCTION_TYPE_0 (BT_FN_BFLOAT16, BT_BFLOAT16)
 DEF_FUNCTION_TYPE_0 (BT_FN_FLOAT16, BT_FLOAT16)
 DEF_FUNCTION_TYPE_0 (BT_FN_FLOAT32, BT_FLOAT32)
 DEF_FUNCTION_TYPE_0 (BT_FN_FLOAT64, BT_FLOAT64)
@@ -257,6 +265,7 @@ DEF_FUNCTION_TYPE_1 (BT_FN_FLOAT_FLOAT, BT_FLOAT, BT_FLOAT)
 DEF_FUNCTION_TYPE_1 (BT_FN_DOUBLE_DOUBLE, BT_DOUBLE, BT_DOUBLE)
 DEF_FUNCTION_TYPE_1 (BT_FN_LONGDOUBLE_LONGDOUBLE,
 BT_LONGDOUBLE, BT_LONGDOUBLE)
+DEF_FUNCTION_TYPE_1 (BT_FN_BFLOAT16_BFLOAT16, BT_BFLOAT16, BT_BFLOAT16)
 DEF_FUNCTION_TYPE_1 (BT_FN_FLOAT16_FLOAT16, BT_FLOAT16, BT_FLOAT16)
 DEF_FUNCTION_TYPE_1 (BT_FN_FLOAT32

[PATCH v2 0/1] RISC-V: Support BF16 interfaces in libgcc

[Xiao Zeng]

1 Why should bf16 be modified to f16b?
--
diff --git a/gcc/c-family/c-cppbuiltin.cc b/gcc/c-family/c-cppbuiltin.cc
index a80372c8991..273bb9cf028 100644
--- a/gcc/c-family/c-cppbuiltin.cc
+++ b/gcc/c-family/c-cppbuiltin.cc
@@ -1422,7 +1422,7 @@ c_cpp_builtins (cpp_reader *pfile)
  else if (bfloat16_type_node
   && mode == TYPE_MODE (bfloat16_type_node))
{
- memcpy (suffix, "bf16", 5);
+ memcpy (suffix, "f16b", 5);
  memcpy (float_h_prefix, "BFLT16", 7);
}
  else
--
  

There is such code:
--
DEF_C99_BUILTIN(BUILT_IN_LOGB, "logb", BT_FN_DOUBLE_DOUBLE, 
ATTR_MATHFN_FPROUNDING_ERRNO)
DEF_C99_BUILTIN(BUILT_IN_LOGBF, "logbf", BT_FN_FLOAT_FLOAT, 
ATTR_MATHFN_FPROUNDING_ERRNO)
--
bf16 and f16 will conflict when expanded, but f16b and f16 will not.

The previous code also used the symbol f16b:
--
-DEF_GCC_BUILTIN(BUILT_IN_NANSF16B, "nansf16b", 
BT_FN_BFLOAT16_CONST_STRING, ATTR_CONST_NOTHROW_NONNULL)
-DEF_GCC_BUILTIN(BUILT_IN_NEXTAFTERF16B, "nextafterf16b", 
BT_FN_BFLOAT16_BFLOAT16_BFLOAT16, ATTR_MATHFN_ERRNO)
--

2 Why should BUILT_IN_NANSF16B and BUILT_IN_NEXTAFTERF16B be deleted? 
--
-DEF_GCC_BUILTIN(BUILT_IN_NANSF16B, "nansf16b", 
BT_FN_BFLOAT16_CONST_STRING, ATTR_CONST_NOTHROW_NONNULL)
-DEF_GCC_BUILTIN(BUILT_IN_NEXTAFTERF16B, "nextafterf16b", 
BT_FN_BFLOAT16_BFLOAT16_BFLOAT16, ATTR_MATHFN_ERRNO)
--

In the general macro definition, it has already been processed to remove 
redundant code.
--
 #define DEF_GCC_FLOATN_NX_BUILTINS(ENUM, NAME, TYPE_MACRO, ATTRS)  \
+  DEF_GCC_BUILTIN (ENUM ## F16B, NAME "f16b", TYPE_MACRO (BFLOAT16), ATTRS) \
   DEF_GCC_BUILTIN (ENUM ## F16, NAME "f16", TYPE_MACRO (FLOAT16), ATTRS) \
   DEF_GCC_BUILTIN (ENUM ## F32, NAME "f32", TYPE_MACRO (FLOAT32), ATTRS) \
   DEF_GCC_BUILTIN (ENUM ## F64, NAME "f64", TYPE_MACRO (FLOAT64), ATTRS) \

// and
 #define DEF_EXT_LIB_FLOATN_NX_BUILTINS(ENUM, NAME, TYPE_MACRO, ATTRS)  \
+  DEF_FLOATN_BUILTIN (ENUM ## F16B, NAME "f16b", TYPE_MACRO (BFLOAT16), ATTRS) 
\
   DEF_FLOATN_BUILTIN (ENUM ## F16, NAME "f16", TYPE_MACRO (FLOAT16), ATTRS) \
   DEF_FLOATN_BUILTIN (ENUM ## F32, NAME "f32", TYPE_MACRO (FLOAT32), ATTRS) \
   DEF_FLOATN_BUILTIN (ENUM ## F64, NAME "f64", TYPE_MACRO (FLOAT64), ATTRS) \
--

3 This modification will have an impact on all architectures that support BF16.

I have completed the following tests:
x86_64 bootstrap based on 18eb6ca136fcd22b381d222cab81265d812ea7b9 passed.
riscv64 bootstrap based on a59c4e496fa916cb9a484a649aa1b4cebd6550f2 passed.
The riscv64 regression passed.
   

Xiao Zeng (1):
  RISC-V: Support BF16 interfaces in libgcc

 gcc/builtin-types.def| 30 ++
 gcc/builtins.cc  |  6 ++
 gcc/builtins.def | 22 +++---
 gcc/c-family/c-cppbuiltin.cc |  2 +-
 gcc/fold-const-call.cc   |  2 --
 gcc/gencfn-macros.cc |  5 +++--
 gcc/match.pd |  9 ++---
 gcc/tree.h   |  2 +-
 libgcc/Makefile.in   |  6 +++---
 libgcc/libgcc2.c | 20 ++--
 libgcc/libgcc2.h | 14 ++
 11 files changed, 89 insertions(+), 29 deletions(-)

-- 
2.43.0

Re: Re: [PATCH] RISC-V: Minimal support for Zimop extension.

[Xiao Zeng]

2024-08-05 23:21  Jiawei  wrote:
>
>
>在 2024/8/5 22:15, Jeff Law 写道:
>>
>>
>> On 8/4/24 8:20 PM, Jiawei wrote:
>>>
>>> 在 2024/8/5 8:45, Jeff Law 写道:
>>>>
>>>>
>>>> On 8/2/24 9:32 AM, Jiawei wrote:
>>>>> https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc
>>>>>
>>>>> gcc/ChangeLog:
>>>>>
>>>>> * common/config/riscv/riscv-common.cc: New extension.
>>>>> * config/riscv/riscv.opt: New mask.
>>>>>
>>>>> gcc/testsuite/ChangeLog:
>>>>>
>>>>> * gcc.target/riscv/arch-42.c: New test.
>>>>> * gcc.target/riscv/arch-43.c: New test.
>>>> Shouldn't the binutils bits go in first?  There's basic support for
>>>> Zimop/Zcmop from Lyut on the binutils list in late 2023 or early
>>>> 2024. I'm pretty sure it marked as DO NOT MERGE because we were
>>>> waiting for the extension to get ratified.
>>>
>>> Christoph informed me that Zimop has been ratified, so we may not
>>> need to worry about the spec lifecycle status:
>>>
>>> https://jira.riscv.org/browse/RVS-1603?src=confmacro
>> Agreed.  No concerns about spec lifecycle at this point.
>>
>>>
>>>>
>>>> I don't know if Lyut is doing any RISC-V work right now, so if you
>>>> wanted to ping the patch on his behalf, it'd be appreciated and I
>>>> can handle the review on the binutils side too.
>>>
>>> I found that ESWIN's patch to support Zimop on the binutils mailing
>>> list last month:
>>>
>>> https://sourceware.org/pipermail/binutils/2024-June/134592.html
>> I don't watch binutils as closely as perhaps I should.
>>
>> That patch looks marginally better than Lyut's version.  It has the
>> updated version #s for the spec and handles the implied extensions.
>> Let's go with Xiao's version.
>>
>> Xiao, the Zimop/Zcmop patches are OK for binutils.
>>
>> Jiawei, the GCC patches are OK once Xiao pushes his changes to the
>> binutils repo.  Alternately if you have permissions in the binutils
>> repo, you can push them for Xiao.
>>
>> Jeff
>
>Thanks Jeff! I think I do not have the permissions in the binutils repo,
>let me contact Nelson to ask him give  some help. 
I am glad that the patch previously submitted can still be discussed and may be 
accepted.

If you have any questions, please feel free to contact me.
>
>
>BR,
>
>Jiawei
Thanks
Xiao Zeng

[COMMITTED] Re: Re: [PATCH] RISC-V: NFC: Do not use zicond for pr105314 testcases

[Xiao Zeng]

2024-08-01 09:53  Jeff Law  wrote:
>
>
>
>On 7/30/24 7:05 PM, Xiao Zeng wrote:
>> 2024-07-31 03:10  Jeff Law  wrote:
>>>
>>>
>>>
>>> On 7/28/24 7:58 PM, Xiao Zeng wrote:
>>>> gcc/testsuite/ChangeLog:
>>>>
>>>>    * gcc.target/riscv/pr105314-rtl.c: Skip zicond.
>>>>    * gcc.target/riscv/pr105314-rtl32.c: Dotto.
>>>>    * gcc.target/riscv/pr105314.c: Dotto.
>>> Why do you want to skip zicond for this test?
>> Yes, I should provide as detailed a description as possible for each 
>> submitted patch.
>>>
>>> Jeff
>> riscv64-unknown-linux-gnu-gcc  -O2 -march=rv64gc_zicond -mabi=lp64d 
>> ../gcc/testsuite/gcc.target/riscv/pr105314.c -fdump-rtl-ce1 -S -o 
>> pr105314.c.S
>>
>> This output will be obtained:
>[ ... ]
>Thanks.  That's exactly what I needed. 
Yes, patches may appear more straightforward in the eyes of the submitter.
But sometimes it's difficult for people without backgrounds to understand.

Providing detailed explanations may benefit everyone.
>
>This is fine for the trunk, though please fix the typo in your
>ChangeLog.  It's spelled "Ditto" rather than "Dotto". 
After fixing this spelling error, push to the trunk.

>
>jeff
Thanks
Xiao Zeng

Re: Re: [PATCH] RISC-V: NFC: Do not use zicond for pr105314 testcases

[Xiao Zeng]

2024-07-31 03:10  Jeff Law  wrote:
>
>
>
>On 7/28/24 7:58 PM, Xiao Zeng wrote:
>> gcc/testsuite/ChangeLog:
>>
>>  * gcc.target/riscv/pr105314-rtl.c: Skip zicond.
>>  * gcc.target/riscv/pr105314-rtl32.c: Dotto.
>>  * gcc.target/riscv/pr105314.c: Dotto.
>Why do you want to skip zicond for this test? 
Yes, I should provide as detailed a description as possible for each submitted 
patch.
>
>Jeff 
riscv64-unknown-linux-gnu-gcc  -O2 -march=rv64gc_zicond -mabi=lp64d 
../gcc/testsuite/gcc.target/riscv/pr105314.c -fdump-rtl-ce1 -S -o pr105314.c.S

This output will be obtained:


;; Function foo (foo, funcdef_no=0, decl_uid=2299, cgraph_uid=1, symbol_order=0)

0 registers.

6 basic blocks, 6 edges.

(note 8 0 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 2 8 4 2 (set (reg/v:DI 135 [ a ])
        (reg:DI 10 a0 [ a ])) 
"../gcc/testsuite/gcc.target/riscv/pr105314.c":8:1 275 {*movdi_64bit}
     (expr_list:REG_DEAD (reg:DI 10 a0 [ a ])
        (nil)))
(insn 4 2 5 2 (set (reg/v:DI 137 [ c ])
        (reg:DI 12 a2 [ c ])) 
"../gcc/testsuite/gcc.target/riscv/pr105314.c":8:1 275 {*movdi_64bit}
     (expr_list:REG_DEAD (reg:DI 12 a2 [ c ])
        (nil)))
(note 5 4 10 2 NOTE_INSN_FUNCTION_BEG)
(jump_insn 10 5 11 2 (set (pc)
        (if_then_else (ne (reg/v:DI 137 [ c ])
                (const_int 0 [0]))
            (label_ref:DI 23)
            (pc))) "../gcc/testsuite/gcc.target/riscv/pr105314.c":9:6 352 
{*branchdi}
     (expr_list:REG_DEAD (reg/v:DI 137 [ c ])
        (int_list:REG_BR_PROB 536870916 (nil)))
 -> 23)

(note 11 10 6 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 6 11 23 3 (set (reg/v:DI 134 [  ])
        (reg/v:DI 135 [ a ])) 
"../gcc/testsuite/gcc.target/riscv/pr105314.c":9:6 275 {*movdi_64bit}
     (expr_list:REG_DEAD (reg/v:DI 135 [ a ])
        (nil)))

(code_label 23 6 22 4 3 (nil) [1 uses])
(note 22 23 7 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 7 22 16 4 (set (reg/v:DI 134 [  ])
        (const_int 0 [0])) "../gcc/testsuite/gcc.target/riscv/pr105314.c":10:7 
275 {*movdi_64bit}
     (nil))

(code_label 16 7 19 5 1 (nil) [0 uses])
(note 19 16 17 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(insn 17 19 18 5 (set (reg/i:DI 10 a0)
        (reg/v:DI 134 [  ])) 
"../gcc/testsuite/gcc.target/riscv/pr105314.c":12:1 275 {*movdi_64bit}
     (expr_list:REG_DEAD (reg/v:DI 134 [  ])
        (nil)))
(insn 18 17 0 5 (use (reg/i:DI 10 a0)) 
"../gcc/testsuite/gcc.target/riscv/pr105314.c":12:1 -1
     (nil))





try_optimize_cfg iteration 1

;; 1 loops found
;;
;; Loop 0
;;  header 0, latch 1
;;  depth 0, outer -1
;;  nodes: 0 1 2 3 4 5
;; 2 succs { 4 3 }
;; 3 succs { 5 }
;; 4 succs { 5 }
;; 5 succs { 1 }
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called

IF-THEN-ELSE-JOIN block found, pass 1, test 2, then 3, else 4, join 5
scanning new insn with uid = 25.
if-conversion succeeded through noce_try_cmove
deleting insn with uid = 7.
deleting block 4
Removing jump 10.
deleting insn with uid = 10.
deleting insn with uid = 6.
deleting block 3
Merging block 5 into block 2...
changing bb of uid 19
changing bb of uid 17
  from 5 to 2
changing bb of uid 18
  from 5 to 2
Merged blocks 2 and 5.
Conversion succeeded on pass 1.


foo

Dataflow summary:
;;  fully invalidated by EH  0 [zero] 1 [ra] 3 [gp] 4 [tp] 5 [t0] 6 [t1] 7 
[t2] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 14 [a4] 15 [a5] 16 [a6] 17 [a7] 28 [t3] 29 
[t4] 30 [t5] 31 [t6] 32 [ft0] 33 [ft1] 34 [ft2] 35 [ft3] 36 [ft4] 37 [ft5] 38 
[ft6] 39 [ft7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47 [fa5] 48 [fa6] 
49 [fa7] 60 [ft8] 61 [ft9] 62 [ft10] 63 [ft11] 66 [vl] 67 [vtype] 68 [vxrm] 69 
[frm] 70 [vxsat] 71 [N/A] 72 [N/A] 73 [N/A] 74 [N/A] 75 [N/A] 76 [N/A] 77 [N/A] 
78 [N/A] 79 [N/A] 80 [N/A] 81 [N/A] 82 [N/A] 83 [N/A] 84 [N/A] 85 [N/A] 86 
[N/A] 87 [N/A] 88 [N/A] 89 [N/A] 90 [N/A] 91 [N/A] 92 [N/A] 93 [N/A] 94 [N/A] 
95 [N/A] 96 [v0] 97 [v1] 98 [v2] 99 [v3] 100 [v4] 101 [v5] 102 [v6] 103 [v7] 
104 [v8] 105 [v9] 106 [v10] 107 [v11] 108 [v12] 109 [v13] 110 [v14] 111 [v15] 
112 [v16] 113 [v17] 114 [v18] 115 [v19] 116 [v20] 117 [v21] 118 [v22] 119 [v23] 
120 [v24] 121 [v25] 122 [v26] 123 [v27] 124 [v28] 125 [v29] 126 [v30] 127 [v31]
;;  hardware regs used   2 [sp] 64 [arg] 65 [frame]
;;  regular block artificial uses2 [sp] 8 [s0] 64 [arg] 65 [frame]
;;  eh block artificial uses 2 [sp] 8 [s0] 64 [arg] 65 [frame]
;;  entry block defs 1 [ra] 2 [sp] 8 [s0] 10 [a0] 11 [a1] 12 [a2] 13 [a3] 
14 [a4] 15 [a5] 16 [a6] 17 [a7] 42 [fa0] 43 [fa1] 44 [fa2] 45 [fa3] 46 [fa4] 47 
[fa5] 48 [fa6] 49 [fa7] 64 [arg] 65 [frame]
;;  exit block uses  1 [ra] 2 [sp] 8 [s0] 10 [a0] 65 [frame]
;;  regs ever live   10 [a0] 12 [a2]
;;  ref usage   r1={

[PATCH] RISC-V: NFC: Do not use zicond for pr105314 testcases

[Xiao Zeng]

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr105314-rtl.c: Skip zicond.
* gcc.target/riscv/pr105314-rtl32.c: Dotto.
* gcc.target/riscv/pr105314.c: Dotto.

Signed-off-by: Xiao Zeng 
---
 gcc/testsuite/gcc.target/riscv/pr105314-rtl.c   | 2 +-
 gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c | 2 +-
 gcc/testsuite/gcc.target/riscv/pr105314.c   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c 
b/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c
index 693291f4dbd..570918f9d9a 100644
--- a/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c
+++ b/gcc/testsuite/gcc.target/riscv/pr105314-rtl.c
@@ -1,7 +1,7 @@
 /* PR rtl-optimization/105314 */
 /* { dg-do compile } */
 /* { dg-require-effective-target rv64 } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-flto" } } */
+/* { dg-skip-if "" { *-*-* } { "-march=*zicond*" "-O0" "-Og" "-Os" "-Oz" 
"-flto" } } */
 /* { dg-options "-fdump-rtl-ce1" } */
 
 long __RTL (startwith ("ce1"))
diff --git a/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c 
b/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c
index 9f9600f7679..018b6c43095 100644
--- a/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c
+++ b/gcc/testsuite/gcc.target/riscv/pr105314-rtl32.c
@@ -1,7 +1,7 @@
 /* PR rtl-optimization/105314 */
 /* { dg-do compile } */
 /* { dg-require-effective-target rv32 } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-flto" } } */
+/* { dg-skip-if "" { *-*-* } { "-march=*zicond*" "-O0" "-Og" "-Os" "-Oz" 
"-flto" } } */
 /* { dg-options "-fdump-rtl-ce1" } */
 
 long __RTL (startwith ("ce1"))
diff --git a/gcc/testsuite/gcc.target/riscv/pr105314.c 
b/gcc/testsuite/gcc.target/riscv/pr105314.c
index 1a7ea671791..75f6ecda2bb 100644
--- a/gcc/testsuite/gcc.target/riscv/pr105314.c
+++ b/gcc/testsuite/gcc.target/riscv/pr105314.c
@@ -1,6 +1,6 @@
 /* PR rtl-optimization/105314 */
 /* { dg-do compile } */
-/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-skip-if "" { *-*-* } { "-march=*zicond*" "-O0" "-Og" "-Os" "-Oz" } } */
 /* { dg-options "-fdump-rtl-ce1" } */
 
 long
-- 
2.43.0

Re: Re: [PATCH] RISC-V: Support __mulbc3 and __divbc3 in libgcc for __bf16

[Xiao Zeng]

2024-07-18 01:53  Jeff Law  wrote:
>
>
>
>On 7/17/24 2:01 AM, Xiao Zeng wrote:
>> libgcc/ChangeLog:
>>
>> * Makefile.in: Support __divbc3 and __mulbc3.
>> * libgcc2.c (if): Support BC mode for __bf16.
>> (defined): Ditto.
>> (MTYPE): Ditto.
>> (CTYPE): Ditto.
>> (AMTYPE): Ditto.
>> (MODE): Ditto.
>> (CEXT): Ditto.
>> (NOTRUNC): Ditto.
>> * libgcc2.h (LIBGCC2_HAS_BF_MODE): Ditto.
>> (__attribute__): Ditto.
>> (__divbc3): Add __divbc3 for __bf16.
>> (__mulbc3): Add __mulbc3 for __bf16.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/bf16-mulbc3-divbc3.c: New test.
>It looks like this failed pre-commit testing:
>
>> https://patchwork.sourceware.org/project/gcc/patch/20240717080159.34038-1-zengx...@eswincomputing.com/
Yes, I will fix this issue in the V2 patch.
>
>
>Jeff 
I'm sorry for replying to this email so late. I noticed that CI build has 
failed. After
inspection, it was found that several bf16 related __builtin_*bf16 symbols were 
not generated.

After passing the ESWIN internal CI test, I will push the V2 patch.

Thanks
Xiao Zeng

[PATCH] RISC-V: Support __mulbc3 and __divbc3 in libgcc for __bf16

[Xiao Zeng]

libgcc/ChangeLog:

* Makefile.in: Support __divbc3 and __mulbc3.
* libgcc2.c (if): Support BC mode for __bf16.
(defined): Ditto.
(MTYPE): Ditto.
(CTYPE): Ditto.
(AMTYPE): Ditto.
(MODE): Ditto.
(CEXT): Ditto.
(NOTRUNC): Ditto.
* libgcc2.h (LIBGCC2_HAS_BF_MODE): Ditto.
(__attribute__): Ditto.
(__divbc3): Add __divbc3 for __bf16.
(__mulbc3): Add __mulbc3 for __bf16.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/bf16-mulbc3-divbc3.c: New test.

Signed-off-by: Xiao Zeng 
---
 .../gcc.target/riscv/bf16-mulbc3-divbc3.c | 31 +++
 libgcc/Makefile.in|  6 ++--
 libgcc/libgcc2.c  | 20 
 libgcc/libgcc2.h  | 14 +
 4 files changed, 62 insertions(+), 9 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16-mulbc3-divbc3.c

diff --git a/gcc/testsuite/gcc.target/riscv/bf16-mulbc3-divbc3.c 
b/gcc/testsuite/gcc.target/riscv/bf16-mulbc3-divbc3.c
new file mode 100644
index 000..5b30de15ccf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/bf16-mulbc3-divbc3.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+#include 
+
+typedef _Complex float __cbf16 __attribute__((__mode__(__BC__)));
+
+__cbf16
+divbc3 (__cbf16 rs1, __cbf16 rs2)
+{
+  return rs1 / rs2;
+}
+
+__cbf16
+mulbc3 (__cbf16 rs1, __cbf16 rs2)
+{
+  return rs1 * rs2;
+}
+
+int main()
+{
+  __cbf16 rs1 = 2.0 + 4.0 * I;
+  __cbf16 rs2 = 1.0 + 2.0 * I;
+  __cbf16 mul = -6.0 + 8.0 * I;
+  __cbf16 div = 2.0 + 0.0 * I;
+  if (mulbc3 (rs1, rs2) != mul)
+__builtin_abort();
+  if (divbc3 (rs1, rs2) != div)
+__builtin_abort();
+  return 0;
+}
diff --git a/libgcc/Makefile.in b/libgcc/Makefile.in
index 0e46e9ef768..b71fd5e2250 100644
--- a/libgcc/Makefile.in
+++ b/libgcc/Makefile.in
@@ -450,9 +450,9 @@ lib2funcs = _muldi3 _negdi2 _lshrdi3 _ashldi3 _ashrdi3 
_cmpdi2 _ucmpdi2\
_negvsi2 _negvdi2 _ctors _ffssi2 _ffsdi2 _clz _clzsi2 _clzdi2  \
_ctzsi2 _ctzdi2 _popcount_tab _popcountsi2 _popcountdi2\
_paritysi2 _paritydi2 _powisf2 _powidf2 _powixf2 _powitf2  \
-   _mulhc3 _mulsc3 _muldc3 _mulxc3 _multc3 _divhc3 _divsc3\
-   _divdc3 _divxc3 _divtc3 _bswapsi2 _bswapdi2 _clrsbsi2  \
-   _clrsbdi2 _mulbitint3
+   _mulhc3 _mulbc3 _mulsc3 _muldc3 _mulxc3 _multc3 _divhc3\
+   _divbc3 _divsc3 _divdc3 _divxc3 _divtc3 _bswapsi2 _bswapdi2\
+   _clrsbsi2 _clrsbdi2 _mulbitint3
 
 # The floating-point conversion routines that involve a single-word integer.
 # XX stands for the integer mode.
diff --git a/libgcc/libgcc2.c b/libgcc/libgcc2.c
index 3fcb85c5b92..1d2aafcfd63 100644
--- a/libgcc/libgcc2.c
+++ b/libgcc/libgcc2.c
@@ -2591,6 +2591,7 @@ NAME (TYPE x, int m)
 #endif
 
 #if((defined(L_mulhc3) || defined(L_divhc3)) && LIBGCC2_HAS_HF_MODE) \
+|| ((defined(L_mulbc3) || defined(L_divbc3)) && LIBGCC2_HAS_BF_MODE) \
 || ((defined(L_mulsc3) || defined(L_divsc3)) && LIBGCC2_HAS_SF_MODE) \
 || ((defined(L_muldc3) || defined(L_divdc3)) && LIBGCC2_HAS_DF_MODE) \
 || ((defined(L_mulxc3) || defined(L_divxc3)) && LIBGCC2_HAS_XF_MODE) \
@@ -2607,6 +2608,13 @@ NAME (TYPE x, int m)
 # define MODE  hc
 # define CEXT  __LIBGCC_HF_FUNC_EXT__
 # define NOTRUNC (!__LIBGCC_HF_EXCESS_PRECISION__)
+#elif defined(L_mulbc3) || defined(L_divbc3)
+# define MTYPE  BFtype
+# define CTYPE  BCtype
+# define AMTYPE SFtype
+# define MODE   bc
+# define CEXT   __LIBGCC_BF_FUNC_EXT__
+# define NOTRUNC (!__LIBGCC_BF_EXCESS_PRECISION__)
 #elif defined(L_mulsc3) || defined(L_divsc3)
 # define MTYPE SFtype
 # define CTYPE SCtype
@@ -2690,8 +2698,8 @@ extern void *compile_type_assert[sizeof(INFINITY) == 
sizeof(MTYPE) ? 1 : -1];
 # define TRUNC(x)  __asm__ ("" : "=m"(x) : "m"(x))
 #endif
 
-#if defined(L_mulhc3) || defined(L_mulsc3) || defined(L_muldc3) \
-|| defined(L_mulxc3) || defined(L_multc3)
+#if defined(L_mulhc3) || defined(L_mulbc3) || defined(L_mulsc3)  \
+|| defined(L_muldc3) || defined(L_mulxc3) || defined(L_multc3)
 
 CTYPE
 CONCAT3(__mul,MODE,3) (MTYPE a, MTYPE b, MTYPE c, MTYPE d)
@@ -2760,16 +2768,16 @@ CONCAT3(__mul,MODE,3) (MTYPE a, MTYPE b, MTYPE c, MTYPE 
d)
 }
 #endif /* complex multiply */
 
-#if defined(L_divhc3) || defined(L_divsc3) || defined(L_divdc3) \
-|| defined(L_divxc3) || defined(L_divtc3)
+#if defined(L_divhc3) || defined(L_divbc3) || defined(L_divsc3) \
+|| defined(L_divdc3) || defined(L_divxc3) || defined(L_divtc3)
 
 CTYPE
 CONCAT3(__div,MODE,3) (MTYPE a, MTYPE b, MTYPE c, MTYPE d)
 {
-#if defined(L_divhc3)  \
+#if (defined(L_divhc3) || defined(L_divbc3) )  \

[COMMITTED] [PATCH v2] RISC-V: Add Zfbfmin extension

[Xiao Zeng]

2024-06-04 04:30  Jeff Law  wrote:
>
>
>
>On 6/1/24 1:45 AM, Xiao Zeng wrote:
>> 1 In the previous patch, the libcall for BF16 was implemented:
>> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8c7cee80eb50792e57d514be1418c453ddd1073e>
>>
>> 2 Riscv provides Zfbfmin extension, which completes the "Scalar BF16 
>> Converts":
>> <https://github.com/riscv/riscv-bfloat16/blob/main/doc/riscv-bfloat16-zfbfmin.adoc>
>>
>> 3 Implemented replacing libcall with Zfbfmin extension instruction.
>>
>> 4 Reused previous testcases in:
>> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8c7cee80eb50792e57d514be1418c453ddd1073e>
>> gcc/ChangeLog:
>>
>> * config/riscv/iterators.md: Add mode_iterator between
>> floating-point modes and BFmode.
>> * config/riscv/riscv.cc (riscv_output_move): Handle BFmode move
>> for zfbfmin.
>> * config/riscv/riscv.md (truncbf2): New pattern for BFmode.
>> (extendbfsf2): Dotto.
>> (*movhf_hardfloat): Add BFmode.
>> (*mov_hardfloat): Dotto.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/zfbfmin-bf16_arithmetic.c: New test.
>> * gcc.target/riscv/zfbfmin-bf16_comparison.c: New test.
>> * gcc.target/riscv/zfbfmin-bf16_float_libcall_convert.c: New test.
>> * gcc.target/riscv/zfbfmin-bf16_integer_libcall_convert.c: New test.
>OK for the trunk.  Thanks! 
Thank you, the changes have been pushed to the trunk.
>
>jeff
Thanks
Xiao Zeng

Re: Re: [PING] [PATCH] RISC-V: Add Zfbfmin extension

[Xiao Zeng]

2024-06-01 12:34  Jeff Law  wrote:
>
>
>
>On 5/30/24 5:38 AM, Xiao Zeng wrote:
>> 1 In the previous patch, the libcall for BF16 was implemented:
>> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8c7cee80eb50792e57d514be1418c453ddd1073e>
>>
>> 2 Riscv provides Zfbfmin extension, which completes the "Scalar BF16 
>> Converts":
>> <https://github.com/riscv/riscv-bfloat16/blob/main/doc/riscv-bfloat16-zfbfmin.adoc>
>>
>> 3 Implemented replacing libcall with Zfbfmin extension instruction.
>>
>> 4 Reused previous testcases in:
>> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8c7cee80eb50792e57d514be1418c453ddd1073e>
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv.cc (riscv_output_move): Handle BFmode move
>> for zfbfmin.
>> * config/riscv/riscv.md (truncsfbf2): New pattern for BFmode.
>> (trunchfbf2): Dotto.
>> (truncdfbf2): Dotto.
>> (trunctfbf2): Dotto.
>> (extendbfsf2): Dotto.
>> (*movhf_hardfloat): Add BFmode.
>> (*mov_hardfloat): Dotto.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/zfbfmin-bf16_arithmetic.c: New test.
>> * gcc.target/riscv/zfbfmin-bf16_comparison.c: New test.
>> * gcc.target/riscv/zfbfmin-bf16_float_libcall_convert.c: New test.
>> * gcc.target/riscv/zfbfmin-bf16_integer_libcall_convert.c: New test.
>> ---
>
>>
>
>
>
>> +
>> +;; The conversion of HF/DF/TF to BF needs to be done with SF if there is a
>> +;; chance to generate at least one instruction, otherwise just using
>> +;; libfunc __trunc[h|d|t]fbf2.
>> +(define_expand "trunchfbf2"
>> +  [(set (match_operand:BF    0 "register_operand" "=f")
>> +(float_truncate:BF
>> +   (match_operand:HF 1 "register_operand" " f")))]
>> +  "TARGET_ZFBFMIN"
>> +  {
>> +    convert_move (operands[0],
>> +  convert_modes (SFmode, HFmode, operands[1], 0), 0);
>> +    DONE;
>> +  }
>> +  [(set_attr "type" "fcvt")
>> +   (set_attr "mode" "BF")])
>I would suggest using a mode iterator to avoid explicit pattern duplication. 

>
>Essentially a mode iterator allows you to specify that the pattern
>should be repeated over a series of modes. 
Yes, this will make the code look more concise and avoid redundancy.

>
>It looks like you've deine a conversion from HF, DF, TF.  
Yes.

>So you define an iterator that includes just those modes. 
Yes.

>You would use the mode iterator rather than BF, DF or TF in your pattern.
Fixed.

>
>That just fixes the mode in the pattern. 
>You also need to have the name automagically adjust as well.  Use  in 
>the name.  so the name
>would be somethig like truncbf2. 
Of course, this is necessary.

>
>When you want to reference the mode in code you can do something like
>E_mode 
Yes.

>
>And that will map down to HFmode, BFmode, TFmode appropriately.
>
>I suspect you can do something similar for the extension patterns.
>
>In fact, it looks like you did this for the movehardfloat pattern.
>
>Jeff 
Thank you for Jeff's suggestion. v2 has already been uploaded.
<https://patchwork.sourceware.org/project/gcc/patch/20240601074547.80271-1-zengx...@eswincomputing.com/>

Thanks
Xiao Zeng

[PATCH v2] RISC-V: Add Zfbfmin extension

[Xiao Zeng]

1 In the previous patch, the libcall for BF16 was implemented:


2 Riscv provides Zfbfmin extension, which completes the "Scalar BF16 Converts":


3 Implemented replacing libcall with Zfbfmin extension instruction.

4 Reused previous testcases in:

gcc/ChangeLog:

* config/riscv/iterators.md: Add mode_iterator between
floating-point modes and BFmode.
* config/riscv/riscv.cc (riscv_output_move): Handle BFmode move
for zfbfmin.
* config/riscv/riscv.md (truncbf2): New pattern for BFmode.
(extendbfsf2): Dotto.
(*movhf_hardfloat): Add BFmode.
(*mov_hardfloat): Dotto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zfbfmin-bf16_arithmetic.c: New test.
* gcc.target/riscv/zfbfmin-bf16_comparison.c: New test.
* gcc.target/riscv/zfbfmin-bf16_float_libcall_convert.c: New test.
* gcc.target/riscv/zfbfmin-bf16_integer_libcall_convert.c: New test.
---
 gcc/config/riscv/iterators.md |  6 +-
 gcc/config/riscv/riscv.cc |  4 +-
 gcc/config/riscv/riscv.md | 49 --
 .../riscv/zfbfmin-bf16_arithmetic.c   | 35 ++
 .../riscv/zfbfmin-bf16_comparison.c   | 33 ++
 .../zfbfmin-bf16_float_libcall_convert.c  | 45 +
 .../zfbfmin-bf16_integer_libcall_convert.c| 66 +++
 7 files changed, 228 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_arithmetic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_comparison.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_float_libcall_convert.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_integer_libcall_convert.c

diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 3c139bc2e30..1e37e843023 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -78,9 +78,13 @@
 ;; Iterator for floating-point modes that can be loaded into X registers.
 (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
 
-;; Iterator for floating-point modes of BF16
+;; Iterator for floating-point modes of BF16.
 (define_mode_iterator HFBF [HF BF])
 
+;; Conversion between floating-point modes and BF16.
+;; SF to BF16 have hardware instructions.
+(define_mode_iterator FBF [HF DF TF])
+
 ;; ---
 ;; Mode attributes
 ;; ---
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 10af38a5a81..c5c4c777349 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4310,7 +4310,7 @@ riscv_output_move (rtx dest, rtx src)
switch (width)
  {
  case 2:
-   if (TARGET_ZFHMIN)
+   if (TARGET_ZFHMIN || TARGET_ZFBFMIN)
  return "fmv.x.h\t%0,%1";
/* Using fmv.x.s + sign-extend to emulate fmv.x.h.  */
return "fmv.x.s\t%0,%1;slli\t%0,%0,16;srai\t%0,%0,16";
@@ -4366,7 +4366,7 @@ riscv_output_move (rtx dest, rtx src)
switch (width)
  {
  case 2:
-   if (TARGET_ZFHMIN)
+   if (TARGET_ZFHMIN || TARGET_ZFBFMIN)
  return "fmv.h.x\t%0,%z1";
/* High 16 bits should be all-1, otherwise HW will treated
   as a n-bit canonical NaN, but isn't matter for softfloat.  */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 25d341ec987..e57bfcf616a 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1763,6 +1763,31 @@
   [(set_attr "type" "fcvt")
(set_attr "mode" "HF")])
 
+(define_insn "truncsfbf2"
+  [(set (match_operand:BF0 "register_operand" "=f")
+   (float_truncate:BF
+  (match_operand:SF 1 "register_operand" " f")))]
+  "TARGET_ZFBFMIN"
+  "fcvt.bf16.s\t%0,%1"
+  [(set_attr "type" "fcvt")
+   (set_attr "mode" "BF")])
+
+;; The conversion of HF/DF/TF to BF needs to be done with SF if there is a
+;; chance to generate at least one instruction, otherwise just using
+;; libfunc __trunc[h|d|t]fbf2.
+(define_expand "truncbf2"
+  [(set (match_operand:BF  0 "register_operand" "=f")
+   (float_truncate:BF
+  (match_operand:FBF   1 "register_operand" " f")))]
+  "TARGET_ZFBFMIN"
+  {
+convert_move (operands[0],
+ convert_modes (SFmode, mode, operands[1], 0), 0);
+DONE;
+  }
+  [(set_attr "type" "fcvt")
+   (set_attr "mode" "BF")])
+
 ;;
 ;;  
 ;;
@@ -1907,6 +1932,15 @@
   [(set_attr "type" "fcvt")
(set_attr "mode" "SF")])
 
+(define_insn "extendbfsf2"
+  

[PING] [PATCH] RISC-V: Add Zfbfmin extension

[Xiao Zeng]

1 In the previous patch, the libcall for BF16 was implemented:


2 Riscv provides Zfbfmin extension, which completes the "Scalar BF16 Converts":


3 Implemented replacing libcall with Zfbfmin extension instruction.

4 Reused previous testcases in:


gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_output_move): Handle BFmode move
for zfbfmin.
* config/riscv/riscv.md (truncsfbf2): New pattern for BFmode.
(trunchfbf2): Dotto.
(truncdfbf2): Dotto.
(trunctfbf2): Dotto.
(extendbfsf2): Dotto.
(*movhf_hardfloat): Add BFmode.
(*mov_hardfloat): Dotto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zfbfmin-bf16_arithmetic.c: New test.
* gcc.target/riscv/zfbfmin-bf16_comparison.c: New test.
* gcc.target/riscv/zfbfmin-bf16_float_libcall_convert.c: New test.
* gcc.target/riscv/zfbfmin-bf16_integer_libcall_convert.c: New test.
---
 gcc/config/riscv/riscv.cc |  4 +-
 gcc/config/riscv/riscv.md | 75 +--
 .../riscv/zfbfmin-bf16_arithmetic.c   | 35 +
 .../riscv/zfbfmin-bf16_comparison.c   | 33 
 .../zfbfmin-bf16_float_libcall_convert.c  | 45 +++
 .../zfbfmin-bf16_integer_libcall_convert.c| 66 
 6 files changed, 249 insertions(+), 9 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_arithmetic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_comparison.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_float_libcall_convert.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_integer_libcall_convert.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index d0c22058b8c..7c6bafedda3 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4106,7 +4106,7 @@ riscv_output_move (rtx dest, rtx src)
switch (width)
  {
  case 2:
-   if (TARGET_ZFHMIN)
+   if (TARGET_ZFHMIN || TARGET_ZFBFMIN)
  return "fmv.x.h\t%0,%1";
/* Using fmv.x.s + sign-extend to emulate fmv.x.h.  */
return "fmv.x.s\t%0,%1;slli\t%0,%0,16;srai\t%0,%0,16";
@@ -4162,7 +4162,7 @@ riscv_output_move (rtx dest, rtx src)
switch (width)
  {
  case 2:
-   if (TARGET_ZFHMIN)
+   if (TARGET_ZFHMIN || TARGET_ZFBFMIN)
  return "fmv.h.x\t%0,%z1";
/* High 16 bits should be all-1, otherwise HW will treated
   as a n-bit canonical NaN, but isn't matter for softfloat.  */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 78c16adee98..7fd2e3aa23e 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1763,6 +1763,57 @@
   [(set_attr "type" "fcvt")
(set_attr "mode" "HF")])
 
+(define_insn "truncsfbf2"
+  [(set (match_operand:BF0 "register_operand" "=f")
+   (float_truncate:BF
+  (match_operand:SF 1 "register_operand" " f")))]
+  "TARGET_ZFBFMIN"
+  "fcvt.bf16.s\t%0,%1"
+  [(set_attr "type" "fcvt")
+   (set_attr "mode" "BF")])
+
+;; The conversion of HF/DF/TF to BF needs to be done with SF if there is a
+;; chance to generate at least one instruction, otherwise just using
+;; libfunc __trunc[h|d|t]fbf2.
+(define_expand "trunchfbf2"
+  [(set (match_operand:BF0 "register_operand" "=f")
+   (float_truncate:BF
+  (match_operand:HF 1 "register_operand" " f")))]
+  "TARGET_ZFBFMIN"
+  {
+convert_move (operands[0],
+ convert_modes (SFmode, HFmode, operands[1], 0), 0);
+DONE;
+  }
+  [(set_attr "type" "fcvt")
+   (set_attr "mode" "BF")])
+
+(define_expand "truncdfbf2"
+  [(set (match_operand:BF0 "register_operand" "=f")
+   (float_truncate:BF
+  (match_operand:DF 1 "register_operand" " f")))]
+  "TARGET_ZFBFMIN"
+  {
+convert_move (operands[0],
+ convert_modes (SFmode, DFmode, operands[1], 0), 0);
+DONE;
+  }
+  [(set_attr "type" "fcvt")
+   (set_attr "mode" "BF")])
+
+(define_expand "trunctfbf2"
+  [(set (match_operand:BF0 "register_operand" "=f")
+   (float_truncate:BF
+  (match_operand:TF 1 "register_operand" " f")))]
+  "TARGET_ZFBFMIN"
+  {
+convert_move (operands[0],
+ convert_modes (SFmode, TFmode, operands[1], 0), 0);
+DONE;
+  }
+  [(set_attr "type" "fcvt")
+   (set_attr "mode" "BF")])
+
 ;;
 ;;  
 ;;
@@ -1907,6 +1958,15 @@
   [(set_attr "type" "fcvt")
(set_attr "mode" "SF")])
 
+(define_insn "extendbfsf2"
+  [(set (match_operand:SF0 "register_operand" "=f")
+   (float_extend:SF
+  (match_operand:BF 1 "regi

[PATCH] RISC-V: Add Zfbfmin extension

[Xiao Zeng]

1 In the previous patch, the libcall for BF16 was implemented:


2 Riscv provides Zfbfmin extension, which completes the "Scalar BF16 Converts":


3 Implemented replacing libcall with Zfbfmin extension instruction.

4 Reused previous testcases in:


gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_output_move): Handle BFmode move
for zfbfmin.
* config/riscv/riscv.md (truncsfbf2): New pattern for BFmode.
(trunchfbf2): Dotto.
(truncdfbf2): Dotto.
(trunctfbf2): Dotto.
(extendbfsf2): Dotto.
(*movhf_hardfloat): Add BFmode.
(*mov_hardfloat): Dotto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zfbfmin-bf16_arithmetic.c: New test.
* gcc.target/riscv/zfbfmin-bf16_comparison.c: New test.
* gcc.target/riscv/zfbfmin-bf16_float_libcall_convert.c: New test.
* gcc.target/riscv/zfbfmin-bf16_integer_libcall_convert.c: New test.
---
 gcc/config/riscv/riscv.cc |  4 +-
 gcc/config/riscv/riscv.md | 75 +--
 .../riscv/zfbfmin-bf16_arithmetic.c   | 35 +
 .../riscv/zfbfmin-bf16_comparison.c   | 33 
 .../zfbfmin-bf16_float_libcall_convert.c  | 45 +++
 .../zfbfmin-bf16_integer_libcall_convert.c| 66 
 6 files changed, 249 insertions(+), 9 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_arithmetic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_comparison.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_float_libcall_convert.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zfbfmin-bf16_integer_libcall_convert.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index d0c22058b8c..7c6bafedda3 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4106,7 +4106,7 @@ riscv_output_move (rtx dest, rtx src)
switch (width)
  {
  case 2:
-   if (TARGET_ZFHMIN)
+   if (TARGET_ZFHMIN || TARGET_ZFBFMIN)
  return "fmv.x.h\t%0,%1";
/* Using fmv.x.s + sign-extend to emulate fmv.x.h.  */
return "fmv.x.s\t%0,%1;slli\t%0,%0,16;srai\t%0,%0,16";
@@ -4162,7 +4162,7 @@ riscv_output_move (rtx dest, rtx src)
switch (width)
  {
  case 2:
-   if (TARGET_ZFHMIN)
+   if (TARGET_ZFHMIN || TARGET_ZFBFMIN)
  return "fmv.h.x\t%0,%z1";
/* High 16 bits should be all-1, otherwise HW will treated
   as a n-bit canonical NaN, but isn't matter for softfloat.  */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 78c16adee98..7fd2e3aa23e 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1763,6 +1763,57 @@
   [(set_attr "type" "fcvt")
(set_attr "mode" "HF")])
 
+(define_insn "truncsfbf2"
+  [(set (match_operand:BF0 "register_operand" "=f")
+   (float_truncate:BF
+  (match_operand:SF 1 "register_operand" " f")))]
+  "TARGET_ZFBFMIN"
+  "fcvt.bf16.s\t%0,%1"
+  [(set_attr "type" "fcvt")
+   (set_attr "mode" "BF")])
+
+;; The conversion of HF/DF/TF to BF needs to be done with SF if there is a
+;; chance to generate at least one instruction, otherwise just using
+;; libfunc __trunc[h|d|t]fbf2.
+(define_expand "trunchfbf2"
+  [(set (match_operand:BF0 "register_operand" "=f")
+   (float_truncate:BF
+  (match_operand:HF 1 "register_operand" " f")))]
+  "TARGET_ZFBFMIN"
+  {
+convert_move (operands[0],
+ convert_modes (SFmode, HFmode, operands[1], 0), 0);
+DONE;
+  }
+  [(set_attr "type" "fcvt")
+   (set_attr "mode" "BF")])
+
+(define_expand "truncdfbf2"
+  [(set (match_operand:BF0 "register_operand" "=f")
+   (float_truncate:BF
+  (match_operand:DF 1 "register_operand" " f")))]
+  "TARGET_ZFBFMIN"
+  {
+convert_move (operands[0],
+ convert_modes (SFmode, DFmode, operands[1], 0), 0);
+DONE;
+  }
+  [(set_attr "type" "fcvt")
+   (set_attr "mode" "BF")])
+
+(define_expand "trunctfbf2"
+  [(set (match_operand:BF0 "register_operand" "=f")
+   (float_truncate:BF
+  (match_operand:TF 1 "register_operand" " f")))]
+  "TARGET_ZFBFMIN"
+  {
+convert_move (operands[0],
+ convert_modes (SFmode, TFmode, operands[1], 0), 0);
+DONE;
+  }
+  [(set_attr "type" "fcvt")
+   (set_attr "mode" "BF")])
+
 ;;
 ;;  
 ;;
@@ -1907,6 +1958,15 @@
   [(set_attr "type" "fcvt")
(set_attr "mode" "SF")])
 
+(define_insn "extendbfsf2"
+  [(set (match_operand:SF0 "register_operand" "=f")
+   (float_extend:SF
+  (match_operand:BF 1 "regi

[COMMITTED] RISC-V: Fix "Nan-box the result of movbf on soft-bf16"

[Xiao Zeng]

2024-05-18 09:57  Jeff Law  wrote:
>
>
>
>On 5/15/24 7:55 PM, Xiao Zeng wrote:
>> 1 According to unpriv-isa spec:
>> <https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-221bd85-2024-05-14/unpriv-isa-asciidoc.pdf>
>>    1.1 "FMV.H.X moves the half-precision value encoded in IEEE 754-2008
>>    standard encoding from the lower 16 bits of integer register rs1
>>    to the floating-point register rd, NaN-boxing the result."
>>    1.2 "FMV.W.X moves the single-precision value encoded in IEEE 754-2008
>>    standard encoding from the lower 32 bits of integer register rs1
>>    to the floating-point register rd. The bits are not modified in the
>>    transfer, and in particular, the payloads of non-canonical NaNs are 
>>preserved."
>>
>> 2 When (!TARGET_ZFHMIN == true && TARGET_HARD_FLOAT == true), instruction 
>> needs
>> to be added to complete the Nan-box, as done in
>> "RISC-V: Nan-box the result of movhf on soft-fp16":
>> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=057dc349021660c40699fb5c98fd9cac8e168653>
>>
>> 3 Consider the "RISC-V: Nan-box the result of movbf on soft-bf16" in:
>> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=ce51e6727c9d69bbab0e766c449e60fd41f5f2f9>
>> It ignores that both hf16 and bf16 are 16bits floating-point.
>>
>> 4 zfbfmin -> zfhmin in:
>> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31>
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv.cc (riscv_legitimize_move): Optimize movbf
>> with Nan-boxing value.
>> * config/riscv/riscv.md (*movhf_softfloat_boxing): Expand movbf
>> with Nan-boxing value.
>> (*mov_softfloat_boxing): Ditto.
>> with Nan-boxing value.
>> (*movbf_softfloat_boxing): Delete abandon pattern.
>> ---
>>   gcc/config/riscv/riscv.cc | 15 +--
>>   gcc/config/riscv/riscv.md | 19 +--
>>   2 files changed, 10 insertions(+), 24 deletions(-)
>>
>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> index 4067505270e..04513537aad 100644
>> --- a/gcc/config/riscv/riscv.cc
>> +++ b/gcc/config/riscv/riscv.cc
>> @@ -3178,13 +3178,10 @@ riscv_legitimize_move (machine_mode mode, rtx dest, 
>> rtx src)
>>    (set (reg:SI/DI mask) (const_int -65536)
>>    (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF/BF src) 
>>0)))
>>    (set (reg:SI/DI temp) (ior:SI/DI (reg:SI/DI mask) (reg:SI/DI temp)))
>> - (set (reg:HF/BF dest) (unspec:HF/BF[ (reg:SI/DI temp) ]
>> -    UNSPEC_FMV_SFP16_X/UNSPEC_FMV_SBF16_X))
>> - */
>> + (set (reg:HF/BF dest) (unspec:HF/BF[ (reg:SI/DI temp) ] 
>> UNSPEC_FMV_FP16_X))
>> +  */
>>  
>> -  if (TARGET_HARD_FLOAT
>> -  && ((!TARGET_ZFHMIN && mode == HFmode)
>> -  || (!TARGET_ZFBFMIN && mode == BFmode))
>> +  if (TARGET_HARD_FLOAT && !TARGET_ZFHMIN && (mode == HFmode || mode == 
>> BFmode)
>We generally prefer not to mix && and || operators on the same line.
>I'd suggest
>
>if (TARGET_HARD_FLOAT
> && !TARGET_ZFHMIN
> && (mode == HFmode || mode == BFmode)
>[ ... ] 
Fixed.

>
>
>> @@ -1959,23 +1958,15 @@
>>  (set_attr "type" "fmove,move,load,store,mtc,mfc")
>>  (set_attr "mode" "")])
>>  
>> -(define_insn "*movhf_softfloat_boxing"
>> -  [(set (match_operand:HF 0 "register_operand"    "=f")
>> -    (unspec:HF [(match_operand:X 1 "register_operand" " r")] 
>> UNSPEC_FMV_SFP16_X))]
>> +(define_insn "*mov_softfloat_boxing"
>> +  [(set (match_operand:HFBF 0 "register_operand"    "=f")
>> +    (unspec:HFBF [(match_operand:X 1 "register_operand" " r")]
>> +UNSPEC_FMV_FP16_X))]
>> "!TARGET_ZFHMIN"
>I think the linter complained about having 8 spaces instead of a tab in
>one of the lines above. 
Fixed.

>
>With those fixes, this is fine for the trunk.
>
>jeff
Thanks
Xiao Zeng

Re: Re: [PATCH] RISC-V: Modify _Bfloat16 to __bf16

[Xiao Zeng]

2024-05-18 08:36  Jeff Law  wrote:
>
>
>
>On 5/17/24 2:19 AM, Kito Cheng wrote:
>> LGTM, thanks for fixing this :)
>And just to be clear for Xiao, you can go ahead and commit this patch to
>the trunk. 
> An ACK from Kito, Juzhe, Palmer, Robin or myself
good.

>is all you need for a change that is isolated to RISC-V code.
>
>jeff
Thanks
Xiao Zeng

[COMMITTED] RISC-V: Modify _Bfloat16 to __bf16

[Xiao Zeng]

2024-05-17 16:19  Kito Cheng  wrote:
>
>LGTM, thanks for fixing this :) 
1 Passed CI testing:
<https://patchwork.sourceware.org/project/gcc/patch/20240517081013.12611-1-zengx...@eswincomputing.com/>

2 pushed to trunk.
>
>On Fri, May 17, 2024 at 4:05 PM Xiao Zeng  wrote:
>>
>> According to the description in:
>> <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/367>,
>> the type representation symbol of BF16 has been corrected.
>>
>> Kito Cheng pointed out relevant information in the email:
>> <https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651850.html>
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv-builtins.cc (riscv_init_builtin_types):
>> Modify _Bfloat16 to __bf16.
>> * config/riscv/riscv.cc (riscv_mangle_type): Ditto.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/_Bfloat16-nanboxing.c: Move to...
>> * gcc.target/riscv/__bf16-nanboxing.c: ...here.
>> * gcc.target/riscv/bf16_arithmetic.c: Modify _Bfloat16 to __bf16.
>> * gcc.target/riscv/bf16_call.c: Ditto.
>> * gcc.target/riscv/bf16_comparison.c: Ditto.
>> * gcc.target/riscv/bf16_float_libcall_convert.c: Ditto.
>> * gcc.target/riscv/bf16_integer_libcall_convert.c: Ditto.
>> ---
>>  gcc/config/riscv/riscv-builtins.cc   |  6 +++---
>>  gcc/config/riscv/riscv.cc    |  2 +-
>>  .../{_Bfloat16-nanboxing.c => __bf16-nanboxing.c}    | 12 ++--
>>  gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c |  6 +++---
>>  gcc/testsuite/gcc.target/riscv/bf16_call.c   |  4 ++--
>>  gcc/testsuite/gcc.target/riscv/bf16_comparison.c |  6 +++---
>>  .../gcc.target/riscv/bf16_float_libcall_convert.c    |  2 +-
>>  .../gcc.target/riscv/bf16_integer_libcall_convert.c  |  2 +-
>>  8 files changed, 20 insertions(+), 20 deletions(-)
>>  rename gcc/testsuite/gcc.target/riscv/{_Bfloat16-nanboxing.c => 
>>__bf16-nanboxing.c} (83%)
>>
>> diff --git a/gcc/config/riscv/riscv-builtins.cc 
>> b/gcc/config/riscv/riscv-builtins.cc
>> index 4c08834288a..dc54e1a59b5 100644
>> --- a/gcc/config/riscv/riscv-builtins.cc
>> +++ b/gcc/config/riscv/riscv-builtins.cc
>> @@ -275,7 +275,7 @@ riscv_init_builtin_types (void)
>>  lang_hooks.types.register_builtin_type (riscv_float16_type_node,
>> "_Float16");
>>
>> -  /* Provide the _Bfloat16 type and bfloat16_type_node if needed.  */
>> +  /* Provide the __bf16 type and bfloat16_type_node if needed.  */
>>    if (!bfloat16_type_node)
>>  {
>>    riscv_bfloat16_type_node = make_node (REAL_TYPE);
>> @@ -286,9 +286,9 @@ riscv_init_builtin_types (void)
>>    else
>>  riscv_bfloat16_type_node = bfloat16_type_node;
>>
>> -  if (!maybe_get_identifier ("_Bfloat16"))
>> +  if (!maybe_get_identifier ("__bf16"))
>>  lang_hooks.types.register_builtin_type (riscv_bfloat16_type_node,
>> -   "_Bfloat16");
>> +   "__bf16");
>>  }
>>
>>  /* Implement TARGET_INIT_BUILTINS.  */
>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> index 4067505270e..cf15a12de3a 100644
>> --- a/gcc/config/riscv/riscv.cc
>> +++ b/gcc/config/riscv/riscv.cc
>> @@ -10262,7 +10262,7 @@ riscv_asan_shadow_offset (void)
>>  static const char *
>>  riscv_mangle_type (const_tree type)
>>  {
>> -  /* Half-precision float, _Float16 is "DF16_" and _Bfloat16 is "DF16b".  */
>> +  /* Half-precision float, _Float16 is "DF16_" and __bf16 is "DF16b".  */
>>    if (SCALAR_FLOAT_TYPE_P (type) && TYPE_PRECISION (type) == 16)
>>  {
>>    if (TYPE_MODE (type) == HFmode)
>> diff --git a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c 
>> b/gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c
>> similarity index 83%
>> rename from gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
>> rename to gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c
>> index 11a73d22234..a9a586c98b9 100644
>> --- a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
>> +++ b/gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c
>> @@ -1,14 +1,14 @@
>>  /* { dg-do compile } */
>>  /* { dg-options "-march=rv64ifd -mabi=lp64d -mcmodel=medlow -O" } */
>>
>> -_Bfloat16 gvar = 9.87654;
>> +__bf16 gvar = 9.87654;
>>  union U
>>  {

[PATCH] RISC-V: Modify _Bfloat16 to __bf16

[Xiao Zeng]

According to the description in:
,
the type representation symbol of BF16 has been corrected.

Kito Cheng pointed out relevant information in the email:


gcc/ChangeLog:

* config/riscv/riscv-builtins.cc (riscv_init_builtin_types):
Modify _Bfloat16 to __bf16.
* config/riscv/riscv.cc (riscv_mangle_type): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/_Bfloat16-nanboxing.c: Move to...
* gcc.target/riscv/__bf16-nanboxing.c: ...here.
* gcc.target/riscv/bf16_arithmetic.c: Modify _Bfloat16 to __bf16.
* gcc.target/riscv/bf16_call.c: Ditto.
* gcc.target/riscv/bf16_comparison.c: Ditto.
* gcc.target/riscv/bf16_float_libcall_convert.c: Ditto.
* gcc.target/riscv/bf16_integer_libcall_convert.c: Ditto.
---
 gcc/config/riscv/riscv-builtins.cc   |  6 +++---
 gcc/config/riscv/riscv.cc|  2 +-
 .../{_Bfloat16-nanboxing.c => __bf16-nanboxing.c}| 12 ++--
 gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c |  6 +++---
 gcc/testsuite/gcc.target/riscv/bf16_call.c   |  4 ++--
 gcc/testsuite/gcc.target/riscv/bf16_comparison.c |  6 +++---
 .../gcc.target/riscv/bf16_float_libcall_convert.c|  2 +-
 .../gcc.target/riscv/bf16_integer_libcall_convert.c  |  2 +-
 8 files changed, 20 insertions(+), 20 deletions(-)
 rename gcc/testsuite/gcc.target/riscv/{_Bfloat16-nanboxing.c => 
__bf16-nanboxing.c} (83%)

diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 4c08834288a..dc54e1a59b5 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -275,7 +275,7 @@ riscv_init_builtin_types (void)
 lang_hooks.types.register_builtin_type (riscv_float16_type_node,
"_Float16");
 
-  /* Provide the _Bfloat16 type and bfloat16_type_node if needed.  */
+  /* Provide the __bf16 type and bfloat16_type_node if needed.  */
   if (!bfloat16_type_node)
 {
   riscv_bfloat16_type_node = make_node (REAL_TYPE);
@@ -286,9 +286,9 @@ riscv_init_builtin_types (void)
   else
 riscv_bfloat16_type_node = bfloat16_type_node;
 
-  if (!maybe_get_identifier ("_Bfloat16"))
+  if (!maybe_get_identifier ("__bf16"))
 lang_hooks.types.register_builtin_type (riscv_bfloat16_type_node,
-   "_Bfloat16");
+   "__bf16");
 }
 
 /* Implement TARGET_INIT_BUILTINS.  */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4067505270e..cf15a12de3a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -10262,7 +10262,7 @@ riscv_asan_shadow_offset (void)
 static const char *
 riscv_mangle_type (const_tree type)
 {
-  /* Half-precision float, _Float16 is "DF16_" and _Bfloat16 is "DF16b".  */
+  /* Half-precision float, _Float16 is "DF16_" and __bf16 is "DF16b".  */
   if (SCALAR_FLOAT_TYPE_P (type) && TYPE_PRECISION (type) == 16)
 {
   if (TYPE_MODE (type) == HFmode)
diff --git a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c 
b/gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c
similarity index 83%
rename from gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
rename to gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c
index 11a73d22234..a9a586c98b9 100644
--- a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
+++ b/gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c
@@ -1,14 +1,14 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64ifd -mabi=lp64d -mcmodel=medlow -O" } */
 
-_Bfloat16 gvar = 9.87654;
+__bf16 gvar = 9.87654;
 union U
 {
   unsigned short i16;
-  _Bfloat16 f16;
+  __bf16 f16;
 };
 
-_Bfloat16
+__bf16
 test1 (unsigned short input)
 {
   union U tmp;
@@ -16,19 +16,19 @@ test1 (unsigned short input)
   return tmp.f16;
 }
 
-_Bfloat16
+__bf16
 test2 ()
 {
   return 1.234f;
 }
 
-_Bfloat16
+__bf16
 test3 ()
 {
   return gvar;
 }
 
-_Bfloat16
+__bf16
 test ()
 {
   return 0.0f;
diff --git a/gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c 
b/gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c
index 9e485051260..190cc1d574a 100644
--- a/gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c
+++ b/gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c
@@ -5,9 +5,9 @@
 /* 1) bf -> sf  (call  __extendbfsf2)  */
 /* 2) sf1 [+|-|*|/] sf2 (call  __[add|sub|mul|div]sf3)  */
 /* 3) sf -> bf  (call  __truncsfbf2)  */
-extern _Bfloat16 bf;
-extern _Bfloat16 bf1;
-extern _Bfloat16 bf2;
+extern __bf16 bf;
+extern __bf16 bf1;
+extern __bf16 bf2;
 
 void bf_add_bf () { bf = bf1 + bf2; }
 
diff --git a/gcc/testsuite/gcc.target/riscv/bf16_call.c 
b/gcc/testsuite/gcc.target/riscv/bf16_call.c
index 29f6771..6ace1494370 100644
--- a/gcc/testsuite/gcc.target/riscv/bf16_call.c
+++ b/gcc/testsuite/gcc.target/riscv/bf16_call.c
@@ -4,9 +

Re: Re: [NOT CODE REVIEW] [PATCH v3 1/1] [RISC-V] Add support for _Bfloat16

[Xiao Zeng]

2024-05-16 16:55  Kito Cheng  wrote:
>
>Hi Xiao Zeng:
>
>Just wondering why use _Bfloat16 rather than __bf16? you mention
>__bf16 in comment, but implementation use _Bfloat16?
Obviously, this is a mistake.
This patch has spanned a considerable amount of time locally.

I will submit a new patch to correct it.
> I would like to use __bf16 to make it consistent between LLVM and psABI if 
> possible :)
Thanks Kito for pointing out this point. Meanwhile, due to my issue, I did not 
see
Andreas Schwab's email. He had already sent me an email earlier, pointing out 
the existing issues.
<https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651529.html>

By the way, if I don't reply to the email in a timely manner, it must be my 
problem.
Please send me another email to remind me.
I will reset the email to avoid missing any emails

Thanks
Xiao Zeng

[PATCH] RISC-V: Fix "Nan-box the result of movbf on soft-bf16"

[Xiao Zeng]

1 According to unpriv-isa spec:

  1.1 "FMV.H.X moves the half-precision value encoded in IEEE 754-2008
  standard encoding from the lower 16 bits of integer register rs1
  to the floating-point register rd, NaN-boxing the result."
  1.2 "FMV.W.X moves the single-precision value encoded in IEEE 754-2008
  standard encoding from the lower 32 bits of integer register rs1
  to the floating-point register rd. The bits are not modified in the
  transfer, and in particular, the payloads of non-canonical NaNs are 
preserved."

2 When (!TARGET_ZFHMIN == true && TARGET_HARD_FLOAT == true), instruction needs
to be added to complete the Nan-box, as done in
"RISC-V: Nan-box the result of movhf on soft-fp16":


3 Consider the "RISC-V: Nan-box the result of movbf on soft-bf16" in:

It ignores that both hf16 and bf16 are 16bits floating-point.

4 zfbfmin -> zfhmin in:


gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_legitimize_move): Optimize movbf
with Nan-boxing value.
* config/riscv/riscv.md (*movhf_softfloat_boxing): Expand movbf
with Nan-boxing value.
(*mov_softfloat_boxing): Ditto.
with Nan-boxing value.
(*movbf_softfloat_boxing): Delete abandon pattern.
---
 gcc/config/riscv/riscv.cc | 15 +--
 gcc/config/riscv/riscv.md | 19 +--
 2 files changed, 10 insertions(+), 24 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4067505270e..04513537aad 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3178,13 +3178,10 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx 
src)
  (set (reg:SI/DI mask) (const_int -65536)
  (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF/BF src) 0)))
  (set (reg:SI/DI temp) (ior:SI/DI (reg:SI/DI mask) (reg:SI/DI temp)))
- (set (reg:HF/BF dest) (unspec:HF/BF[ (reg:SI/DI temp) ]
-   UNSPEC_FMV_SFP16_X/UNSPEC_FMV_SBF16_X))
- */
+ (set (reg:HF/BF dest) (unspec:HF/BF[ (reg:SI/DI temp) ] 
UNSPEC_FMV_FP16_X))
+  */
 
-  if (TARGET_HARD_FLOAT
-  && ((!TARGET_ZFHMIN && mode == HFmode)
- || (!TARGET_ZFBFMIN && mode == BFmode))
+  if (TARGET_HARD_FLOAT && !TARGET_ZFHMIN && (mode == HFmode || mode == BFmode)
   && REG_P (dest) && FP_REG_P (REGNO (dest))
   && REG_P (src) && !FP_REG_P (REGNO (src))
   && can_create_pseudo_p ())
@@ -3199,10 +3196,8 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx 
src)
   else
emit_insn (gen_iordi3 (temp, mask, temp));
 
-  riscv_emit_move (dest,
-  gen_rtx_UNSPEC (mode, gen_rtvec (1, temp),
-  mode == HFmode ? UNSPEC_FMV_SFP16_X
- : UNSPEC_FMV_SBF16_X));
+  riscv_emit_move (dest, gen_rtx_UNSPEC (mode, gen_rtvec (1, temp),
+UNSPEC_FMV_FP16_X));
 
   return true;
 }
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index ee15c63db10..4734bbc17df 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -87,8 +87,7 @@
   UNSPEC_STRLEN
 
   ;; Workaround for HFmode and BFmode without hardware extension
-  UNSPEC_FMV_SFP16_X
-  UNSPEC_FMV_SBF16_X
+  UNSPEC_FMV_FP16_X
 
   ;; XTheadFmv moves
   UNSPEC_XTHEADFMV
@@ -1959,23 +1958,15 @@
(set_attr "type" "fmove,move,load,store,mtc,mfc")
(set_attr "mode" "")])
 
-(define_insn "*movhf_softfloat_boxing"
-  [(set (match_operand:HF 0 "register_operand""=f")
-(unspec:HF [(match_operand:X 1 "register_operand" " r")] 
UNSPEC_FMV_SFP16_X))]
+(define_insn "*mov_softfloat_boxing"
+  [(set (match_operand:HFBF 0 "register_operand"   "=f")
+(unspec:HFBF [(match_operand:X 1 "register_operand" " r")]
+UNSPEC_FMV_FP16_X))]
   "!TARGET_ZFHMIN"
   "fmv.w.x\t%0,%1"
   [(set_attr "type" "fmove")
(set_attr "mode" "SF")])
 
-(define_insn "*movbf_softfloat_boxing"
-  [(set (match_operand:BF 0 "register_operand"   "=f")
-   (unspec:BF [(match_operand:X 1 "register_operand" " r")]
-UNSPEC_FMV_SBF16_X))]
-  "!TARGET_ZFBFMIN"
-  "fmv.w.x\t%0,%1"
-  [(set_attr "type" "fmove")
-   (set_attr "mode" "SF")])
-
 ;;
 ;;  
 ;;
-- 
2.17.1

[COMMITTED] RISC-V: Add Zvfbfwma extension to the -march= option

[Xiao Zeng]

2024-05-15 13:48  Kito Cheng  wrote:
>
>LGTM, I agree we should only implement what Embedded Processor
>implies, we have no way to know that from the arch string
Thanks, Kito.

1 Passed CI testing, except for formatting issues. 
<https://patchwork.sourceware.org/project/gcc/patch/20240515054029.52476-1-zengx...@eswincomputing.com/>

2 After fixing the format, pushed to trunk.

>
>On Wed, May 15, 2024 at 1:35 PM Xiao Zeng  wrote:
>>
>> This patch would like to add new sub extension (aka Zvfbfwma) to the
>> -march= option. It introduces a new data type BF16.
>>
>> 1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin 
>> extension."
>>   1.1 In Embedded    Processor: Zvfbfwma -> Zvfbfmin -> Zve32f
>>   1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V
>>   1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin
>>
>> 2 Zvfbfmin's information is in:
>> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09>
>>
>> 3 Zfbfmin's formation is in:
>> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31>
>>
>> 4 Depending on different usage scenarios, the Zvfbfwma extension may
>> depend on 'V' or 'Zve32f'. This patch only implements dependencies in
>> scenario of Embedded Processor. This is consistent with the processing
>> strategy in Zvfbfmin. In scenario of Application Processor, it is
>> necessary to explicitly indicate the dependent 'V' extension.
>>
>> 5 You can locate more information about Zvfbfwma from below spec doc:
>> <https://github.com/riscv/riscv-bfloat16/releases/download/v59042fc71c31a9bcb2f1957621c960ed36fac401/riscv-bfloat16.pdf>
>>
>> gcc/ChangeLog:
>>
>> * common/config/riscv/riscv-common.cc:
>> (riscv_implied_info): Add zvfbfwma item.
>> (riscv_ext_version_table): Ditto.
>> (riscv_ext_flag_table): Ditto.
>> * config/riscv/riscv.opt:
>> (MASK_ZVFBFWMA): New macro.
>> (TARGET_ZVFBFWMA): Ditto.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/arch-37.c: New test.
>> * gcc.target/riscv/arch-38.c: New test.
>> * gcc.target/riscv/predef-36.c: New test.
>> * gcc.target/riscv/predef-37.c: New test.
>> ---
>>  gcc/common/config/riscv/riscv-common.cc    |  5 +++
>>  gcc/config/riscv/riscv.opt |  2 +
>>  gcc/testsuite/gcc.target/riscv/arch-37.c   |  5 +++
>>  gcc/testsuite/gcc.target/riscv/arch-38.c   |  5 +++
>>  gcc/testsuite/gcc.target/riscv/predef-36.c | 48 ++
>>  gcc/testsuite/gcc.target/riscv/predef-37.c | 48 ++
>>  6 files changed, 113 insertions(+)
>>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-37.c
>>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-38.c
>>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-36.c
>>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-37.c
>>
>> diff --git a/gcc/common/config/riscv/riscv-common.cc 
>> b/gcc/common/config/riscv/riscv-common.cc
>> index fb76017ffbc..88204393fde 100644
>> --- a/gcc/common/config/riscv/riscv-common.cc
>> +++ b/gcc/common/config/riscv/riscv-common.cc
>> @@ -162,6 +162,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
>>    {"zfa", "f"},
>>
>>    {"zvfbfmin", "zve32f"},
>> +  {"zvfbfwma", "zvfbfmin"},
>> +  {"zvfbfwma", "zfbfmin"},
>>    {"zvfhmin", "zve32f"},
>>    {"zvfh", "zve32f"},
>>    {"zvfh", "zfhmin"},
>> @@ -336,6 +338,7 @@ static const struct riscv_ext_version 
>> riscv_ext_version_table[] =
>>    {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
>>    {"zfhmin",    ISA_SPEC_CLASS_NONE, 1, 0},
>>    {"zvfbfmin",  ISA_SPEC_CLASS_NONE, 1, 0},
>> +  {"zvfbfwma",  ISA_SPEC_CLASS_NONE, 1, 0},
>>    {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
>>    {"zvfh",  ISA_SPEC_CLASS_NONE, 1, 0},
>>
>> @@ -1667,6 +1670,7 @@ static const riscv_ext_flag_table_t 
>> riscv_ext_flag_table[] =
>>    {"zve64f",   &gcc_options::x_riscv_vector_elen_flags, 
>>MASK_VECTOR_ELEN_FP_32},
>>    {"zve64d",   &gcc_options::x_riscv_vector_elen_flags, 
>>MASK_VECTOR_ELEN_FP_64},
>>    {"zvfbfmin", &gcc_options::x_riscv_vector_elen_flags, 
>>MAS

[PATCH] RISC-V: Add Zvfbfwma extension to the -march= option

[Xiao Zeng]

This patch would like to add new sub extension (aka Zvfbfwma) to the
-march= option. It introduces a new data type BF16.

1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin extension."
  1.1 In EmbeddedProcessor: Zvfbfwma -> Zvfbfmin -> Zve32f
  1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V
  1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin

2 Zvfbfmin's information is in:


3 Zfbfmin's formation is in:


4 Depending on different usage scenarios, the Zvfbfwma extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies in
scenario of Embedded Processor. This is consistent with the processing
strategy in Zvfbfmin. In scenario of Application Processor, it is
necessary to explicitly indicate the dependent 'V' extension.

5 You can locate more information about Zvfbfwma from below spec doc:


gcc/ChangeLog:

* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zvfbfwma item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv.opt:
(MASK_ZVFBFWMA): New macro.
(TARGET_ZVFBFWMA): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-37.c: New test.
* gcc.target/riscv/arch-38.c: New test.
* gcc.target/riscv/predef-36.c: New test.
* gcc.target/riscv/predef-37.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc|  5 +++
 gcc/config/riscv/riscv.opt |  2 +
 gcc/testsuite/gcc.target/riscv/arch-37.c   |  5 +++
 gcc/testsuite/gcc.target/riscv/arch-38.c   |  5 +++
 gcc/testsuite/gcc.target/riscv/predef-36.c | 48 ++
 gcc/testsuite/gcc.target/riscv/predef-37.c | 48 ++
 6 files changed, 113 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-37.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-38.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-36.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-37.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index fb76017ffbc..88204393fde 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -162,6 +162,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zfa", "f"},
 
   {"zvfbfmin", "zve32f"},
+  {"zvfbfwma", "zvfbfmin"},
+  {"zvfbfwma", "zfbfmin"},
   {"zvfhmin", "zve32f"},
   {"zvfh", "zve32f"},
   {"zvfh", "zfhmin"},
@@ -336,6 +338,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvfbfmin",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zvfbfwma",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvfh",  ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1667,6 +1670,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zve64f",   &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_32},
   {"zve64d",   &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_64},
   {"zvfbfmin", &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_BF_16},
+  {"zvfbfwma", &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_BF_16},
   {"zvfhmin",  &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_16},
   {"zvfh", &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_16},
 
@@ -1704,6 +1708,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
   {"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
   {"zvfbfmin",  &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN},
+  {"zvfbfwma",  &gcc_options::x_riscv_zf_subext, MASK_ZVFBFWMA},
   {"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
   {"zvfh",  &gcc_options::x_riscv_zf_subext, MASK_ZVFH},
 
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 1252834aec5..d209ac896fd 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -401,6 +401,8 @@ Mask(ZFH) Var(riscv_zf_subext)
 
 Mask(ZVFBFMIN) Var(riscv_zf_subext)
 
+Mask(ZVFBFWMA) Var(riscv_zf_subext)
+
 Mask(ZVFHMIN) Var(riscv_zf_subext)
 
 Mask(ZVFH)Var(riscv_zf_subext)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-37.c 
b/gcc/testsuite/gcc.target/riscv/arch-37.c
new file mode 100644
index 000..5b19a73c556
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-37.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zvfbfwma -mabi=ilp32f" } */
+int
+foo ()
+{}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-38.c 
b/gcc/testsuite/gcc.target/

Re: [COMMITED] MAINTAINERS: Fix an entry using spaces instead of tabs

[Xiao Zeng]

2024-05-14 16:37  Filip Kastl  wrote:
>
>In the MAINTAINERS file, names and emails are separated by tabs.  One of
>the entries recently added used spaces.  This patch corrects this. 
Thanks.

>
>The check-MAINTAINERS.py script breaks a bit when this happens.  This
>patch also adds warning about this situation into the script.
>
>ChangeLog:
>
>   * MAINTAINERS: Use tabs between name and email.
>
>contrib/ChangeLog:
>
>   * check-MAINTAINERS.py: Add warning about not using tabs.
>
>Signed-off-by: Filip Kastl 
>---
> MAINTAINERS  | 2 +-
> contrib/check-MAINTAINERS.py | 8 
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
>diff --git a/MAINTAINERS b/MAINTAINERS
>index 361059fd55c..8bb435dd54e 100644
>--- a/MAINTAINERS
>+++ b/MAINTAINERS
>@@ -738,7 +738,7 @@ Kwok Cheung Yeung  
> Greta Yorsh   
> David Yuste   
> Adhemerval Zanella
>-Xiao Zeng   
>+Xiao Zeng 
> Dennis Zhang  
> Yufeng Zhang  
> Qing Zhao 
>diff --git a/contrib/check-MAINTAINERS.py b/contrib/check-MAINTAINERS.py
>index 9f31a10bcff..2bac67f0821 100755
>--- a/contrib/check-MAINTAINERS.py
>+++ b/contrib/check-MAINTAINERS.py
>@@ -71,6 +71,14 @@ def check_group(name, lines):
> print(f'Line should not start with space: "{line}"')
> exit_code = 2
>
>+    # Special-case some names
>+    if line == 'James Norris':
>+    continue
>+
>+    if '\t' not in line:
>+    print(f'Name and email should be separated by tabs: "{line}"')
>+    exit_code = 2
>+
> lines = [line + '\n' for line in lines]
> sorted_lines = sorted(lines, key=sort_by_surname)
> if lines != sorted_lines:
>--
>2.45.0
Thanks
Xiao Zeng

MAINTAINERS: Add myself to write after approval

[Xiao Zeng]

ChangeLog:

* MAINTAINERS: Add myself.
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 71e02abc426..361059fd55c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -738,6 +738,7 @@ Kwok Cheung Yeung   

 Greta Yorsh
 David Yuste
 Adhemerval Zanella 
+Xiao Zeng   
 Dennis Zhang   
 Yufeng Zhang   
 Qing Zhao  
-- 
2.17.1

Re: Re: [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16

[Xiao Zeng]

2024-05-09 04:01  Jeff Law  wrote:
>
>
>
>On 5/7/24 6:38 PM, Xiao Zeng wrote:
>> 1 This patch implements the Nan-box of bf16.
>>
>> 2 Please refer to the Nan-box implementation of hf16 in:
>> <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=057dc349021660c40699fb5c98fd9cac8e168653>
>>
>> 3 The discussion about Nan-box can be found on the website:
>> <https://www.mail-archive.com/search?q=Nan-box+the+result+of+movhf+on+soft-fp16&l=gcc-patches%40gcc.gnu.org>
>>
>> 4 Below test are passed for this patch
>>  * The riscv fully regression test.
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv.cc (riscv_legitimize_move): Expand movbf
>> with Nan-boxing value.
>> * config/riscv/riscv.md (*movbf_softfloat_boxing): New pattern.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/_Bfloat16-nanboxing.c: New test.
>> ---
>>   gcc/config/riscv/riscv.cc | 51 ++-
>>   gcc/config/riscv/riscv.md | 12 -
>>   .../gcc.target/riscv/_Bfloat16-nanboxing.c    | 38 ++
>>   3 files changed, 76 insertions(+), 25 deletions(-)
>>   create mode 100644 gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
>>
>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> index 545e68566dc..be2cb245733 100644
>> --- a/gcc/config/riscv/riscv.cc
>> +++ b/gcc/config/riscv/riscv.cc
>> @@ -3120,35 +3120,38 @@ riscv_legitimize_move (machine_mode mode, rtx dest, 
>> rtx src)
>
>>  
>> - if (TARGET_HARD_FLOAT
>> - && !TARGET_ZFHMIN && mode == HFmode
>> - && REG_P (dest) && FP_REG_P (REGNO (dest))
>> - && REG_P (src) && !FP_REG_P (REGNO (src))
>> - && can_create_pseudo_p ())
>[ ... ]
>
>> +  if (TARGET_HARD_FLOAT
>> +  && ((!TARGET_ZFHMIN && mode == HFmode)
>> +  || (!TARGET_ZFBFMIN && mode == BFmode))
>> +  && REG_P (dest) && FP_REG_P (REGNO (dest)) && REG_P (src)
>> +  && !FP_REG_P (REGNO (src)) && can_create_pseudo_p ())
>
>So there's a bit of gratutious rewriting going on here.  I realize you
>were fixing formatting problems (thanks!), 
> but I don't see a need to rewriting the tests starting with REG_P.  I put 
> those back in their
>original form with the whitespace fixes. 
Thanks

>
>I'll push the fixed version momentarily. 
Thanks

>
>Thanks again!
>
>jeff
> 
In the past few days, I have been on vacation. Okay, let's continue to push 
forward with bf16.

Thanks
Xiao Zeng

[PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16

[Xiao Zeng]

1 This patch implements the Nan-box of bf16.

2 Please refer to the Nan-box implementation of hf16 in:


3 The discussion about Nan-box can be found on the website:


4 Below test are passed for this patch
* The riscv fully regression test.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_legitimize_move): Expand movbf
with Nan-boxing value.
* config/riscv/riscv.md (*movbf_softfloat_boxing): New pattern.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/_Bfloat16-nanboxing.c: New test.
---
 gcc/config/riscv/riscv.cc | 51 ++-
 gcc/config/riscv/riscv.md | 12 -
 .../gcc.target/riscv/_Bfloat16-nanboxing.c| 38 ++
 3 files changed, 76 insertions(+), 25 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 545e68566dc..be2cb245733 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3120,35 +3120,38 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx 
src)
 }
 
   /* In order to fit NaN boxing, expand
- (set FP_REG (reg:HF src))
+ (set FP_REG (reg:HF/BF src))
  to
  (set (reg:SI/DI mask) (const_int -65536)
- (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF src) 0)))
+ (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF/BF src) 0)))
  (set (reg:SI/DI temp) (ior:SI/DI (reg:SI/DI mask) (reg:SI/DI temp)))
- (set (reg:HF dest) (unspec:HF [ (reg:SI/DI temp) ] UNSPEC_FMV_SFP16_X))
+ (set (reg:HF/BF dest) (unspec:HF/BF[ (reg:SI/DI temp) ]
+   UNSPEC_FMV_SFP16_X/UNSPEC_FMV_SBF16_X))
  */
 
- if (TARGET_HARD_FLOAT
- && !TARGET_ZFHMIN && mode == HFmode
- && REG_P (dest) && FP_REG_P (REGNO (dest))
- && REG_P (src) && !FP_REG_P (REGNO (src))
- && can_create_pseudo_p ())
-   {
- rtx mask = force_reg (word_mode, gen_int_mode (-65536, word_mode));
- rtx temp = gen_reg_rtx (word_mode);
- emit_insn (gen_extend_insn (temp,
-simplify_gen_subreg (HImode, src, mode, 0),
-word_mode, HImode, 1));
- if (word_mode == SImode)
-   emit_insn (gen_iorsi3 (temp, mask, temp));
- else
-   emit_insn (gen_iordi3 (temp, mask, temp));
-
- riscv_emit_move (dest, gen_rtx_UNSPEC (HFmode, gen_rtvec (1, temp),
-   UNSPEC_FMV_SFP16_X));
-
- return true;
-   }
+  if (TARGET_HARD_FLOAT
+  && ((!TARGET_ZFHMIN && mode == HFmode)
+ || (!TARGET_ZFBFMIN && mode == BFmode))
+  && REG_P (dest) && FP_REG_P (REGNO (dest)) && REG_P (src)
+  && !FP_REG_P (REGNO (src)) && can_create_pseudo_p ())
+{
+  rtx mask = force_reg (word_mode, gen_int_mode (-65536, word_mode));
+  rtx temp = gen_reg_rtx (word_mode);
+  emit_insn (gen_extend_insn (temp,
+ simplify_gen_subreg (HImode, src, mode, 0),
+ word_mode, HImode, 1));
+  if (word_mode == SImode)
+   emit_insn (gen_iorsi3 (temp, mask, temp));
+  else
+   emit_insn (gen_iordi3 (temp, mask, temp));
+
+  riscv_emit_move (dest,
+  gen_rtx_UNSPEC (mode, gen_rtvec (1, temp),
+  mode == HFmode ? UNSPEC_FMV_SFP16_X
+ : UNSPEC_FMV_SBF16_X));
+
+  return true;
+}
 
   /* We need to deal with constants that would be legitimate
  immediate_operands but aren't legitimate move_operands.  */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 24558682eb8..236293e2fcd 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -86,8 +86,9 @@
   ;; String unspecs
   UNSPEC_STRLEN
 
-  ;; Workaround for HFmode without hardware extension
+  ;; Workaround for HFmode and BFmode without hardware extension
   UNSPEC_FMV_SFP16_X
+  UNSPEC_FMV_SBF16_X
 
   ;; XTheadFmv moves
   UNSPEC_XTHEADFMV
@@ -1926,6 +1927,15 @@
   [(set_attr "type" "fmove")
(set_attr "mode" "SF")])
 
+(define_insn "*movbf_softfloat_boxing"
+  [(set (match_operand:BF 0 "register_operand"   "=f")
+   (unspec:BF [(match_operand:X 1 "register_operand" " r")]
+UNSPEC_FMV_SBF16_X))]
+  "!TARGET_ZFBFMIN"
+  "fmv.w.x\t%0,%1"
+  [(set_attr "type" "fmove")
+   (set_attr "mode" "SF")])
+
 ;;
 ;;  
 ;;
diff --git a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c 
b/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
new file mode 100644
index 000..11a73d22234
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "

[PATCH v1 0/1] RISC-V: Nan-box the result of movbf on soft-bf16

[Xiao Zeng]

Compared to the initial patch:
<https://gcc.gnu.org/pipermail/gcc-patches/2024-May/650864.html>

1 Fixed the formatting issue, although the modified format can pass the
CI format check, it looks strange.

2 Due to CI not using the latest code for patch, the initial patch build failed.

3 V1 submission will trigger CI again, hoping to resolve this issue. If not, I 
will
send an email to the CI management personnel requesting them to manually run it.

4 For information about CI, you can refer to the following email conversation:
---
On 5/7/24 01:25, Xiao Zeng wrote:
> Hi, during the use of CI, I discovered a possible issue and am now providing 
> feedback to you
>
> https://github.com/ewlu/gcc-precommit-ci/issues/1481
>
> The RISCV_Nanbox_the_result_of_movbf_on_softbf16 relies on the mainline with 
> a CommitID
> of <8c7cee80eb50792e57d514be1418c453ddd1073e>, but in CI,  is used 
> as the
> parent CommitID, which obviously leads to patch compilation failure.
>
> Expect that each CI is performed on the latest code.
>
> Of course, perhaps there are other considerations here.
>
> How can I operate to enable CI to use the latest mainline code?
>
> Looking forward to your reply very much.
>
> Thanks
> Xiao Zeng
>
Hi Xiao,

Thanks for reaching out.

Currently we rely on postcommit generate a baseline of known failures:

https://github.com/patrick-rivos/gcc-postcommit-ci/issues

Precommit then applies patches to that same baseline hash and compares
the results.

We don't currently have enough compute to generate a baseline for each
patch sent to the mailing list. We'll be asking for more compute from
the RISE project in the next week or so to allow us to use the most
recent GCC hash.

What you noticed yesterday was a bad change to the postcommit-CI which
prevented a new baseline from being generated.

It's expected that precommit uses a ~8 hour old commit as a baseline. If
a patch ever requires a recent commit, feel free to email us and we'll
rerun the precommit CI once a new baseline exists.

We should have a new baseline in ~8 hours and I'll rerun your patch for
you once that happens.

Thanks,
Patrick
---

Xiao Zeng (1):
  RISC-V: Nan-box the result of movbf on soft-bf16

 gcc/config/riscv/riscv.cc | 51 ++-
 gcc/config/riscv/riscv.md | 12 -
 .../gcc.target/riscv/_Bfloat16-nanboxing.c| 38 ++
 3 files changed, 76 insertions(+), 25 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c

-- 
2.17.1

[PATCH] RISC-V: Nan-box the result of movbf on soft-bf16

[Xiao Zeng]

1 This patch implements the Nan-box of bf16.

2 Please refer to the Nan-box implementation of hf16 in:


3 The discussion about Nan-box can be found on the website:


4 Below test are passed for this patch
* The riscv fully regression test.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_legitimize_move): Expand movbf
with Nan-boxing value.
* config/riscv/riscv.md (*movbf_softfloat_boxing): New pattern.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/_Bfloat16-nanboxing.c: New test.
---
 gcc/config/riscv/riscv.cc | 51 ++-
 gcc/config/riscv/riscv.md | 11 +++-
 .../gcc.target/riscv/_Bfloat16-nanboxing.c| 38 ++
 3 files changed, 75 insertions(+), 25 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 545e68566dc..6976064b88b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3120,35 +3120,38 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx 
src)
 }
 
   /* In order to fit NaN boxing, expand
- (set FP_REG (reg:HF src))
+ (set FP_REG (reg:HF/BF src))
  to
  (set (reg:SI/DI mask) (const_int -65536)
- (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF src) 0)))
+ (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF/BF src) 0)))
  (set (reg:SI/DI temp) (ior:SI/DI (reg:SI/DI mask) (reg:SI/DI temp)))
- (set (reg:HF dest) (unspec:HF [ (reg:SI/DI temp) ] UNSPEC_FMV_SFP16_X))
+ (set (reg:HF/BF dest) (unspec:HF/BF [ (reg:SI/DI temp) ]
+   UNSPEC_FMV_SFP16_X/UNSPEC_FMV_SBF16_X))
  */
 
- if (TARGET_HARD_FLOAT
- && !TARGET_ZFHMIN && mode == HFmode
- && REG_P (dest) && FP_REG_P (REGNO (dest))
- && REG_P (src) && !FP_REG_P (REGNO (src))
- && can_create_pseudo_p ())
-   {
- rtx mask = force_reg (word_mode, gen_int_mode (-65536, word_mode));
- rtx temp = gen_reg_rtx (word_mode);
- emit_insn (gen_extend_insn (temp,
-simplify_gen_subreg (HImode, src, mode, 0),
-word_mode, HImode, 1));
- if (word_mode == SImode)
-   emit_insn (gen_iorsi3 (temp, mask, temp));
- else
-   emit_insn (gen_iordi3 (temp, mask, temp));
-
- riscv_emit_move (dest, gen_rtx_UNSPEC (HFmode, gen_rtvec (1, temp),
-   UNSPEC_FMV_SFP16_X));
-
- return true;
-   }
+  if (TARGET_HARD_FLOAT
+  && ((!TARGET_ZFHMIN && mode == HFmode)
+ || (!TARGET_ZFBFMIN && mode == BFmode))
+  && REG_P (dest) && FP_REG_P (REGNO (dest)) && REG_P (src)
+  && !FP_REG_P (REGNO (src)) && can_create_pseudo_p ())
+{
+  rtx mask = force_reg (word_mode, gen_int_mode (-65536, word_mode));
+  rtx temp = gen_reg_rtx (word_mode);
+  emit_insn (gen_extend_insn (temp,
+ simplify_gen_subreg (HImode, src, mode, 0),
+ word_mode, HImode, 1));
+  if (word_mode == SImode)
+   emit_insn (gen_iorsi3 (temp, mask, temp));
+  else
+   emit_insn (gen_iordi3 (temp, mask, temp));
+
+  riscv_emit_move (dest,
+  gen_rtx_UNSPEC (mode, gen_rtvec (1, temp),
+  mode == HFmode ? UNSPEC_FMV_SFP16_X
+ : UNSPEC_FMV_SBF16_X));
+
+  return true;
+}
 
   /* We need to deal with constants that would be legitimate
  immediate_operands but aren't legitimate move_operands.  */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 24558682eb8..b34043bc6b8 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -86,8 +86,9 @@
   ;; String unspecs
   UNSPEC_STRLEN
 
-  ;; Workaround for HFmode without hardware extension
+  ;; Workaround for HFmode and BFmode without hardware extension
   UNSPEC_FMV_SFP16_X
+  UNSPEC_FMV_SBF16_X
 
   ;; XTheadFmv moves
   UNSPEC_XTHEADFMV
@@ -1926,6 +1927,14 @@
   [(set_attr "type" "fmove")
(set_attr "mode" "SF")])
 
+(define_insn "*movbf_softfloat_boxing"
+  [(set (match_operand:BF 0 "register_operand"   "=f")
+   (unspec:BF [(match_operand:X 1 "register_operand" " r")] 
UNSPEC_FMV_SBF16_X))]
+  "!TARGET_ZFBFMIN"
+  "fmv.w.x\t%0,%1"
+  [(set_attr "type" "fmove")
+   (set_attr "mode" "SF")])
+
 ;;
 ;;  
 ;;
diff --git a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c 
b/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
new file mode 100644
index 000..11a73d22234
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=r

Re: Re: [PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= option

[Xiao Zeng]

2024-05-07 06:40  Jeff Law  wrote:
>
 
>
>
>On 4/11/24 9:32 PM, Xiao Zeng wrote:
>> This patch would like to add new sub extension (aka Zfbfmin) to the
>> -march= option. It introduces a new data type BF16.
>>
>> 1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and
>> FMV.H.X instructions as defined in the Zfh extension.
>>
>> 2 The Zfhmin extension includes the following instructions from the
>> Zfh extension: FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S.
>>
>> 3 Zfhmin extension depend on 'F'.
>>
>> 4 Simply put, just make Zfbfmin dependent on Zfhmin.
>>
>> Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and
>> FMV.H.X instructions an independent extension to achieve precise dependency
>> relationships for the Zfbfmin.
>>
>> You can locate more information about Zfbfmin from below spec doc.
>>
>> <https://github.com/riscv/riscv-bfloat16/releases/download/v59042fc71c31a9bcb2f1957621c960ed36fac401/riscv-bfloat16.pdf>
>>
>> Below test are passed for this patch
>>  * The riscv fully regression test.
>I wrote a suitable ChangeLog entry and pushed this patch to the trunk. 
Thanks, jeff

>
>THanks,
>jeff
>
 
Thanks
Xiao Zeng

[NOT CODE REVIEW] [PATCH v3 1/1] [RISC-V] Add support for _Bfloat16

[Xiao Zeng]

1 At point ,
  BF16 has already been completed "post public review".

2 LLVM has also added support for RISCV BF16 in
   and
  .

3 According to the discussion 
,
  this use __bf16 and use DF16b in riscv_mangle_type like x86.

Below test are passed for this patch
* The riscv fully regression test.

gcc/ChangeLog:

* config/riscv/iterators.md: New mode iterator HFBF.
* config/riscv/riscv-builtins.cc (riscv_init_builtin_types):
Initialize data type _Bfloat16.
* config/riscv/riscv-modes.def (FLOAT_MODE): New.
(ADJUST_FLOAT_FORMAT): New.
* config/riscv/riscv.cc (riscv_mangle_type): Support for BFmode.
(riscv_scalar_mode_supported_p): Ditto.
(riscv_libgcc_floating_mode_supported_p): Ditto.
(riscv_init_libfuncs): Set the conversion method for BFmode and
HFmode.
(riscv_block_arith_comp_libfuncs_for_mode): Set the arithmetic
and comparison libfuncs for the mode.
* config/riscv/riscv.md (mode" ): Add BF.
(movhf): Support for BFmode.
(mov): Ditto.
(*movhf_softfloat): Ditto.
(*mov_softfloat): Ditto.

libgcc/ChangeLog:

* config/riscv/sfp-machine.h (_FP_NANFRAC_B): New.
(_FP_NANSIGN_B): Ditto.
* config/riscv/t-softfp32: Add support for BF16 libfuncs.
* config/riscv/t-softfp64: Ditto.
* soft-fp/floatsibf.c: For si -> bf16.
* soft-fp/floatunsibf.c: For unsi -> bf16.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/bf16_arithmetic.c: New test.
* gcc.target/riscv/bf16_call.c: New test.
* gcc.target/riscv/bf16_comparison.c: New test.
* gcc.target/riscv/bf16_float_libcall_convert.c: New test.
* gcc.target/riscv/bf16_integer_libcall_convert.c: New test.

Co-authored-by: Jin Ma 
---
 gcc/config/riscv/iterators.md |  2 +
 gcc/config/riscv/riscv-builtins.cc| 16 
 gcc/config/riscv/riscv-modes.def  |  3 +
 gcc/config/riscv/riscv.cc | 64 ++-
 gcc/config/riscv/riscv.md | 24 +++---
 .../gcc.target/riscv/bf16_arithmetic.c| 42 ++
 gcc/testsuite/gcc.target/riscv/bf16_call.c| 12 +++
 .../gcc.target/riscv/bf16_comparison.c| 36 +
 .../riscv/bf16_float_libcall_convert.c| 57 +
 .../riscv/bf16_integer_libcall_convert.c  | 81 +++
 libgcc/config/riscv/sfp-machine.h |  3 +
 libgcc/config/riscv/t-softfp32| 10 ++-
 libgcc/config/riscv/t-softfp64|  3 +-
 libgcc/soft-fp/floatsibf.c| 45 +++
 libgcc/soft-fp/floatunsibf.c  | 45 +++
 15 files changed, 407 insertions(+), 36 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_call.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_comparison.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c
 create mode 100644 libgcc/soft-fp/floatsibf.c
 create mode 100644 libgcc/soft-fp/floatunsibf.c

diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 75e119e407a..32e1b140305 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -75,6 +75,8 @@
 ;; Iterator for floating-point modes that can be loaded into X registers.
 (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
 
+;; Iterator for floating-point modes of BF16
+(define_mode_iterator HFBF [HF BF])
 
 ;; ---
 ;; Mode attributes
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index d457e306dd1..4c08834288a 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -230,6 +230,7 @@ static GTY(()) int riscv_builtin_decl_index[NUM_INSN_CODES];
   riscv_builtin_decls[riscv_builtin_decl_index[(CODE)]]
 
 tree riscv_float16_type_node = NULL_TREE;
+tree riscv_bfloat16_type_node = NULL_TREE;
 
 /* Return the function type associated with function prototype TYPE.  */
 
@@ -273,6 +274,21 @@ riscv_init_builtin_types (void)
   if (!maybe_get_identifier ("_Float16"))
 lang_hooks.types.register_builtin_type (riscv_float16_type_node,
"_Float16");
+
+  /* Provide the _Bfloat16 type and bfloat16_type_node if needed.  */
+  if (!bfloat16_type_node)
+{
+  riscv_bfloat16_type_node = make_node (REAL_TYPE);
+  TYPE_PRECISION (riscv_bfloat16_type_node) = 16;
+  SET_TYPE_MODE (riscv_bfloat16_type_node, BFmode);
+  layout_type (riscv_bfloat16_type_node);
+ 

[NOT CODE REVIEW] [PATCH v3 0/1] [RISC-V] Add support for _Bfloat16

[Xiao Zeng]

This v3 submission is only for testing whether the code meets the
format requirements of CI.

The CI testing website is located at: 
<https://patchwork.sourceware.org/project/gcc/patch/20240402092210.80779-2-zengx...@eswincomputing.com/>

If satisfied, this code will be immediately pushed into trunk.

Detailed information can be found: 
<https://gcc.gnu.org/pipermail/gcc-patches/2024-May/650716.html>

Xiao Zeng (1):
  [RISC-V] Add support for _Bfloat16

 gcc/config/riscv/iterators.md |  2 +
 gcc/config/riscv/riscv-builtins.cc| 16 
 gcc/config/riscv/riscv-modes.def  |  3 +
 gcc/config/riscv/riscv.cc | 64 ++-
 gcc/config/riscv/riscv.md | 24 +++---
 .../gcc.target/riscv/bf16_arithmetic.c| 42 ++
 gcc/testsuite/gcc.target/riscv/bf16_call.c| 12 +++
 .../gcc.target/riscv/bf16_comparison.c| 36 +
 .../riscv/bf16_float_libcall_convert.c| 57 +
 .../riscv/bf16_integer_libcall_convert.c  | 81 +++
 libgcc/config/riscv/sfp-machine.h |  3 +
 libgcc/config/riscv/t-softfp32| 10 ++-
 libgcc/config/riscv/t-softfp64|  3 +-
 libgcc/soft-fp/floatsibf.c| 45 +++
 libgcc/soft-fp/floatunsibf.c  | 45 +++
 15 files changed, 407 insertions(+), 36 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_call.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_comparison.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c
 create mode 100644 libgcc/soft-fp/floatsibf.c
 create mode 100644 libgcc/soft-fp/floatunsibf.c

-- 
2.17.1

Re: Re: [PATCH v2 1/1] [RISC-V] Add support for _Bfloat16

[Xiao Zeng]

2024-05-04 23:23  Jeff Law  wrote:
>
 
>
>
>On 4/2/24 3:22 AM, Xiao Zeng wrote:
>> 1 At point <https://github.com/riscv/riscv-bfloat16>,
>>    BF16 has already been completed "post public review".
>>
>> 2 LLVM has also added support for RISCV BF16 in
>> <https://reviews.llvm.org/D151313> and
>> <https://reviews.llvm.org/D150929>.
>>
>> 3 According to the discussion 
>> <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/367>,
>>    this use __bf16 and use DF16b in riscv_mangle_type like x86.
>>
>> Below test are passed for this patch
>>  * The riscv fully regression test.
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/iterators.md: New mode iterator HFBF.
>> * config/riscv/riscv-builtins.cc (riscv_init_builtin_types):
>> Initialize data type _Bfloat16.
>> * config/riscv/riscv-modes.def (FLOAT_MODE): New.
>> (ADJUST_FLOAT_FORMAT): New.
>> * config/riscv/riscv.cc (riscv_mangle_type): Support for BFmode.
>> (riscv_scalar_mode_supported_p): Ditto.
>> (riscv_libgcc_floating_mode_supported_p): Ditto.
>> (riscv_init_libfuncs): Set the conversion method for BFmode and
>> HFmode.
>> (riscv_block_arith_comp_libfuncs_for_mode): Set the arithmetic
>> and comparison libfuncs for the mode.
>> * config/riscv/riscv.md (mode" ): Add BF.
>> (movhf): Support for BFmode.
>> (mov): Ditto.
>> (*movhf_softfloat): Ditto.
>> (*mov_softfloat): Ditto.
>>
>> libgcc/ChangeLog:
>>
>> * config/riscv/sfp-machine.h (_FP_NANFRAC_B): New.
>> (_FP_NANSIGN_B): Ditto.
>> * config/riscv/t-softfp32: Add support for BF16 libfuncs.
>> * config/riscv/t-softfp64: Ditto.
>> * soft-fp/floatsibf.c: For si -> bf16.
>> * soft-fp/floatunsibf.c: For unsi -> bf16.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/bf16_arithmetic.c: New test.
>> * gcc.target/riscv/bf16_call.c: New test.
>> * gcc.target/riscv/bf16_comparison.c: New test.
>> * gcc.target/riscv/bf16_float_libcall_convert.c: New test.
>> * gcc.target/riscv/bf16_integer_libcall_convert.c: New test.
>Just some nits.  In t-softfp32 and t-softfp64 the code you've added
>should be using tabs, not 8 spaces, as noted by the CI "Lint Status":
>
>https://github.com/ewlu/gcc-precommit-ci/issues/1412#issuecomment-2031568644
In the future, my patch will strictly adhere to the formatting suggestions 
provided by CI.

>
>With that fixed, this is fine for the trunk.  No need to repost, 
>go ahead and commit.
Currently, I do not have commit permission. Can I have this permission?

>
>Thanks for your patience,
>Jeff
 
Thanks
Xiao Zeng

[PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= option

[Xiao Zeng]

This patch would like to add new sub extension (aka Zfbfmin) to the
-march= option. It introduces a new data type BF16.

1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and
FMV.H.X instructions as defined in the Zfh extension.

2 The Zfhmin extension includes the following instructions from the
Zfh extension: FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S.

3 Zfhmin extension depend on 'F'.

4 Simply put, just make Zfbfmin dependent on Zfhmin.

Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and
FMV.H.X instructions an independent extension to achieve precise dependency
relationships for the Zfbfmin.

You can locate more information about Zfbfmin from below spec doc.



Below test are passed for this patch
* The riscv fully regression test.
---
 gcc/common/config/riscv/riscv-common.cc|  3 ++
 gcc/config/riscv/riscv.opt |  2 +
 gcc/testsuite/gcc.target/riscv/arch-35.c   |  5 +++
 gcc/testsuite/gcc.target/riscv/arch-36.c   |  5 +++
 gcc/testsuite/gcc.target/riscv/predef-34.c | 47 ++
 gcc/testsuite/gcc.target/riscv/predef-35.c | 47 ++
 6 files changed, 109 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-35.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-36.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-34.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-35.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 43b7549e3ec..49c4783eaf2 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -155,6 +155,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zvksed", "zve32x"},
   {"zvksh",  "zve32x"},
 
+  {"zfbfmin", "zfhmin"},
   {"zfh", "zfhmin"},
   {"zfhmin", "f"},
 
@@ -331,6 +332,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zfbfmin",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvfbfmin",  ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1698,6 +1700,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B},
   {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B},
 
+  {"zfbfmin",   &gcc_options::x_riscv_zf_subext, MASK_ZFBFMIN},
   {"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
   {"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
   {"zvfbfmin",  &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN},
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 8da0764eb4b..5c96e951d45 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -393,6 +393,8 @@ Mask(ZICBOP) Var(riscv_zicmo_subext)
 TargetVariable
 int riscv_zf_subext
 
+Mask(ZFBFMIN)  Var(riscv_zf_subext)
+
 Mask(ZFHMIN)  Var(riscv_zf_subext)
 
 Mask(ZFH) Var(riscv_zf_subext)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-35.c 
b/gcc/testsuite/gcc.target/riscv/arch-35.c
new file mode 100644
index 000..6c783769666
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-35.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zfbfmin -mabi=ilp32f" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-36.c 
b/gcc/testsuite/gcc.target/riscv/arch-36.c
new file mode 100644
index 000..cbdccf12807
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-36.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zfbfmin -mabi=lp64f" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-34.c 
b/gcc/testsuite/gcc.target/riscv/predef-34.c
new file mode 100644
index 000..0a993271f7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-34.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32i_zfbfmin -mabi=ilp32f -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 32
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_zfhmin)
+#error "__riscv_zfhmin"
+#endif
+
+#if !defined(__riscv_zfbfmin)
+#error "__riscv_zfbfmin"
+#endif
+
+#if defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-35.c 
b/gcc/testsuite/gcc.target/riscv/predef-35.c
new file mode 100644
index 000..76b328a8932
--- /dev/null
++

Re: Re:[PATCH v2 1/1] [RISC-V] Add support for _Bfloat16

[Xiao Zeng]

2024-04-03 11:19  Jin Ma  wrote:
>
 
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/bf16_arithmetic.c: New test.
>> * gcc.target/riscv/bf16_call.c: New test.
>> * gcc.target/riscv/bf16_comparison.c: New test.
>> * gcc.target/riscv/bf16_float_libcall_convert.c: New test.
>> * gcc.target/riscv/bf16_integer_libcall_convert.c: New test.
>
>  Hi, I have test this patch and it is very good. I think we need to add some
>runable tests to ensure that the results are right for various types of
>conversions, operations, and libfuncs. 
Yes, we must ensure that running tests is also feasible.

A great testcase has already been provided in the gcc test suite: 
gcc/testsuite/g++.dg/cpp23/ext-floating14.C

So, I didn't add any test cases to run the tests.
>
>BR,
>Jin
 
Thanks
Xiao Zeng

[PATCH v2 1/1] [RISC-V] Add support for _Bfloat16

[Xiao Zeng]

1 At point ,
  BF16 has already been completed "post public review".

2 LLVM has also added support for RISCV BF16 in
   and
  .

3 According to the discussion 
,
  this use __bf16 and use DF16b in riscv_mangle_type like x86.

Below test are passed for this patch
* The riscv fully regression test.

gcc/ChangeLog:

* config/riscv/iterators.md: New mode iterator HFBF.
* config/riscv/riscv-builtins.cc (riscv_init_builtin_types):
Initialize data type _Bfloat16.
* config/riscv/riscv-modes.def (FLOAT_MODE): New.
(ADJUST_FLOAT_FORMAT): New.
* config/riscv/riscv.cc (riscv_mangle_type): Support for BFmode.
(riscv_scalar_mode_supported_p): Ditto.
(riscv_libgcc_floating_mode_supported_p): Ditto.
(riscv_init_libfuncs): Set the conversion method for BFmode and
HFmode.
(riscv_block_arith_comp_libfuncs_for_mode): Set the arithmetic
and comparison libfuncs for the mode.
* config/riscv/riscv.md (mode" ): Add BF.
(movhf): Support for BFmode.
(mov): Ditto.
(*movhf_softfloat): Ditto.
(*mov_softfloat): Ditto.

libgcc/ChangeLog:

* config/riscv/sfp-machine.h (_FP_NANFRAC_B): New.
(_FP_NANSIGN_B): Ditto.
* config/riscv/t-softfp32: Add support for BF16 libfuncs.
* config/riscv/t-softfp64: Ditto.
* soft-fp/floatsibf.c: For si -> bf16.
* soft-fp/floatunsibf.c: For unsi -> bf16.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/bf16_arithmetic.c: New test.
* gcc.target/riscv/bf16_call.c: New test.
* gcc.target/riscv/bf16_comparison.c: New test.
* gcc.target/riscv/bf16_float_libcall_convert.c: New test.
* gcc.target/riscv/bf16_integer_libcall_convert.c: New test.

Co-authored-by: Jin Ma 
---
 gcc/config/riscv/iterators.md |  2 +
 gcc/config/riscv/riscv-builtins.cc| 16 
 gcc/config/riscv/riscv-modes.def  |  3 +
 gcc/config/riscv/riscv.cc | 64 ++-
 gcc/config/riscv/riscv.md | 24 +++---
 .../gcc.target/riscv/bf16_arithmetic.c| 42 ++
 gcc/testsuite/gcc.target/riscv/bf16_call.c| 12 +++
 .../gcc.target/riscv/bf16_comparison.c| 36 +
 .../riscv/bf16_float_libcall_convert.c| 57 +
 .../riscv/bf16_integer_libcall_convert.c  | 81 +++
 libgcc/config/riscv/sfp-machine.h |  3 +
 libgcc/config/riscv/t-softfp32| 10 ++-
 libgcc/config/riscv/t-softfp64|  3 +-
 libgcc/soft-fp/floatsibf.c| 45 +++
 libgcc/soft-fp/floatunsibf.c  | 45 +++
 15 files changed, 407 insertions(+), 36 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_call.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_comparison.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c
 create mode 100644 libgcc/soft-fp/floatsibf.c
 create mode 100644 libgcc/soft-fp/floatunsibf.c

diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index a7694137685..40bf20f42bb 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -75,6 +75,8 @@
 ;; Iterator for floating-point modes that can be loaded into X registers.
 (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
 
+;; Iterator for floating-point modes of BF16
+(define_mode_iterator HFBF [HF BF])
 
 ;; ---
 ;; Mode attributes
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index d457e306dd1..4c08834288a 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -230,6 +230,7 @@ static GTY(()) int riscv_builtin_decl_index[NUM_INSN_CODES];
   riscv_builtin_decls[riscv_builtin_decl_index[(CODE)]]
 
 tree riscv_float16_type_node = NULL_TREE;
+tree riscv_bfloat16_type_node = NULL_TREE;
 
 /* Return the function type associated with function prototype TYPE.  */
 
@@ -273,6 +274,21 @@ riscv_init_builtin_types (void)
   if (!maybe_get_identifier ("_Float16"))
 lang_hooks.types.register_builtin_type (riscv_float16_type_node,
"_Float16");
+
+  /* Provide the _Bfloat16 type and bfloat16_type_node if needed.  */
+  if (!bfloat16_type_node)
+{
+  riscv_bfloat16_type_node = make_node (REAL_TYPE);
+  TYPE_PRECISION (riscv_bfloat16_type_node) = 16;
+  SET_TYPE_MODE (riscv_bfloat16_type_node, BFmode);
+  layout_type (riscv_bfloat16_type_node);
+ 

[PATCH v2 0/1] [RISC-V] Add support for _Bfloat16

[Xiao Zeng]

Hi all RISC-V folks:

This patch completes the support for the bf16 data type in the
riscv architecture.On this basis, there will be a series of
patches in the future to strengthen support for BF16.

It is recommended to first review this patch from the testcases,
where detailed explanations have been provided on the flow of
data type conversion.

The basis of this patch is: 
<https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630858.html>

The website for the first patch submission is: 
<https://gcc.gnu.org/pipermail/gcc-patches/2024-March/648517.html>

However, considering the non-standard commit information, this
submission was made.

Patch v2 fixed failed test cases.

*** BLURB HERE ***

Xiao Zeng (1):
  [RISC-V] Add support for _Bfloat16

 gcc/config/riscv/iterators.md |  2 +
 gcc/config/riscv/riscv-builtins.cc| 16 
 gcc/config/riscv/riscv-modes.def  |  3 +
 gcc/config/riscv/riscv.cc | 64 ++-
 gcc/config/riscv/riscv.md | 24 +++---
 .../gcc.target/riscv/bf16_arithmetic.c| 42 ++
 gcc/testsuite/gcc.target/riscv/bf16_call.c| 12 +++
 .../gcc.target/riscv/bf16_comparison.c| 36 +
 .../riscv/bf16_float_libcall_convert.c| 57 +
 .../riscv/bf16_integer_libcall_convert.c  | 81 +++
 libgcc/config/riscv/sfp-machine.h |  3 +
 libgcc/config/riscv/t-softfp32| 10 ++-
 libgcc/config/riscv/t-softfp64|  3 +-
 libgcc/soft-fp/floatsibf.c| 45 +++
 libgcc/soft-fp/floatunsibf.c  | 45 +++
 15 files changed, 407 insertions(+), 36 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_call.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_comparison.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c
 create mode 100644 libgcc/soft-fp/floatsibf.c
 create mode 100644 libgcc/soft-fp/floatunsibf.c

-- 
2.17.1

[PATCH 1/1] [RISC-V] Add support for _Bfloat16

[Xiao Zeng]

1 At point ,
  BF16 has already been completed "post public review".

2 LLVM has also added support for RISCV BF16 in
   and
  .

3 According to the discussion 
,
  this use __bf16 and use DF16b in riscv_mangle_type like x86.

Below test are passed for this patch
* The riscv fully regression test.

gcc/ChangeLog:

* config/riscv/iterators.md: New mode iterator HFBF.
* config/riscv/riscv-builtins.cc (riscv_init_builtin_types):
Initialize data type _Bfloat16.
* config/riscv/riscv-modes.def (FLOAT_MODE): New.
(ADJUST_FLOAT_FORMAT): New.
* config/riscv/riscv.cc (riscv_mangle_type): Support for BFmode.
(riscv_scalar_mode_supported_p): Ditto.
(riscv_libgcc_floating_mode_supported_p): Ditto.
(riscv_init_libfuncs): Set the conversion method for BFmode and
HFmode.
(riscv_block_arith_comp_libfuncs_for_mode): Set the arithmetic
and comparison libfuncs for the mode.
* config/riscv/riscv.md (mode" ): Add BF.
(movhf): Support for BFmode.
(mov): Ditto.
(*movhf_softfloat): Ditto.
(*mov_softfloat): Ditto.

libgcc/ChangeLog:

* config/riscv/sfp-machine.h (_FP_NANFRAC_B): New.
(_FP_NANSIGN_B): Ditto.
* config/riscv/t-softfp32: Add support for BF16 libfuncs.
* config/riscv/t-softfp64: Ditto.
* soft-fp/floatsibf.c: For si -> bf16.
* soft-fp/floatunsibf.c: For unsi -> bf16.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/bf16_arithmetic.c: New test.
* gcc.target/riscv/bf16_call.c: New test.
* gcc.target/riscv/bf16_comparison.c: New test.
* gcc.target/riscv/bf16_float_libcall_convert.c: New test.
* gcc.target/riscv/bf16_integer_libcall_convert.c: New test.

Co-authored-by: Jin Ma 
---
 gcc/config/riscv/iterators.md |  2 +
 gcc/config/riscv/riscv-builtins.cc| 16 
 gcc/config/riscv/riscv-modes.def  |  3 +
 gcc/config/riscv/riscv.cc | 64 ++-
 gcc/config/riscv/riscv.md | 24 +++---
 .../gcc.target/riscv/bf16_arithmetic.c| 42 ++
 gcc/testsuite/gcc.target/riscv/bf16_call.c| 12 +++
 .../gcc.target/riscv/bf16_comparison.c| 36 +
 .../riscv/bf16_float_libcall_convert.c| 57 +
 .../riscv/bf16_integer_libcall_convert.c  | 81 +++
 libgcc/config/riscv/sfp-machine.h |  3 +
 libgcc/config/riscv/t-softfp32| 10 ++-
 libgcc/config/riscv/t-softfp64|  3 +-
 libgcc/soft-fp/floatsibf.c| 45 +++
 libgcc/soft-fp/floatunsibf.c  | 45 +++
 15 files changed, 407 insertions(+), 36 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_call.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_comparison.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c
 create mode 100644 libgcc/soft-fp/floatsibf.c
 create mode 100644 libgcc/soft-fp/floatunsibf.c

diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index a7694137685..40bf20f42bb 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -75,6 +75,8 @@
 ;; Iterator for floating-point modes that can be loaded into X registers.
 (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
 
+;; Iterator for floating-point modes of BF16
+(define_mode_iterator HFBF [HF BF])
 
 ;; ---
 ;; Mode attributes
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index d457e306dd1..4c08834288a 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -230,6 +230,7 @@ static GTY(()) int riscv_builtin_decl_index[NUM_INSN_CODES];
   riscv_builtin_decls[riscv_builtin_decl_index[(CODE)]]
 
 tree riscv_float16_type_node = NULL_TREE;
+tree riscv_bfloat16_type_node = NULL_TREE;
 
 /* Return the function type associated with function prototype TYPE.  */
 
@@ -273,6 +274,21 @@ riscv_init_builtin_types (void)
   if (!maybe_get_identifier ("_Float16"))
 lang_hooks.types.register_builtin_type (riscv_float16_type_node,
"_Float16");
+
+  /* Provide the _Bfloat16 type and bfloat16_type_node if needed.  */
+  if (!bfloat16_type_node)
+{
+  riscv_bfloat16_type_node = make_node (REAL_TYPE);
+  TYPE_PRECISION (riscv_bfloat16_type_node) = 16;
+  SET_TYPE_MODE (riscv_bfloat16_type_node, BFmode);
+  layout_type (riscv_bfloat16_type_node);
+ 

[PATCH 0/1] [RISC-V] Add support for _Bfloat16

[Xiao Zeng]

Hi all RISC-V folks:

This patch completes the support for the bf16 data type in the
riscv architecture.On this basis, there will be a series of
patches in the future to strengthen support for BF16.

It is recommended to first review this patch from the testcases,
where detailed explanations have been provided on the flow of
data type conversion.

The basis of this patch is: 
<https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630858.html>

The website for the first patch submission is: 
<https://gcc.gnu.org/pipermail/gcc-patches/2024-March/648517.html>

However, considering the non-standard commit information, this
submission was made.

Xiao Zeng (1):
  [RISC-V] Add support for _Bfloat16

 gcc/config/riscv/iterators.md |  2 +
 gcc/config/riscv/riscv-builtins.cc| 16 
 gcc/config/riscv/riscv-modes.def  |  3 +
 gcc/config/riscv/riscv.cc | 64 ++-
 gcc/config/riscv/riscv.md | 24 +++---
 .../gcc.target/riscv/bf16_arithmetic.c| 42 ++
 gcc/testsuite/gcc.target/riscv/bf16_call.c| 12 +++
 .../gcc.target/riscv/bf16_comparison.c| 36 +
 .../riscv/bf16_float_libcall_convert.c| 57 +
 .../riscv/bf16_integer_libcall_convert.c  | 81 +++
 libgcc/config/riscv/sfp-machine.h |  3 +
 libgcc/config/riscv/t-softfp32| 10 ++-
 libgcc/config/riscv/t-softfp64|  3 +-
 libgcc/soft-fp/floatsibf.c| 45 +++
 libgcc/soft-fp/floatunsibf.c  | 45 +++
 15 files changed, 407 insertions(+), 36 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_call.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_comparison.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c
 create mode 100644 libgcc/soft-fp/floatsibf.c
 create mode 100644 libgcc/soft-fp/floatunsibf.c

-- 
2.17.1

[PATCH 1/1] [RISCV] Add support for _Bfloat16

[Xiao Zeng]

1 At point ,
  BF16 has already been completed "post public review".

2 LLVM has also added support for RISCV BF16 in
   and
  .

3 According to the discussion 
,
  this use __bf16 and use DF16b in riscv_mangle_type like x86.

Below test are passed for this patch
* The riscv fully regression test.

gcc/ChangeLog:

* config/riscv/iterators.md: New mode iterator HFBF.
* config/riscv/riscv-builtins.cc (riscv_init_builtin_types):
Initialize data type _Bfloat16.
* config/riscv/riscv-modes.def (FLOAT_MODE): New.
(ADJUST_FLOAT_FORMAT): New.
* config/riscv/riscv.cc (riscv_mangle_type): Support for BFmode.
(riscv_scalar_mode_supported_p): Ditto.
(riscv_libgcc_floating_mode_supported_p): Ditto.
(riscv_init_libfuncs): Set the conversion method for BFmode and
HFmode.
(riscv_block_arith_comp_libfuncs_for_mode): Set the arithmetic
and comparison libfuncs for the mode.
* config/riscv/riscv.md (mode" ): Add BF.
(movhf): Support for BFmode.
(mov): Ditto.
(*movhf_softfloat): Ditto.
(*mov_softfloat): Ditto.

libgcc/ChangeLog:

* config/riscv/sfp-machine.h (_FP_NANFRAC_B): New.
(_FP_NANSIGN_B): Ditto.
* config/riscv/t-softfp32: Add support for BF16 libfuncs.
* config/riscv/t-softfp64: Ditto.
* soft-fp/floatsibf.c: For si -> bf16.
* soft-fp/floatunsibf.c: For unsi -> bf16.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/bf16_arithmetic.c: New test.
* gcc.target/riscv/bf16_call.c: New test.
* gcc.target/riscv/bf16_comparison.c: New test.
* gcc.target/riscv/bf16_float_libcall_convert.c: New test.
* gcc.target/riscv/bf16_integer_libcall_convert.c: New test.

Co-authored-by: Jin Ma 
---
 gcc/config/riscv/iterators.md |  2 +
 gcc/config/riscv/riscv-builtins.cc| 16 
 gcc/config/riscv/riscv-modes.def  |  3 +
 gcc/config/riscv/riscv.cc | 64 ++-
 gcc/config/riscv/riscv.md | 24 +++---
 .../gcc.target/riscv/bf16_arithmetic.c| 42 ++
 gcc/testsuite/gcc.target/riscv/bf16_call.c| 12 +++
 .../gcc.target/riscv/bf16_comparison.c| 36 +
 .../riscv/bf16_float_libcall_convert.c| 57 +
 .../riscv/bf16_integer_libcall_convert.c  | 81 +++
 libgcc/config/riscv/sfp-machine.h |  3 +
 libgcc/config/riscv/t-softfp32| 10 ++-
 libgcc/config/riscv/t-softfp64|  3 +-
 libgcc/soft-fp/floatsibf.c| 45 +++
 libgcc/soft-fp/floatunsibf.c  | 45 +++
 15 files changed, 407 insertions(+), 36 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_call.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_comparison.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c
 create mode 100644 libgcc/soft-fp/floatsibf.c
 create mode 100644 libgcc/soft-fp/floatunsibf.c

diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index a7694137685..40bf20f42bb 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -75,6 +75,8 @@
 ;; Iterator for floating-point modes that can be loaded into X registers.
 (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
 
+;; Iterator for floating-point modes of BF16
+(define_mode_iterator HFBF [HF BF])
 
 ;; ---
 ;; Mode attributes
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index d457e306dd1..4c08834288a 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -230,6 +230,7 @@ static GTY(()) int riscv_builtin_decl_index[NUM_INSN_CODES];
   riscv_builtin_decls[riscv_builtin_decl_index[(CODE)]]
 
 tree riscv_float16_type_node = NULL_TREE;
+tree riscv_bfloat16_type_node = NULL_TREE;
 
 /* Return the function type associated with function prototype TYPE.  */
 
@@ -273,6 +274,21 @@ riscv_init_builtin_types (void)
   if (!maybe_get_identifier ("_Float16"))
 lang_hooks.types.register_builtin_type (riscv_float16_type_node,
"_Float16");
+
+  /* Provide the _Bfloat16 type and bfloat16_type_node if needed.  */
+  if (!bfloat16_type_node)
+{
+  riscv_bfloat16_type_node = make_node (REAL_TYPE);
+  TYPE_PRECISION (riscv_bfloat16_type_node) = 16;
+  SET_TYPE_MODE (riscv_bfloat16_type_node, BFmode);
+  layout_type (riscv_bfloat16_type_node);
+ 

[PATCH 0/1] [RISCV] Add support for _Bfloat16

[Xiao Zeng]

Hi all RISC-V folks:

This patch completes the support for the bf16 data type in the 
riscv architecture.On this basis, there will be a series of
patches in the future to strengthen support for BF16.

It is recommended to first review this patch from the testcases,
where detailed explanations have been provided on the flow of
data type conversion.

The basis of this patch is: 
<https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630858.html>

Xiao Zeng (1):
  [RISCV] Add support for _Bfloat16

 gcc/config/riscv/iterators.md |  2 +
 gcc/config/riscv/riscv-builtins.cc| 16 
 gcc/config/riscv/riscv-modes.def  |  3 +
 gcc/config/riscv/riscv.cc | 64 ++-
 gcc/config/riscv/riscv.md | 24 +++---
 .../gcc.target/riscv/bf16_arithmetic.c| 42 ++
 gcc/testsuite/gcc.target/riscv/bf16_call.c| 12 +++
 .../gcc.target/riscv/bf16_comparison.c| 36 +
 .../riscv/bf16_float_libcall_convert.c| 57 +
 .../riscv/bf16_integer_libcall_convert.c  | 81 +++
 libgcc/config/riscv/sfp-machine.h |  3 +
 libgcc/config/riscv/t-softfp32| 10 ++-
 libgcc/config/riscv/t-softfp64|  3 +-
 libgcc/soft-fp/floatsibf.c| 45 +++
 libgcc/soft-fp/floatunsibf.c  | 45 +++
 15 files changed, 407 insertions(+), 36 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_call.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_comparison.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/bf16_float_libcall_convert.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/bf16_integer_libcall_convert.c
 create mode 100644 libgcc/soft-fp/floatsibf.c
 create mode 100644 libgcc/soft-fp/floatunsibf.c

-- 
2.17.1

Re: Re: [PATCH] RISC-V: Add Zvfbfmin extension to the -march= option

[Xiao Zeng]

2023-12-16 03:27  Jeff Law  wrote:
>
 
>
>
>On 12/12/23 20:24, Xiao Zeng wrote:
>> This patch would like to add new sub extension (aka Zvfbfmin) to the
>> -march= option. It introduces a new data type BF16.
>>
>> Depending on different usage scenarios, the Zvfbfmin extension may
>> depend on 'V' or 'Zve32f'. This patch only implements dependencies
>> in scenario of Embedded Processor. In scenario of Application
>> Processor, it is necessary to explicitly indicate the dependent
>> 'V' extension.
>>
>> You can locate more information about Zvfbfmin from below spec doc.
>>
>> https://github.com/riscv/riscv-bfloat16/releases/download/20231027/riscv-bfloat16.pdf
>>
>> gcc/ChangeLog:
>>
>> * common/config/riscv/riscv-common.cc:
>> (riscv_implied_info): Add zvfbfmin item.
>>  (riscv_ext_version_table): Ditto.
>>  (riscv_ext_flag_table): Ditto.
>> * config/riscv/riscv.opt:
>> (MASK_ZVFBFMIN): New macro.
>> (MASK_VECTOR_ELEN_BF_16): Ditto.
>> (TARGET_ZVFBFMIN): Ditto.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/arch-31.c: New test.
>> * gcc.target/riscv/arch-32.c: New test.
>> * gcc.target/riscv/predef-32.c: New test.
>> * gcc.target/riscv/predef-33.c: New test.
>I fixed the trivial whitespace issue with the ChangeLog and pushed this
>to the trunk. 
Thank you, Jeff. I will pay attention to these issues in the future patches.

>However, I do want to stress that all future
>contributions need to indicate that the patch was successfully
>regression tested. 
Similarly, this should also be indicated.

>
>jeff
 
Thanks
Xiao Zeng

Re: Re: [PATCH] RISC-V: Add Zvfbfmin extension to the -march= option

[Xiao Zeng]

len_flags)
>>
>> +Mask(VECTOR_ELEN_BF_16) Var(riscv_vector_elen_flags)
>> +
>>  TargetVariable
>>  int riscv_zvl_flags
>>
>> @@ -366,6 +368,8 @@ Mask(ZFHMIN)  Var(riscv_zf_subext)
>>
>>  Mask(ZFH) Var(riscv_zf_subext)
>>
>> +Mask(ZVFBFMIN) Var(riscv_zf_subext)
>> +
>>  Mask(ZVFHMIN) Var(riscv_zf_subext)
>>
>>  Mask(ZVFH)    Var(riscv_zf_subext)
>> diff --git a/gcc/testsuite/gcc.target/riscv/arch-31.c 
>> b/gcc/testsuite/gcc.target/riscv/arch-31.c
>> new file mode 100644
>> index 000..5180753b905
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/arch-31.c
>> @@ -0,0 +1,5 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-march=rv32i_zvfbfmin -mabi=ilp32f" } */
>> +int foo()
>> +{
>> +}
>> diff --git a/gcc/testsuite/gcc.target/riscv/arch-32.c 
>> b/gcc/testsuite/gcc.target/riscv/arch-32.c
>> new file mode 100644
>> index 000..49616832512
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/arch-32.c
>> @@ -0,0 +1,5 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-march=rv64iv_zvfbfmin -mabi=lp64d" } */
>> +int foo()
>> +{
>> +}
>> diff --git a/gcc/testsuite/gcc.target/riscv/predef-32.c 
>> b/gcc/testsuite/gcc.target/riscv/predef-32.c
>> new file mode 100644
>> index 000..7417e0d996f
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/predef-32.c
>> @@ -0,0 +1,43 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-O2 -march=rv32i_zvfbfmin -mabi=ilp32f -mcmodel=medlow 
>> -misa-spec=20191213" } */
>> +
>> +int main () {
>> +
>> +#ifndef __riscv_arch_test
>> +#error "__riscv_arch_test"
>> +#endif
>> +
>> +#if __riscv_xlen != 32
>> +#error "__riscv_xlen"
>> +#endif
>> +
>> +#if !defined(__riscv_i)
>> +#error "__riscv_i"
>> +#endif
>> +
>> +#if !defined(__riscv_f)
>> +#error "__riscv_f"
>> +#endif
>> +
>> +#if !defined(__riscv_zvfbfmin)
>> +#error "__riscv_zvfbfmin"
>> +#endif
>> +
>> +#if defined(__riscv_v)
>> +#error "__riscv_v"
>> +#endif
>> +
>> +#if defined(__riscv_d)
>> +#error "__riscv_d"
>> +#endif
>> +
>> +#if defined(__riscv_c)
>> +#error "__riscv_c"
>> +#endif
>> +
>> +#if defined(__riscv_a)
>> +#error "__riscv_a"
>> +#endif
>> +
>> +  return 0;
>> +}
>> diff --git a/gcc/testsuite/gcc.target/riscv/predef-33.c 
>> b/gcc/testsuite/gcc.target/riscv/predef-33.c
>> new file mode 100644
>> index 000..74d05bc9719
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/predef-33.c
>> @@ -0,0 +1,43 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-O2 -march=rv64iv_zvfbfmin -mabi=lp64d -mcmodel=medlow 
>> -misa-spec=20191213" } */
>> +
>> +int main () {
>> +
>> +#ifndef __riscv_arch_test
>> +#error "__riscv_arch_test"
>> +#endif
>> +
>> +#if __riscv_xlen != 64
>> +#error "__riscv_xlen"
>> +#endif
>> +
>> +#if !defined(__riscv_i)
>> +#error "__riscv_i"
>> +#endif
>> +
>> +#if !defined(__riscv_f)
>> +#error "__riscv_f"
>> +#endif
>> +
>> +#if !defined(__riscv_d)
>> +#error "__riscv_d"
>> +#endif
>> +
>> +#if !defined(__riscv_v)
>> +#error "__riscv_v"
>> +#endif
>> +
>> +#if !defined(__riscv_zvfbfmin)
>> +#error "__riscv_zvfbfmin"
>> +#endif
>> +
>> +#if defined(__riscv_c)
>> +#error "__riscv_c"
>> +#endif
>> +
>> +#if defined(__riscv_a)
>> +#error "__riscv_a"
>> +#endif
>> +
>> +  return 0;
>> +}
>
>Reviewed-by: Palmer Dabbelt  
Thank you for Palmer's code review
 
Thanks
Xiao Zeng

Re: Re: [PING^1][PATCH] RISC-V: Add Zvfbfmin extension to the -march= option

[Xiao Zeng]

2023-12-15 09:27  juzhe.zhong  wrote:
>
 
>CCing Kito.
>
>I am sorry I can't review ABI even though it is vector related, this patch 
>needs kito's review. 
Thank you for a reminder
In fact, in 
<https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640405.html>,
Palmer Dabbelt has already completed the review.

>
>But I will be available on reviewing the following real vector BF16 intrinsic 
>and auto-vectorization support.
> 
Of course, in the upcoming patch support for BF16, we need to request your code 
review.

>Thanks.
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Xiao Zeng
>Date: 2023-12-15 09:22
>To: gcc-patches
>CC: jeffreyalaw; research_trasio; juzhe.zhong; pan2.li; Xiao Zeng
>Subject: [PING^1][PATCH] RISC-V: Add Zvfbfmin extension to the -march= option
>This patch would like to add new sub extension (aka Zvfbfmin) to the
>-march= option. It introduces a new data type BF16.
>
>Depending on different usage scenarios, the Zvfbfmin extension may
>depend on 'V' or 'Zve32f'. This patch only implements dependencies
>in scenario of Embedded Processor. In scenario of Application
>Processor, it is necessary to explicitly indicate the dependent
>'V' extension.
>
>You can locate more information about Zvfbfmin from below spec doc.
>
>https://github.com/riscv/riscv-bfloat16/releases/download/20231027/riscv-bfloat16.pdf
>
>gcc/ChangeLog:
>
>* common/config/riscv/riscv-common.cc:
>(riscv_implied_info): Add zvfbfmin item.
>    (riscv_ext_version_table): Ditto.
>    (riscv_ext_flag_table): Ditto.
>* config/riscv/riscv.opt:
>(MASK_ZVFBFMIN): New macro.
>(MASK_VECTOR_ELEN_BF_16): Ditto.
>(TARGET_ZVFBFMIN): Ditto.
>
>gcc/testsuite/ChangeLog:
>
>* gcc.target/riscv/arch-31.c: New test.
>* gcc.target/riscv/arch-32.c: New test.
>* gcc.target/riscv/predef-32.c: New test.
>* gcc.target/riscv/predef-33.c: New test.
>---
>gcc/common/config/riscv/riscv-common.cc    |  4 ++
>gcc/config/riscv/riscv.opt |  4 ++
>gcc/testsuite/gcc.target/riscv/arch-31.c   |  5 +++
>gcc/testsuite/gcc.target/riscv/arch-32.c   |  5 +++
>gcc/testsuite/gcc.target/riscv/predef-32.c | 43 ++
>gcc/testsuite/gcc.target/riscv/predef-33.c | 43 ++
>6 files changed, 104 insertions(+)
>create mode 100644 gcc/testsuite/gcc.target/riscv/arch-31.c
>create mode 100644 gcc/testsuite/gcc.target/riscv/arch-32.c
>create mode 100644 gcc/testsuite/gcc.target/riscv/predef-32.c
>create mode 100644 gcc/testsuite/gcc.target/riscv/predef-33.c
>
>diff --git a/gcc/common/config/riscv/riscv-common.cc 
>b/gcc/common/config/riscv/riscv-common.cc
>index 4d5a2f874a2..370d00b8f7a 100644
>--- a/gcc/common/config/riscv/riscv-common.cc
>+++ b/gcc/common/config/riscv/riscv-common.cc
>@@ -151,6 +151,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
>   {"zfa", "f"},
>+  {"zvfbfmin", "zve32f"},
>   {"zvfhmin", "zve32f"},
>   {"zvfh", "zve32f"},
>   {"zvfh", "zfhmin"},
>@@ -313,6 +314,7 @@ static const struct riscv_ext_version 
>riscv_ext_version_table[] =
>   {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
>   {"zfhmin",    ISA_SPEC_CLASS_NONE, 1, 0},
>+  {"zvfbfmin",  ISA_SPEC_CLASS_NONE, 1, 0},
>   {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
>   {"zvfh",  ISA_SPEC_CLASS_NONE, 1, 0},
>@@ -1657,6 +1659,7 @@ static const riscv_ext_flag_table_t 
>riscv_ext_flag_table[] =
>   {"zve64x",   &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64},
>   {"zve64f",   &gcc_options::x_riscv_vector_elen_flags, 
>MASK_VECTOR_ELEN_FP_32},
>   {"zve64d",   &gcc_options::x_riscv_vector_elen_flags, 
>MASK_VECTOR_ELEN_FP_64},
>+  {"zvfbfmin", &gcc_options::x_riscv_vector_elen_flags, 
>MASK_VECTOR_ELEN_BF_16},
>   {"zvfhmin",  &gcc_options::x_riscv_vector_elen_flags, 
>MASK_VECTOR_ELEN_FP_16},
>   {"zvfh", &gcc_options::x_riscv_vector_elen_flags, 
>MASK_VECTOR_ELEN_FP_16},
>@@ -1692,6 +1695,7 @@ static const riscv_ext_flag_table_t 
>riscv_ext_flag_table[] =
>   {"zfhmin",    &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
>   {"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
>+  {"zvfbfmin",  &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN},
>   {"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
>   {"zvfh",  &gcc_options::x_riscv_zf_subext, MASK_ZVFH},
>diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
>index 59ce7106ecf..b7c0b72265e 100644

[PING^1][PATCH] RISC-V: Add Zvfbfmin extension to the -march= option

[Xiao Zeng]

This patch would like to add new sub extension (aka Zvfbfmin) to the
-march= option. It introduces a new data type BF16.

Depending on different usage scenarios, the Zvfbfmin extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies
in scenario of Embedded Processor. In scenario of Application
Processor, it is necessary to explicitly indicate the dependent
'V' extension.

You can locate more information about Zvfbfmin from below spec doc.

https://github.com/riscv/riscv-bfloat16/releases/download/20231027/riscv-bfloat16.pdf

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zvfbfmin item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv.opt:
(MASK_ZVFBFMIN): New macro.
(MASK_VECTOR_ELEN_BF_16): Ditto.
(TARGET_ZVFBFMIN): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-31.c: New test.
* gcc.target/riscv/arch-32.c: New test.
* gcc.target/riscv/predef-32.c: New test.
* gcc.target/riscv/predef-33.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc|  4 ++
 gcc/config/riscv/riscv.opt |  4 ++
 gcc/testsuite/gcc.target/riscv/arch-31.c   |  5 +++
 gcc/testsuite/gcc.target/riscv/arch-32.c   |  5 +++
 gcc/testsuite/gcc.target/riscv/predef-32.c | 43 ++
 gcc/testsuite/gcc.target/riscv/predef-33.c | 43 ++
 6 files changed, 104 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-31.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-33.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 4d5a2f874a2..370d00b8f7a 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -151,6 +151,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
 
   {"zfa", "f"},
 
+  {"zvfbfmin", "zve32f"},
   {"zvfhmin", "zve32f"},
   {"zvfh", "zve32f"},
   {"zvfh", "zfhmin"},
@@ -313,6 +314,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zvfbfmin",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvfh",  ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1657,6 +1659,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zve64x",   &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64},
   {"zve64f",   &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_32},
   {"zve64d",   &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_64},
+  {"zvfbfmin", &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_BF_16},
   {"zvfhmin",  &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_16},
   {"zvfh", &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_16},
 
@@ -1692,6 +1695,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
   {"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
+  {"zvfbfmin",  &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN},
   {"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
   {"zvfh",  &gcc_options::x_riscv_zf_subext, MASK_ZVFH},
 
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 59ce7106ecf..b7c0b72265e 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -285,6 +285,8 @@ Mask(VECTOR_ELEN_FP_64) Var(riscv_vector_elen_flags)
 
 Mask(VECTOR_ELEN_FP_16) Var(riscv_vector_elen_flags)
 
+Mask(VECTOR_ELEN_BF_16) Var(riscv_vector_elen_flags)
+
 TargetVariable
 int riscv_zvl_flags
 
@@ -366,6 +368,8 @@ Mask(ZFHMIN)  Var(riscv_zf_subext)
 
 Mask(ZFH) Var(riscv_zf_subext)
 
+Mask(ZVFBFMIN) Var(riscv_zf_subext)
+
 Mask(ZVFHMIN) Var(riscv_zf_subext)
 
 Mask(ZVFH)Var(riscv_zf_subext)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-31.c 
b/gcc/testsuite/gcc.target/riscv/arch-31.c
new file mode 100644
index 000..5180753b905
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-31.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zvfbfmin -mabi=ilp32f" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-32.c 
b/gcc/testsuite/gcc.target/riscv/arch-32.c
new file mode 100644
index 000..49616832512
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-32.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64iv_zvfbfmin -mabi=lp64d" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-32.c 
b/gcc/testsuite/gcc.target/riscv/predef-32.c
new file mode 100644
index 000..7417e0d996f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-32.c
@@ -0,0 +1,43 @@
+/* { dg-do compile

[PATCH] RISC-V: Add Zvfbfmin extension to the -march= option

[Xiao Zeng]

This patch would like to add new sub extension (aka Zvfbfmin) to the
-march= option. It introduces a new data type BF16.

Depending on different usage scenarios, the Zvfbfmin extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies
in scenario of Embedded Processor. In scenario of Application
Processor, it is necessary to explicitly indicate the dependent
'V' extension.

You can locate more information about Zvfbfmin from below spec doc.

https://github.com/riscv/riscv-bfloat16/releases/download/20231027/riscv-bfloat16.pdf

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zvfbfmin item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv.opt:
(MASK_ZVFBFMIN): New macro.
(MASK_VECTOR_ELEN_BF_16): Ditto.
(TARGET_ZVFBFMIN): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-31.c: New test.
* gcc.target/riscv/arch-32.c: New test.
* gcc.target/riscv/predef-32.c: New test.
* gcc.target/riscv/predef-33.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc|  4 ++
 gcc/config/riscv/riscv.opt |  4 ++
 gcc/testsuite/gcc.target/riscv/arch-31.c   |  5 +++
 gcc/testsuite/gcc.target/riscv/arch-32.c   |  5 +++
 gcc/testsuite/gcc.target/riscv/predef-32.c | 43 ++
 gcc/testsuite/gcc.target/riscv/predef-33.c | 43 ++
 6 files changed, 104 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-31.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-33.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 4d5a2f874a2..370d00b8f7a 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -151,6 +151,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
 
   {"zfa", "f"},
 
+  {"zvfbfmin", "zve32f"},
   {"zvfhmin", "zve32f"},
   {"zvfh", "zve32f"},
   {"zvfh", "zfhmin"},
@@ -313,6 +314,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zvfbfmin",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvfh",  ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1657,6 +1659,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zve64x",   &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64},
   {"zve64f",   &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_32},
   {"zve64d",   &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_64},
+  {"zvfbfmin", &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_BF_16},
   {"zvfhmin",  &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_16},
   {"zvfh", &gcc_options::x_riscv_vector_elen_flags, 
MASK_VECTOR_ELEN_FP_16},
 
@@ -1692,6 +1695,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
   {"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
+  {"zvfbfmin",  &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN},
   {"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
   {"zvfh",  &gcc_options::x_riscv_zf_subext, MASK_ZVFH},
 
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 59ce7106ecf..b7c0b72265e 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -285,6 +285,8 @@ Mask(VECTOR_ELEN_FP_64) Var(riscv_vector_elen_flags)
 
 Mask(VECTOR_ELEN_FP_16) Var(riscv_vector_elen_flags)
 
+Mask(VECTOR_ELEN_BF_16) Var(riscv_vector_elen_flags)
+
 TargetVariable
 int riscv_zvl_flags
 
@@ -366,6 +368,8 @@ Mask(ZFHMIN)  Var(riscv_zf_subext)
 
 Mask(ZFH) Var(riscv_zf_subext)
 
+Mask(ZVFBFMIN) Var(riscv_zf_subext)
+
 Mask(ZVFHMIN) Var(riscv_zf_subext)
 
 Mask(ZVFH)Var(riscv_zf_subext)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-31.c 
b/gcc/testsuite/gcc.target/riscv/arch-31.c
new file mode 100644
index 000..5180753b905
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-31.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zvfbfmin -mabi=ilp32f" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-32.c 
b/gcc/testsuite/gcc.target/riscv/arch-32.c
new file mode 100644
index 000..49616832512
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-32.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64iv_zvfbfmin -mabi=lp64d" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-32.c 
b/gcc/testsuite/gcc.target/riscv/predef-32.c
new file mode 100644
index 000..7417e0d996f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-32.c
@@ -0,0 +1,43 @@
+/* { dg-do compile

Re: Re: [PATCH v3] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

[Xiao Zeng]

On Sat, Aug 05, 2023 at 05:31:00 AM  Jeff Law  wrote:
>
>On 8/1/23 19:38, Xiao Zeng wrote:
>> This patch recognizes Zicond patterns when the select pattern
>> with condition eq or neq to 0 (using eq as an example), namely:
>>
>> 1 rd = (rs2 == 0) ? non-imm : 0
>> 2 rd = (rs2 == 0) ? non-imm : non-imm
>> 3 rd = (rs2 == 0) ? reg : non-imm
>> 4 rd = (rs2 == 0) ? reg : reg
>>
>> gcc/ChangeLog:
>>
>>  * config/riscv/riscv.cc (riscv_expand_conditional_move): Recognize
>>  Zicond patterns
>>  * config/riscv/riscv.md: Recognize Zicond patterns through 
>>movcc
>So I've made minor adjustments to the remaining three cases.  First we
>need to check the code before optimizing the cases were one of the arms
>of the conditional move matches op0.
>
>I slightly adjusted the case for out of range constants.  Its better to
>check SMALL_OPERAND rather than testing for specific constants.  And
>when that triggers, we can just force the value into a register and
>continue as-is rather than recursing.
> 
These changes make the code more concise and readable. Thumbs up!

>The patch I'm committing fixes one comment typo (whitespace) and a bit
>of accidentally duplicated code I added in a prior commit.
>
>Next up Raphael's patches to handle nontrival conditionals by emiting an
>scc insn :-) 
It would be great to see other implementations for conditional execution. :-)

>
>Jeff
>
>ps.  I'm deferrring the testsuite bits until we sort out the costing
>problems.  THey're definitely not forgotten and I still use them in my
>local tree. 
Thank you Jeff, I look forward to a unified, complete and concise
implementation method for cost calculation as soon as possible.
 
Thanks
Xiao Zeng

Re: [committed] [RISC-V] Avoid sub-word mode comparisons with Zicond

[Xiao Zeng]

might have a 64bit comparison and produce a 32bit sign extended result
>much like the setcc insns support.
>
>This patch changes the 6 zicond patterns to use the X iterator on the
>comparison inputs.  That at least makes the patterns correct and fixes
>this particular testcase.   There's a few other lurking problems that
>I'll address in additional patches.
>
>Committed to the trunk,
>Jeff

1 In any case, jeff's analysis is convincing, here I will add a little bit of 
my own analysis.

2 First, for the test cases:

foo(long long int x, long long int y) {
  if (((int)x | (int)y) != 0)
    return 6;
  return x + y;
}

look directly at the compared assembly code. This allows people to quickly
realize where the error occurred.

X_mode.s(right)                                                    
ANYI_mode.S(error)
10 foo:                                                                  10 
foo:                                                                            
                
      11         or      a5,a0,a1                                          11   
     or      a5,a0,a1                                                           
             
      12         sext.w  a5,a5                                            12    
    li      a4,6                                                                
            
      13         addw    a0,a0,a1                                      13       
 addw    a0,a0,a1                                                               
         
      14         li      a4,6                                                   
                                                                                
                                                    
      15         czero.nez       a1,a0,a5                             14        
czero.nez       a1,a0,a5                                                        
        
      16         czero.eqz       a0,a4,a5                             15        
czero.eqz       a0,a4,a5                                                        
        
      17         or      a0,a0,a1                                          16   
     or      a0,a0,a1                                                           
             
      18         ret                                                            
17        ret        

3 You will find that the correct assembly is just one more assembly
instruction: sext.w  a5,a5, the rest of the two are exactly the same.

4 From the perspective of assembly instructions, the a5 value obtained
by sext.w a5, a5 may be different from the original a5 value, which leads
to errors in the test case.

5 However, it is difficult to directly see that an error has occurred
from the rtl log of gcc's passe.

6 I'm wondering about transforms like this:

In test.c.c.301r.ira
(insn 36 34 42 2 (set (reg:DI 153)
        (if_then_else:DI (eq:DI (subreg:SI (reg:DI 145) 0)
                (const_int 0 [0]))
            (reg:DI 149)
            (const_int 0 [0]))) "test.c":4:12 13599 {*czero.nez.disi}
     (expr_list:REG_DEAD (reg:DI 149)
        (nil)))

In test.c.c.302r.reload it becomes
(insn 36 34 42 2 (set (reg:DI 11 a1 [153])
        (if_then_else:DI (eq:DI (reg:SI 15 a5 [145])
                (const_int 0 [0]))
            (reg:DI 10 a0 [149])
            (const_int 0 [0]))) "test.c":4:12 13599 {*czero.nez.disi}
     (nil))

Obviously, (subreg:SI (reg:DI 145) 0) is transformed into (reg:SI 15 a5 [145]) 
after
passing through reload pass. This conversion is wrong, why did gcc not warn?

7 I'm not very familiar with reload pass, maybe someone can give me a
brief introduction, or tell me where to find relevant information? Thanks.

 
Thanks
Xiao Zeng

Re: [committed][RISC-V] Fix 20010221-1.c with zicond

[Xiao Zeng]

On Thu, Aug 03, 2023 at 01:20:00 AM  Jeff Law  wrote:
>
>
>
>So we're being a bit too aggressive with the .opt zicond patterns.
>
>
>> (define_insn "*czero.eqz..opt1"
>>   [(set (match_operand:GPR 0 "register_operand"   "=r")
>> (if_then_else:GPR (eq (match_operand:X 1 "register_operand" "r")
>>   (const_int 0))
>>   (match_operand:GPR 2 "register_operand" "1")
>>   (match_operand:GPR 3 "register_operand" "r")))]
>>   "(TARGET_ZICOND || 1) && rtx_equal_p (operands[1], operands[2])"
>>   "czero.eqz\t%0,%3,%1"
>> )
>>
>The RTL semantics here are op0 = (op1 == 0) ? op1 : op2.  That maps
>directly to czero.eqz.  ie, we select op1 when we know it's zero, op2
>otherwise.  So this pattern is fine.
>
>
>
>> (define_insn "*czero.eqz..opt2"
>>   [(set (match_operand:GPR 0 "register_operand"   "=r")
>> (if_then_else:GPR (eq (match_operand:X 1 "register_operand" "r")
>>   (const_int 0))
>>   (match_operand:GPR 2 "register_operand" "r")
>>   (match_operand:GPR 3 "register_operand" "1")))]
>>   "(TARGET_ZICOND || 1) && rtx_equal_p (operands[1],  operands[3])"
>>   "czero.nez\t%0,%2,%1"
>> )
>
>The RTL semantics of this pattern are are: op0 = (op1 == 0) ? op2 : op1;
>
>That's not something that can be expressed by the zicond extension as it
>selects op1 if and only if op1 is not equal to zero.
>
>
>
>> (define_insn "*czero.nez..opt3"
>>   [(set (match_operand:GPR 0 "register_operand"   "=r")
>> (if_then_else:GPR (ne (match_operand:X 1 "register_operand" "r")
>>   (const_int 0))
>>   (match_operand:GPR 2 "register_operand" "r")
>>   (match_operand:GPR 3 "register_operand" "1")))]
>>   "(TARGET_ZICOND || 1) && rtx_equal_p (operands[1], operands[3])"
>>   "czero.eqz\t%0,%2,%1"
>> )
>The RTL semantics of this pattern are op0 = (op1 != 0) ? op2 : op1.
>That maps to czero.nez.  But the output template uses czero.eqz.  Opps.
>
>> (define_insn "*czero.nez..opt4"
>>   [(set (match_operand:GPR 0 "register_operand"   "=r")
>> (if_then_else:GPR (ne (match_operand:X 1 "register_operand" "r")
>>   (const_int 0))
>>   (match_operand:GPR 2 "register_operand" "1")
>>   (match_operand:GPR 3 "register_operand" "r")))]
>>   "(TARGET_ZICOND || 1) && rtx_equal_p (operands[1], operands[2])"
>>   "czero.nez\t%0,%3,%1"
>> )
>The RTL semantics of this pattern are op0 = (op1 != 0) ? op1 : op2 which
>obviously doesn't match to any zicond instruction as op1 is selected
>when it is not zero.
>
>
>So two of the patterns are just totally bogus as they are not
>implementable with zicond.  They are removed.  The asm template for the
>.opt3 pattern is fixed to use czero.nez and its name is changed to .opt2.
>
>This fixes the known issues with the zicond.md bits.  Onward to the rest
>of the expansion work :-)
>
>Committed to the trunk,
>
>jeff
>

Yes, two of these four optimization patterns are wrong.

In the wrong two optimization modes, I only considered the
case of satisfying the ELSE branch, but in fact, like the correct
two optimization modes, I should consider the case of satisfying
both the THAN and ELSE branches.

By the way, I was assigned other tasks during the week and
didn't have time to reply to emails, sorry.

Although I can't reply in time to the emails received from the
gcc community, I will definitely reply when I am free.

At the same time, I will improve my time management skills, keep
the same frequency with the community as much as possible, and
work better with everyone.

Thanks
Xiao Zeng

Re: Re: [PATCH V2] [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

[Xiao Zeng]

On Tue, Aug 01, 2023 at 02:06:00 PM Jeff Law  wrote:
>
>
>
>On 7/29/23 03:13, Xiao Zeng wrote:
>> This patch recognizes Zicond patterns when the select pattern
>> with condition eq or neq to 0 (using eq as an example), namely:
>>
>> 1 rd = (rs2 == 0) ? non-imm : 0
>> 2 rd = (rs2 == 0) ? non-imm : non-imm
>> 3 rd = (rs2 == 0) ? reg : non-imm
>> 4 rd = (rs2 == 0) ? reg : reg
>>
>> gcc/ChangeLog:
>>
>>  * config/riscv/riscv.cc (riscv_expand_conditional_move): Recognize
>>  Zicond patterns
>>  * config/riscv/riscv.md: Recognize Zicond patterns through 
>>movcc
>>
>> gcc/testsuite/ChangeLog:
>>
>>  * gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c: New 
>>test.
>>  * gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c: New 
>>test.
>>  * gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c: New 
>>test.
>>  * gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c: New 
>>test.
>> ---
>>   gcc/config/riscv/riscv.cc | 144 ++
>>   gcc/config/riscv/riscv.md |   4 +-
>>   .../zicond-primitiveSemantics_return_0_imm.c  |  65 
>>   ...zicond-primitiveSemantics_return_imm_imm.c |  73 +
>>   ...zicond-primitiveSemantics_return_imm_reg.c |  65 
>>   ...zicond-primitiveSemantics_return_reg_reg.c |  65 
>>   6 files changed, 414 insertions(+), 2 deletions(-)
>>   create mode 100644 
>>gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c
>>   create mode 100644 
>>gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c
>>   create mode 100644 
>>gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c
>>   create mode 100644 
>>gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c
>>
>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> index 941ea25e1f2..6ac39f63dd7 100644
>> --- a/gcc/config/riscv/riscv.cc
>> +++ b/gcc/config/riscv/riscv.cc
>> @@ -3516,6 +3516,150 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx 
>> cons, rtx alt)
>>     cond, cons, alt)));
>> return true;
>>   }
>> +  else if (TARGET_ZICOND
>> +   && (code == EQ || code == NE)
>> +   && GET_MODE_CLASS (mode) == MODE_INT)
>> +    {
>> +  need_eq_ne_p = true;
>> +  /* 0 + imm  */
>> +  if (GET_CODE (cons) == CONST_INT && cons == const0_rtx
>> +  && GET_CODE (alt) == CONST_INT && alt != const0_rtx)
>A couple nits.  Rather than test the GET_CODE (object) == CONST_INT,
>instead use CONST_INT_P (object). 
fixed

>
>Rather than using const0_rtx, use CONST0_RTX (mode).  That makes it more
>general. 
fixed

>
>
>
>> +    {
>> +  riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
>Might as well use "true" rather than "need_eq_ne_p" here and for the
>other calls in your new code.
> 
fixed

>> +  /* imm + imm  */
>> +  else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx
>> +   && GET_CODE (alt) == CONST_INT && alt != const0_rtx)
>So same comments on using CONST_INT_P and CONST0_RTX 
fixed

>> +    {
>> +  riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
>> +  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
>> +  rtx reg = gen_reg_rtx (mode);
>> +  rtx temp = GEN_INT (INTVAL (alt) - INTVAL (cons));
>> +  emit_insn (gen_rtx_SET (reg, temp));
>Use force_reg here rather than directly emitting the insn to initialize
>"reg".  What you're doing works when the difference is small but will
>not work when the difference does not fit into a signed 12bit value. 
fixed

>
>> +  /* imm + reg  */
>> +  else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx
>> +   && GET_CODE (alt) == REG)
>Same comments about CONST_INT_P and CONST0_RTX.  And instead of using
>GET_CODE (object) == REG, use REG_P (object).
>
>
>> +    {
>> +  /* Optimize for register value of 0.  */
>> +  if (op0 == alt && op1 == const0_rtx)
>> +    {
>> +  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
>> +  cons = force_reg (mode, cons);
>> +  emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (m

[PATCH v3] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

[Xiao Zeng]

This patch recognizes Zicond patterns when the select pattern
with condition eq or neq to 0 (using eq as an example), namely:

1 rd = (rs2 == 0) ? non-imm : 0
2 rd = (rs2 == 0) ? non-imm : non-imm
3 rd = (rs2 == 0) ? reg : non-imm
4 rd = (rs2 == 0) ? reg : reg

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_expand_conditional_move): Recognize
Zicond patterns
* config/riscv/riscv.md: Recognize Zicond patterns through movcc

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c: New test.
* gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c: New test.
* gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c: New test.
* gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c: New test.
---
 gcc/config/riscv/riscv.cc | 137 ++
 gcc/config/riscv/riscv.md |   4 +-
 .../zicond-primitiveSemantics_return_0_imm.c  |  65 +
 ...zicond-primitiveSemantics_return_imm_imm.c |  73 ++
 ...zicond-primitiveSemantics_return_imm_reg.c |  65 +
 ...zicond-primitiveSemantics_return_reg_reg.c |  65 +
 6 files changed, 407 insertions(+), 2 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index b6a57d0306d..6353d08ba9d 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3557,6 +3557,143 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx 
cons, rtx alt)
  cond, cons, alt)));
   return true;
 }
+  else if (TARGET_ZICOND
+   && (code == EQ || code == NE)
+   && GET_MODE_CLASS (mode) == MODE_INT)
+{
+  /* 0 + imm  */
+  if (CONST_INT_P (cons) && cons == CONST0_RTX (GET_MODE (cons))
+  && CONST_INT_P (alt) && alt != CONST0_RTX (GET_MODE (alt)))
+{
+  riscv_emit_int_compare (&code, &op0, &op1, true);
+  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+  alt = force_reg (mode, alt);
+  emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond,
+  cons, alt)));
+  return true;
+}
+  /* imm + imm  */
+  else if (CONST_INT_P (cons) && cons != CONST0_RTX (GET_MODE (cons))
+   && CONST_INT_P (alt) && alt != CONST0_RTX (GET_MODE (alt)))
+{
+  riscv_emit_int_compare (&code, &op0, &op1, true);
+  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+  alt = force_reg (mode, GEN_INT (INTVAL (alt) - INTVAL (cons)));
+  emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond,
+  CONST0_RTX 
(mode),
+  alt)));
+  riscv_emit_binary (PLUS, dest, dest, cons);
+  return true;
+}
+  /* imm + reg  */
+  else if (CONST_INT_P (cons) && cons != CONST0_RTX (GET_MODE (cons))
+   && REG_P (alt))
+{
+  if (op0 == alt && op1 == CONST0_RTX (GET_MODE (op1)))
+{
+  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+  cons = force_reg (mode, cons);
+  emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond,
+  cons, alt)));
+  return true;
+}
+  /* Handle the special situation of: -2048 == INTVAL (alt)
+ to avoid failure due to an unrecognized insn. Let the costing
+ model determine if the conditional move sequence is better
+ than the branching sequence.  */
+  if (-2048 == INTVAL (cons))
+{
+  rtx reg = gen_reg_rtx (mode);
+  emit_insn (gen_rtx_SET (reg, cons));
+  return riscv_expand_conditional_move (dest, op, reg, alt);
+}
+  riscv_emit_int_compare (&code, &op0, &op1, true);
+  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+  rtx temp = GEN_INT (-1 * INTVAL (cons));
+  riscv_emit_binary (PLUS, alt, alt, temp);
+  emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond,
+  CONST0_RTX 
(mode),
+  alt)));
+  riscv_emit_binary (PLUS, dest, dest, cons);
+  return true;
+}
+  /* imm + 0  */
+  els

Re: Re: [PATCH 0/5] Recognize Zicond extension

[Xiao Zeng]

On Fri, Jul 28, 2023 at 11:03:00 PM  Jeff Law  wrote:
>
>
>
>On 7/28/23 00:34, Xiao Zeng wrote:
>
>>>>
>>>> Does that work for you?
>>> I'm going to look at 3/5 today pretty closely.  Exposing zicond to
>>> movcc is something we had implemented inside Ventana and I want to
>>> compare/contrast your work with ours.
>>
>> What a coincidence!
>Zicond is a direct descendant of xventanacondops.  The only notable
>difference is in their encodings. 
It explains the matter.

>
>>
>>>
>>> What I like about yours is it keeps all the logic in riscv.cc rather
>>> than scattering it across riscv.cc and riscv.md.
>>
>> Yes, when I use enough test cases, I cannot find a concise way to optimize
>> all test cases. When I enumerated all possible cases in the movcc
>> function of the RISC-V backend, I found a method that satisfied me, which
>> is the method in patch [3/5].
>I got pulled away to another task yesterday, so didn't get as far as I
>wanted.   The biggest inight from yesterday was determining that some of
>the cases you're handling in riscv_expand_conditional_move were things
>we were doing inside ifcvt.cc.
>
>The difference is likely because the initial work on zicond here was
>primarily driven by changes to ifcvt.  It was only after evaluating that
>initial implementation that we started to the effort to use zicond at
>RTL expansion time.
>
>I could make a case for either approach, but the more I ponder them the
>more I'm inclined to go with something like yours.  

>We want to capture
>the cases implementable as a conditional move as early as possible in
>the RTL pipeline rather than relying on ifcvt to catch it later.  It
>also avoids polluting ifcvt with transformations that are only likely
>needed on risc-v. 
That's why I did this optimization in riscv.cc riscv_expand_conditional_move.

>
>
>>>
>>
>> If it's just for the Zicond instruction set, is it necessary to make 
>> judgments
>> outside of eq/ne? After all, it does not support comparison actions other
>> than eq/ne. Of course, it is also possible to use a special technique to use
>> Zicond in non eq/ne comparisons.
>It's not necessary, but it's definitely helpful to cover the other
>conditions.  In fact, we can even cover a variety of fp conditions by
>utilizing the sCC type insns. 
It would be great if we could do this.

>
>
>So what I'm looking at for patch #3 is to split out the costing bits
>into its own patch which can go forward immediately.  
As you expected, V2-patch[3/5] has arrived,
and its address is: 
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/625781.html

>THen continue
>evaluating the best way to handle unifying the expander/canonicalization
>code.
That's nice.
  
>Your testcases in patch #3 are particularly helpful to make sure
>we're not missing cases. 
Yes, I have always believed that test cases can be redundant, but they cannot
be omitted. As we all know, the compiler will always make some magical changes
without our knowledge, which may not be what we expect. And test cases
can help us stay away from this risk.

>
>Jeff 

Thanks
Xiao Zeng

Re: Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

[Xiao Zeng]

On Fri, Jul 28, 2023 at 11:09:00 PM  Jeff Law  wrote:
>
>
>
>On 7/25/23 11:55, Andreas Schwab wrote:
>> On Jul 19 2023, Xiao Zeng wrote:
>>
>>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>>> index 38d8eb2fcf5..7e6b24bd232 100644
>>> --- a/gcc/config/riscv/riscv.cc
>>> +++ b/gcc/config/riscv/riscv.cc
>>> @@ -2448,6 +2448,17 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
>>> outer_code, int opno ATTRIBUTE_UN
>>>     *total = COSTS_N_INSNS (1);
>>>     return true;
>>>   }
>>> +  else if (TARGET_ZICOND && outer_code == SET &&
>>> +   ((GET_CODE (XEXP (x, 1)) == REG && XEXP (x, 2) == 
>>> const0_rtx) ||
>>> +   (GET_CODE (XEXP (x, 2)) == REG && XEXP (x, 1) == 
>>> const0_rtx) ||
>>> +   (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
>>> +    XEXP (x, 1) == XEXP (XEXP (x, 0), 0)) ||
>>> +   (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
>>> +    XEXP (x, 2) == XEXP (XEXP (x, 0), 0
>>
>> Line breaks before the operator, not after.
>Also note that && GET_CODE (XEXP (x, 2)) && that appears twice. 

This is an error that I will fix in patch[cost] and provide a detailed 
explanation.

>
>That just verifies the code isn't RTX_UNKNOWN which I suspect isn't what
>the author intended.  It probably needs to be adjusted for SUBREGs and
>the pointer equality issues with REGs after reload.
>
>I'll take care of these goofs since the costing ought to be able to move
>forward independently of the improvements Xiao made to generating
>conditional move sequences.
>
>Jeff 

After V2-patch[3/5] is accepted, a patch[cost] will be submitted to provide 
detailed
explanation of this issue. Of course, as Jeff mentioned, some issues will also 
be fixed.

Thanks
Xiao Zeng

Re: Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

[Xiao Zeng]

On Sat, Jul 29, 2023 at 04:59:00 AM  Jeff Law  wrote:
>
>
>
>On 7/19/23 04:11, Xiao Zeng wrote:
>
>> +  else if (TARGET_ZICOND
>> +   && (code == EQ || code == NE)
>> +   && GET_MODE_CLASS (mode) == MODE_INT)
>> +    {
>> +  need_eq_ne_p = true;
>> +  /* 0 + imm  */
>> +  if (GET_CODE (cons) == CONST_INT && cons == const0_rtx
>> +  && GET_CODE (alt) == CONST_INT && alt != const0_rtx)
>> +    {
>> +  riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
>> +  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
>> +  alt = force_reg (mode, alt);
>> +  emit_insn (gen_rtx_SET (dest,
>> +  gen_rtx_IF_THEN_ELSE (mode, cond,
>> +    cons, alt)));
>> +  return true;
>> +    }
>> +  /* imm + imm  */
>> +  else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx
>> +   && GET_CODE (alt) == CONST_INT && alt != const0_rtx)
>> +    {
>> +  riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
>> +  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
>> +  alt = force_reg (mode, alt);
>> +  rtx temp1 = gen_reg_rtx (mode);
>> +  rtx temp2 = GEN_INT(-1 * INTVAL (cons));
>> +  riscv_emit_binary(PLUS, temp1, alt, temp2);
>So in this sequence you're just computing a constant since both ALT and
>CONS are constants.  It's better to just form the constant directly,
>then force that into a register because it'll make the costing more
>correct, particularly if the resulting constant needs more than one
>instruction to synthesize. 

Fixed

>
>And a nit.  There should always be a space between a function name and
>its argument list. 

Fixed

>
>
>
>> +  emit_insn (gen_rtx_SET (dest,
>> +  gen_rtx_IF_THEN_ELSE (mode, cond,
>> +    const0_rtx, alt)));
>> +  riscv_emit_binary(PLUS, dest, dest, cons);
>> +  return true;
>I don't see how this can be correct from a code generation standpoint.
>You compute ALT-CONS into TEMP1 earlier.  But you never use TEMP1 after
>that.  I think you meant to use TEMP1 instead of ALT as the false arm if
>the IF-THEN-ELSE you constructed. 

Fixed

>
>In general you should be using CONST0_RTX (mode) rather than const0_rtx.
> 

Fixed

>> +    }
>> +  /* imm + reg  */
>> +  else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx
>> +   && GET_CODE (alt) == REG)
>> +    {
>> +  /* Optimize for register value of 0.  */
>> +  if (op0 == alt && op1 == const0_rtx)
>> +    {
>> +  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
>> +  cons = force_reg (mode, cons);
>> +  emit_insn (gen_rtx_SET (dest,
>> +  gen_rtx_IF_THEN_ELSE (mode, cond,
>> +    cons, alt)));
>> +  return true;
>> +    }
>> +  riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
>> +  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
>> +  rtx temp1 = gen_reg_rtx (mode);
>> +  rtx temp2 = GEN_INT(-1 * INTVAL (cons));
>> +  riscv_emit_binary(PLUS, temp1, alt, temp2);
>Here you have to be careful if CONS is -2048.  You negate it resulting
>in +2048 which can't be used in an addi.  This will cause the entire
>sequence to fail due to an unrecognized insn.  It would be better to
>handle that scenario directly so the generated sequence is still valid.
>
>By generating recognizable code in that case we let the costing model
>determine if the conditional move sequence is better than the branching
>sequence. 

Thank you for pointing out this special situation, it has been fixed

>
>
>> +  emit_insn (gen_rtx_SET (dest,
>> +  gen_rtx_IF_THEN_ELSE (mode, cond,
>> +    const0_rtx, alt)));
>I think we have the same problem with the use of ALT here rather than
>TEMP1 that we had in the previous case. 

Fixed

>
>
>
>> +  /* reg + imm  */
>> +  else if (GET_CODE (cons) == REG
>> +   && GET_CODE (alt) 

[PATCH V2] [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

[Xiao Zeng]

This patch recognizes Zicond patterns when the select pattern
with condition eq or neq to 0 (using eq as an example), namely:

1 rd = (rs2 == 0) ? non-imm : 0
2 rd = (rs2 == 0) ? non-imm : non-imm
3 rd = (rs2 == 0) ? reg : non-imm
4 rd = (rs2 == 0) ? reg : reg

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_expand_conditional_move): Recognize
Zicond patterns
* config/riscv/riscv.md: Recognize Zicond patterns through movcc

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c: New test.
* gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c: New test.
* gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c: New test.
* gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c: New test.
---
 gcc/config/riscv/riscv.cc | 144 ++
 gcc/config/riscv/riscv.md |   4 +-
 .../zicond-primitiveSemantics_return_0_imm.c  |  65 
 ...zicond-primitiveSemantics_return_imm_imm.c |  73 +
 ...zicond-primitiveSemantics_return_imm_reg.c |  65 
 ...zicond-primitiveSemantics_return_reg_reg.c |  65 
 6 files changed, 414 insertions(+), 2 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 941ea25e1f2..6ac39f63dd7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3516,6 +3516,150 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx 
cons, rtx alt)
  cond, cons, alt)));
   return true;
 }
+  else if (TARGET_ZICOND
+   && (code == EQ || code == NE)
+   && GET_MODE_CLASS (mode) == MODE_INT)
+{
+  need_eq_ne_p = true;
+  /* 0 + imm  */
+  if (GET_CODE (cons) == CONST_INT && cons == const0_rtx
+  && GET_CODE (alt) == CONST_INT && alt != const0_rtx)
+{
+  riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
+  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+  alt = force_reg (mode, alt);
+  emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond,
+  cons, alt)));
+  return true;
+}
+  /* imm + imm  */
+  else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx
+   && GET_CODE (alt) == CONST_INT && alt != const0_rtx)
+{
+  riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
+  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+  rtx reg = gen_reg_rtx (mode);
+  rtx temp = GEN_INT (INTVAL (alt) - INTVAL (cons));
+  emit_insn (gen_rtx_SET (reg, temp));
+  emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond,
+  CONST0_RTX 
(mode),
+  reg)));
+  riscv_emit_binary (PLUS, dest, dest, cons);
+  return true;
+}
+  /* imm + reg  */
+  else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx
+   && GET_CODE (alt) == REG)
+{
+  /* Optimize for register value of 0.  */
+  if (op0 == alt && op1 == const0_rtx)
+{
+  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+  cons = force_reg (mode, cons);
+  emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond,
+  cons, alt)));
+  return true;
+}
+  /* Handle the special situation of: -2048 == INTVAL (alt)
+ to avoid failure due to an unrecognized insn. Let the costing
+ model determine if the conditional move sequence is better
+ than the branching sequence.  */
+  if (-2048 == INTVAL (cons))
+{
+  rtx reg = gen_reg_rtx (mode);
+  emit_insn (gen_rtx_SET (reg, cons));
+  return riscv_expand_conditional_move (dest, op, reg, alt);
+}
+  riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
+  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+  rtx temp = GEN_INT (-1 * INTVAL (cons));
+  riscv_emit_binary (PLUS, alt, alt, temp);
+  emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cond,
+  CONST0_RTX 
(mode),
+ 

Re: Re: [PATCH 0/5] Recognize Zicond extension

[Xiao Zeng]

On Thu, Jul 27, 2023 at 10:43:00 PM  Jeff Law  wrote:
>
>
>
>On 7/27/23 02:43, Xiao Zeng wrote:
>
>>
>> 2. According to your opinions, I have modified the code, but out of caution
>> for upstream, I conducted a complete regression tests on patch V2, which took
>> some time. I was unable to reply to emails and upload patch V2 in a timely 
>> manner.
>Sorry to have wasted your time 

It's okay
I am very willing to accept opinions from the gcc community.

>-- zicond/xventanacondops has lingered
>for quite a while and I had a bit of free time yesterday.  I felt it was
>most useful to try and move this stuff forward.
>
>
>
>>
>> 3 After you and other maintainers made minor modifications to my patch[1/5]
>> and patch[2/5], it has been merged into the master, so I will no longer 
>> upload patch V2.
>Agreed.
>
>>
>> 4 patch[1/5] and patch[2/5], which have been merged into the master, have 
>> only
>> completed basic support for Zicond, and further optimization work needs to be
>> completed. These further optimization reactions are reflected in my 
>> patch[3/5]
>> patch[4/5] and patch[5/5].
>Agreed.
>
>>
>> 5 As you mentioned in your previous email 
>> https://gcc.gnu.org/pipermail/gcc-patches/2023-July/625427.html
>> "eswincomputing and ventana can both reduce our divergence from the trunk
>> and work together on the rest of the bits...". I will reorganize patch[3/5] 
>> patch[4/5]
>> and patch[5/5], provide more detailed explanations, and submit them as an 
>> alternative
>> solution for further optimization of Zicond.
>>
>> Does that work for you?
>I'm going to look at 3/5 today pretty closely.  Exposing zicond to
>movcc is something we had implemented inside Ventana and I want to
>compare/contrast your work with ours. 

What a coincidence!

>
>What I like about yours is it keeps all the logic in riscv.cc rather
>than scattering it across riscv.cc and riscv.md.  

Yes, when I use enough test cases, I cannot find a concise way to optimize
all test cases. When I enumerated all possible cases in the movcc
function of the RISC-V backend, I found a method that satisfied me, which
is the method in patch [3/5].

>What I like about the
>internal Ventana bits is its ability to support arbitrary comparisons by
>utilizing sCC if the original is not an eq/ne comparison.
> 

If it's just for the Zicond instruction set, is it necessary to make judgments
outside of eq/ne? After all, it does not support comparison actions other
than eq/ne. Of course, it is also possible to use a special technique to use
Zicond in non eq/ne comparisons.

>Ideally we'll be able to get the best of both. 

Of course, it is best to unify all situations in one framework.

>
>Jeff

Now that the code on the master has preliminary support for
Zicond, I will still submit the optimization patches for Zicond to
the community for the convenience of finding the ideal method.

Thanks
Xiao Zeng

Re: Re: [PATCH 0/5] Recognize Zicond extension

[Xiao Zeng]

On Wed, Jul 26, 2023 at 01:51:00 AM  Jeff Law  wrote:
>
>
>
>On 7/19/23 04:11, Xiao Zeng wrote:
>> Hi all RISC-V folks:
>>
>> This series of patches completes support for the riscv architecture's
>> Zicond standard extension instruction set.
>>
>> Currently, Zicond is in a frozen state.
>>
>> See the Zicond specification for details:
>> https://github.com/riscv/riscv-zicond/releases/download/v1.0-rc2/riscv-zicond-v1.0-rc2.pdf
>>
>> Prior to this, other community members have also done related work, as shown 
>> in:
>> https://gcc.gnu.org/pipermail/gcc-patches/2023-February/611767.html
>> https://sourceware.org/pipermail/binutils/2023-January/125773.html
>>
>> Xiao Zeng (5):
>>    [RISC-V] Recognize Zicond extension
>>    [RISC-V] Generate Zicond instruction for basic semantics
>>    [RISC-V] Generate Zicond instruction for select pattern with condition
>>  eq or neq to 0
>>    [RISC-V] Generate Zicond instruction for select pattern with condition
>>  eq or neq to non-zero
>>    [RISC-V] Generate Zicond instruction for conditional execution
>[ ... ]
>So what I'm thinking for the overall kit is to stage it in a bit
>differently given we have some bits which clearly can go forward as-is
>or with very minor changes and others that are going to need some
>iteration/refinement.
>
>So I'm going to suggest a few changes so that bits which are non
>controversial can move forward immediately.
>
>1/5 looked fine as-is.
>
>I would split 2/5.  The first two patterns you added are
>non-controversial and could go in immediately.  The other 4 patterns
>(which require some operand matching) will likely need at least one
>round of iteration and should be a distinct patch.
>
>
>I would split 3/5 as well.  3a would be the costing which I think just
>needs to use COSTS_N_INSNS (1) rather than 0 for the cost of a
>conditional move and could then move forward immediately.  The bits to
>wire everything up into the conditional move pattern would be a distinct
>patch.  We did something similar internally in Ventana and I'd like to
>take the time to make sure the issues we ran into are addressed in your
>version then do an evaluation of the two approaches.
>
>I think patch 4 is probably going to need some work too.  I *think* what
>we did internally at Ventana will work better (utilizing scc for a
>non-trivial condition).
>
>Let's defer patch #5 initially as well.  It's going to get tangled up in
>a whole bunch of changes I think we need to make to ifcvt.cc.
>
>The point being that with the bits from #1, #2 and #3 we can get some
>initial support in immediately.  eswincomputing and ventana can both
>reduce our divergence from the trunk and work together on the rest of
>the bits.
>
>Does that work for you?
>
>jeff 

1 Thanks Jeff for your code review feedback.

2. According to your opinions, I have modified the code, but out of caution
for upstream, I conducted a complete regression tests on patch V2, which took
some time. I was unable to reply to emails and upload patch V2 in a timely 
manner.

3 After you and other maintainers made minor modifications to my patch[1/5] 
and patch[2/5], it has been merged into the master, so I will no longer upload 
patch V2.

4 patch[1/5] and patch[2/5], which have been merged into the master, have only
completed basic support for Zicond, and further optimization work needs to be
completed. These further optimization reactions are reflected in my patch[3/5]
patch[4/5] and patch[5/5].

5 As you mentioned in your previous email 
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/625427.html
"eswincomputing and ventana can both reduce our divergence from the trunk
and work together on the rest of the bits...". I will reorganize patch[3/5] 
patch[4/5]
and patch[5/5], provide more detailed explanations, and submit them as an 
alternative
solution for further optimization of Zicond.

Does that work for you?

Xiao Zeng

Re: Re: [PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

[Xiao Zeng]

On Wed, Jul 26, 2023 at 01:55:00 AM Andreas Schwab  
wrote:
>
>On Jul 19 2023, Xiao Zeng wrote:
>
>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> index 38d8eb2fcf5..7e6b24bd232 100644
>> --- a/gcc/config/riscv/riscv.cc
>> +++ b/gcc/config/riscv/riscv.cc
>> @@ -2448,6 +2448,17 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
>> outer_code, int opno ATTRIBUTE_UN
>>    *total = COSTS_N_INSNS (1);
>>    return true;
>>  }
>> +  else if (TARGET_ZICOND && outer_code == SET &&
>> +   ((GET_CODE (XEXP (x, 1)) == REG && XEXP (x, 2) == 
>> const0_rtx) ||
>> +   (GET_CODE (XEXP (x, 2)) == REG && XEXP (x, 1) == const0_rtx) 
>> ||
>> +   (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
>> +    XEXP (x, 1) == XEXP (XEXP (x, 0), 0)) ||
>> +   (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
>> +    XEXP (x, 2) == XEXP (XEXP (x, 0), 0
>
>Line breaks before the operator, not after.
>
>--
>Andreas Schwab, sch...@linux-m68k.org
>GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
>"And now for something completely different." 

Thank you for pointing out the code format issue. I will fix it in the future 
patch.

[PATCH 3/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

[Xiao Zeng]

This patch completes the recognition of Zicond when the select pattern
with condition eq or neq to 0 (using equality as an example), namely:

1 rd = (rs2 == 0) ? non-imm : 0
2 rd = (rs2 == 0) ? non-imm : non-imm
3 rd = (rs2 == 0) ? reg : non-imm
4 rd = (rs2 == 0) ? reg : reg

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_rtx_costs): IF_THEN_ELSE costs in Zicond.
(riscv_expand_conditional_move): Recognize Zicond.
* config/riscv/riscv.md: Zicond patterns.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c: New test.
* gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c: New test.
* gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c: New test.
* gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c: New test.
---
 gcc/config/riscv/riscv.cc | 125 ++
 gcc/config/riscv/riscv.md |   2 +-
 .../zicond-primitiveSemantics_return_0_imm.c  |  65 +
 ...zicond-primitiveSemantics_return_imm_imm.c |  73 ++
 ...zicond-primitiveSemantics_return_imm_reg.c |  65 +
 ...zicond-primitiveSemantics_return_reg_reg.c |  65 +
 6 files changed, 394 insertions(+), 1 deletion(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 38d8eb2fcf5..7e6b24bd232 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2448,6 +2448,17 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
  *total = COSTS_N_INSNS (1);
  return true;
}
+  else if (TARGET_ZICOND && outer_code == SET &&
+   ((GET_CODE (XEXP (x, 1)) == REG && XEXP (x, 2) == const0_rtx) ||
+   (GET_CODE (XEXP (x, 2)) == REG && XEXP (x, 1) == const0_rtx) ||
+   (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
+XEXP (x, 1) == XEXP (XEXP (x, 0), 0)) ||
+   (GET_CODE (XEXP (x, 1)) == REG && GET_CODE (XEXP (x, 2)) &&
+XEXP (x, 2) == XEXP (XEXP (x, 0), 0
+{
+  *total = 0;
+  return true;
+}
   else if (LABEL_REF_P (XEXP (x, 1)) && XEXP (x, 2) == pc_rtx)
{
  if (equality_operator (XEXP (x, 0), mode)
@@ -3501,6 +3512,120 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx 
cons, rtx alt)
  cond, cons, alt)));
   return true;
 }
+  else if (TARGET_ZICOND
+   && (code == EQ || code == NE)
+   && GET_MODE_CLASS (mode) == MODE_INT)
+{
+  need_eq_ne_p = true;
+  /* 0 + imm  */
+  if (GET_CODE (cons) == CONST_INT && cons == const0_rtx
+  && GET_CODE (alt) == CONST_INT && alt != const0_rtx)
+{
+  riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
+  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+  alt = force_reg (mode, alt);
+  emit_insn (gen_rtx_SET (dest,
+  gen_rtx_IF_THEN_ELSE (mode, cond,
+cons, alt)));
+  return true;
+}
+  /* imm + imm  */
+  else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx
+   && GET_CODE (alt) == CONST_INT && alt != const0_rtx)
+{
+  riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
+  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+  alt = force_reg (mode, alt);
+  rtx temp1 = gen_reg_rtx (mode);
+  rtx temp2 = GEN_INT(-1 * INTVAL (cons));
+  riscv_emit_binary(PLUS, temp1, alt, temp2);
+  emit_insn (gen_rtx_SET (dest,
+  gen_rtx_IF_THEN_ELSE (mode, cond,
+const0_rtx, alt)));
+  riscv_emit_binary(PLUS, dest, dest, cons);
+  return true;
+}
+  /* imm + reg  */
+  else if (GET_CODE (cons) == CONST_INT && cons != const0_rtx
+   && GET_CODE (alt) == REG)
+{
+  /* Optimize for register value of 0.  */
+  if (op0 == alt && op1 == const0_rtx)
+{
+  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+  cons = force_reg (mode, cons);
+  emit_insn (gen_rtx_SET (dest,
+  gen_rtx_IF_THEN_ELSE (mode, cond,
+cons, alt)));
+  return true;
+}
+  riscv_emit_int_c

[PATCH 1/5] [RISC-V] Recognize Zicond extension

[Xiao Zeng]

This patch is the minimal support for Zicond extension, include
the extension name, mask and target defination.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New extension.
* config/riscv/riscv-opts.h (MASK_ZICOND): New mask.
(TARGET_ZICOND): New target.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/attribute-20.c: New test.
* gcc.target/riscv/attribute-21.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   | 3 +++
 gcc/config/riscv/riscv-opts.h | 3 +++
 gcc/testsuite/gcc.target/riscv/attribute-20.c | 6 ++
 gcc/testsuite/gcc.target/riscv/attribute-21.c | 6 ++
 4 files changed, 18 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-21.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 6091d8f281b..8460d83b0f1 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -183,6 +183,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
   {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
 
+  {"zicond", ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1243,6 +1245,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"zicsr",&gcc_options::x_riscv_zi_subext, MASK_ZICSR},
   {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
+  {"zicond",   &gcc_options::x_riscv_zi_subext, MASK_ZICOND},
 
   {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index cfcf608ea62..cecaee7d200 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -236,6 +236,9 @@ enum riscv_entity
 #define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
 #define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
 
+#define MASK_ZICOND   (1 << 2)
+#define TARGET_ZICOND ((riscv_zi_subext & MASK_ZICOND) != 0)
+
 #define MASK_ZFHMIN   (1 << 0)
 #define MASK_ZFH  (1 << 1)
 #define MASK_ZVFHMIN  (1 << 2)
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-20.c 
b/gcc/testsuite/gcc.target/riscv/attribute-20.c
new file mode 100644
index 000..b69c36cf4f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-20.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv32i_zicond -mabi=ilp32" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_zicond1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-21.c 
b/gcc/testsuite/gcc.target/riscv/attribute-21.c
new file mode 100644
index 000..160312a0d48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-21.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv64i_zicond -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicond1p0\"" } } */
-- 
2.17.1

[PATCH 5/5] [RISC-V] Generate Zicond instruction for conditional execution

[Xiao Zeng]

This patch completes the recognition of conditional execution
(using equality as an example), namely:

1 rd = (rc == 0) ? (rs1 arith_op rs2) : rs1

Here, arith_op represents the arithmetic operation symbol, which has 8
possibilities: + - | ^ << >>(Shift Right Arithmetic) >>(Shift Right Logical) &

At the same time, more Zicond non basic conditional execution test cases have
also been added, namely:

2 rd = (rc == 0) ? (rs1 arith_op non-imm) : rs1
3 rd = (rc == non-imm) ? (rs1 arith_op rs2) : rs1
4 rd = (rc == non-imm) ? (rs1 arith_op non-imm) : rs1
5 rd = (rc == reg) ? (rs1 arith_op rs2) : rs1
6 rd = (rc == reg) ? (rs1 arith_op non-imm) : rs1

gcc/ChangeLog:

* ifcvt.cc (noce_emit_condzero_arith): Helper function for 
noce_emit_condzero_arith.
(noce_try_condzero_arith): Recognize Zicond patterns.
(noce_process_if_block): Add noce_try_condzero_arith function.

gcc/testsuite/ChangeLog:

* 
gcc.target/riscv/zicond-conditionalArithmetic_compare_0_return_imm_reg.c: New 
test.
* 
gcc.target/riscv/zicond-conditionalArithmetic_compare_0_return_reg_reg.c: New 
test.
* 
gcc.target/riscv/zicond-conditionalArithmetic_compare_imm_return_imm_reg.c: New 
test.
* 
gcc.target/riscv/zicond-conditionalArithmetic_compare_imm_return_reg_reg.c: New 
test.
* 
gcc.target/riscv/zicond-conditionalArithmetic_compare_reg_return_imm_reg.c: New 
test.
* 
gcc.target/riscv/zicond-conditionalArithmetic_compare_reg_return_reg_reg.c: New 
test.
---
 gcc/ifcvt.cc  | 251 
 ...ionalArithmetic_compare_0_return_imm_reg.c | 553 +
 ...ionalArithmetic_compare_0_return_reg_reg.c | 585 ++
 ...nalArithmetic_compare_imm_return_imm_reg.c | 297 +
 ...nalArithmetic_compare_imm_return_reg_reg.c | 297 +
 ...nalArithmetic_compare_reg_return_imm_reg.c | 297 +
 ...nalArithmetic_compare_reg_return_reg_reg.c | 329 ++
 7 files changed, 2609 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-conditionalArithmetic_compare_0_return_imm_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-conditionalArithmetic_compare_0_return_reg_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-conditionalArithmetic_compare_imm_return_imm_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-conditionalArithmetic_compare_imm_return_reg_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-conditionalArithmetic_compare_reg_return_imm_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-conditionalArithmetic_compare_reg_return_reg_reg.c

diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc
index 0b180b4568f..0261d2f1673 100644
--- a/gcc/ifcvt.cc
+++ b/gcc/ifcvt.cc
@@ -781,12 +781,15 @@ static int noce_try_store_flag_constants (struct 
noce_if_info *);
 static int noce_try_store_flag_mask (struct noce_if_info *);
 static rtx noce_emit_cmove (struct noce_if_info *, rtx, enum rtx_code, rtx,
rtx, rtx, rtx, rtx = NULL, rtx = NULL);
+static rtx noce_emit_condzero_arith (struct noce_if_info *, rtx, enum 
rtx_code, rtx,
+ rtx, rtx, rtx);
 static int noce_try_cmove (struct noce_if_info *);
 static int noce_try_cmove_arith (struct noce_if_info *);
 static rtx noce_get_alt_condition (struct noce_if_info *, rtx, rtx_insn **);
 static int noce_try_minmax (struct noce_if_info *);
 static int noce_try_abs (struct noce_if_info *);
 static int noce_try_sign_mask (struct noce_if_info *);
+static int noce_try_condzero_arith (struct noce_if_info *);
 
 /* Return the comparison code for reversed condition for IF_INFO,
or UNKNOWN if reversing the condition is not possible.  */
@@ -1830,6 +1833,60 @@ noce_emit_cmove (struct noce_if_info *if_info, rtx x, 
enum rtx_code code,
 return NULL_RTX;
 }
 
+/* Helper function for noce_emit_condzero_arith.  */
+
+static rtx
+noce_emit_condzero_arith (struct noce_if_info *if_info, rtx x, enum rtx_code 
code,
+  rtx cmp_a, rtx cmp_b, rtx vfalse, rtx vtrue)
+{
+  rtx cond = NULL;
+
+  /* Standard form of conditional comparison.  */
+  if (GET_CODE(cmp_a) == REG && cmp_b == const0_rtx)
+cond = gen_rtx_fmt_ee (code, GET_MODE (if_info->cond), cmp_a, cmp_b);
+
+  /* Register and non-zero immediate comparison.  */
+  else if (GET_CODE(cmp_a) == REG && GET_CODE(cmp_b) == CONST_INT &&
+   cmp_b != const0_rtx)
+{
+  rtx temp1 = gen_reg_rtx (GET_MODE(cmp_a));
+  rtx temp2 = GEN_INT(-1 * INTVAL (cmp_b));
+  rtx src = gen_rtx_fmt_ee (PLUS, GET_MODE (cmp_a), cmp_a, temp2);
+  emit_insn (gen_rtx_SET (temp1, src));
+  cond = gen_rtx_fmt_ee (code, GET_MODE (if_info->cond), temp1, 
const0_rtx);
+}
+
+  /* Register and Register comparison.  */
+  else if (GET_CODE(cmp_a) == REG && GET_CODE(cmp_b) == REG)
+{
+  rtx temp1 = gen_reg_rtx (GET_MODE(cmp_a));
+  rtx src = gen_rtx_fmt_ee (MINUS, GET_MODE (c

[PATCH 4/5] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to non-zero

[Xiao Zeng]

This patch completes the recognition of Zicond when the select pattern with
condition eq or neq to non-zero (using equality as an example), namely:

1 rd = (rs2 == non-imm) ? 0 : rs1
2 rd = (rs2 == reg) ? 0 : rs1

At the same time, more Zicond non basic semantic test cases have been added.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_expand_conditional_move): Recognize 
Zicond.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zicond-primitiveSemantics_compare_imm.c: New test.
* 
gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_0_imm.c: New test.
* 
gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_imm.c: New 
test.
* 
gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_reg.c: New 
test.
* 
gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_reg_reg.c: New 
test.
* gcc.target/riscv/zicond-primitiveSemantics_compare_reg.c: New test.
* 
gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_0_imm.c: New test.
* 
gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_imm.c: New 
test.
* 
gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_reg.c: New 
test.
* 
gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_reg_reg.c: New 
test.
---
 gcc/config/riscv/riscv.cc | 16 
 .../zicond-primitiveSemantics_compare_imm.c   | 57 ++
 ...mitiveSemantics_compare_imm_return_0_imm.c | 73 ++
 ...tiveSemantics_compare_imm_return_imm_imm.c | 73 ++
 ...tiveSemantics_compare_imm_return_imm_reg.c | 65 
 ...tiveSemantics_compare_imm_return_reg_reg.c | 65 
 .../zicond-primitiveSemantics_compare_reg.c   | 65 
 ...mitiveSemantics_compare_reg_return_0_imm.c | 73 ++
 ...tiveSemantics_compare_reg_return_imm_imm.c | 73 ++
 ...tiveSemantics_compare_reg_return_imm_reg.c | 65 
 ...tiveSemantics_compare_reg_return_reg_reg.c | 77 +++
 11 files changed, 702 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_0_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_reg_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_0_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_reg_reg.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 7e6b24bd232..9450457e613 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3625,6 +3625,22 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx 
cons, rtx alt)
   riscv_emit_binary(IOR, dest, reg1, reg2);
   return true;
 }
+  /* For complex semantics of comparison value.
+ reg + 0 or 0 + reg  */
+  else if ((GET_CODE (cons) == REG &&
+   GET_CODE (alt) == CONST_INT &&
+alt == const0_rtx)
+   || (GET_CODE (alt) == REG &&
+   GET_CODE (cons) == CONST_INT &&
+   cons == const0_rtx))
+{
+  riscv_emit_int_compare (&code, &op0, &op1, need_eq_ne_p);
+  rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
+  emit_insn (gen_rtx_SET (dest,
+  gen_rtx_IF_THEN_ELSE (mode, cond,
+cons, alt)));
+  return true;
+}
 }
 
   return false;
diff --git 
a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm.c 
b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm.c
new file mode 100644
index 000..6de50039c31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */
+/* { dg-skip-if "" { *-*-* } {"-O0"} } */
+
+long primitiveSemantics_compare_imm_00(long a, long b) {
+  return a == 2 ? 0 : b;
+}
+
+long primitiveSemantics_compare_imm_01(long a, long b) {
+  return a != 2 ? 0 : b;
+}
+
+long primitiveSemanti

[PATCH 2/5] [RISC-V] Generate Zicond instruction for basic semantics

[Xiao Zeng]

This patch completes the recognition of the basic semantics
defined in the spec, namely:

Conditional zero, if condition is equal to zero
  rd = (rs2 == 0) ? 0 : rs1
Conditional zero, if condition is non zero
  rd = (rs2 != 0) ? 0 : rs1

gcc/ChangeLog:

* config/riscv/riscv.md: Include zicond.md
* config/riscv/zicond.md: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zicond-primitiveSemantics.c: New test.
---
 gcc/config/riscv/riscv.md |  1 +
 gcc/config/riscv/zicond.md| 84 +++
 .../riscv/zicond-primitiveSemantics.c | 49 +++
 3 files changed, 134 insertions(+)
 create mode 100644 gcc/config/riscv/zicond.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index d63b584a4c1..6b8c2e8e268 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3317,3 +3317,4 @@
 (include "sifive-7.md")
 (include "thead.md")
 (include "vector.md")
+(include "zicond.md")
diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
new file mode 100644
index 000..1cf28589c87
--- /dev/null
+++ b/gcc/config/riscv/zicond.md
@@ -0,0 +1,84 @@
+;; Machine description for the RISC-V Zicond extension
+;; Copyright (C) 2022-23 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+(define_code_iterator eq_or_ne [eq ne])
+(define_code_attr eqz [(eq "nez") (ne "eqz")])
+(define_code_attr nez [(eq "eqz") (ne "nez")])
+
+;; Zicond
+(define_insn "*czero.."
+  [(set (match_operand:GPR 0 "register_operand"  "=r")
+(if_then_else:GPR (eq_or_ne (match_operand:ANYI 1 "register_operand" 
"r")
+(const_int 0))
+  (match_operand:GPR 2 "register_operand""r")
+  (const_int 0)))]
+  "TARGET_ZICOND"
+  "czero.\t%0,%2,%1"
+)
+
+(define_insn "*czero.."
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+(if_then_else:GPR (eq_or_ne (match_operand:ANYI 1 "register_operand" 
"r")
+(const_int 0))
+  (const_int 0)
+  (match_operand:GPR 2 "register_operand"   "r")))]
+  "TARGET_ZICOND"
+  "czero.\t%0,%2,%1"
+)
+
+;; Special optimization under eq/ne in primitive semantics
+(define_insn "*czero.eqz..opt1"
+  [(set (match_operand:GPR 0 "register_operand"   "=r")
+(if_then_else:GPR (eq (match_operand:ANYI 1 "register_operand" "r")
+  (const_int 0))
+  (match_operand:GPR 2 "register_operand" "1")
+  (match_operand:GPR 3 "register_operand" "r")))]
+  "TARGET_ZICOND && operands[1] == operands[2]"
+  "czero.eqz\t%0,%3,%1"
+)
+
+(define_insn "*czero.eqz..opt2"
+  [(set (match_operand:GPR 0 "register_operand"   "=r")
+(if_then_else:GPR (eq (match_operand:ANYI 1 "register_operand" "r")
+  (const_int 0))
+  (match_operand:GPR 2 "register_operand" "r")
+  (match_operand:GPR 3 "register_operand" "1")))]
+  "TARGET_ZICOND && operands[1] == operands[3]"
+  "czero.nez\t%0,%2,%1"
+)
+
+(define_insn "*czero.nez..opt3"
+  [(set (match_operand:GPR 0 "register_operand"   "=r")
+(if_then_else:GPR (ne (match_operand:ANYI 1 "register_operand" "r")
+  (const_int 0))
+  (match_operand:GPR 2 "register_operand" "r")
+  (match_operand:GPR 3 "register_operand" "1")))]
+  "TARGET_ZICOND && operands[1] == operands[3]"
+  "czero.eqz\t%0,%2,%1"
+)
+
+(define_insn "*czero.nez..opt4"
+  [(set (match_operand:GPR 0 "register_operand"   "=r")
+(if_then_else:GPR (ne (match_operand:ANYI 1 "register_operand" "r")
+  (const_int 0))
+  (match_operand:GPR 2 "register_operand" "1")
+  (match_operand:GPR 3 "register_operand" "r")))]
+  "TARGET_ZICOND && operands[1] == operands[2]"
+  "czero.nez\t%0,%3,%1"
+)
diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c 
b/gcc/testsuite/gcc.target/riscv/zicond-p

[PATCH 0/5] Recognize Zicond extension

[Xiao Zeng]

Hi all RISC-V folks:

This series of patches completes support for the riscv architecture's
Zicond standard extension instruction set.

Currently, Zicond is in a frozen state.

See the Zicond specification for details:
https://github.com/riscv/riscv-zicond/releases/download/v1.0-rc2/riscv-zicond-v1.0-rc2.pdf

Prior to this, other community members have also done related work, as shown 
in: 
https://gcc.gnu.org/pipermail/gcc-patches/2023-February/611767.html
https://sourceware.org/pipermail/binutils/2023-January/125773.html

Xiao Zeng (5):
  [RISC-V] Recognize Zicond extension
  [RISC-V] Generate Zicond instruction for basic semantics
  [RISC-V] Generate Zicond instruction for select pattern with condition
eq or neq to 0
  [RISC-V] Generate Zicond instruction for select pattern with condition
eq or neq to non-zero
  [RISC-V] Generate Zicond instruction for conditional execution

 gcc/common/config/riscv/riscv-common.cc   |   3 +
 gcc/config/riscv/riscv-opts.h |   3 +
 gcc/config/riscv/riscv.cc | 141 +
 gcc/config/riscv/riscv.md |   3 +-
 gcc/config/riscv/zicond.md|  84 +++
 gcc/ifcvt.cc  | 251 
 gcc/testsuite/gcc.target/riscv/attribute-20.c |   6 +
 gcc/testsuite/gcc.target/riscv/attribute-21.c |   6 +
 ...ionalArithmetic_compare_0_return_imm_reg.c | 553 +
 ...ionalArithmetic_compare_0_return_reg_reg.c | 585 ++
 ...nalArithmetic_compare_imm_return_imm_reg.c | 297 +
 ...nalArithmetic_compare_imm_return_reg_reg.c | 297 +
 ...nalArithmetic_compare_reg_return_imm_reg.c | 297 +
 ...nalArithmetic_compare_reg_return_reg_reg.c | 329 ++
 .../riscv/zicond-primitiveSemantics.c |  49 ++
 .../zicond-primitiveSemantics_compare_imm.c   |  57 ++
 ...mitiveSemantics_compare_imm_return_0_imm.c |  73 +++
 ...tiveSemantics_compare_imm_return_imm_imm.c |  73 +++
 ...tiveSemantics_compare_imm_return_imm_reg.c |  65 ++
 ...tiveSemantics_compare_imm_return_reg_reg.c |  65 ++
 .../zicond-primitiveSemantics_compare_reg.c   |  65 ++
 ...mitiveSemantics_compare_reg_return_0_imm.c |  73 +++
 ...tiveSemantics_compare_reg_return_imm_imm.c |  73 +++
 ...tiveSemantics_compare_reg_return_imm_reg.c |  65 ++
 ...tiveSemantics_compare_reg_return_reg_reg.c |  77 +++
 .../zicond-primitiveSemantics_return_0_imm.c  |  65 ++
 ...zicond-primitiveSemantics_return_imm_imm.c |  73 +++
 ...zicond-primitiveSemantics_return_imm_reg.c |  65 ++
 ...zicond-primitiveSemantics_return_reg_reg.c |  65 ++
 29 files changed, 3857 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/zicond.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-21.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-conditionalArithmetic_compare_0_return_imm_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-conditionalArithmetic_compare_0_return_reg_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-conditionalArithmetic_compare_imm_return_imm_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-conditionalArithmetic_compare_imm_return_reg_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-conditionalArithmetic_compare_reg_return_imm_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-conditionalArithmetic_compare_reg_return_reg_reg.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_0_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_reg_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_0_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_reg_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_0_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_imm.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_imm_reg.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_return_reg_reg.c

-- 
2.17.1